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Adesto Technologies Corporation patents


Recent patent applications related to Adesto Technologies Corporation. Adesto Technologies Corporation is listed as an Agent/Assignee. Note: Adesto Technologies Corporation may have other listings under different names/spellings. We're not affiliated with Adesto Technologies Corporation, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "A" | Adesto Technologies Corporation-related inventors


Nonvolatile memory elements having conductive structures with semimetals and/or semiconductors

A memory element programmable between different impedance states, comprising: a first electrode layer comprising a semimetal or semiconductor (semimetal/semiconductor) and at least one other first electrode element; a second electrode; and a switch layer formed between the first and second electrodes and comprising an insulating material; wherein atoms of the... Adesto Technologies Corporation

Read latency reduction in a memory device

A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory... Adesto Technologies Corporation

Memory device having multiple read buffers for read latency reduction

A memory device can include: a memory array arranged to store data lines; an interface that receives a first read command requesting bytes of data in a consecutively addressed order from a starting byte; a cache memory having a first buffer storing a first data line including the starting byte,... Adesto Technologies Corporation

Memory elements having conductive cap layers and methods therefor

A memory element can include a first electrode; at least one switching layer formed over the first electrode; a second electrode layer; and at least one conductive cap layer formed over the second electrode layer having substantially no grain boundaries extending through to the second electrode layer; wherein the at... Adesto Technologies Corporation

Read latency reduction in a memory device

A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory... Adesto Technologies Corporation

Memory device ultra-deep power-down mode exit control

A memory device operable in an ultra-deep power-down mode can include: a command user interface; a voltage regulator having an output that provides a supply voltage for a plurality of components of the memory device, where the plurality of components comprises the command user interface; a wake-up circuit that remains... Adesto Technologies Corporation

Support for improved throughput in a memory device

A method of controlling a memory device can include: (i) receiving a first read command for a critical byte, where the critical byte resides in a first group of a memory array on the memory device; (ii) reading the critical byte from the memory array in response to the first... Adesto Technologies Corporation

Memory devices and methods having instruction acknowledgement

A system can include memory circuits configured to execute memory access operations in response to commands, a serial interface circuit configured to receive commands, including at least a first type command, and a controller circuit configured to generate a command complete acknowledgement that is output at the interface circuit after... Adesto Technologies Corporation








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