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Advanced Micro Devices Inc patents


Recent patent applications related to Advanced Micro Devices Inc. Advanced Micro Devices Inc is listed as an Agent/Assignee. Note: Advanced Micro Devices Inc may have other listings under different names/spellings. We're not affiliated with Advanced Micro Devices Inc, we're just tracking patents.

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 new patent  Memory heaps in a memory model for a unified computing system

A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a... Advanced Micro Devices Inc

Control system and architecture for incorporating microelectromechanical (mem) switches in fluid-based cooling of 3d integrated circuits

A cooling system is provided for a 3D integrated circuit (IC) to deliver fluid in x, y, and z dimensions to interior regions of the IC as a means to regulate heat. An IC includes a microfluidic network of channels, at least one sensor and at least one microelectromechanical system... Advanced Micro Devices Inc

Method and processing gating redundant threads

Described is a method and processing apparatus to improve power efficiency by gating redundant threads processing. In particular, the method for gating redundant threads in a graphics processor includes determining if data for a thread and data for at least another thread are within a predetermined similarity threshold, gating execution... Advanced Micro Devices Inc

Method and memory efficiency improvement by providing burst memory access control

Methods and apparatus monitor memory access activities of non-real-time processing engines to determine time intervals when the memory access activities are low. When such time intervals are found, the methods and apparatus perform burst memory access control for real-time processing engines by bursting data from a memory to a burst... Advanced Micro Devices Inc

System and scheduling instructions in a multithread simd architecture with a fixed number of registers

A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU,... Advanced Micro Devices Inc

System and using virtual vector register files

Described is a system and method for using virtual vector register files. In particular, a graphics processor includes a logic unit, a virtual vector register file coupled to the logic unit, a vector register backing store coupled to the virtual vector register file, and a virtual vector register file controller... Advanced Micro Devices Inc

System and processing data in a computing system

Systems, apparatuses, and methods for adjusting group sizes to match a processor lane width are described. In early iterations of an algorithm, a processor partitions a dataset into groups of data points which are integer multiples of the processing lane width of the processor. For example, when performing a K-means... Advanced Micro Devices Inc

Virtualization of a graphics processing unit for network applications

An accelerated processing unit includes a first processing unit configured to implement one or more virtual machines and a second processing unit configured to implement one or more acceleration modules. The one or more virtual machines are configured to provide information identifying a task or data to the one or... Advanced Micro Devices Inc

Temperature-aware task scheduling and proactive power management

Systems, apparatuses, and methods for performing temperature-aware task scheduling and proactive power management. A SoC includes a plurality of processing units and a task queue storing pending tasks. The SoC calculates a thermal metric for each pending task to predict an amount of heat the pending task will generate. The... Advanced Micro Devices Inc

Multi-processor apparatus and detection and acceleration of lagging tasks

A method and processing apparatus for accelerating program processing is provided that includes a plurality of processors configured to process a plurality of tasks of a program and a controller. The controller is configured to determine, from the plurality of tasks being processed by the plurality of processors, a task... Advanced Micro Devices Inc

System and protecting gpu memory instructions against faults

A system and method for protecting memory instructions against faults are described. The system and method include converting the slave instructions to dummy operations, modifying memory arbiter to issue up to N master and N slave global/shared memory instructions per cycle, sending master memory requests to memory system, using slave... Advanced Micro Devices Inc

Real-time performance tracking using dynamic compilation

Systems, apparatuses, and methods for performing real-time tracking of performance targets using dynamic compilation. A performance target is specified in a service level agreement. A dynamic compiler analyzes a software application executing in real-time and determine which high-level application metrics to track. The dynamic compiler then inserts instructions into the... Advanced Micro Devices Inc

Targeted per-line operations for remote scope promotion

A processing system includes one or more first caches and one or more first lock tables associated with the one or more first caches. The processing system also includes one or more processing units that each include a plurality of compute units for concurrently executing work-groups of work items, a... Advanced Micro Devices Inc

Shadow tag memory to monitor state of cachelines at different cache level

A processing system includes a plurality of processor cores and a plurality of private caches. Each private cache is associated with a corresponding processor core of the plurality of processor cores and includes a corresponding first set of cachelines. The processing system further includes a shared cache shared by the... Advanced Micro Devices Inc

Contended lock request elision scheme

A system and method for network traffic management between multiple nodes are described. A computing system includes multiple nodes connected to one another. When a home node determines a number of nodes requesting read access for a given data block assigned to the home node exceeds a threshold and a... Advanced Micro Devices Inc

Method and reducing tlb shootdown overheads in accelerator-based systems

A method and apparatus for reducing TLB shootdown operation overheads in accelerator-based computing systems is described. The disclosed method and apparatus may also be used in the areas of near-memory and in-memory computing, where near-memory or in-memory compute units may need to share a host CPU's virtual address space. Metadata... Advanced Micro Devices Inc

Culling objects from a 3-d graphics pipeline using hierarchical z buffers

A shader in a graphics pipeline accesses an object that represents a portion of a model of a scene in object space and one or more far-z values that indicate a furthest distance of a previously rendered portion of one or more tiles from a viewpoint used to render the... Advanced Micro Devices Inc

Asynchronous feedback training

Systems, apparatuses, and methods for implementing asynchronous feedback training sequences are described. A transmitter transmits a training sequence indication to a receiver via a communication channel including a plurality of data lines. The training sequence indication includes a bit sequence to indicate the beginning of a training sequence. The indication... Advanced Micro Devices Inc

Channel training using a replica lane

Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to... Advanced Micro Devices Inc

Achieving balanced execution through runtime detection of performance variation

Systems, apparatuses, and methods for achieving balanced execution in a multi-node cluster through runtime detection of performance variation are described. During a training phase, performance counters and an amount of time spent waiting for synchronization is monitored for a plurality of tasks for each node of the multi-node cluster. These... Advanced Micro Devices Inc

Write buffer design for high-latency memories

A memory system includes a write buffer, a main memory having a higher latency than the write buffer, and a memory controller. In response to a write request indicating first data for storing at a write address in the main memory, the memory controller adds a new write entry in... Advanced Micro Devices Inc

Fingerprinting of redundant threads using compiler-inserted transformation code

A first processing element is configured to execute a first thread and one or more second processing elements are configured to execute one or more second threads that are redundant to the first thread. The first thread and the one or more second threads are to selectively bypass one or... Advanced Micro Devices Inc

Managing cluster-level performance variability without a centralized controller

Systems, apparatuses, and methods for managing cluster-level performance variability without a centralized controller are described. Each node of a multi-node cluster tracks a maximum and minimum progress across the plurality of nodes for a workload executed by the cluster. Each node also tracks its local progress on its current task.... Advanced Micro Devices Inc

Cache entry replacement based on availability of entries at another cache

A processing system selects entries for eviction at one cache based at least in part on the validity status of corresponding entries at a different cache. The processing system includes a memory hierarchy having at least two caches, a higher level cache and a lower level cache. The lower level... Advanced Micro Devices Inc

Power management of instruction processors in a system-on-a-chip

A system-on-a-chip includes a plurality of instruction processors and a hardware block such as a system management unit. The hardware block accesses values of performance counters associated with the plurality of instruction processors and modifies one or more operating points of one or more of the plurality of instruction processors... Advanced Micro Devices Inc

Asynchronous cache flushing

Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device to a second memory in response to execution of a non-blocking flush instruction. Reactive flush logic in the computing system is configured to,... Advanced Micro Devices Inc

Setting cache entry age based on hints from another cache level

A processor replaces data at a first cache based on hints from a second cache, wherein the hints indicate information about the data that is not available to the first cache directly. When data at an entry is transferred from the first cache to the second cache, the first cache... Advanced Micro Devices Inc

Up/down prefetcher

In a processing system comprising a cache, a method includes monitoring demand cache accesses for a thread to maintain a first running count of a number of times demand cache accesses for the thread are directed to cachelines that are adjacent in a first direction to cachelines that are targets... Advanced Micro Devices Inc

Scaled set dueling for cache replacement policies

A processing system includes a cache that includes a cache lines that are partitioned into a first subset of the cache lines and a second subsets of the cache lines. The processing system also includes one or more counters that are associated with the second subsets of the cache lines.... Advanced Micro Devices Inc

Dynamically adjustable inclusion bias for inclusive caches

A first cache that includes a plurality of cache lines and is inclusive of a second cache. The plurality of cache lines are associated with a plurality of N-bit values. The first cache modifies each N-bit value in response to a hit at the corresponding one of the plurality of... Advanced Micro Devices Inc

Self refresh state machine mop array

In one form, a memory controller includes a controller and a memory operation array. The controller has an input for receiving a power state change request signal and an output for providing memory operations. The memory operation array comprises a plurality of entries, each entry comprising a plurality of encoded... Advanced Micro Devices Inc

Offloading execution of an application by a network connected device

A client device detects one or more servers to which an application can be offloaded. The client device receives information from the servers regarding their graphics processing unit (GPU) compute resources. The client device selects one of the servers to offload the application based on such factors as the GPU... Advanced Micro Devices Inc

Low power memory throttling

In one form, a data processing system includes a memory channel having a plurality of ranks, and a data processor. The data processor is coupled to the memory channel and is adapted to access each of the plurality of ranks. In response to detecting a predetermined event, the data processor... Advanced Micro Devices Inc

Integral post package repair

A post-package repair system includes a memory channel controller, a first error counter, a scrubber, and a data processor. The memory channel controller converts data access requests to corresponding memory accesses, and provides returned data to the host interface in response to responses received from a memory interface, wherein the... Advanced Micro Devices Inc

Cache coherence for processing in memory

A cache coherence bridge protocol provides an interface between a cache coherence protocol of a host processor and a cache coherence protocol of a processor-in-memory, thereby decoupling coherence mechanisms of the host processor and the processor-in-memory. The cache coherence bridge protocol requires limited change to existing host processor cache coherence... Advanced Micro Devices Inc

11/30/17 / #20170344490

Using multiple memory elements in an input-output memory management unit for performing virtual address to physical address translations

The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to... Advanced Micro Devices Inc

11/30/17 / #20170345482

Fine granularity refresh

A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor is adapted to access at least one rank and has refresh logic. In response to an activation of the refresh logic, the data processor generates refresh cycles to a bank... Advanced Micro Devices Inc

11/30/17 / #20170345512

Wear-limiting non-volatile memory

A non-volatile memory device having at least one non-volatile flash memory formatted with physical addresses to read and write data that is organized into blocks of data, wherein the blocks of data are organized into pages of data, and wherein the pages of data are organized into cells of data.... Advanced Micro Devices Inc

11/30/17 / #20170347498

Multi-compartment computing device with shared cooling device

Various computing devices, thermal solutions and enclosures are disclosed. In one aspect, a computing device enclosure is provided that includes a first compartment that has a first upper side and is adapted to house the computing device and a liquid cooling device. The computing device has at least one heat... Advanced Micro Devices Inc

11/23/17 / #20170337136

Managing cache coherence using information in a page table

The described embodiments include a computing device with two or more types of processors and a memory that is shared between the two or more types of processors. The computing device performs operations for handling cache coherency between the two or more types of processors. During operation, the computing device... Advanced Micro Devices Inc

11/16/17 / #20170332096

System and dynamically stitching video streams

A video codec includes a stitching module configured to select stored encoded video frames that are to be composed into a concatenated frame for display. The stitching module arranges the selected encoded video frames into a specified pattern, and stitches the arranged encoded video frames together to generate a stitched... Advanced Micro Devices Inc

11/02/17 / #20170315915

Leases for blocks of memory in a multi-level memory

The described embodiments include a computing device that has two or more levels of memory, each level of memory having different performance characteristics. During operation, the computing device receives a request to lease an available block of memory in a specified level of memory for storing an object. When a... Advanced Micro Devices Inc

11/02/17 / #20170315927

Method and translation lookaside buffer with multiple compressed encodings

Methods and apparatus obtain one or more system page table entries that represent virtual system (e.g., memory) page to physical system page translations. A number of the obtained system page table entries that can be encoded in each of a plurality of translation lookaside buffer (TLB) entry encoding formats are... Advanced Micro Devices Inc

11/02/17 / #20170315932

Selecting cache aging policy for prefetches based on cache test regions

A cache controller applies an aging policy to a portion of a cache based on access metrics for different test regions of the cache, whereby each test region implements a different aging policy. The aging policy for each region establishes an initial age value for each entry of the cache,... Advanced Micro Devices Inc

10/26/17 / #20170308297

Object tagged memory monitoring method and processing apparatus

Described are a method and processing apparatus to tag and track objects related to memory allocation calls. An application or software adds a tag to a memory allocation call to enable object level tracking. An entry is made into an object tracking table, which stores the tag and a variety... Advanced Micro Devices Inc

10/19/17 / #20170300101

Redirecting messages from idle compute units of a processor

A power management module of a processor places a compute unit in a low power mode (e.g., an idle mode) in response to identifying that the compute unit is expected to experience little to no processing activity for a threshold amount of time. In response to receiving an indication from... Advanced Micro Devices Inc

10/19/17 / #20170300592

Bucketized hash tables with remap entries

Methods and mechanisms for managing data in a hash table are disclosed. A computing system includes a hash table configured to store data and hash management logic. In response to receiving a request to insert data into the hash table, the hash management logic is configured to generate a first... Advanced Micro Devices Inc

10/19/17 / #20170302918

Efficient streaming of virtual reality content

Systems, methods and apparatuses of processing data of a VR system are disclosed that comprise receiving tracking information which includes at least one of user position information and eye gaze point information. One or more processors may be used to predict, based on the user tracking information, a user viewpoint... Advanced Micro Devices Inc

10/19/17 / #20170302972

Low latency wireless virtual reality systems and methods

Virtual Reality (VR) systems, apparatuses and methods of processing data are provided which include predicting, at a server, a user viewpoint of a next frame of video data based on received user feedback information sensed at a client, rendering a portion of the next frame using the prediction, encoding the... Advanced Micro Devices Inc

10/12/17 / #20170293487

Flexible framework to support memory synchronization operations

A method of performing memory synchronization operations is provided that includes receiving, at a programmable cache controller in communication with one or more caches, an instruction in a first language to perform a memory synchronization operation of synchronizing a plurality of instruction sequences executing on a processor, mapping the received... Advanced Micro Devices Inc

10/12/17 / #20170293499

Message handler compiling and scheduling in heterogeneous system architectures

A receiving node in a computer system that includes a plurality of types of execution units receives an active message from a sending node. The receiving node compiles an intermediate language message handler corresponding to the active message into a machine instruction set architecture (ISA) message handler and the receiver... Advanced Micro Devices Inc

10/12/17 / #20170293560

Method and performing memory prefetching

A method and apparatus for performing memory prefetching includes determining whether to initiate prefetching. Upon a determination to initiate prefetching, a first memory row is determined as a suitable prefetch candidate, and it is determined whether a particular set of one or more cachelines of the first memory row is... Advanced Micro Devices Inc

10/12/17 / #20170293564

Adaptive resizable cache/lcm for improved power

Systems, apparatuses and methods of adaptively controlling a cache operating voltage are provided that comprise receiving indications of a plurality of cache usage amounts. Each cache usage amount corresponds to an amount of data to be accessed in a cache by one of a plurality of portions of a data... Advanced Micro Devices Inc

10/12/17 / #20170295111

Methods and processing in a network on chip (noc)

Methods and apparatus of delegating instructions or data from a CU to an NOC node in a network on chip (NOC) is disclosed. The NOC node executes the delegated instructions or processes the delegated data. An NOC controller (NCC), which is operatively coupled to the CU and the NOC node,... Advanced Micro Devices Inc

10/05/17 / #20170289057

Self-timed router with virtual channel control

Systems, apparatuses, and methods for implementing an asynchronous router with virtual channel (VC) control. The asynchronous router may support multiple VCs for connections to other routers. The asynchronous router may include an interface unit on each switch boundary, with each interface unit including a data merge unit. The data merge... Advanced Micro Devices Inc

10/05/17 / #20170289078

Systems and methods of supporting parallel processor message-based communications

A method of message-based communication is provided which includes executing, on one or more accelerated processing units, a plurality of groups of work items, receiving a first message from a first group of work items of the plurality of groups of work items executing on the one or more accelerated... Advanced Micro Devices Inc

09/28/17 / #20170277441

Performance-aware and reliability-aware data placement for n-level heterogeneous memory systems

Techniques for selecting one of a plurality of heterogeneous memory units for placement of blocks of data (e.g., memory pages), based on both reliability and performance, are disclosed. A “cost” for each data block/memory unit combination is determined, based on the frequency of access of the data block, the latency... Advanced Micro Devices Inc

09/28/17 / #20170277634

Using leases for entries in a translation lookaside buffer

The described embodiments include a computing device with two or more translation lookaside buffers (TLB) that performs operations for handling entries in the TLBs. During operation, the computing device maintains lease values for entries in the TLBs, the lease values representing times until leases for the entries expire, wherein a... Advanced Micro Devices Inc

09/28/17 / #20170277639

Adaptive extension of leases for entries in a translation lookaside buffer

The described embodiments include a computing device with two or more translation lookaside buffers (TLB). During operation, the computing device updates an entry in the TLB based on a virtual address to physical address translation and metadata from a page table entry that were acquired during a page table walk.... Advanced Micro Devices Inc

09/28/17 / #20170277898

Key management for secure memory address spaces

A processor employs a security module to manage authentication and encryption keys for the processor. The security module can authenticate itself to other processing systems, such as processing systems providing software to be executed at the processor, can generate keys for encrypting address spaces for the provided software, and can... Advanced Micro Devices Inc

09/28/17 / #20170278213

Hierarchical register file at a graphics processing unit

A processor employs a hierarchical register file for a graphics processing unit (GPU). A top level of the hierarchical register file is stored at a local memory of the GPU (e.g., a memory on the same integrated circuit die as the GPU). Lower levels of the hierarchical register file are... Advanced Micro Devices Inc

09/28/17 / #20170279703

Managing variations among nodes in parallel system frameworks

Systems, apparatuses, and methods for managing variations among nodes in parallel system frameworks. Sensor and performance data associated with the nodes of a multi-node cluster may be monitored to detect variations among the nodes. A variability metric may be calculated for each node of the cluster based on the sensor... Advanced Micro Devices Inc

09/21/17 / #20170269651

Method and managing power in a thermal couple aware system

A method and apparatus for managing power in a thermal couple aware system includes determining a candidate configuration mapping based upon one or more criteria, the candidate configuration mapping being a mapping of performance for a candidate configuration of processor sockets in the thermal couple aware system. The candidate configuration... Advanced Micro Devices Inc

09/14/17 / #20170262289

Method and system for yield operation supporting thread-like behavior

A method, system, and computer program product synchronize a group of workitems executing an instruction stream on a processor. The processor is yielded by a first workitem responsive to a synchronization instruction in the instruction stream. A first one of a plurality of program counters is updated to point to... Advanced Micro Devices Inc

09/07/17 / #20170255397

Efficient implementation of queues and other data structures using processing near memory

Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return,... Advanced Micro Devices Inc

Patent Packs
08/17/17 / #20170235700

Peripheral component

Embodiments of a peripheral component are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors in one peripheral component can use one peripheral interface slot without requiring an external bridge IC.... Advanced Micro Devices Inc

08/17/17 / #20170237658

Assigning variable length address identifiers to packets in a processing system

A controller assigns variable length addresses to addressable elements that are connected to a network. The variable length addresses are determined based on probabilities that packets are addressed to the corresponding addressable element. The controller transmits, to the addressable elements via the network, a routing table indicating the variable length... Advanced Micro Devices Inc

08/10/17 / #20170227765

Method and system for streaming information in wireless virtual reality

Described is a method and system to efficiently compress and stream texture-space rendered content that enables low latency wireless virtual reality applications. In particular, camera motion, object motion/deformation, and shading information are decoupled and each type of information is then compressed as needed and streamed separately, while taking into account... Advanced Micro Devices Inc

08/10/17 / #20170228164

User-level instruction for memory locality determination

Systems and methods for efficiently processing data in a non-uniform memory access (NUMA) computing system are disclosed. A computing system includes multiple nodes connected in a NUMA configuration. Each node includes a processing unit which includes one or more processors. A processor in a processing unit executes an instruction that... Advanced Micro Devices Inc

08/10/17 / #20170228321

Pinning objects in multi-level memory hierarchies

The described embodiments include a computer system having a multi-level memory hierarchy with two or more levels of memory, each level being one of two or more types of memory. The computer system handles storing objects in the multi-level memory hierarchy. During operation, a system runtime in the computer system... Advanced Micro Devices Inc

08/03/17 / #20170220022

Determining thermal time constants of processing systems

A processing system includes one or more processing units to perform operations and one or more sensors to measure a temperature concurrently with the one or more processing units performing the operations. The processing system also includes a controller to receive feedback indicating the temperature and to determine a peak... Advanced Micro Devices Inc

08/03/17 / #20170220346

Method and inter-lane thread migration

Briefly, methods and apparatus to migrate a software thread from one wavefront executing on one execution unit to another wavefront executing on another execution unit whereby both execution units are associated with a compute unit of a processing device such as, for example, a GPU. The methods and apparatus may... Advanced Micro Devices Inc

08/03/17 / #20170220369

Hypervisor post-write notification of control and debug register updates

Systems, apparatuses, and methods for implementing hypervisor post-write notification of processor state register modifications. A write to a state register of the processor may be detected during guest execution. In response to detecting the write to the state register, the processor may trigger microcode to perform the write and copy... Advanced Micro Devices Inc

08/03/17 / #20170220485

Routing direct memory access requests in a virtualized computing environment

A device may receive a direct memory access request that identifies a virtual address. The device may determine whether the virtual address is within a particular range of virtual addresses. The device may selectively perform a first action or a second action based on determining whether the virtual address is... Advanced Micro Devices Inc

08/03/17 / #20170223370

System for video compression

A system and method for providing video compression that includes encoding using an encoding engine a YUV stream wherein Y, U and V color values are encoded in parallel and patching together the Y, U and V color streams to form a compressed YUV output stream. The encoding engine further... Advanced Micro Devices Inc

07/27/17 / #20170212757

Simd processing unit with local data share and access to a global data share of a gpu

A graphics processing unit is disclosed, the graphics processing unit having a processor having one or more SIMD processing units, and a local data share corresponding to one of the one or more SIMD processing units, the local data share comprising one or more low latency accessible memory regions for... Advanced Micro Devices Inc

07/27/17 / #20170212760

Instruction set and micro-architecture supporting asynchronous memory access

A system and method for reducing latencies of main memory data accesses are described. A non-blocking load (NBLD) instruction identifies an address of requested data and a subroutine. The subroutine includes instructions dependent on the requested data. A processing unit verifies that address translations are available for both the address... Advanced Micro Devices Inc

07/27/17 / #20170212837

Adaptive value range profiling for enhanced system performance

Enhanced adaptive profiling of ranges of values in a stream of events includes identifying a set of contiguous ranges of the values and corresponding access frequencies in the stream of events. The enhanced adaptive profiling uses a merge threshold value and a split threshold value. The set of contiguous ranges... Advanced Micro Devices Inc

07/27/17 / #20170212845

Region migration cache

A memory access profiling and region migration technique makes allocation and replacement decisions for periodic migration of most frequently accessed regions of main memory to least frequently accessed regions of a region migration cache, in background operations. The technique improves performance in sparsely-used memory systems by migrating regions of main... Advanced Micro Devices Inc

07/27/17 / #20170212851

Using processor types for processing interrupts in a computing device

The described embodiments include a computing device with multiple interrupt processors for processing interrupts. In the described embodiments, each of the multiple processors is classified as one or more processor types based on factors such as features and functionality of the processor, an operating environment of the processor, the characteristics... Advanced Micro Devices Inc

Patent Packs
07/20/17 / #20170206625

Method and apparatus to accelerate rendering of graphics images

Described is a method and apparatus to accelerate rendering of 3D graphics images. When rendering, the transformation matrix (or equivalent) used for projecting primitives is modified so that a resulting image is smaller and/or warped compared to a regular unmodified rendering. The effect of such transformation is fewer pixels being... Advanced Micro Devices Inc

07/20/17 / #20170206626

Techniques for sampling sub-pixels of an image

Systems, apparatuses, and methods for generating and utilizing sub-pixel sampling patterns on a processor are disclosed. In one embodiment, a processor includes at least multiple execution units and a memory. The processor generates sub-pixel sampling coordinates within each pixel of an image being rendered based on a rotated grid superimposed... Advanced Micro Devices Inc

07/20/17 / #20170206630

Memory management in graphics and compute application programming interfaces

Methods are provided for creating objects in a way that permits an API client to explicitly participate in memory management for an object created using the API. Methods for managing data object memory include requesting memory requirements for an object using an API and expressly allocating a memory location for... Advanced Micro Devices Inc

07/20/17 / #20170206638

Hybrid anti-aliasing

Systems, apparatuses, and methods for performing hybrid anti-aliasing operations are disclosed. The hybrid anti-aliasing resolve operation combines multi-sampling anti-aliasing (MSAA) and post-processing anti-aliasing to generate higher-quality images in a computationally efficient manner. In one embodiment, a processor detects a request to perform an anti-aliasing resolve operation on an image stored... Advanced Micro Devices Inc

07/13/17 / #20170201503

Memory operation encryption

A processing system includes a processing module having a first interface coupleable to an interconnect. The first interface includes a first cryptologic engine to encrypt a representation of store data of a store operation and a memory address using a first key and a first feedback-based cryptologic process to generate... Advanced Micro Devices Inc

07/13/17 / #20170200672

Interposer having a pattern of sites for mounting chiplets

The described embodiments include an interposer with signal routes located therein. The interposer includes a set of sites arranged in a pattern, each site including a set of connection points. Each connection point in each site is coupled to a corresponding one of the signal routes. Integrated circuit chiplets may... Advanced Micro Devices Inc

07/06/17 / #20170193697

Method and performing high throughput tessellation

A method, a system, and a computer-readable storage medium directed to performing high-speed parallel tessellation of 3D surface patches are disclosed. The method includes generating a plurality of primitives in parallel. Each primitive in the plurality is generated by a sequence of functional blocks, in which each sequence acts independently... Advanced Micro Devices Inc

07/06/17 / #20170195683

Texture compression techniques

A texture compression method is described. The method comprises splitting an original texture having a plurality of pixels into original blocks of pixels. Then, for each of the original blocks of pixels, a partition is identified that has one or more disjoint subsets of pixels whose union is the original... Advanced Micro Devices Inc

06/29/17 / #20170185409

Hardware accuracy counters for application precision and quality feedback

Methods, devices, and systems for capturing an accuracy of an instruction executing on a processor. An instruction may be executed on the processor, and the accuracy of the instruction may be captured using a hardware counter circuit. The accuracy of the instruction may be captured by analyzing bits of at... Advanced Micro Devices Inc

06/29/17 / #20170185451

Data driven scheduler on multiple computing cores

Methods, devices, and systems for data driven scheduling of a plurality of computing cores of a processor. A plurality of threads may be executed on the plurality of computing cores, according to a default schedule. The plurality of threads may be analyzed, based on the execution, to determine correlations among... Advanced Micro Devices Inc

06/29/17 / #20170185514

Caching policies for processing units on multiple sockets

A processing system includes a first socket, a second socket, and an interface between the first socket and the second socket. A first memory is associated with the first socket and a second memory is associated with the second socket. The processing system also includes a controller for the first... Advanced Micro Devices Inc

06/22/17 / #20170177484

Region probe filter for distributed memory system

A probe filter determines whether to issue a probe to at least one other processing node in response to a memory access request, and includes a region probe filter directory, a line probe filter directory, and a controller. The region probe filter directory identifies regions of memory for which at... Advanced Micro Devices Inc

06/22/17 / #20170177492

Hybrid cache

Systems, apparatuses, and methods for implementing a hybrid cache. A processor may include a hybrid L2/L3 cache which allows the processor to dynamically adjust a size of the L2 cache and a size of the L3 cache. In some embodiments, the processor may be a multi-core processor and there may... Advanced Micro Devices Inc

06/22/17 / #20170177498

Centrally managed unified shared virtual address space

Systems, apparatuses, and methods for managing a unified shared virtual address space. A host may execute system software and manage a plurality of nodes coupled to the host. The host may send work tasks to the nodes, and for each node, the host may externally manage the node's view of... Advanced Micro Devices Inc

06/22/17 / #20170178275

Method and system for using solid state device as eviction pad for graphics processing unit

Described is a method and system for using a solid state device (SSD) as an eviction pad for graphics processing units (GPUs). The method for eviction processing includes a processor that determines when a dedicated memory associated with a GPU and a host memory associated with the processor are congested.... Advanced Micro Devices Inc

06/22/17 / #20170178397

Texel shading in texture space

A graphics processing unit is configured to map pixels of a first frame of a video stream to texels, select a subset of the texels for shading based on previously cached texels that were shaded for a second frame, and shade the subset of the texels. The graphics processing unit... Advanced Micro Devices Inc

06/15/17 / #20170168546

Method and performing inter-lane power management

A method and apparatus for performing inter-lane power management includes de-energizing one or more execution lanes upon a determination that the one or more execution lanes are to be predicated. Energy from the predicated execution lanes is redistributed to one or more active execution lanes.... Advanced Micro Devices Inc

06/08/17 / #20170160781

Balancing computation and communication power in power constrained clusters

Systems, apparatuses, and methods for balancing computation and communication power in power constrained environments. A data processing cluster with a plurality of compute nodes may perform parallel processing of a workload in a power constrained environment. Nodes that finish tasks early may be power-gated based on one or more conditions.... Advanced Micro Devices Inc

06/08/17 / #20170160955

Page migration in a 3d stacked hybrid memory

A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the... Advanced Micro Devices Inc

06/08/17 / #20170161114

Method and time-based scheduling of tasks

A computing device is disclosed. The computing device includes an Accelerated Processing Unit (APU) including at least a first Heterogeneous System Architecture (HSA) computing device and at least a second HSA computing device, the second computing device being a different type than the first computing device, and an HSA Memory... Advanced Micro Devices Inc

06/08/17 / #20170161194

Page-based prefetching triggered by tlb activity

A method of prefetching data includes issuing to a translation lookaside buffer (TLB) an address translation request for a virtual memory address, detecting a TLB miss generated in response to the address translation request, and in response to the TLB miss, selecting the data for prefetching from memory based on... Advanced Micro Devices Inc

06/08/17 / #20170161212

System and application migration

Described is a method and apparatus for application migration between a dockable device and a docking station in a seamless manner. The dockable device includes a processor and the docking station includes a high-performance processor. The method includes determining a docking state of a dockable device while at least an... Advanced Micro Devices Inc

06/08/17 / #20170163282

Reducing power needed to send signals over wires

Methods and apparatus are described. A method, implemented in a decoder, includes receiving two or more signals from an encoder over two or more respective wires. At least one of the two or more signals includes at least one code that was recoded by the encoder. The decoder receives a... Advanced Micro Devices Inc








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