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Advanced Micro Devices Inc patents

Recent patent applications related to Advanced Micro Devices Inc. Advanced Micro Devices Inc is listed as an Agent/Assignee. Note: Advanced Micro Devices Inc may have other listings under different names/spellings. We're not affiliated with Advanced Micro Devices Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "A" | Advanced Micro Devices Inc-related inventors




Date Advanced Micro Devices Inc patents (updated weekly) - BOOKMARK this page
05/25/17 new patent  Computation along a datapath between memory blocks
05/25/17 new patent  Floating point multiply accumulator multi-precision mantissa aligner
05/25/17 new patent  Method and performing a parallel search operation
05/18/17Interconnect architecture for three-dimensional processing systems
05/18/17Efficient processor load balancing using predication
05/11/17Cache with address space mapping to slice subsets
05/04/17Method and systems of controlling memory-to-memory copy operations
05/04/17Relocatable and resizable tables in a computing device
05/04/17In-memory interconnect protocol configuration registers
04/27/17Estimation of bit widths of variables based on liveness
04/13/17Minimizing latency from peripheral devices to compute engines
04/13/17Method and workload placement on heterogeneous systems
04/06/17Mode-dependent access to embedded memory elements
03/30/17Method and device for noise reduction in multi-frequency clocking environment
03/23/17Thermally-aware throttling in a three-dimensional processor stack
03/23/17Power management of interactive workloads driven by direct and indirect user feedback
03/23/17Power management for heterogeneous computing systems
03/23/17Selective data copying between memory modules
03/23/17Power-aware work stealing
03/23/17Dynamic multithreaded cache allocation
03/23/17Configuring fast memory as cache for slow memory
03/23/17Cache access statistics accumulation for cache line replacement selection
03/23/17Distributed memory controller
03/23/17Multi-protocol header generation system
03/16/17Preemptive context switching of processes on an accelerated processing device (apd) based on time quanta
03/02/17Programmable memory command sequencer
03/02/17Graphics library extensions
02/23/17Priority-based command execution
02/16/17Media system having three dimensional navigation via dynamic carousel
02/16/17Logical memory address regions
02/16/17Distributed gather/scatter operations across a network of memory nodes
02/16/17Register files for i/o packet compression
02/02/17Mechanism for resource utilization metering in a computer system
02/02/17Communication device with selective encoding
01/19/17Split storage of anti-aliased samples
01/05/17System performance management using prioritized compute units
12/29/16Dynamic power management optimization
12/29/16Protecting state information for virtual machines
12/29/16Scriptable dynamic load balancing in computer systems
12/29/16Hot page selection in multi-level memory hierarchies
12/29/16Independent between-module prefetching for processor memory modules
12/29/16Memory module with embedded access metadata
12/29/16Shared virtual address space for heterogeneous processors
12/29/16Method and performing a search operation on heterogeneous computing systems
12/29/16Reducing the load on the bitlines of a rom bitcell array
12/29/16Semiconductor area optimization
12/29/16Computer architecture using rapidly reconfigurable circuits and high-bandwidth memory interfaces
12/29/16Mechanism of identifying available memory resources in a network of multi-level memory modules
12/22/16Ordering memory commands in a computer system
12/22/16Instruction context switching
12/22/16Heterogeneous enqueuing and dequeuing mechanism for task scheduling
12/22/16Memory speculation for multiple memories
12/22/16Memory heaps in a memory model for a unified computing system
12/22/16Hybrid render with preferred primitive batch binning and sorting
12/15/16Managing coherent memory between an accelerated processing device and a central processing unit
12/08/16Conditional atomic operations at a processor
12/08/16Per-block sort for performance enhancement of parallel processors
12/08/16Source-side resource request network admission control
12/01/16Method and system for constant time cryptography using a co-processor
12/01/16Message aggregation, combining and compression for efficient data communications in gpu-based clusters
11/24/16Thermal oscillator
11/24/16Scan flip-flop circuit with dedicated clocks
11/24/16Droop detection for low-dropout regulator
11/24/16Droop detection and regulation for processor tiles
11/24/16Saving the architectural state of a computing device using sectors
Patent Packs
11/24/16Two-phase hybrid vertex classification
11/17/16Infrastructure to support accelerator computation models for active storage
11/17/16System and determining concurrency factors for dispatch size of parallel processor kernels
11/17/16Control of thermal energy transfer for phase change material in data center
11/10/16Methods and optical blur modeling for improved video encoding
11/03/16Early cache prefetching in preparation for exit from idle mode
10/20/16Performance state selection for low activity scenarios
10/13/16Real time on-chip texture decompression using shader processors
10/06/16Power reduction in bus interconnects
09/29/16Integrated differential clock gater
09/15/16Power management to change power limits based on device skin temperature
09/15/16Changing power limits based on device state
09/08/16Hardware and runtime coordinated load balancing for parallel applications
09/08/16Redundancy shader column repair
09/08/16Providing asynchronous display shader functionality on a shared shader core
Patent Packs
09/08/16Efficient asynchronous communication protocol
09/08/16Content-adaptive b-picture pattern video encoding
09/01/16Method and directing application requests for rendering
08/25/16Pruning of low power state information for a processor
08/25/16Scheduling of data migration
08/25/16Technique for translating dependent instructions
08/25/16Memory module with volatile and non-volatile storage arrays
08/25/16Flip-flop circuit with latch bypass
08/18/16Bit remapping mechanism to enhance lossy compression in floating-point applications
08/18/16Generating a schedule of instructions based on a processor memory tree
08/18/16Dynamic wavefront creation for processing units using a hybrid compactor
08/11/16Memory page access detection
08/11/16Memory configuration operations for a computing device
08/11/16Query operations for stacked-die memory device
08/04/16Exploiting limited context streams
07/07/16Location aware cryptography
06/30/16Nvram-aware data processing system
06/23/16Replica path timing adjustment and normalization for adaptive voltage and frequency scaling
06/23/16Techniques for changing management modes of multilevel memory hierarchy
06/23/16Load balancing at a graphics processing unit
06/16/16Batching modified blocks to the same dram page
06/16/16Traffic rate control for inter-class data migration in a multiclass memory system
06/16/16Address and control signal training
06/16/16Storage location assignment at a cluster compute server
06/16/16Methods and decoding video using re-ordered motion vector buffer
06/09/16Memory management in graphics and compute application programming interfaces
06/09/16Shader pipelines and hierarchical shader resources
06/02/16Memory persistence management control
05/26/16Reliable wear-leveling for non-volatile memory and method therefor
05/26/16Method and securing access to an integrated circuit
Social Network Patent Pack
05/19/16Processor and methods for remote scoped synchronization
05/19/16Efficient sparse matrix-vector multiplication on parallel processors
05/05/16Memory management for graphics processing unit workloads
05/05/16External data processing for a display device
05/05/16Memory system with region-specific memory access scheduling
04/28/16Power management
04/28/16Command replacement for communication at a processor
04/28/16Method and system for block scheduling control in a processor by remapping
04/28/16Coherency probe response accumulation
04/28/16Coherency probe with link or domain indicator
Patent Packs
04/14/16Hybrid block based compression
04/07/16Thermal-aware compiler for parallel instruction execution in processors
04/07/16Crystal oscillator circuit with reduced startup time
03/31/16Automatic source code generation for accelerated function calls
03/24/16Scheduling applications in processing devices based on predicted thermal impact
03/24/16Heterogeneous function unit dispatch in a graphics processing unit
03/24/16System and repurposing dead cache blocks
03/24/16Method for privileged mode based secure input mechanism
03/24/16Thermal aware data placement and compute dispatch in a memory system
03/17/16Power and performance management of asynchronous timing domains in a processing device
03/17/16Frequency configuration of asynchronous timing domains under power constraints
03/17/16Interface to expose interrupt times to hardware
03/17/16Predictive management of heterogeneous processing systems
03/17/16Method and efficient user-level io in a virtualized system
03/10/16Concurrently executing critical sections in program code in a processor
03/03/16Selecting a resource from a set of resources for performing an operation
03/03/16Routing direct memory access requests in a virtualized computing environment
02/25/16System and page-conscious gpu instruction
02/25/16Runtime for automatically load-balancing and synchronizing heterogeneous computer systems with scoped synchronization
02/25/16System and reverse inclusion in multilevel cache hierarchy
02/25/16Graphics processing method, system, and apparatus
02/18/16Data distribution among multiple managed memories
02/18/16Portable binary image format (pbif) for pre-compiled kernels
02/18/16Virtual memory mapping for improved dram page locality
02/11/16Tracking source availability for instructions in a scheduler instruction queue
02/11/16Moving data between caches in a heterogeneous processor system
02/11/16Cache bypassing policy based on prefetch streams
02/11/16Method and system for frame pacing
02/04/16Dynamic cache prefetching based on power gating and prefetching policies
02/04/16Dependence tracking by skipping in user mode queues
Patent Packs
01/28/16Technique to improve performance of memory copies and stores
01/28/16Measuring delay between signal edges of different signals using an undersampling clock
01/21/16Controlling energy consumption of an electronic device in response to availability of an energy source
01/14/16Method and apparatis for processor standby
01/07/16Devices and methods for interconnecting server nodes
12/31/15Calibrating a power supply using power supply monitors
12/31/15Integrated controller for training memory physical layer interface
12/31/15Memory physical layer interface logic for generating dynamic random access memory (dram) commands with programmable delays
12/31/15Video and image compression based on position of the image generating device
12/24/15Source synchronous bus clock gating system
12/24/15Decoupled entry and exit prediction for power gating
12/24/15Method and bezel mitigation with head tracking
12/24/15Dual-rail encoding
12/17/15Memory controller power management based on latency
12/17/15Memory heaps in a memory model for a unified computing system
12/17/15Wavefront resource virtualization
12/17/15Sidecar sram for high granularity in floor plan aspect ratio
12/10/15Power management across heterogeneous processing units
12/10/15Resizable and relocatable queue
12/10/15Translation lookaside buffer
Social Network Patent Pack
12/10/15Die-stacked device with partitioned multi-hop network
12/03/15System and adjusting performance based on thermal conditions within a processor
12/03/15Floating point multiply accumulator multi-precision mantissa aligner
11/26/15Channel rotating error correction code
11/26/15Locally asynchronous logic circuit and method therefor
11/19/15Hybrid determining performance levels based on thermal conditions within a processor
11/19/15Thin provisioning architecture for high seek-time devices
11/19/15Redundancy shader column repair
11/19/15Configuration of a cluster server using cellular automata
11/19/15Centralized distribution of configuration parameters for a cluster server
11/19/15Route mapping at individual nodes of a cluster server
11/19/15Apparatus to facilitate orthogonal coupling of a server sled with a server backplane
11/19/15Bimodal cooling in modular server system
11/12/15System and memory allocation in a multiclass memory system
11/05/15Memory array test logic
11/05/15Memory access monitor
11/05/15Switching a computer system from a high performance mode to a low power mode
10/22/15Methods and systems for mitigating memory drift
10/22/15Processor management based on application performance data
10/15/15Error-correction coding for hot-swapping semiconductor devices
Social Network Patent Pack
10/15/15Multi-level memory hierarchy
10/15/15Dynamic remapping of cache lines
10/08/15Method and system of sampling to automatically scale digital power estimates with frequency
10/08/15System and testing processor units using cache resident testing
10/01/15Chip debug during power gating events
10/01/15Dynamic power allocation based on phy power estimation
10/01/15Method and encoding erroneous data in an error correction code protected memory
10/01/15Stacked semiconductor chips packaging
09/24/15Using temperature margin to balance performance with power allocation
09/24/15Energy-aware boosting of processor operating points for limited duration workloads
09/17/15Mechanisms to save user/kernel copy for cross device communications
09/17/15Memory interface supporting both ecc and per-byte data masking
09/17/15Handling pointers in program code in a system that supports multiple address spaces
09/17/15Address-partitioned multi-class physical memory system
09/03/15Cryptographic protection of information in a processing system
08/27/15Adaptive voltage scaling
08/20/15Control of performance levels of different types of processors via a user interface
08/13/15Method and apparatus of adaptive application performance
08/13/15Thermally-aware process scheduling
08/06/15Memory and memory controller for high reliability operation and method
08/06/15Self-adjusting clock doubler and integrated circuit clock distribution system using same
07/30/15Mode-dependent access to embedded memory elements
07/30/15Region-based image decompression
07/23/15Low insertion delay clock doubler and integrated circuit clock distribution system using same
07/23/15Handling reads following transactional writes during transactions in a computing device
07/23/15Relocating infrequently-accessed dynamic random access memory (dram) data to non-volatile storage
07/23/15Connector adaptor to facilitate coupling of a mating card edge with a female card-edge connector
07/16/15Predicting power management state durations on a per-process basis
07/16/15Page migration in a 3d stacked hybrid memory
07/16/15Performing logical operations in a memory
Social Network Patent Pack
07/09/15Dedicated interface for coupling flash memory and dynamic random access memory
07/09/15Boosting the operating point of a processing device for new user activities
07/09/15Lever mechanism to facilitate edge coupling of circuit board
07/02/15Power gating based on cache dirtiness
07/02/15Partitionable memory interfaces
07/02/15Configuring processor policies based on predicted durations of active performance states
07/02/15Extensible i/o activity logs
07/02/15Circuit and data processor with headroom monitoring and method therefor
07/02/15Semiconductor device having high-k gate dielectric above an sti region
07/02/15Methods and systems of synchronizer selection
06/18/15Multiple-candidate motion estimation with advanced spatial filtering of differential motion vectors
06/11/15Voltage droop mitigation in 3d chip system
06/04/15Die-stacked memory device with reconfigurable logic
05/14/15Method and power-up detection for an electrical monitoring circuit
04/30/15Predictive periodic synchronization using phase-locked loop digital ratio updates
04/30/15Method and providing performance data over a debug bus
04/30/15Method and performing a bus lock and translation lookaside buffer invalidation
04/30/15Input/output memory map unit and northbridge
04/30/15Method and reformatting page table entries for cache storage
04/30/15Unified store queue
04/30/15Method and providing dedicated entries in a content addressable memory to facilitate real-time clients
04/30/15Processor and methods for floating point register aliasing
04/30/15Processor and methods for immediate handling and flag handling
04/30/15Ordering and bandwidth improvements for load and store unit and data cache
04/30/15Bandwidth increase in branch prediction unit and level 1 instruction cache
04/30/15Platform secure boot
04/30/15Using an idle duration history to configure an idle state of an entity in a computing device
04/30/15Dynamic and adaptive sleep state management
04/30/15Methods and software chaining of co-processor commands before submission to a command queue







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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