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Advanced Micro Devices Inc patents


Recent patent applications related to Advanced Micro Devices Inc. Advanced Micro Devices Inc is listed as an Agent/Assignee. Note: Advanced Micro Devices Inc may have other listings under different names/spellings. We're not affiliated with Advanced Micro Devices Inc, we're just tracking patents.

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 new patent  Identifying duplicate indices in an input index stream

Techniques for removing duplicate indices from an index stream are disclosed. The techniques involve dividing the indices into chunks. ... Advanced Micro Devices Inc

 new patent  Low power and low latency gpu coprocessor for persistent computing

Systems, apparatuses, and methods for implementing a graphics processing unit (gpu) coprocessor are disclosed. The gpu coprocessor includes a simd unit with the ability to self-schedule sub-wave procedures based on input data flow events. ... Advanced Micro Devices Inc

 new patent  Dynamic application of software data caching hints based on cache test regions

A processor applies a software hint policy to a portion of a cache based on access metrics for different test regions of the cache, wherein each test region applies a different software hint policy for data associated with cache entries in each region of the cache. One test region applies a software hint policy under which software hints are followed. ... Advanced Micro Devices Inc

 new patent  Dual mode local data store

A system and method for efficiently processing access requests for a shared resource are described. Each of many requestors are assigned to a partition of a shared resource. ... Advanced Micro Devices Inc

 new patent  Network-aware cache coherence protocol enhancement

A non-uniform memory access system includes several nodes that each have one or more processors, caches, local main memory, and a local bus that connects a node's processor(s) to its memory. The nodes are coupled to one another over a collection of point-to-point interconnects, thereby permitting processors in one node to access data stored in another node. ... Advanced Micro Devices Inc

 new patent  Bufferless communication for redundant multithreading using register permutation

Systems, apparatuses, and methods for implementing bufferless communication for redundant multithreading applications using register permutation are disclosed. In one embodiment, a system includes a parallel processing unit, a register file, and a scheduler. ... Advanced Micro Devices Inc

 new patent  Detecting buffer overflows in general-purpose gpu applications

A processing apparatus is provided that includes a plurality of memory regions each corresponding to a memory address and configured to store data associated with the corresponding memory address. The processing apparatus also includes an accelerated processing device in communication with the memory regions and configured to determine a request to allocate an initial memory buffer comprising a number of contiguous memory regions, create a new memory buffer comprising one or more additional memory regions adjacent to the contiguous memory regions of the initial memory buffer, assign one or more values to the one or more additional memory regions and detect a change to the one or more values at the one or more additional memory regions.. ... Advanced Micro Devices Inc

Identifying primitives in input index stream

Techniques for removing reset indices from, and identifying primitives in, an index stream that defines a set of primitives to be rendered, are disclosed. The index stream may be specified by an application program executing on the central processing unit. ... Advanced Micro Devices Inc

Method and system for yield operation supporting thread-like behavior

A method, system, and computer program product synchronize a group of workitems executing an instruction stream on a processor. The processor is yielded by a first workitem responsive to a synchronization instruction in the instruction stream. ... Advanced Micro Devices Inc

Region-based image decompression

A method and a non-transitory computer readable medium for decompressing an image including one or more regions are presented. A region of the image is selected to be decoded. ... Advanced Micro Devices Inc

Super single instruction multiple data (super-simd) for graphics processing unit (gpu) computing

A super single instruction, multiple data (simd) computing structure and a method of executing instructions in the super-simd is disclosed. The super-simd structure is capable of executing more than one instruction from a single or multiple thread and includes a plurality of vector general purpose registers (vgprs), a first arithmetic logic unit (alu), the first alu coupled to the plurality of vgprs, a second alu, the second alu coupled to the plurality of vgprs, and a destination cache (do$) that is coupled via bypass and forwarding logic to the first alu, the second alu and receiving an output of the first alu and the second alu. ... Advanced Micro Devices Inc

System and method for energy reduction based on history of reliability of a system

A system and method for managing operating parameters within a system for optimal power and reliability are described. A device includes a functional unit and a corresponding reliability evaluator. ... Advanced Micro Devices Inc

Processor support for hardware transactional memory

A processing core of a plurality of processing cores is configured to execute a speculative region of code a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.. ... Advanced Micro Devices Inc

Systems and methods for trusted cluster attestation

Systems, apparatuses, and methods for implementing trusted cluster attestation techniques are disclosed. A cluster includes multiple computing devices connected together and at least one cluster security module. ... Advanced Micro Devices Inc

04/19/18 / #20180108166

System and method for identifying graphics workloads for dynamic allocation of resources among gpu shaders

A gpu filters graphics workloads to identify candidates for profiling. In response to receiving a graphics workload for the first time, the gpu determines if the graphics workload would require the gpu shaders to use fewer resources than would be spent profiling and determining a resource allocation for subsequent receipts of the same or a similar graphics workload. ... Advanced Micro Devices Inc

04/19/18 / #20180108106

System and method for dynamically allocating resources among gpu shaders

A gpu stores resource allocations for a plurality of shaders to process processing a graphics workload, and applies those stored resource allocations when the same or a similar graphics workload is received subsequently by the gpu. In response to receiving a new graphics workload with a given unique identifier for the first time, the gpu employs a series of performance monitors to measure performance characteristics for processing the workload. ... Advanced Micro Devices Inc

04/19/18 / #20180107627

Gpu remote communication with triggered operations

Methods, devices, and systems for transmitting data over a computer communications network are disclosed. A queue of communications commands can be pre-generated using a central processing unit (cpu) and stored in a device memory of a network interface controller (nic). ... Advanced Micro Devices Inc

04/19/18 / #20180107598

Cluster-based migration in a multi-level memory hierarchy

Cluster manager functional blocks perform operations for migrating pages in portions in corresponding migration clusters. During operation, each cluster manager keeps an access record that includes information indicating accesses of pages in the portions in the corresponding migration cluster. ... Advanced Micro Devices Inc

04/12/18 / #20180102338

Circuit board with bridge chiplets

Various circuit boards and methods of fabricating and using the same are disclosed. In one aspect, a system is provided that has a circuit board with a pocket and a conductor layer. ... Advanced Micro Devices Inc

04/05/18 / #20180096938

Circuit board with multiple density regions

Various circuit boards and methods of fabricating and using the same are disclosed. In one aspect, a system is provided that includes a circuit board that has a first region including a first group of circuit structures adapted to interconnect two or more semiconductor chips and arranged according to a first design rule of a first density. ... Advanced Micro Devices Inc

03/29/18 / #20180088979

Virtual machine liveliness detection

A time stamp value associated with a virtual function of a guest virtual machine (vm) is periodically updated. One of a plurality of idle worker threads in a thread pool is assigned to periodically increment the time stamp value after initialization of an instance of the guest vm. ... Advanced Micro Devices Inc

03/29/18 / #20180088948

Efficient vectorization techniques for operands in non-sequential memory locations

Systems, apparatuses, and methods for utilizing efficient vectorization techniques for operands in non-sequential memory locations are disclosed. A system includes a vector processing unit (vpu) and one or more memory devices. ... Advanced Micro Devices Inc

03/29/18 / #20180088862

Multi-purpose register pages for read training

Dynamic random access memory (dram) chips in memory modules include multi-purpose registers (mprs) having pre-defined data patterns which, when selected, are accessed with read commands and output on data lines for performing read training. The mprs are accessed by issuing read commands to specific register addresses to request reads from specific mpr locations. ... Advanced Micro Devices Inc

03/29/18 / #20180088858

Scoped persistence barriers for non-volatile memories

A processing apparatus is provided that includes nvram and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the nvram before second data persists in the nvram. ... Advanced Micro Devices Inc

03/29/18 / #20180088649

On-chip power sequence validator and monitor

Systems, apparatuses, and methods for monitoring power rails during power sequences are disclosed. An apparatus includes one or more voltage regulators, a plurality of registers, and control logic. ... Advanced Micro Devices Inc

03/29/18 / #20180088606

Method and apparatus for temperature and voltage management control

A method and apparatus for managing processing power determine a supply voltage to supply to a processing unit, such as a central processing unit (cpu) or graphics processing unit (gpu), based on temperature inversion based voltage, frequency, temperature (vft) data. The temperature inversion based vft data includes supply voltages and corresponding operating temperatures that cause the processing unit's transistors to operate in a temperature inversion region. ... Advanced Micro Devices Inc

03/22/18 / #20180082470

Combined world-space pipeline shader stages

Improvements to graphics processing pipelines are disclosed. More specifically, the vertex shader stage, which performs vertex transformations, and the hull or geometry shader stages, are combined. ... Advanced Micro Devices Inc

03/22/18 / #20180082398

Adaptive filtering of packets in a graphics processing system

An adaptive list stores previously received hardware state information that has been used to configure a graphics processing core. One or more filters are configured to filter packets from a packet stream directed to the graphics processing core. ... Advanced Micro Devices Inc

03/22/18 / #20180081830

Hardware supervision of page tables

A processing system includes one or more processing units, a memory including a protected region, and a hardware security module. The hardware security module is configured to selectively modify a page table stored in the protected region of the memory in response to write or modify requests from the at least one processing unit. ... Advanced Micro Devices Inc

03/22/18 / #20180081829

Virtualized process isolation

Systems, apparatuses, and methods for implementing virtualized process isolation are disclosed. A system includes a kernel and multiple guest vms executing on the system's processing hardware. ... Advanced Micro Devices Inc

03/22/18 / #20180081818

Method and apparatus for masking and transmitting data

A method and apparatus for transmitting data includes determining whether to apply a mask to a cache line that includes a first type of data and a second type of data for transmission based upon a first criteria. The second type of data is filtered from the cache line, and the first type of data along with an identifier of the applied mask is transmitted. ... Advanced Micro Devices Inc

03/22/18 / #20180081810

Techniques for handling cache coherency traffic for contended semaphores

The techniques described herein improve cache traffic performance in the context of contended lock instructions. More specifically, each core maintains a lock address contention table that stores addresses corresponding to contended lock instructions. ... Advanced Micro Devices Inc

03/22/18 / #20180081715

Network interface controller-based scheduling of processing tasks in a distributed computing system

Techniques for scheduling processing tasks in a device having multiple computing elements are disclosed. A network interface controller of the device receives processing tasks, for execution on the computing elements, from a network that is external to the device. ... Advanced Micro Devices Inc

03/22/18 / #20180081625

Ring buffer design

A system and method for managing data in a ring buffer is disclosed. The system includes a legacy ring buffer functioning as an on-chip ring buffer, a supplemental buffer for storing data in the ring buffer, a preload ring buffer that is on-chip and capable of receiving preload data from the supplemental buffer, a write controller that determines where to write data that is write requested by a write client of the ring buffer, and a read controller that controls a return of data to a read client pursuant to a read request to the ring buffer.. ... Advanced Micro Devices Inc

03/22/18 / #20180081590

System and method for dynamically allocating memory at a memory controller

A processing system employs a memory module as a temporary write buffer to store write requests when a write buffer at a memory controller reaches a threshold capacity, and de-allocates the temporary write buffer when the write buffer capacity falls below the threshold. Upon receiving a write request, the memory controller stores the write request in a write buffer until the write request can be written to main memory. ... Advanced Micro Devices Inc

03/22/18 / #20180081585

Page migration acceleration using a two-level bloom filter on high bandwidth memory systems

Systems, apparatuses, and methods for accelerating page migration using a two-level bloom filter are disclosed. In one embodiment, a system includes a gpu and a cpu and a multi-level memory hierarchy. ... Advanced Micro Devices Inc

03/22/18 / #20180081583

Programming in-memory accelerators to improve the efficiency of datacenter operations

Systems, apparatuses, and methods for utilizing in-memory accelerators to perform data conversion operations are disclosed. A system includes one or more main processors coupled to one or more memory modules. ... Advanced Micro Devices Inc

03/22/18 / #20180081563

Method and apparatus for reducing memory access latency

Logic such as a memory controller writes primary data from an incoming write request as well as corresponding replicated primary data (which is a copy of the primary data) to one or more different memory banks of random access memory in response to determining a memory access contention condition for the address (including a range of addresses) corresponding to the incoming write request. When the memory bank containing the primary data is busy servicing a write request, such as to another row of memory in the bank, a read request for the primary data is serviced by reading the replicated primary data from the different memory bank of the random access memory to service the incoming read request.. ... Advanced Micro Devices Inc

03/22/18 / #20180081544

Lock address contention predictor

Techniques for selectively executing a lock instruction speculatively or non-speculatively based on lock address prediction and/or temporal lock prediction. Including methods an devices for locking an entry in a memory device. ... Advanced Micro Devices Inc

03/22/18 / #20180081541

Memory-sampling based migrating page cache

Systems, apparatuses, and methods for implementing a memory sampling based migrating page cache are disclosed. In one embodiment, a system includes one or more processors and a multi-level memory hierarchy. ... Advanced Micro Devices Inc

03/15/18 / #20180077228

Dynamic configuration of inter-chip and on-chip networks in cloud computing system

A server includes a plurality of nodes that are connected by a network that includes an on-chip network or an inter-chip network that connects the nodes. The server also includes a controller to configure the network based on relative priorities of workloads that are executing on the nodes. ... Advanced Micro Devices Inc

03/15/18 / #20180075574

Method and apparatus for compressing randomly accessed data

A method and apparatus for real time compressing randomly accessed data includes extracting a block of randomly accessed data from a memory hierarchy. One or more individual portions of the randomly accessed data are independently compressed in real time to create a lossless compressed image surface. ... Advanced Micro Devices Inc

03/15/18 / #20180074977

Speculative retirement of post-lock instructions

Techniques for improving execution of a lock instruction are provided herein. A lock instruction and younger instructions are allowed to speculatively retire prior to the store portion of the lock instruction committing its value to memory. ... Advanced Micro Devices Inc

03/15/18 / #20180074965

System and method for efficient pointer chasing

Described is a system and method for efficient pointer chasing in systems having a single memory node or a network of memory nodes. In particular, a pointer chasing command is sent along with a memory request by an issuing node to a memory node. ... Advanced Micro Devices Inc

03/15/18 / #20180074958

Light-weight cache coherence for data processors with limited data sharing

A data processing system includes a plurality of processors, local memories associated with a corresponding processor, and at least one inter-processor link in response to a first processor performing a load or store operation on an address of a corresponding local memory that is not currently in the local cache, a local cache allocates a first cache line and encodes a local state with the first cache line. In response to a load operation from an address of a remote memory that is not currently in the local cache, the local cache allocates a second cache line and encodes a remote state with the second cache line. ... Advanced Micro Devices Inc

03/15/18 / #20180074715

Dynamic adaptation of memory page management policy

Systems, apparatuses, and methods for determining preferred memory page management policies by software are disclosed. Software executing on one or more processing units generates a memory request. ... Advanced Micro Devices Inc

03/08/18 / #20180069767

Preserving quality of service constraints in heterogeneous processing systems

Techniques described herein improve processor performance in situations where a large number of system service requests are being received from other devices. More specifically, upon detecting that certain operating conditions that indicate a processor slowdown are present, the processor performs one or more system service adjustment techniques. ... Advanced Micro Devices Inc

03/08/18 / #20180067856

Systems and method for delayed cache utilization

A system for managing cache utilization includes a processor core, a lower-level cache, and a higher-level cache. In response to activating the higher-level cache, the system counts lower-level cache victims evicted from the lower-level cache. ... Advanced Micro Devices Inc

03/01/18 / #20180061124

Parallel micropolygon rasterizers

A parallel adaptable graphics rasterization system in which a primitive assembler includes a router to selectively route a primitive to a first rasterizer or one of a plurality of second rasterizers. The second rasterizers concurrently operate on different primitives and the primitive is selectively routed based on an area of the primitive. ... Advanced Micro Devices Inc

03/01/18 / #20180060257

Nondeterministic memory access requests to non-volatile memory

A memory module includes a memory, a cache to cache copies of information stored in the memory, and a controller. The controller is configured to access first data from the memory or the cache in response to receiving a read request from a processor. ... Advanced Micro Devices Inc

03/01/18 / #20180060124

Heterogeneous parallel primitives programming model

With the success of programming models such as opencl and cuda, heterogeneous computing platforms are becoming mainstream. However, these heterogeneous systems are low-level, not composable, and their behavior is often implementation defined even for standardized programming models. ... Advanced Micro Devices Inc

03/01/18 / #20180060074

Method and device for determining branch history for branch prediction

Disclosed are a method and a processing device directed to determining global branch history for branch prediction. The method includes shifting first bits of a branch signature into a current global branch history and performing a bitwise exclusive-or (xor) function on second bits of the branch signature and shifted bits of the current global branch history. ... Advanced Micro Devices Inc

03/01/18 / #20180060073

Branch target buffer compression

Techniques for improving branch target buffer (“btb”) operation. A compressed btb is included within a branch prediction unit along with an uncompressed btb. ... Advanced Micro Devices Inc

03/01/18 / #20180060039

Computer-based square root and division operations

Square root operations in a computer processor are disclosed. A first iteration for calculating partial results of a square root operation is performed in a larger number of cycles than remaining iterations. ... Advanced Micro Devices Inc

02/22/18 / #20180054223

Active equalizing negative resistance amplifier for bi-directional bandwidth extension

Systems, apparatuses, and methods for implementing a negative resistance circuit for bandwidth extension are disclosed. Within a feedback path of a differential signal path, capacitors are placed on the inputs and outputs of a fully differential amplifier connecting to the differential signal path. ... Advanced Micro Devices Inc

02/22/18 / #20180054188

Low power adaptive synchronizer

A circuit adapts to the occurrence of metastable states. The circuit inhibits passing of the metastable state to circuits that follow, by clock gating the output stage. ... Advanced Micro Devices Inc

02/22/18 / #20180054187

Self timed data sampler

A sampling circuit automatically resamples the data from another timing domain until the sampled data is represented correctly in the new domain by assuring that no metastable states exist. If a metastable state exists, a sampling signal recirculates through the sampling circuit until the metastable state no longer exists. ... Advanced Micro Devices Inc

02/22/18 / #20180052779

Data cache region prefetcher

A data cache region prefetcher creates a region when a data cache miss occurs. Each region includes a predetermined range of data lines proximate to each data cache miss and is tagged with an associated instruction pointer register (rip). ... Advanced Micro Devices Inc

02/22/18 / #20180052778

Increase cache associativity using hot set detection

A processing apparatus and a method of accessing data using cache hot set detection is provided that includes receiving a plurality of requests to access data in a cache. The cache includes a plurality of cache sets each including n number of cache lines. ... Advanced Micro Devices Inc

02/22/18 / #20180052770

Predictive multistage comparison for associative memory

A processing system includes a shadow tag memory, which stores a plurality of entries containing coherency information for the cachelines residing at the various levels of private caches. If a cache miss occurs at a private cache, or if coherency information for a cacheline requires updating, a probe is sent to the shadow tag memory maintained at the shared cache to determine whether the requested (or affected) cacheline is stored at another private cache. ... Advanced Micro Devices Inc

02/22/18 / #20180052631

Method and apparatus for compressing addresses

A method and apparatus of compressing addresses for transmission includes receiving a transaction at a first device from a source that includes a memory address request for a memory location on a second device. It is determined if a first part of the memory address is stored in a cache located on the first device. ... Advanced Micro Devices Inc

02/22/18 / #20180052613

Tracking stores and loads by bypassing load store units

A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. The system and method include storing data in one or more memory dependent architectural register numbers (mdarns), allocating the one or more mdarns to a memfile, writing the allocated one or more mdarns to a map file, wherein the map file contains a mdarn map to enable subsequent access to an entry in the memfile, upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the map file to identify an entry in the memfile and an associated store, and on a hit, providing the entry responsive to the load request from the one or more mdarns.. ... Advanced Micro Devices Inc

02/15/18 / #20180046583

Updating least-recently-used data for greater persistence of higher generality cache entries

Techniques for improving translation lookaside buffer (tlb) operation are disclosed. A particular entry of the tlb is to be updated with data associated with a large page size. ... Advanced Micro Devices Inc

02/15/18 / #20180046463

System and method for load and store queue allocations at address generation time

A system and method for load queue (ldq) and store queue (stq) entry allocations at address generation time that maintains age-order of instructions is described. In particular, writing ldq and stq entries are delayed until address generation time. ... Advanced Micro Devices Inc

02/08/18 / #20180039777

Mechanism for throttling untrusted interconnect agents

A host system-on-chip (soc) includes a network on chip (noc) for transmitting local traffic between internal blocks of the soc, an external processor link for receiving messages at the host soc from an untrusted device. A traffic controller in the host soc that is coupled with the external processor link monitors an amount of external traffic from the untrusted device over a set of one or more time intervals, detects a violation of a traffic policy based on the amount of external traffic, and in response to detecting the violation, reduces traffic in the noc resulting from the messages from the untrusted device.. ... Advanced Micro Devices Inc

02/08/18 / #20180039587

Network of memory modules with logarithmic access

A memory network includes a plurality of memory nodes each identifiable by an ordinal number m, and a set of links divided into n subsets of links, where each subset of links is identifiable by an ordinal number n. For each subset of the plurality of n subsets of links, each link in the subset connects two memory nodes that have ordinal numbers m differing by b(n-1), where b is a positive number. ... Advanced Micro Devices Inc

02/08/18 / #20180039531

Paired value comparison for redundant multi-threading operations

Techniques for performing redundant multi-threading (“rmt”) include the use of an rmt compare instruction by two program instances (“work-items”). The rmt compare instruction specifies a value from each work-item to be compared. ... Advanced Micro Devices Inc

02/01/18 / #20180033184

Primitive culling using automatically compiled compute shaders

Techniques for culling primitives are provided herein. The techniques involve automatic generation of shader programs to be executed by an accelerated processing device. ... Advanced Micro Devices Inc

02/01/18 / #20180032477

High performance inplace transpose operations

Systems, apparatuses, and methods for performing in-place matrix transpose operations are disclosed. Operations for transposing tiles of a matrix are scheduled in an order determined by moving diagonally through tiles of the matrix. ... Advanced Micro Devices Inc

02/01/18 / #20180032447

Controlling access to pages in a memory in a computing device

A table walker receives, from a requesting entity, a request to translate a first address into a second address associated with a page of memory. During a corresponding table walk, when a lock indicator in an entry in a reverse map table (rmt) for the page is set to mark the entry in the rmt as locked, the table walker halts processing the request and performs a remedial action. ... Advanced Micro Devices Inc

02/01/18 / #20180032443

Controlling access to pages in a memory in a computing device

The described embodiments perform a method for handling memory accesses by virtual machines in a computing device. The described embodiments include a reverse map table (rmt) and a separate guest accessed pages table (gapt) for each virtual machine. ... Advanced Micro Devices Inc

01/25/18 / #20180024938

Allocating physical pages to sparse data sets in virtual memory without page faulting

A processing system for reduction of a virtual memory page fault rate that includes a first memory to store a dataset, a second memory to store a subset of the dataset, and a processing unit. The processing unit is configured to receive a memory access request including a virtual address and determine whether the virtual address is mapped to a first physical page in the first memory and or a second physical page in the second memory. ... Advanced Micro Devices Inc

01/25/18 / #20180024935

Data block sizing for channels in a multi-channel high-bandwidth memory

The described embodiments include a computing device that caches data acquired from a main memory in a high-bandwidth memory (hbm), the computing device including channels for accessing data stored in corresponding portions of the hbm. During operation, the computing device sets each of the channels so that data blocks stored in the corresponding portions of the hbm include corresponding numbers of cache lines. ... Advanced Micro Devices Inc

01/25/18 / #20180024934

Scheduling independent and dependent operations for processing

A processor includes an operations scheduler to schedule execution of operations at, for example, a set of execution units or a cache of the processor. The operations scheduler periodically adds sets of operations to a tracking array, and further identifies when an operation in the tracked set is blocked from execution scheduling in response to, for example, identifying that the operation is dependent on another operation that has not completed execution. ... Advanced Micro Devices Inc

01/25/18 / #20180024931

Selecting cache transfer policy for prefetched data based on cache test regions

A processor applies a transfer policy to a portion of a cache based on access metrics for different test regions of the cache, wherein each test region applies a different transfer policy for data in cache entries that were stored in response to a prefetch requests but were not the subject of demand requests. One test region applies a transfer policy under which unused prefetches are transferred to a higher level cache in a cache hierarchy upon eviction from the test region of the cache. ... Advanced Micro Devices Inc

01/25/18 / #20180024837

Controlling the operating speed of stages of an asynchronous pipeline

An asynchronous pipeline includes a first stage and one or more second stages. A controller provides control signals to the first stage to indicate a modification to an operating speed of the first stage. ... Advanced Micro Devices Inc

01/18/18 / #20180019006

Memory controller with flexible address decoding

A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. ... Advanced Micro Devices Inc

01/18/18 / #20180018419

Integrated circuit implementing standard cells with metal layer segments extending out of cell boundary

A computer-implemented method of fabricating an integrated circuit structure includes selecting a first cell from a standard cell library, the first cell having a cell boundary and comprising a metal segment at a first metal track at a metal layer, the metal segment extending along a direction and terminating a specified distance beyond a first edge of the cell boundary. The method further includes placing the first cell at a first location of a physical layout for the integrated circuit structure. ... Advanced Micro Devices Inc

01/18/18 / #20180018291

Command arbitration for high speed memory interfaces

In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. ... Advanced Micro Devices Inc

01/18/18 / #20180018271

System and method for storing cache location information for cache entry transfer

A cache stores, along with data that is being transferred from a higher level cache to a lower level cache, information indicating the higher level cache location from which the data was transferred. Upon receiving a request for data that is stored at the location in the higher level cache, a cache controller stores the higher level cache location information in a status tag of the data. ... Advanced Micro Devices Inc

01/18/18 / #20180018266

Stride prefetcher for inconsistent strides

A processing system includes a cache and a prefetcher to prefetch lines from a memory into the cache. The prefetcher receives a memory access request to a first address in the memory and sets a stride length associated with an instruction that issued the memory access request to a length of a line in the cache. ... Advanced Micro Devices Inc

01/18/18 / #20180018264

System and method for identifying pendency of a memory access request at a cache entry

A processing system indicates the pendency of a memory access request for data at the cache entry that is assigned to store the data in response to the memory access request. While executing instructions, the processor issues requests for data to the cache most proximal to the processor. ... Advanced Micro Devices Inc

01/18/18 / #20180018242

Method and apparatus for providing distributed checkpointing

Methods and apparatus presented herein provide distributed checkpointing in a multi-node system, such as a network of servers in a data center. When checkpointing of application state data is needed in a node, the methods and apparatus determine whether checkpoint memory space is available in the node for checkpointing the application state data. ... Advanced Micro Devices Inc

01/18/18 / #20180018221

Ddr memory error recovery

In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. ... Advanced Micro Devices Inc

01/18/18 / #20180018133

Memory controller arbiter with streak and read/write transaction management

In one form, an apparatus includes a memory controller. The memory controller includes a command queue and an arbiter. ... Advanced Micro Devices Inc

01/18/18 / #20180018105

Memory controller with virtual controller mode

In one form, a memory controller has a memory channel controller including a command queue and an arbiter. The command queue stores memory access requests including a sub-channel number in a virtual controller mode. ... Advanced Micro Devices Inc

01/18/18 / #20180018104

Dynamic write latency for memory controller using data pattern extraction

Methods and apparatus of dynamically determining a variable reset latency time based on a data pattern of the data to be written into memory is disclosed. A memory controller determines a variable reset latency time for a plurality of memory cells depending on the bit values to be written into the plurality of memory cells in response to a write request having corresponding bit values. ... Advanced Micro Devices Inc

01/18/18 / #20180018009

Clock adjustment for voltage droop

A processor adjusts frequencies of one or more clock signals in response to a voltage droop at the processor. The processor generates at least one clock signal by generating a plurality of base clock signals, each of the base clock signals having a common frequency but a different phase. ... Advanced Micro Devices Inc

01/18/18 / #20180017988

Managing frequency changes of clock signals across different clock domains

A processor maintains a minimum setup time for data being transferred between clock domains, including maintaining the minimum setup time in response to a frequency change in a clock signal for at least one of the clock domains. The processor employs one or more control modules that monitor clock edges in each of the clock domains to ensure that data is not accessed by the receiving clock domain from a storage location until a minimum number of phases have elapsed in the transferring clock domain after the data has been written to the storage location. ... Advanced Micro Devices Inc

12/28/17 / #20170373955

Achieving balanced execution through runtime detection of performance variation

Systems, apparatuses, and methods for achieving balanced execution in a multi-node cluster through runtime detection of performance variation are described. During a training phase, performance counters and an amount of time spent waiting for synchronization is monitored for a plurality of tasks for each node of the multi-node cluster. ... Advanced Micro Devices Inc

12/28/17 / #20170372509

Culling objects from a 3-d graphics pipeline using hierarchical z buffers

A shader in a graphics pipeline accesses an object that represents a portion of a model of a scene in object space and one or more far-z values that indicate a furthest distance of a previously rendered portion of one or more tiles from a viewpoint used to render the scene on a screen. The one or more tiles overlap a bounding box of the object in a plane of the screen. ... Advanced Micro Devices Inc

12/28/17 / #20170371805

Method and apparatus for reducing tlb shootdown overheads in accelerator-based systems

A method and apparatus for reducing tlb shootdown operation overheads in accelerator-based computing systems is described. The disclosed method and apparatus may also be used in the areas of near-memory and in-memory computing, where near-memory or in-memory compute units may need to share a host cpu's virtual address space. ... Advanced Micro Devices Inc

12/28/17 / #20170371787

Contended lock request elision scheme

A system and method for network traffic management between multiple nodes are described. A computing system includes multiple nodes connected to one another. ... Advanced Micro Devices Inc

12/28/17 / #20170371786

Shadow tag memory to monitor state of cachelines at different cache level

A processing system includes a plurality of processor cores and a plurality of private caches. Each private cache is associated with a corresponding processor core of the plurality of processor cores and includes a corresponding first set of cachelines. ... Advanced Micro Devices Inc

12/28/17 / #20170371784

Targeted per-line operations for remote scope promotion

A processing system includes one or more first caches and one or more first lock tables associated with the one or more first caches. The processing system also includes one or more processing units that each include a plurality of compute units for concurrently executing work-groups of work items, a plurality of second caches associated with the plurality of compute units and configured in a hierarchy with the one or more first caches, and a plurality of second lock tables associated with the plurality of second caches. ... Advanced Micro Devices Inc

12/28/17 / #20170371761

Real-time performance tracking using dynamic compilation

Systems, apparatuses, and methods for performing real-time tracking of performance targets using dynamic compilation. A performance target is specified in a service level agreement. ... Advanced Micro Devices Inc

12/28/17 / #20170371743

System and method for protecting gpu memory instructions against faults

A system and method for protecting memory instructions against faults are described. The system and method include converting the slave instructions to dummy operations, modifying memory arbiter to issue up to n master and n slave global/shared memory instructions per cycle, sending master memory requests to memory system, using slave requests for error checking, entering master requests to the gm/lm fifo, storing slave requests in a register, and comparing the entered master requests with the stored slave requests.. ... Advanced Micro Devices Inc

12/28/17 / #20170371720

Multi-processor apparatus and method of detection and acceleration of lagging tasks

A method and processing apparatus for accelerating program processing is provided that includes a plurality of processors configured to process a plurality of tasks of a program and a controller. The controller is configured to determine, from the plurality of tasks being processed by the plurality of processors, a task being processed on a first processor to be a lagging task causing a delay in execution of one or more other tasks of the plurality of tasks. ... Advanced Micro Devices Inc

12/28/17 / #20170371719

Temperature-aware task scheduling and proactive power management

Systems, apparatuses, and methods for performing temperature-aware task scheduling and proactive power management. A soc includes a plurality of processing units and a task queue storing pending tasks. ... Advanced Micro Devices Inc

12/28/17 / #20170371694

Virtualization of a graphics processing unit for network applications

An accelerated processing unit includes a first processing unit configured to implement one or more virtual machines and a second processing unit configured to implement one or more acceleration modules. The one or more virtual machines are configured to provide information identifying a task or data to the one or more acceleration modules via first queues. ... Advanced Micro Devices Inc

12/28/17 / #20170371665

System and method for processing data in a computing system

Systems, apparatuses, and methods for adjusting group sizes to match a processor lane width are described. In early iterations of an algorithm, a processor partitions a dataset into groups of data points which are integer multiples of the processing lane width of the processor. ... Advanced Micro Devices Inc

12/28/17 / #20170371653

System and method for scheduling instructions in a multithread simd architecture with a fixed number of registers

A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (gpu) with a fixed number of registers. The method and apparatus include computing, via a processing unit (pu), a liveness-based register usage across all basic blocks in the shader program, computing, via the pu, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the pu, the scoring data based on number of waves of the plurality of registers, and computing, via the pu, the number of waves for execution for the plurality of registers.. ... Advanced Micro Devices Inc

12/28/17 / #20170371564

Method and apparatus for memory efficiency improvement by providing burst memory access control

Methods and apparatus monitor memory access activities of non-real-time processing engines to determine time intervals when the memory access activities are low. When such time intervals are found, the methods and apparatus perform burst memory access control for real-time processing engines by bursting data from a memory to a burst memory buffer, or from the burst memory buffer to the memory, to allow fast data access by the real-time processing engines.. ... Advanced Micro Devices Inc

12/28/17 / #20170371386

Control system and architecture for incorporating microelectromechanical (mem) switches in fluid-based cooling of 3d integrated circuits

A cooling system is provided for a 3d integrated circuit (ic) to deliver fluid in x, y, and z dimensions to interior regions of the ic as a means to regulate heat. An ic includes a microfluidic network of channels, at least one sensor and at least one microelectromechanical system (mems)-based device that is disposed within the network of channels and that is configured to regulate a flow of fluid within the network of channels. ... Advanced Micro Devices Inc

12/21/17 / #20170366412

Managing cluster-level performance variability without a centralized controller

Systems, apparatuses, and methods for managing cluster-level performance variability without a centralized controller are described. Each node of a multi-node cluster tracks a maximum and minimum progress across the plurality of nodes for a workload executed by the cluster. ... Advanced Micro Devices Inc

12/21/17 / #20170364332

Fingerprinting of redundant threads using compiler-inserted transformation code

A first processing element is configured to execute a first thread and one or more second processing elements are configured to execute one or more second threads that are redundant to the first thread. The first thread and the one or more second threads are to selectively bypass one or more comparisons of results of operations performed by the first thread and the one or more second threads depending on whether an event trigger for the comparison has occurred a configurable number of times since a previous comparison of previously encoded values of the results. ... Advanced Micro Devices Inc

12/21/17 / #20170364262

Write buffer design for high-latency memories

A memory system includes a write buffer, a main memory having a higher latency than the write buffer, and a memory controller. In response to a write request indicating first data for storing at a write address in the main memory, the memory controller adds a new write entry in the write buffer, where the new write entry includes the write address and the first data, and updates a pointer of a previous write entry in the write buffer to point to the new write entry. ... Advanced Micro Devices Inc

12/14/17 / #20170357596

Dynamically adjustable inclusion bias for inclusive caches

A first cache that includes a plurality of cache lines and is inclusive of a second cache. The plurality of cache lines are associated with a plurality of n-bit values. ... Advanced Micro Devices Inc

12/14/17 / #20170357588

Scaled set dueling for cache replacement policies

A processing system includes a cache that includes a cache lines that are partitioned into a first subset of the cache lines and a second subsets of the cache lines. The processing system also includes one or more counters that are associated with the second subsets of the cache lines. ... Advanced Micro Devices Inc

12/14/17 / #20170357587

Up/down prefetcher

In a processing system comprising a cache, a method includes monitoring demand cache accesses for a thread to maintain a first running count of a number of times demand cache accesses for the thread are directed to cachelines that are adjacent in a first direction to cachelines that are targets of a set of sampled cache accesses for the thread. In response to determining the first running count has exceeded a first threshold, the method further includes enabling a first prefetching mode in which a received demand cache access for the thread triggers a prefetch request for a cacheline adjacent in the first direction to a cacheline targeted by the received demand cache access.. ... Advanced Micro Devices Inc

12/14/17 / #20170357585

Setting cache entry age based on hints from another cache level

A processor replaces data at a first cache based on hints from a second cache, wherein the hints indicate information about the data that is not available to the first cache directly. When data at an entry is transferred from the first cache to the second cache, the first cache can provide an age hint to the second cache to indicate that the data should be assigned a higher or lower initial age relative to a nominal initial age. ... Advanced Micro Devices Inc

12/14/17 / #20170357583

Asynchronous cache flushing

Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device to a second memory in response to execution of a non-blocking flush instruction. Reactive flush logic in the computing system is configured to, in response to a memory request issued prior to completion of the proactive flush operation, interrupt the proactive flush operation and perform a reactive flush operation to flush requested data from the first memory to the second memory.. ... Advanced Micro Devices Inc

12/14/17 / #20170357509

Power management of instruction processors in a system-on-a-chip

A system-on-a-chip includes a plurality of instruction processors and a hardware block such as a system management unit. The hardware block accesses values of performance counters associated with the plurality of instruction processors and modifies one or more operating points of one or more of the plurality of instruction processors based on comparisons of the instruction arrival rates and the instruction service rates to achieve optimized system metrics.. ... Advanced Micro Devices Inc

12/14/17 / #20170357446

Cache entry replacement based on availability of entries at another cache

A processing system selects entries for eviction at one cache based at least in part on the validity status of corresponding entries at a different cache. The processing system includes a memory hierarchy having at least two caches, a higher level cache and a lower level cache. ... Advanced Micro Devices Inc

12/07/17 / #20170353397

Offloading execution of an application by a network connected device

A client device detects one or more servers to which an application can be offloaded. The client device receives information from the servers regarding their graphics processing unit (gpu) compute resources. ... Advanced Micro Devices Inc

12/07/17 / #20170351450

Self refresh state machine mop array

In one form, a memory controller includes a controller and a memory operation array. The controller has an input for receiving a power state change request signal and an output for providing memory operations. ... Advanced Micro Devices Inc

11/30/17 / #20170347498

Multi-compartment computing device with shared cooling device

Various computing devices, thermal solutions and enclosures are disclosed. In one aspect, a computing device enclosure is provided that includes a first compartment that has a first upper side and is adapted to house the computing device and a liquid cooling device. ... Advanced Micro Devices Inc

11/30/17 / #20170345512

Wear-limiting non-volatile memory

A non-volatile memory device having at least one non-volatile flash memory formatted with physical addresses to read and write data that is organized into blocks of data, wherein the blocks of data are organized into pages of data, and wherein the pages of data are organized into cells of data. The non-volatile memory device includes a non-volatile memory controller to direct read and write requests to the non-volatile flash memory for the storage and retrieval of data. ... Advanced Micro Devices Inc

11/30/17 / #20170345482

Fine granularity refresh

A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor is adapted to access at least one rank and has refresh logic. ... Advanced Micro Devices Inc

11/30/17 / #20170344490

Using multiple memory elements in an input-output memory management unit for performing virtual address to physical address translations

The described embodiments include an input-output memory management unit (iommu) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the iommu. ... Advanced Micro Devices Inc

11/30/17 / #20170344479

Cache coherence for processing in memory

A cache coherence bridge protocol provides an interface between a cache coherence protocol of a host processor and a cache coherence protocol of a processor-in-memory, thereby decoupling coherence mechanisms of the host processor and the processor-in-memory. The cache coherence bridge protocol requires limited change to existing host processor cache coherence protocols. ... Advanced Micro Devices Inc

11/30/17 / #20170344421

Integral post package repair

A post-package repair system includes a memory channel controller, a first error counter, a scrubber, and a data processor. The memory channel controller converts data access requests to corresponding memory accesses, and provides returned data to the host interface in response to responses received from a memory interface, wherein the responses comprise returned data and a plurality of error correcting code (ecc) bits. ... Advanced Micro Devices Inc

11/30/17 / #20170344309

Low power memory throttling

In one form, a data processing system includes a memory channel having a plurality of ranks, and a data processor. The data processor is coupled to the memory channel and is adapted to access each of the plurality of ranks. ... Advanced Micro Devices Inc

11/23/17 / #20170337136

Managing cache coherence using information in a page table

The described embodiments include a computing device with two or more types of processors and a memory that is shared between the two or more types of processors. The computing device performs operations for handling cache coherency between the two or more types of processors. ... Advanced Micro Devices Inc

10/26/17 / #20170308297

Object tagged memory monitoring method and processing apparatus

Described are a method and processing apparatus to tag and track objects related to memory allocation calls. An application or software adds a tag to a memory allocation call to enable object level tracking. ... Advanced Micro Devices Inc

10/12/17 / #20170295111

Methods and apparatus for processing in a network on chip (noc)

Methods and apparatus of delegating instructions or data from a cu to an noc node in a network on chip (noc) is disclosed. The noc node executes the delegated instructions or processes the delegated data. ... Advanced Micro Devices Inc

10/12/17 / #20170293560

Method and apparatus for performing memory prefetching

A method and apparatus for performing memory prefetching includes determining whether to initiate prefetching. Upon a determination to initiate prefetching, a first memory row is determined as a suitable prefetch candidate, and it is determined whether a particular set of one or more cachelines of the first memory row is to be prefetched.. ... Advanced Micro Devices Inc

10/12/17 / #20170293499

Message handler compiling and scheduling in heterogeneous system architectures

A receiving node in a computer system that includes a plurality of types of execution units receives an active message from a sending node. The receiving node compiles an intermediate language message handler corresponding to the active message into a machine instruction set architecture (isa) message handler and the receiver executes the isa message handler on a selected one of the execution units. ... Advanced Micro Devices Inc

10/12/17 / #20170293487

Flexible framework to support memory synchronization operations

A method of performing memory synchronization operations is provided that includes receiving, at a programmable cache controller in communication with one or more caches, an instruction in a first language to perform a memory synchronization operation of synchronizing a plurality of instruction sequences executing on a processor, mapping the received instruction in the first language to one or more selected cache operations in a second language executable by the cache controller and executing the one or more cache operations to perform the memory synchronization operation. The method further comprises receiving a second mapping that provides mapping instructions to map the received instruction to one or more other cache operations, mapping the received instruction to one or more other cache operations and executing the one or more other cache operations to perform the memory synchronization operation.. ... Advanced Micro Devices Inc

10/05/17 / #20170289078

Systems and methods of supporting parallel processor message-based communications

A method of message-based communication is provided which includes executing, on one or more accelerated processing units, a plurality of groups of work items, receiving a first message from a first group of work items of the plurality of groups of work items executing on the one or more accelerated processing units and storing the first message at a first segment of memory allocated to a second group of work items of the plurality of groups of work items executing on the accelerated processing unit.. . ... Advanced Micro Devices Inc

10/05/17 / #20170289057

Self-timed router with virtual channel control

Systems, apparatuses, and methods for implementing an asynchronous router with virtual channel (vc) control. The asynchronous router may support multiple vcs for connections to other routers. ... Advanced Micro Devices Inc

09/28/17 / #20170279703

Managing variations among nodes in parallel system frameworks

Systems, apparatuses, and methods for managing variations among nodes in parallel system frameworks. Sensor and performance data associated with the nodes of a multi-node cluster may be monitored to detect variations among the nodes. ... Advanced Micro Devices Inc

09/28/17 / #20170278213

Hierarchical register file at a graphics processing unit

A processor employs a hierarchical register file for a graphics processing unit (gpu). A top level of the hierarchical register file is stored at a local memory of the gpu (e.g., a memory on the same integrated circuit die as the gpu). ... Advanced Micro Devices Inc

09/28/17 / #20170277898

Key management for secure memory address spaces

A processor employs a security module to manage authentication and encryption keys for the processor. The security module can authenticate itself to other processing systems, such as processing systems providing software to be executed at the processor, can generate keys for encrypting address spaces for the provided software, and can securely import and export information at the encrypted address spaces to and from the processing system. ... Advanced Micro Devices Inc

09/28/17 / #20170277639

Adaptive extension of leases for entries in a translation lookaside buffer

The described embodiments include a computing device with two or more translation lookaside buffers (tlb). During operation, the computing device updates an entry in the tlb based on a virtual address to physical address translation and metadata from a page table entry that were acquired during a page table walk. ... Advanced Micro Devices Inc

09/28/17 / #20170277634

Using leases for entries in a translation lookaside buffer

The described embodiments include a computing device with two or more translation lookaside buffers (tlb) that performs operations for handling entries in the tlbs. During operation, the computing device maintains lease values for entries in the tlbs, the lease values representing times until leases for the entries expire, wherein a given entry in the tlb is invalid when the associated lease has expired. ... Advanced Micro Devices Inc

09/28/17 / #20170277441

Performance-aware and reliability-aware data placement for n-level heterogeneous memory systems

Techniques for selecting one of a plurality of heterogeneous memory units for placement of blocks of data (e.g., memory pages), based on both reliability and performance, are disclosed. A “cost” for each data block/memory unit combination is determined, based on the frequency of access of the data block, the latency of the memory unit, and, optionally, an architectural vulnerability factor (which represents the level of exposure of a particular memory data value to memory faults such as bit flips). ... Advanced Micro Devices Inc

09/21/17 / #20170269651

Method and apparatus for managing power in a thermal couple aware system

A method and apparatus for managing power in a thermal couple aware system includes determining a candidate configuration mapping based upon one or more criteria, the candidate configuration mapping being a mapping of performance for a candidate configuration of processor sockets in the thermal couple aware system. The candidate configuration mapping is evaluated by comparing the candidate configuration mapping to a stored configuration. ... Advanced Micro Devices Inc

09/14/17 / #20170262289

Method and system for yield operation supporting thread-like behavior

A method, system, and computer program product synchronize a group of workitems executing an instruction stream on a processor. The processor is yielded by a first workitem responsive to a synchronization instruction in the instruction stream. ... Advanced Micro Devices Inc

09/07/17 / #20170255397

Efficient implementation of queues and other data structures using processing near memory

Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. ... Advanced Micro Devices Inc

08/17/17 / #20170237658

Assigning variable length address identifiers to packets in a processing system

A controller assigns variable length addresses to addressable elements that are connected to a network. The variable length addresses are determined based on probabilities that packets are addressed to the corresponding addressable element. ... Advanced Micro Devices Inc

08/17/17 / #20170235700

Peripheral component

Embodiments of a peripheral component are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (ic) architecture. ... Advanced Micro Devices Inc

08/10/17 / #20170228321

Pinning objects in multi-level memory hierarchies

The described embodiments include a computer system having a multi-level memory hierarchy with two or more levels of memory, each level being one of two or more types of memory. The computer system handles storing objects in the multi-level memory hierarchy. ... Advanced Micro Devices Inc

08/10/17 / #20170228164

User-level instruction for memory locality determination

Systems and methods for efficiently processing data in a non-uniform memory access (numa) computing system are disclosed. A computing system includes multiple nodes connected in a numa configuration. ... Advanced Micro Devices Inc

08/03/17 / #20170220369

Hypervisor post-write notification of control and debug register updates

Systems, apparatuses, and methods for implementing hypervisor post-write notification of processor state register modifications. A write to a state register of the processor may be detected during guest execution. ... Advanced Micro Devices Inc

08/03/17 / #20170220346

Method and apparatus for inter-lane thread migration

Briefly, methods and apparatus to migrate a software thread from one wavefront executing on one execution unit to another wavefront executing on another execution unit whereby both execution units are associated with a compute unit of a processing device such as, for example, a gpu. The methods and apparatus may execute compiled dynamic thread migration swizzle buffer instructions that when executed allow access to a dynamic thread migration swizzle buffer that allows for the migration of register context information when migrating software threads. ... Advanced Micro Devices Inc

08/03/17 / #20170220022

Determining thermal time constants of processing systems

A processing system includes one or more processing units to perform operations and one or more sensors to measure a temperature concurrently with the one or more processing units performing the operations. The processing system also includes a controller to receive feedback indicating the temperature and to determine a peak temperature and a thermal time constant for heating of the processing system based on a comparison of the measured temperature to a first temperature that is predicted based on the peak temperature and a previously determined thermal time constant for heating. ... Advanced Micro Devices Inc

07/27/17 / #20170212851

Using processor types for processing interrupts in a computing device

The described embodiments include a computing device with multiple interrupt processors for processing interrupts. In the described embodiments, each of the multiple processors is classified as one or more processor types based on factors such as features and functionality of the processor, an operating environment of the processor, the characteristics of some or all of the available interrupts, etc. ... Advanced Micro Devices Inc

07/27/17 / #20170212845

Region migration cache

A memory access profiling and region migration technique makes allocation and replacement decisions for periodic migration of most frequently accessed regions of main memory to least frequently accessed regions of a region migration cache, in background operations. The technique improves performance in sparsely-used memory systems by migrating regions of main memory corresponding to the working footprint of main memory to the region migration cache. ... Advanced Micro Devices Inc

07/27/17 / #20170212837

Adaptive value range profiling for enhanced system performance

Enhanced adaptive profiling of ranges of values in a stream of events includes identifying a set of contiguous ranges of the values and corresponding access frequencies in the stream of events. The enhanced adaptive profiling uses a merge threshold value and a split threshold value. ... Advanced Micro Devices Inc








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