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Altera Corporation patents


Recent patent applications related to Altera Corporation. Altera Corporation is listed as an Agent/Assignee. Note: Altera Corporation may have other listings under different names/spellings. We're not affiliated with Altera Corporation, we're just tracking patents.

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Methods and dynamically configuring soft processors on an integrated circuit

An offloading engine integrated circuit that includes soft processors may be implemented using an aggregated profiler and a soft processor system generation tool. In particular, the aggregated profiler may generate a suggested configuration for soft processors within the integrated circuit. The soft processor system generation tool may use inputs based... Altera Corporation

Methods and managing application-specific power gating on multichip packages

A multichip package is provided that includes multiple integrated circuit (IC) dies mounted on a shared interposer. The IC dies may communicate with one another via corresponding input-output (IO) elements on the dies. The interposer may include a system-level power management block that is configured to coordinate low-power entry and... Altera Corporation

Circuitry for reducing leakage current in configuration memory

Integrated circuits may include dual mode memory cells. Dual mode memory cells may be operated in a lookup-table mode or a memory mode. A dual mode memory cell may have configuration ports for supporting a configuration operation and user ports for supporting a user mode operation. When performing configuration operations... Altera Corporation

Adaptive rate-matching first-in first-out (fifo) system

A control system controls First-In First-Out (FIFO) settings of a receiving system. The control system includes a FIFO settings controller that receives a first signal indicative of a first frequency of data received by the receiving system. The FIFO settings controller receives a second signal indicative of a second frequency... Altera Corporation

Integrated circuits with specialized processing blocks for performing floating-point fast fourier transforms and complex multiplication

Integrated circuits with specialized processing blocks are provided. A specialized processing block may include one real addition stage and one real multiplier stage. The multiplier stage may simultaneously feed its output to the addition stage and directly to an adjacent specialized processing block. The addition stage may also produce sum... Altera Corporation

Hybrid programmable many-core device with on-chip interconnect

The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may... Altera Corporation

Smart diagnosis of integrated circuits including ip cores with encrypted simulation models

The present embodiments relate to methods for simulating the behavior of an IP core that has an encrypted simulation model. The encrypted simulation model of the IP core may include a plurality of probes, which a debug option may activate selectively, if desired. The encrypted simulation model may collect data... Altera Corporation

Reset sequencing for reducing noise on a power distribution network

A computer-implemented method includes receiving a first circuit design for an integrated circuit device, determining when multiple power-drawing events are to occur at substantially the same time via one or more circuitry components of the integrated circuit device, which would have a disruptive effect on a power distribution network of... Altera Corporation

Fluid routing devices and methods for cooling integrated circuit packages

A fluid routing device includes a fluid inlet, first vertical channels, a horizontal channel, a second vertical channel, and a fluid outlet. The first vertical channels are open to the fluid inlet. The horizontal channel is open to each of the first vertical channels. The first vertical channels are oriented... Altera Corporation

Interconnection of an embedded die

Devices and methods related to an integrated circuit device are provided. The integrated circuit device includes a mother die and a daughter die, in which the daughter die embedded is in a substrate of the integrated circuit device. Micro bumps of the mother die and the daughter die interface together... Altera Corporation

Zero-offset sampling for clock duty cycle correction

Duty cycle sampling circuitry is disclosed that may generate offsets that cancel each other out, thereby improving the accuracy of duty cycle sampling of input clock signals based on sampling clock signals. The input clock input signals may be swapped, or the sampling clock signals may be swapped, or both... Altera Corporation

Methods and devices for reducing clock skew in bidirectional clock trees

The present disclosure provides systems and methods for improving operation of integrated circuit device including a logic region, which includes a plurality of logic gates that operate based at least in part on a clock signal to facilitate providing a target function, and a clock tree, which includes a clock... Altera Corporation

Methods and automated adaptation of transmitter equalizer tap settings

One embodiment relates to a method of automated adaptation of a transmitter equalizer. A multi-dimensional search space of tap settings for the transmitter equalizer is divided into multiple single-dimensional search spaces, each single-dimensional search space being associated with a single tap of the transmitter equalizer. The multiple single-dimensional search spaces... Altera Corporation

Distributed double-precision floating-point multiplication

The present embodiments relate to circuitry that efficiently performs double-precision floating-point multiplication operations, single-precision floating-point multiplication operations, and fixed-point multiplication operations. Such circuitry may be implemented in specialized processing blocks. If desired, each specialized processing block efficiently may perform a single-precision floating-point multiplication operation, and multiple specialized processing blocks may... Altera Corporation

Reduced floating-point precision arithmetic circuitry

The present embodiments relate to performing reduced-precision floating-point arithmetic operations using specialized processing blocks with higher-precision floating-point arithmetic circuitry. A specialized processing block may receive four floating-point numbers that represent two single-precision floating-point numbers, each separated into an LSB portion and an MSB portion, or four half-precision floating-point numbers. A... Altera Corporation

Variable precision floating-point adder and subtractor

An integrated circuit may include a floating-point adder that supports variable precisions. The floating-point adder may receive first and second inputs to be added, where the first and second inputs each have a mantissa and an exponent. The mantissa and exponent values may be split into a near path and... Altera Corporation

Integrated circuits having expandable processor memory

Integrated circuits may have programmable logic circuitry and hard-coded circuitry. The hard-coded circuitry may include data circuitry, a processor, and memory. As the hard-coded circuitry has a limited capacity, a portion of the programmable logic circuitry may be configured using configuration data to serve as expanded soft-coded memory for the... Altera Corporation

Methods and performing partial reconfiguration in a pipeline-based network topology

A programmable integrated circuit that can support partial reconfiguration is provided. The programmable integrated circuit may include multiple processing nodes that serve as accelerator blocks for an associated host processor that is communicating with the integrated circuit. The processing nodes may be connected in a hybrid shared-pipelined topology. Each pipeline... Altera Corporation

Pipelined interconnect circuitry having reset values holding capabilities

An integrated circuit may have pipelined interconnects that includes reset control circuitry, which provide desirable reset values to combinational logic. The pipelined interconnects may include multiple parallel input data paths coupled to the combinational logic. The reset control circuitry may include multiplexers coupled between the pipelined interconnects and the combinational... Altera Corporation

On-die capacitor (odc) structure

An on-die-capacitor structure includes a first capacitor and a second capacitor. The first capacitor may have first and second terminals. The first and second terminals are directly connected to first and second power supply rail structures, respectively. The first power supply rail structure is different from the second power supply... Altera Corporation

Techniques for power control of circuit blocks

An integrated circuit includes a circuit block, a storage circuit that stores a static power gating control signal, a logic gate circuit that receives a dynamic power gating control signal and the static power gating control signal from the storage circuit, and a transistor coupled between the circuit block and... Altera Corporation

Multi-rate transceiver circuitry

Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the... Altera Corporation

Memory controller architecture with improved memory scheduling efficiency

Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and controller circuitry may include a user logic interface, a memory controller, and a physical layer input-output interface. The user logic interface may be operated in a first clock domain. The... Altera Corporation

Fast filtering

Devices and methods for filtering data include calculating intermediate input values from input elements using a transformation function. The transformation function is based at least in part on a size of the filter and a number of filter outputs. Intermediate filter values are calculated from filter elements of the filter... Altera Corporation

Dot product based processing elements

Systems and methods for calculating a dot product using digital signal processing units that are organized into a dot product processing unit for dot product processing using multipliers and adders of the digital signal processing units.... Altera Corporation

Programmable logic device virtualization

A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area... Altera Corporation

Systems and methods for detecting and mitigating of programmable logic device tampering

Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during... Altera Corporation

Systems and methods for a low hold-time sequential input stage

Systems and methods for a low hold-time sequential input stage provide circuitry that includes a first latch element receiving a first input. The first latch element is connected to a first two-input multiplexer. The circuitry further includes a second latch element receiving a second input. The second latch element is... Altera Corporation

Scalable 2.5d interface architecture

Systems and methods for interface block. The interface block includes input/output modules distributed along the interface block and a mid-stack module interspersed within the input/output modules. The input/output modules include at least one data module and at least one command module. At least one of the input/output modules is shared... Altera Corporation

Systems and methods for authenticating firmware stored on an integrated circuit

The invention discloses a method of authenticating data stored in an integrated circuit. The method includes storing randomized data in the integrated circuit such that the randomized data occupies each address space of the memory circuit that is not occupied by the stored data. The method also includes generating a... Altera Corporation

Variable precision floating-point multiplier

Integrated circuits with specialized processing blocks are provided. The specialized processing blocks may include floating-point multiplier circuits that can be configured to support variable precision. A multiplier circuit may include a first carry-propagate adder (CPA), a second carry-propagate adder (CPA), and an associated rounding circuit. The first CPA may be... Altera Corporation

Voltage regulator with jitter control

A voltage regulator package includes a voltage regulator module that outputs a voltage signal of a particular voltage level through an output terminal is provided. The voltage regulator module may be switched on according to a periodic signal having a periodic signal frequency as a variable. The periodic signal frequency... Altera Corporation

Method and verifying structural correctness in retimed circuits

A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. Whether the retimed design is structurally correct is verified by performing register retiming on the retimed design.... Altera Corporation

Techniques for generating pulse-width modulation data

An integrated circuit includes a control circuit, a first-in first-out circuit, and a serializer circuit. The control circuit generates parallel pulse-width modulation data in first parallel pulse-width modulation signals. The first-in first-out circuit stores the parallel pulse-width modulation data indicated by the first parallel pulse-width modulation signals. The first-in first-out... Altera Corporation

Dynamic clock-data phase alignment in a source synchronous interface circuit

The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to... Altera Corporation

02/01/18 / #20180034748

Multi-function, multi-protocol fifo for high-speed communication

Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit... Altera Corporation

01/25/18 / #20180025100

Method and improving system operation by replacing components for performing division during design compilation

A method for designing a system on a target device includes identifying components in a netlist that perform a division operation. The netlist is modified during synthesis to utilize other components to compute a result of the division operation by performing a multiplication operation.... Altera Corporation

01/25/18 / #20180026638

Apparatus for configurable interface and associated methods

An field programmable gate array (FPGA) includes a circuit implemented using the FPGA fabric. The FPGA further includes another circuit implemented as hardened circuitry. The FPGA also includes a configurable interface circuit that is adapted to couple together the two circuits.... Altera Corporation

01/25/18 / #20180026642

Feedback control systems with pulse density signal processing capabilities

A feedback control system may include a feedback controller for controlling a plant using pulse density signals. The feedback controller may include a pulse density signal generator and a controller logic circuit. The pulse density signal generator may receive input command signals and generate signed or unsigned pulse density input... Altera Corporation

01/04/18 / #20180004878

Circuit design instrumentation for state visualization

An integrated circuit includes user storage circuits, a local control circuit, and scan storage circuits arranged in a scan chain. At least a portion of a design-under-test is implemented in a subset of the integrated circuit that comprises the user storage circuits. The local control circuit retrieves data stored in... Altera Corporation

01/04/18 / #20180006653

Integrated circuits with hybrid fixed/configurable clock networks

An integrated circuit with a clock distribution network is provided. The clock distribution network may include configurable clock routing paths linking a clock source to one or more clock tree roots and may also include fixed clock routing paths linking the clock tree roots to corresponding leaf nodes. Both the... Altera Corporation

01/04/18 / #20180006664

Methods and performing reed-solomon encoding by lagrangian polynomial fitting

An integrated circuit for implementing a Reed-Solomon encoder circuit is provided. The encoder circuit may include partial syndrome calculation circuitry and matrix multiplication circuitry. The partial syndrome calculation circuitry may receive a message and generate corresponding partial syndromes. The matrix multiplication circuitry may receive the partial syndromes and may compute... Altera Corporation

12/28/17 / #20170371594

Methods and smart memory interface

One embodiment relates to a memory structure that includes a bank group and a port emulation circuit module. The bank group includes a plurality of memory banks, each memory bank having one read port and one write port. The port emulation circuit module provides a group read/write port and a... Altera Corporation

12/28/17 / #20170371818

Method and data detection and event capture

One embodiment relates to a data detection and event capture circuit. Data comparator logic receives a monitored data word from a parallel data bus and generates a plurality of pattern detected signals. Any pattern detection logic receives the plurality of pattern detected signals and generates a plurality of any pattern... Altera Corporation

12/28/17 / #20170371836

Methods for specifying processor architectures for programmable integrated circuits

A programmable integrated circuit may include soft and hard logic for implementing a reduced instruction set computing (RISC) processor. Processor generator tools implemented on specialized computing equipment may be used to specify desired parameters for the processor architecture, including the data word size of one or more data paths, the... Altera Corporation

12/28/17 / #20170373675

Method and phase-aligned 2x frequency clock generation

One embodiment relates to a multiple-channel serializer circuit that includes a plurality of one-channel serializers. A one-channel serializer of the plurality of one-channel serializes includes a local 2× frequency clock generator with a non-divider structure. Other embodiments relate to methods of using a non-divider circuit to generate a local 2×... Altera Corporation

12/28/17 / #20170373690

Apparatus and methods for on-die temperature sensing to improve fpga performance

A field programmable gate array (FPGA) includes a temperature sensor array. The FPGA also includes a supply voltage modulation circuit. The supply voltage modulation circuit is coupled to the temperature sensor array.... Altera Corporation

12/21/17 / #20170365643

Parallel configured resistive memory elements

The present invention discloses a memory cell that includes at least two non-volatile resistive memory elements coupled in parallel. The non-volatile resistive memory elements are capable of existing in different resistive states such that each of the different resistive state represents a different data state. The non-volatile resistive memory elements... Altera Corporation

12/21/17 / #20170366174

Techniques for detecting and correcting errors on a ring oscillator

A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through... Altera Corporation

12/21/17 / #20170366186

Selectively disabled output

Circuits, methods, and apparatus are directed to an integrated circuit having a disabling element that can disable a reading of data from the circuit. Once the disabling element is set to not allow a reading of the data, the disabling element cannot be changed to allow a reading of the... Altera Corporation

12/21/17 / #20170366190

Phase-locked loops with electrical overstress protection circuitry

An integrated circuit with a phase-locked loop (PLL) is provided. The PLL may include a phase frequency detector, a charge pump, a source follower circuit, a variable oscillator, a frequency divider, and a control block. The phase frequency detector may be configured to align or lock a feedback clock signal... Altera Corporation

12/14/17 / #20170357606

Configuration via high speed serial link

Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode... Altera Corporation

12/14/17 / #20170359073

Supporting pseudo open drain input/output standards in a programmable logic device

Techniques and mechanisms allow a Programmable Logic Device (PLD) to support a pseudo open drain (POD) input/output (I/O) standard used in interface protocols such as fourth generation double data rate (DDR4). An OR gate with inputs including data and an inverted output enable from a user's design may be inserted... Altera Corporation

12/07/17 / #20170350937

Integrated circuit calibration system using general purpose processors

In one embodiment, an integrated circuit is disclosed. The integrated includes a general purpose processor, an interface circuit, and a calibration adapter circuit. The general purpose processor circuit generates calibration test inputs based on user instruction. The analog interface circuit may include a calibration bus circuit. The calibration bus circuit... Altera Corporation

12/07/17 / #20170352393

Emulated multiport memory element circuitry with exclusive-or based control circuitry

Integrated circuits may include memory element circuitry. The memory element circuitry may include multiple dual-port memory elements that are controlled to effectively form a multi-port memory element having multiple read and write ports. A respective bank of dual-port memory elements may be coupled to each write port. Write data may... Altera Corporation

12/07/17 / #20170353335

Low-skew channel bonding using phase-measuring fifo buffer

Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission... Altera Corporation

11/23/17 / #20170337318

Method and implementing soft constraints in tools used for designing programmable logic devices

A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.... Altera Corporation

11/23/17 / #20170339116

Method and secure provisioning of an integrated circuit device

A method of operating an integrated circuit may include generating a session key with a random number generator circuit. The session key may then be used to establish a secure communications channel between the integrated circuit and a remote server. The integrated circuit may be placed in a non-operational mode... Altera Corporation

11/16/17 / #20170328951

Embedded built-in self-test (bist) circuitry for digital signal processor (dsp) validation

Configured in this way, the LIFR and the MISR circuits of the DSP blocks are not implemented using soft logic and can therefore easily meet performance criteria.... Altera Corporation

11/16/17 / #20170331363

Current limited power converter circuits and methods

A power converter circuit regulates an output voltage of a power train circuit and controls the current in the power train circuit. A current sensor circuit measures a current in the power train circuit. A hysteretic comparison circuit compares the current in the power train circuit to positive and negative... Altera Corporation

11/09/17 / #20170322769

Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks

The present embodiments relate to circuitry that efficiently performs floating-point arithmetic operations and fixed-point arithmetic operations. Such circuitry may be implemented in specialized processing blocks. If desired, the specialized processing blocks may include configurable interconnect circuitry to support a variety of different use modes. For example, the specialized processing block... Altera Corporation

11/09/17 / #20170322775

Structures for lut-based arithmetic in plds

A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic... Altera Corporation

11/09/17 / #20170322813

Pipelined cascaded digital signal processing structures and methods

Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic... Altera Corporation

11/02/17 / #20170315781

Circuitry and methods for implementing galois-field reduction

Galois-field reduction circuitry for reducing a Galois-field expansion value, using an irreducible polynomial, includes a plurality of memories, each for storing a respective value derived from the irreducible polynomial and a respective combination of expansion bit values, wherein expansion bits of the expansion value address the plurality of memories to... Altera Corporation

11/02/17 / #20170316120

Method and implementing a system-level design tool for design planning and architecture exploration

A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.... Altera Corporation

Patent Packs
10/26/17 / #20170308721

Setting security features of programmable logic devices

Systems and methods are disclosed for allowing security features to be selectively enabled during device configuration. For example, a programmable integrated circuit device is provided that receives configuration data and security requirement data. Control circuitry compares enabled security features in the device against the security requirements, and can configure the... Altera Corporation

10/26/17 / #20170310340

Serial memory interface circuitry for programmable integrated circuits

A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of... Altera Corporation

10/19/17 / #20170300337

Pipelined cascaded digital signal processing structures and methods

Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic... Altera Corporation

10/19/17 / #20170300375

Transceiver parameter solution space visualization to reduce bit error rate

Techniques and mechanisms provide a solution space visualization of bit error rates (BER) for combinations of parameter settings of transceivers. Different types of visualizations may be generated.... Altera Corporation

10/12/17 / #20170293703

Safety features for high level design

Aspects of this disclosure relate generally to electronic design automation, and more specifically, to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. Some innovative aspects can be implemented in computer-readable media, systems and methods capable of accessing an algorithmic description representation of... Altera Corporation

10/12/17 / #20170294913

Method high-level programs with general control flow

A method of configuring a programmable integrated circuit device to implement control flow at a current basic block. A branch selector node within the current basic block is configured to receive at least one control signal, where each of the at least one control signal is associated with a respective... Altera Corporation

10/12/17 / #20170294914

Power gated lookup table circuitry

A programmable integrated circuit with lookup table circuitry is provided. The lookup table (LUT) circuitry may be formed using multiplexers. A multiplexer in the lookup table circuitry may be implemented using only tristate inverting circuits. Each tristate inverting circuit may include a first set of n-channel and p-channel transistors that... Altera Corporation

10/12/17 / #20170295015

Secure physically unclonable function (puf) error correction

The ECC processor may return information back to the secure subsystem, and the control circuitry may then obtain a corrected PUF response that matches the desired PUF response.... Altera Corporation

10/05/17 / #20170286582

Efficient integrated circuits configuration data mangement

Circuitry for efficient configuration data management is presented. The circuitry may include an encoding circuit that compares the configuration data of a circuit design with the base configuration data of a base circuit design. The encoding circuit may compress the difference between the configuration data and the base configuration data... Altera Corporation

10/05/17 / #20170286590

Method and performing register retiming in the presence of timing analysis exceptions

A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for... Altera Corporation

10/05/17 / #20170287543

Adaptive refresh scheduling for memory

The present disclosure provides for adaptive scheduling of memory refreshes. One embodiment relates to a method of adapting an initial refresh sequence. In this method, flow and blockage scores for each refresh sequence of a plurality of refresh sequences are obtained and stored in an array of scores. An initial... Altera Corporation

10/05/17 / #20170287872

Bumpless wafer level fan-out package

An integrated circuit package may include a first conductive pad on an interposer substrate, and a second conductive pad formed on a front surface of an integrated circuit die. The second conductive pad may directly contact the first conductive pad on the interposer substrate. The integrated circuit package may further... Altera Corporation

10/05/17 / #20170288648

Pulse-width modulation voltage identification interface

Systems, methods, and devices for voltage identification using a pulse-width modulation signal are provided. Such an integrated circuit device may include an input/output (I/O) interface and voltage identification (VID) circuitry. The VID circuitry may be coupled to the input/output interface. The voltage identification circuitry may generate a voltage identification signal... Altera Corporation

10/05/17 / #20170288671

Pipelined interconnect circuitry with double data rate interconnections

An integrated circuit may have pipelined interconnects that are configurable to operate in registered single data rate mode, registered double data rate mode, or in combinational mode. The pipelined interconnect may include routing multiplexers for selecting incoming signals, circuitry for serialization and de-serialization, and memory elements that are configurable to... Altera Corporation

09/21/17 / #20170270995

Circuits and methods for dqs autogating

In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second... Altera Corporation

Patent Packs
09/21/17 / #20170272073

Dynamic parameter operation of an fpga

Methods and systems for operating a programmable logic fabric including a dynamic parameter scaling controller that tracks an operating parameter that functions at multiple operating conditions by maintaining the operating parameter while cycling through a multiple operating conditions during a calibration mode using the calibration configuration for the programmable logic... Altera Corporation

09/14/17 / #20170262563

State visibility and manipulation in integrated circuits

In a first mode, a control circuit may implement a circuit design with storage circuits in an integrated circuit by programming configuration memory bits via configuration resources. The storage circuits may be accessed for read and write operations during the execution of the circuit design implementation with the integrated circuit.... Altera Corporation

09/14/17 / #20170264283

Techniques for enabling and disabling transistor legs in an output driver circuit

An output driver circuit includes a control circuit and first and second transistor legs that are coupled to an output pad. Each of the first and second transistor legs includes a pull-up transistor and a pull-down transistor. The control circuit is coupled to the first and second transistor legs. The... Altera Corporation

09/07/17 / #20170257222

Techniques for protecting security features of integrated circuits

An integrated circuit includes a control circuit, a one-time programmable circuit, and a security feature. The control circuit determines if the one-time programmable circuit is programmed in response to a request by a user of the integrated circuit to access the security feature. The control circuit generates a signal to... Altera Corporation

09/07/17 / #20170257369

Flexible feature enabling integrated circuit and methods to operate the integrated circuit

A method for enabling a circuit feature on an integrated circuit device having inactive circuit features includes a step to receive an encrypted message and a signed digital signature from a server using an input/output (I/O) terminal within the integrated circuit device. The method also includes a step to decrypt... Altera Corporation

08/31/17 / #20170249409

Emulation of synchronous pipeline registers in integrated circuits with asynchronous interconnection resources

Integrated circuits may include synchronous nodes and asynchronous routing elements coupled between the synchronous nodes. A synchronous design implemented in such an integrated circuit may identify a register chain having a source register, a destination register, and intermediate registers. A virtual register may be created for each of the intermediate... Altera Corporation

08/31/17 / #20170250155

Multi-access memory system and a method to manufacture the system

A multiple memory access system is disclosed. The system includes a first die disposed on a package substrate. A second die is stacked above the first die. The first die, the second die and the package substrate form a first package. An IC is placed within a close proximity of... Altera Corporation

08/31/17 / #20170250681

Techniques for detecting and correcting errors on a ring oscillator

A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through... Altera Corporation

08/31/17 / #20170250713

Methods and performing reed-solomon encoding

The present embodiments relate to Reed-Solomon encoding, and to circuitry for performing such encoding, particularly in an integrated circuit. A Reed-Solomon encoder circuit may receive a message with data symbols and compute a partial syndrome vector by multiplying the data symbols with a first matrix. The Reed-Solomon encoder circuit may... Altera Corporation

08/24/17 / #20170244411

Apparatus for flexible electronic interfaces and associated methods

A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a... Altera Corporation

08/24/17 / #20170244413

Hybrid architecture for signal processing and signal processing accelerator

Systems and methods for configuring circuitry for use with a field programmable gate array (FPGA) are disclosed. The circuitry includes an array of signal processing accelerators (SPAs) and an array of network nodes. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of... Altera Corporation

08/17/17 / #20170237433

Circuits and methods for impedance calibration

A driver circuit drives data to an output based on an input data signal in a transmission mode. The driver circuit includes transistors. A comparator generates a comparison output in a calibration mode based on a reference signal and a signal at the output of the driver circuit. A calibration... Altera Corporation

08/10/17 / #20170230209

High-speed serial data signal receiver circuitry

Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for... Altera Corporation

08/03/17 / #20170221537

High speed fpga boot-up through concurrent multi-frame configuration scheme

Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated... Altera Corporation

08/03/17 / #20170222651

Transformable logic and routing structures for datapath optimization

Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions may include lookup table (LUT) circuitry driven using vectored multiplexing circuits. The vectored multiplexing circuits may include a first multiplexer stage controlled by common configuration... Altera Corporation

07/27/17 / #20170214557

Digital equalizer adaptation using on-die instrument

Systems and methods are provided for adjusting gain of a receiver. Adaptation circuitry is operable to identify, based on a matrix representation of a receiver's output generated from horizontal and vertical sweeps of the receiver's output, an eye opening of the receiver's output. The adaptation circuitry is also operable to... Altera Corporation

07/20/17 / #20170206176

Integrated circuit device with embedded programmable logic

Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the... Altera Corporation

07/13/17 / #20170200484

Programmable integrated circuits with in-operation reconfiguration capability

Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but... Altera Corporation

07/13/17 / #20170201256

Power gated lookup table circuitry

A programmable integrated circuit with lookup table circuitry is provided. The lookup table (LUT) circuitry may be formed using multiplexers. A multiplexer in the lookup table circuitry may be implemented using only tristate inverting circuits. Each tristate inverting circuit may include a first set of n-channel and p-channel transistors that... Altera Corporation

07/06/17 / #20170194964

Programmable routing performance, power, and area by recovering aging in routing pass gates

Transistors degrade when subjected to voltage stress. Methods are described for reducing this aging problem by applying a reverse voltage to the gates of the circuit on an intermittent or periodic basis. By applying such a voltage for a brief period of time such as one second, the aging process... Altera Corporation

06/01/17 / #20170154951

Scalable fixed-footprint capacitor structure

In one embodiment, a capacitor structure includes a substrate, a dielectric stack, a first conductor segment, a second conductor segment and a shielding conductor segment. The dielectric stack is formed on the substrate. A first layer of the dielectric stack includes a plurality of conductor segments routed only in a... Altera Corporation

06/01/17 / #20170155529

Clock data recovery circuitry associated with programmable logic device circuitry

A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated... Altera Corporation








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