RealTimeTouch.com RealTimeTouch.com Patent US9639150 RealTimeTouch.com message RealTimeTouch.com RealTimeTouch.com



new TOP 200 Companies filing patents this week

new Companies with the Most Patent Filings (2010+)




RealTimeTouch.com RealTimeTouch.com Patent US9639150 RealTimeTouch.com message RealTimeTouch.com RealTimeTouch.com

Similar
Filing Names

Altera Corporation
Altera Corporation_20100114
Altera Corporation_20131212
Altera Corporation_20100128
  

Altera Corporation patents

Recent patent applications related to Altera Corporation. Altera Corporation is listed as an Agent/Assignee. Note: Altera Corporation may have other listings under different names/spellings. We're not affiliated with Altera Corporation, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "A" | Altera Corporation-related inventors




Date Altera Corporation patents (updated weekly) - BOOKMARK this page
06/01/17Scalable fixed-footprint capacitor structure
06/01/17Clock data recovery circuitry associated with programmable logic device circuitry
05/25/17Embedded memory blocks with adjustable memory boundaries
05/11/17Integrated circuit package with enhanced cooling structure
05/11/172.5d electronic package
04/27/17Methods and performing product series operations in multiplier accumulator blocks
04/27/17Integrated circuit packages with detachable interconnect structures
04/27/17Systems and methods for configuring an sopc without a need to use an external memory
04/13/17State visibility and manipulation in integrated circuits
04/13/17Method and designing and implementing a convolution neural net accelerator
04/13/17Method and implementing layers on a convolutional neural network accelerator
04/06/17Methods and sequencing multiply-accumulate operations
04/06/17Efficient virtual i/o address translation
04/06/17Control block size reduction through ip migration in an integrated circuit device
04/06/17Programmable logic device virtualization
03/30/17Multi-level signaling for on-package chip-to-chip interconnect through silicon bridge
03/23/17Systems and methods for particle detection and error correction in an integrated circuit
03/23/17Tranmission line bridge interconnects
03/16/17Asymmetric power flow controller for a power converter and operating the same
03/09/17Distributed multi-die protocol application interface
03/09/17Incremental register retiming of an integrated circuit design
03/09/17Method and performing parallel routing using a multi-threaded routing procedure
03/02/17Efficient integrated circuits configuration data management
03/02/17Systems and methods for multiport to multiport cryptography
02/16/17Application-based dynamic heterogeneous many-core systems and methods
02/16/17Method and implementing a system-level design tool for design planning and architecture exploration
02/09/17Programmable logic device with integrated network-on-chip
01/26/17Hybrid programmable many-core device with on-chip interconnect
01/05/17Programmable high-speed i/o interface
01/05/17Programmable high-speed i/o interface
12/29/16Channel sizing for inter-kernel communication
12/29/16Methods and embedding an error correction code in storage circuits
12/22/16Method and utilizing estimations for register retiming in a design compilation flow
12/22/16Apparatus for improving power consumption of communication circuitry and associated methods
12/22/16Circuitry and decomposable decoder
12/22/16Techniques for variable forward error correction
12/22/16Phase detection in an analog clock data recovery circuit with decision feedback equalization
12/15/16Mixed redundancy scheme for inter-die interconnects in a multichip package
12/15/16Techniques for providing data rate changes
12/08/16Methods for performing register retiming operations into synchronization regions interposed between circuits associated with different clock domains
12/08/16Integrated circuits with embedded double-clocked components
12/08/16Hardware programmable device with integrated search engine
12/08/16N-well/p-well strap structures
12/01/16Configuring a programmable device using high-level language
12/01/16Behavioral simulation model for clock-data recovery phase-locked loop
12/01/16Methods and probing signals from a circuit after register retiming
12/01/16On-die capacitor (odc) structure
12/01/16Methods and configuring and reconfiguring a partial reconfiguration region
11/24/16Pipelined cascaded digital signal processing structures and methods
11/24/16Resource-saving circuit structures for deeply pipelined systolic finite impulse response filters
11/24/16Routing and programming for resistive switch arrays
11/17/16Silicon-glass hybrid interposer circuitry
11/03/16Network functions virtualization platforms with function chaining capabilities
11/03/16Implementing integrated circuit designs using depopulation and repopulation operations
10/27/16Circuitry and methods for implementing galois-field reduction
10/27/16Flexible physical function and virtual function mapping
10/20/16High speed fpga boot-up through concurrent multi-frame configuration scheme
10/20/16Methods for packaging integrated circuits
10/20/16Asymmetric power flow controller for a power converter and operating the same
10/20/16Digital equalizer adaptation using on-die instrument
10/06/16Floating-point adder circuitry
10/06/16Methods and embedding an error correction code in memory cells
09/29/16Combined adder and pre-adder for high-radix multiplier circuit
09/29/16Method and implementing periphery devices on a programmable circuit using partial reconfiguration
09/22/16Configurable multi-lane scrambler for flexible protocol support
Patent Packs
09/15/16Method and placing and routing partial reconfiguration modules
09/15/16Self-stuffing multi-clock fifo requiring no synchronizers
09/08/16Apparatus for source-synchronous information transfer and associated methods
09/01/16Methods and two-dimensional block bit-stream compression and decompression
09/01/16Packaged integrated circuit including a switch-mode regulator and forming the same
08/25/16Security ram block with multiple partitions
08/18/16Clocking for pipelined routing
08/18/16Integrated circuit packages with dual-sided stacking structure
08/11/16Integrated circuits with asymmetric and stacked transistors
08/04/16Methods and reducing power consumption in memory circuitry by controlling precharge duration
06/09/16Methods and testing auxiliary components in a multichip package
06/09/16Multi-rate transceiver circuitry
05/12/16Circuits and methods for dqs autogating
04/28/16Methods and automatic fault detection
04/28/16Systems and methods for maintaining memory access coherency in embedded memory blocks
Patent Packs
04/07/16Scalable 2.5d interface architecture
04/07/16Integrated circuit device configuration methods adapted to account for retiming
03/24/16Operational time extension
02/18/16Programmable circuit having multiple sectors
02/11/16Routing and programming for resistive switch arrays
01/28/16Runtime loading of configuration data in a configurable ic
12/31/15Multiple plane network-on-chip with master/slave inter-relationships
12/03/15Non-intrusive monitoring and control of integrated circuits
12/03/15Accelerator architecture on a programmable platform
11/26/15Method and circuit for scalable cross point switching using 3-d die stacking
11/12/15Optimizing ic performance using sequential timing
11/12/15System and using fabric-graph flow to determine resource costs
11/12/15Sequential timing using level-sensitive clocked elements to optimize ic performance
11/12/15Identifying the cause of timing failure of an ic design using sequential timing
11/12/15User registers implemented with routing circuits in a configurable ic
11/05/15Integrated circuits with asymmetric and stacked transistors
10/15/15System reset controller replacing individual asynchronous resets
10/08/15Multi-rate transceiver circuitry
10/01/15Integrated current replicator and operating the same
10/01/15Apparatus and methods for determining latency of a network port
09/17/15Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
08/20/15Silicon-glass hybrid interposer circuitry
08/20/15Stability-enhanced physically unclonable function circuitry
08/13/15Methods for packaging integrated circuits
07/30/15Configuration bit architecture for programmable integrated circuit device
07/23/15Deterministic fifo buffer
07/23/15High performance finfet
07/23/15Digital equalizer adaptation using on-die instrument
07/16/15Semiconductor device having mirror-symmetric terminals and methods of forming the same
07/16/15Module having mirror-symmetric terminals and methods of forming the same
Social Network Patent Pack
06/25/15High-speed serial data signal receiver circuitry
06/18/15Three electrode circuit element
06/04/15Method and performing parallel routing using a multi-threaded routing procedure
05/28/15Integrated circuit with a high-speed debug access port
05/14/15Clocking for pipelined routing
05/14/15Apparatus and methods for optimization of integrated circuits
05/07/15Configurable multi-lane scrambler for flexible protocol support
04/30/15Integrated circuit device with embedded programmable logic
04/30/15Methods and tools for designing integrated circuits with auto-pipelining capabilities
04/30/15Configuring a programmable device using high-level language
Patent Packs
04/23/15Circuitry and techniques for updating configuration data in an integrated circuit
03/26/15Hybrid architecture for signal processing
03/12/15Regulator circuitry capable of tracking reference voltages
03/05/15Methods and structures for handling integrated circuits
03/05/15Floating-point adder circuitry
02/19/15Metastability prediction and avoidance in memory arbitration circuitry
02/05/15Efficient complex multiplication and fast fourier transform (fft) implementation on the manarray architecture
02/05/15Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
01/29/15Error resilient packaged components
01/29/15Processors operable to allow flexible instruction alignment
01/29/15Cache debug system for programmable circuits
01/29/15Integrated circuit device configuration methods adapted to account for retiming
01/29/15Method and securing configuration scan chains of a programmable device
01/22/15Apparatus and methods for time-multiplex field-programmable gate arrays
01/15/15Configuration via high speed serial link
01/01/15Central alignment circutry for high-speed serial receiver circuits
12/25/14Integrated circuits with on-die decoupling capacitors
12/25/14Method and implementing a system-level design tool for design planning and architecture exploration
12/18/14Multiple-voltage programmable logic fabric
12/18/14Programmable high-speed voltage-mode differential driver
12/18/14Bridge circuitry for communications with dynamically reconfigurable circuits
12/04/14Adaptive video reference frame compression with control elements
12/04/14Data encoding for attenuating image encoders
12/04/14Cache memory controller for accelerated data transfer
12/04/14Systems and methods for intermediate message authentication in a switched-path network
10/23/14Methods and motion search refinement in a simd array processor
10/09/14Efficient 2d adaptive noise thresholding for video processing
09/18/14Apparatus for electronic assembly with improved interconnect and associated methods
09/18/14Methods to achieve accurate time stamp in ieee 1588 for system with fec encoder
09/18/14Digital equalizer adaptation using on-die instrument
Patent Packs
09/18/14Apparatus for improved communication and associated methods
09/18/14Hybrid programmable many-core device with on-chip interconnect
09/11/14Sub-rate mapping for lowest-order optical data unit
09/11/14Apparatus and methods for power management in integrated circuits
08/28/14Heat spreading in molded semiconductor packages
08/28/14Heat pipe in overmolded flip chip package
08/28/14Memory array with redundant bits and memory element voting circuits
08/28/14Configuring a programmable logic device using a configuration bit stream without phantom bits
08/21/14Methods and scalable array processor interrupt detection and response
08/21/14Method and placing and routing partial reconfiguration modules
08/14/14Parallel decomposition of reed solomon umbrella codes
08/07/14Hardened programmable devices
08/07/14Techniques for alignment of parallel signals
08/07/14Apparatus and methods for communicating with programmable devices
08/07/14Method and performing parallel routing using a multi-threaded routing procedure
07/31/14Integrated circuit package with active interposer
07/31/14Bypassable clocked storage circuitry for dynamic voltage-frequency scaling
07/31/14Pld architecture for flexible placement of ip function blocks
07/31/14Adaptable datapath for a digital processing system
07/17/14Metal-programmable integrated circuits
Social Network Patent Pack
07/17/14Methods and aligning clock signals on an integrated circuit
07/17/14Systems and methods for detecting and mitigating programmable logic device tampering
07/03/143d built-in self-test scheme for 3d assembly defect detection
07/03/14Method and system for operating a communication circuit configurable to support one or more data rates
07/03/14Partitioning designs to facilitate certification
06/26/14Integrated circuit device with stitched interposer
06/26/14Heterogeneous high-speed serial interface system architecture
06/26/14System and scheduling and arbitrating events in computing and networking
06/19/14Memory elements with stacked pull-up devices
06/19/14Apparatus and methods for equalizer adaptation
06/19/14Methods and storing expanded width instructions in a vliw memory for deferred execution
06/19/14Processors and compiling methods for processors
06/12/14Antenna diode circuitry and manufacture
06/05/14Method and translating graphical symbols into query keywords
05/29/14Memory interface circuitry with improved timing margins
05/29/14Apparatus for automatically configured interface and associated methods
05/22/14Bidirectional wavelength cross connect architectures using wavelength routing elements
05/15/14Apparatus and methods for adaptive receiver delay equalization
05/15/14Methods for testing network circuitry
05/08/14Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device
Social Network Patent Pack
05/08/14Programmable logic device with integrated network-on-chip
05/01/14Techniques and circuitry for configuring and calibrating an integrated circuit
05/01/14Apparatus for improved encoding and associated methods
05/01/14Apparatus for improved encoding and associated methods
05/01/14Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
04/24/14Methods and building bus interconnection networks using programmable interconnection resources
04/17/14Simulation tool for high-speed communications links
04/10/14Side stack interconnection for integrated circuits and the like
04/10/14Method for finding starting bit of reference frames for an alternating-parity reference channel
04/10/143d memory based address generator
04/10/14Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
03/27/14Memory elements with relay devices
03/27/14Method and securing programming data of a programmable device
03/20/14Clock signal networks for structured asic devices
03/20/14Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry
03/13/14Methods and providing bit-reversal and multicast functions utilizing dma controller
03/13/14Methods and adapting pipeline stage latency based on instruction type
02/20/14Shielding structure for transmission lines
02/20/14Multiple data rate interface architecture
02/13/14Reconfigurable logic block
02/13/14Method and implementing soft constraints in tools used for designing programmable logic devices
02/06/14Techniques for aligning and reducing skew in serial data signals
02/06/14Techniques for varying a periodic signal based on changes in a data rate
01/16/14Apparatus and methods for communicating with programmable devices
01/16/14Methods and matrix decompositions in programmable logic devices
01/09/14Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits
12/26/13Methods and providing a scalable deblocking filtering assist function within an array processor
12/26/13Integrated circuit compilation
12/26/13Opencl compilation
12/12/13Integrated circuits with dual-edge clocking
Social Network Patent Pack
12/12/13Apparatus for using metastability-hardened storage circuits in logic devices and associated methods
12/12/13Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry
12/05/13Apparatus and adaptive multimedia reception and transmission in communication environments
11/28/13Application-specific integrated circuit equivalents of programmable logic and associated methods
11/28/13Method and performing parallel routing using a multi-threaded routing procedure
11/21/13Device with logic circuitry supporting quaternary addition
11/14/13Apparatus, configuration of adaptive integrated circuitry having fixed, application specific computational elements
10/24/13Methods and attaching application specific functions within an array processor
10/24/13Methods and scalable array processor interrupt detection and response
10/03/13Power management of components having clock processing circuits
10/03/13Method and implementing periphery devices on a programmable circuit using partial reconfiguration
08/29/13Methods and automatic fault detection
08/29/13Adaptable datapath for a digital processing system
08/22/13Pld architecture for flexible placement of ip function blocks
08/15/13Apparatus and methods for time-multiplex field-programmable gate arrays
08/15/13Configuring a programmable device using high-level language
08/15/13Configuring a programmable device using high-level language
07/18/13Methods and motion search refinement in a simd array processor
06/13/13Bidirectional wavelength cross connect architectures using wavelength routing elements
06/06/13Methods and matrix decompositions in programmable logic devices
06/06/13N-well/p-well strap structures
06/06/13Logic device having a compressed configuration image stored on an internal read only memory
04/18/13Clock and data recovery circuitry with auto-speed negotiation and other possible features
03/07/13Processor to message-based network interface using speculative techniques
01/17/13Manifold array processor
01/10/13Field programmable gate array with integrated application specific integrated circuit fabric
01/10/13Software-to-hardware compiler with symbol set inference analysis
01/03/13Application-specific integrated circuit equivalents of programmable logic and associated methods
01/03/13Methods and efficient vocoder implementations







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



###

This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Altera Corporation in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Altera Corporation with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

###




';