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Altera Corporation patents


Recent patent applications related to Altera Corporation. Altera Corporation is listed as an Agent/Assignee. Note: Altera Corporation may have other listings under different names/spellings. We're not affiliated with Altera Corporation, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "A" | Altera Corporation-related inventors


Circuit design instrumentation for state visualization

An integrated circuit includes user storage circuits, a local control circuit, and scan storage circuits arranged in a scan chain. At least a portion of a design-under-test is implemented in a subset of the integrated circuit that comprises the user storage circuits. The local control circuit retrieves data stored in... Altera Corporation

Integrated circuits with hybrid fixed/configurable clock networks

An integrated circuit with a clock distribution network is provided. The clock distribution network may include configurable clock routing paths linking a clock source to one or more clock tree roots and may also include fixed clock routing paths linking the clock tree roots to corresponding leaf nodes. Both the... Altera Corporation

Methods and performing reed-solomon encoding by lagrangian polynomial fitting

An integrated circuit for implementing a Reed-Solomon encoder circuit is provided. The encoder circuit may include partial syndrome calculation circuitry and matrix multiplication circuitry. The partial syndrome calculation circuitry may receive a message and generate corresponding partial syndromes. The matrix multiplication circuitry may receive the partial syndromes and may compute... Altera Corporation

Methods and smart memory interface

One embodiment relates to a memory structure that includes a bank group and a port emulation circuit module. The bank group includes a plurality of memory banks, each memory bank having one read port and one write port. The port emulation circuit module provides a group read/write port and a... Altera Corporation

Method and data detection and event capture

One embodiment relates to a data detection and event capture circuit. Data comparator logic receives a monitored data word from a parallel data bus and generates a plurality of pattern detected signals. Any pattern detection logic receives the plurality of pattern detected signals and generates a plurality of any pattern... Altera Corporation

Methods for specifying processor architectures for programmable integrated circuits

A programmable integrated circuit may include soft and hard logic for implementing a reduced instruction set computing (RISC) processor. Processor generator tools implemented on specialized computing equipment may be used to specify desired parameters for the processor architecture, including the data word size of one or more data paths, the... Altera Corporation

Method and phase-aligned 2x frequency clock generation

One embodiment relates to a multiple-channel serializer circuit that includes a plurality of one-channel serializers. A one-channel serializer of the plurality of one-channel serializes includes a local 2× frequency clock generator with a non-divider structure. Other embodiments relate to methods of using a non-divider circuit to generate a local 2×... Altera Corporation

Apparatus and methods for on-die temperature sensing to improve fpga performance

A field programmable gate array (FPGA) includes a temperature sensor array. The FPGA also includes a supply voltage modulation circuit. The supply voltage modulation circuit is coupled to the temperature sensor array.... Altera Corporation

Parallel configured resistive memory elements

The present invention discloses a memory cell that includes at least two non-volatile resistive memory elements coupled in parallel. The non-volatile resistive memory elements are capable of existing in different resistive states such that each of the different resistive state represents a different data state. The non-volatile resistive memory elements... Altera Corporation

Techniques for detecting and correcting errors on a ring oscillator

A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through... Altera Corporation

Selectively disabled output

Circuits, methods, and apparatus are directed to an integrated circuit having a disabling element that can disable a reading of data from the circuit. Once the disabling element is set to not allow a reading of the data, the disabling element cannot be changed to allow a reading of the... Altera Corporation

Phase-locked loops with electrical overstress protection circuitry

An integrated circuit with a phase-locked loop (PLL) is provided. The PLL may include a phase frequency detector, a charge pump, a source follower circuit, a variable oscillator, a frequency divider, and a control block. The phase frequency detector may be configured to align or lock a feedback clock signal... Altera Corporation

Configuration via high speed serial link

Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode... Altera Corporation

Supporting pseudo open drain input/output standards in a programmable logic device

Techniques and mechanisms allow a Programmable Logic Device (PLD) to support a pseudo open drain (POD) input/output (I/O) standard used in interface protocols such as fourth generation double data rate (DDR4). An OR gate with inputs including data and an inverted output enable from a user's design may be inserted... Altera Corporation

Integrated circuit calibration system using general purpose processors

In one embodiment, an integrated circuit is disclosed. The integrated includes a general purpose processor, an interface circuit, and a calibration adapter circuit. The general purpose processor circuit generates calibration test inputs based on user instruction. The analog interface circuit may include a calibration bus circuit. The calibration bus circuit... Altera Corporation

Emulated multiport memory element circuitry with exclusive-or based control circuitry

Integrated circuits may include memory element circuitry. The memory element circuitry may include multiple dual-port memory elements that are controlled to effectively form a multi-port memory element having multiple read and write ports. A respective bank of dual-port memory elements may be coupled to each write port. Write data may... Altera Corporation

Low-skew channel bonding using phase-measuring fifo buffer

Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission... Altera Corporation

Method and implementing soft constraints in tools used for designing programmable logic devices

A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.... Altera Corporation

Method and secure provisioning of an integrated circuit device

A method of operating an integrated circuit may include generating a session key with a random number generator circuit. The session key may then be used to establish a secure communications channel between the integrated circuit and a remote server. The integrated circuit may be placed in a non-operational mode... Altera Corporation

Embedded built-in self-test (bist) circuitry for digital signal processor (dsp) validation

Configured in this way, the LIFR and the MISR circuits of the DSP blocks are not implemented using soft logic and can therefore easily meet performance criteria.... Altera Corporation

Current limited power converter circuits and methods

A power converter circuit regulates an output voltage of a power train circuit and controls the current in the power train circuit. A current sensor circuit measures a current in the power train circuit. A hysteretic comparison circuit compares the current in the power train circuit to positive and negative... Altera Corporation

Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks

The present embodiments relate to circuitry that efficiently performs floating-point arithmetic operations and fixed-point arithmetic operations. Such circuitry may be implemented in specialized processing blocks. If desired, the specialized processing blocks may include configurable interconnect circuitry to support a variety of different use modes. For example, the specialized processing block... Altera Corporation

Structures for lut-based arithmetic in plds

A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic... Altera Corporation

Pipelined cascaded digital signal processing structures and methods

Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic... Altera Corporation

Circuitry and methods for implementing galois-field reduction

Galois-field reduction circuitry for reducing a Galois-field expansion value, using an irreducible polynomial, includes a plurality of memories, each for storing a respective value derived from the irreducible polynomial and a respective combination of expansion bit values, wherein expansion bits of the expansion value address the plurality of memories to... Altera Corporation

Method and implementing a system-level design tool for design planning and architecture exploration

A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.... Altera Corporation

Setting security features of programmable logic devices

Systems and methods are disclosed for allowing security features to be selectively enabled during device configuration. For example, a programmable integrated circuit device is provided that receives configuration data and security requirement data. Control circuitry compares enabled security features in the device against the security requirements, and can configure the... Altera Corporation

Serial memory interface circuitry for programmable integrated circuits

A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of... Altera Corporation

Pipelined cascaded digital signal processing structures and methods

Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic... Altera Corporation

Transceiver parameter solution space visualization to reduce bit error rate

Techniques and mechanisms provide a solution space visualization of bit error rates (BER) for combinations of parameter settings of transceivers. Different types of visualizations may be generated.... Altera Corporation

Safety features for high level design

Aspects of this disclosure relate generally to electronic design automation, and more specifically, to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. Some innovative aspects can be implemented in computer-readable media, systems and methods capable of accessing an algorithmic description representation of... Altera Corporation

Method high-level programs with general control flow

A method of configuring a programmable integrated circuit device to implement control flow at a current basic block. A branch selector node within the current basic block is configured to receive at least one control signal, where each of the at least one control signal is associated with a respective... Altera Corporation

Power gated lookup table circuitry

A programmable integrated circuit with lookup table circuitry is provided. The lookup table (LUT) circuitry may be formed using multiplexers. A multiplexer in the lookup table circuitry may be implemented using only tristate inverting circuits. Each tristate inverting circuit may include a first set of n-channel and p-channel transistors that... Altera Corporation

Secure physically unclonable function (puf) error correction

The ECC processor may return information back to the secure subsystem, and the control circuitry may then obtain a corrected PUF response that matches the desired PUF response.... Altera Corporation

Efficient integrated circuits configuration data mangement

Circuitry for efficient configuration data management is presented. The circuitry may include an encoding circuit that compares the configuration data of a circuit design with the base configuration data of a base circuit design. The encoding circuit may compress the difference between the configuration data and the base configuration data... Altera Corporation

10/05/17 / #20170286590

Method and performing register retiming in the presence of timing analysis exceptions

A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for... Altera Corporation

10/05/17 / #20170287543

Adaptive refresh scheduling for memory

The present disclosure provides for adaptive scheduling of memory refreshes. One embodiment relates to a method of adapting an initial refresh sequence. In this method, flow and blockage scores for each refresh sequence of a plurality of refresh sequences are obtained and stored in an array of scores. An initial... Altera Corporation

10/05/17 / #20170287872

Bumpless wafer level fan-out package

An integrated circuit package may include a first conductive pad on an interposer substrate, and a second conductive pad formed on a front surface of an integrated circuit die. The second conductive pad may directly contact the first conductive pad on the interposer substrate. The integrated circuit package may further... Altera Corporation

10/05/17 / #20170288648

Pulse-width modulation voltage identification interface

Systems, methods, and devices for voltage identification using a pulse-width modulation signal are provided. Such an integrated circuit device may include an input/output (I/O) interface and voltage identification (VID) circuitry. The VID circuitry may be coupled to the input/output interface. The voltage identification circuitry may generate a voltage identification signal... Altera Corporation

10/05/17 / #20170288671

Pipelined interconnect circuitry with double data rate interconnections

An integrated circuit may have pipelined interconnects that are configurable to operate in registered single data rate mode, registered double data rate mode, or in combinational mode. The pipelined interconnect may include routing multiplexers for selecting incoming signals, circuitry for serialization and de-serialization, and memory elements that are configurable to... Altera Corporation

09/21/17 / #20170270995

Circuits and methods for dqs autogating

In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second... Altera Corporation

09/21/17 / #20170272073

Dynamic parameter operation of an fpga

Methods and systems for operating a programmable logic fabric including a dynamic parameter scaling controller that tracks an operating parameter that functions at multiple operating conditions by maintaining the operating parameter while cycling through a multiple operating conditions during a calibration mode using the calibration configuration for the programmable logic... Altera Corporation

09/14/17 / #20170262563

State visibility and manipulation in integrated circuits

In a first mode, a control circuit may implement a circuit design with storage circuits in an integrated circuit by programming configuration memory bits via configuration resources. The storage circuits may be accessed for read and write operations during the execution of the circuit design implementation with the integrated circuit.... Altera Corporation

09/14/17 / #20170264283

Techniques for enabling and disabling transistor legs in an output driver circuit

An output driver circuit includes a control circuit and first and second transistor legs that are coupled to an output pad. Each of the first and second transistor legs includes a pull-up transistor and a pull-down transistor. The control circuit is coupled to the first and second transistor legs. The... Altera Corporation

09/07/17 / #20170257222

Techniques for protecting security features of integrated circuits

An integrated circuit includes a control circuit, a one-time programmable circuit, and a security feature. The control circuit determines if the one-time programmable circuit is programmed in response to a request by a user of the integrated circuit to access the security feature. The control circuit generates a signal to... Altera Corporation

09/07/17 / #20170257369

Flexible feature enabling integrated circuit and methods to operate the integrated circuit

A method for enabling a circuit feature on an integrated circuit device having inactive circuit features includes a step to receive an encrypted message and a signed digital signature from a server using an input/output (I/O) terminal within the integrated circuit device. The method also includes a step to decrypt... Altera Corporation

08/31/17 / #20170249409

Emulation of synchronous pipeline registers in integrated circuits with asynchronous interconnection resources

Integrated circuits may include synchronous nodes and asynchronous routing elements coupled between the synchronous nodes. A synchronous design implemented in such an integrated circuit may identify a register chain having a source register, a destination register, and intermediate registers. A virtual register may be created for each of the intermediate... Altera Corporation

08/31/17 / #20170250155

Multi-access memory system and a method to manufacture the system

A multiple memory access system is disclosed. The system includes a first die disposed on a package substrate. A second die is stacked above the first die. The first die, the second die and the package substrate form a first package. An IC is placed within a close proximity of... Altera Corporation

08/31/17 / #20170250681

Techniques for detecting and correcting errors on a ring oscillator

A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through... Altera Corporation

08/31/17 / #20170250713

Methods and performing reed-solomon encoding

The present embodiments relate to Reed-Solomon encoding, and to circuitry for performing such encoding, particularly in an integrated circuit. A Reed-Solomon encoder circuit may receive a message with data symbols and compute a partial syndrome vector by multiplying the data symbols with a first matrix. The Reed-Solomon encoder circuit may... Altera Corporation

08/24/17 / #20170244411

Apparatus for flexible electronic interfaces and associated methods

A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a... Altera Corporation

08/24/17 / #20170244413

Hybrid architecture for signal processing and signal processing accelerator

Systems and methods for configuring circuitry for use with a field programmable gate array (FPGA) are disclosed. The circuitry includes an array of signal processing accelerators (SPAs) and an array of network nodes. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of... Altera Corporation

08/17/17 / #20170237433

Circuits and methods for impedance calibration

A driver circuit drives data to an output based on an input data signal in a transmission mode. The driver circuit includes transistors. A comparator generates a comparison output in a calibration mode based on a reference signal and a signal at the output of the driver circuit. A calibration... Altera Corporation

08/10/17 / #20170230209

High-speed serial data signal receiver circuitry

Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for... Altera Corporation

08/03/17 / #20170221537

High speed fpga boot-up through concurrent multi-frame configuration scheme

Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated... Altera Corporation

08/03/17 / #20170222651

Transformable logic and routing structures for datapath optimization

Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions may include lookup table (LUT) circuitry driven using vectored multiplexing circuits. The vectored multiplexing circuits may include a first multiplexer stage controlled by common configuration... Altera Corporation

07/27/17 / #20170214557

Digital equalizer adaptation using on-die instrument

Systems and methods are provided for adjusting gain of a receiver. Adaptation circuitry is operable to identify, based on a matrix representation of a receiver's output generated from horizontal and vertical sweeps of the receiver's output, an eye opening of the receiver's output. The adaptation circuitry is also operable to... Altera Corporation

07/20/17 / #20170206176

Integrated circuit device with embedded programmable logic

Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the... Altera Corporation

07/13/17 / #20170200484

Programmable integrated circuits with in-operation reconfiguration capability

Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but... Altera Corporation

07/13/17 / #20170201256

Power gated lookup table circuitry

A programmable integrated circuit with lookup table circuitry is provided. The lookup table (LUT) circuitry may be formed using multiplexers. A multiplexer in the lookup table circuitry may be implemented using only tristate inverting circuits. Each tristate inverting circuit may include a first set of n-channel and p-channel transistors that... Altera Corporation

07/06/17 / #20170194964

Programmable routing performance, power, and area by recovering aging in routing pass gates

Transistors degrade when subjected to voltage stress. Methods are described for reducing this aging problem by applying a reverse voltage to the gates of the circuit on an intermittent or periodic basis. By applying such a voltage for a brief period of time such as one second, the aging process... Altera Corporation

06/01/17 / #20170154951

Scalable fixed-footprint capacitor structure

In one embodiment, a capacitor structure includes a substrate, a dielectric stack, a first conductor segment, a second conductor segment and a shielding conductor segment. The dielectric stack is formed on the substrate. A first layer of the dielectric stack includes a plurality of conductor segments routed only in a... Altera Corporation

06/01/17 / #20170155529

Clock data recovery circuitry associated with programmable logic device circuitry

A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated... Altera Corporation

05/25/17 / #20170147226

Embedded memory blocks with adjustable memory boundaries

An integrated circuit for configuring memory block portions is provided. The integrated circuit may include a memory block that is partitioned into first and second memory block portions. The first memory block portion has a first memory type and the second memory block portion has a second memory type that... Altera Corporation

05/11/17 / #20170133298

Integrated circuit package with enhanced cooling structure

An integrated circuit package may include an integrated circuit die having first and second circuit regions and a surface. The first circuit region of the integrated circuit package has an operating temperature that is different than that of the second circuit region. A cooling structure is formed on the surface... Altera Corporation

Patent Packs
05/11/17 / #20170133329

2.5d electronic package

A 2.5D electronic package is provided in which at least one integrated circuit is mounted on an interposer that is mounted on a package substrate. To reduce warpage, the interconnection array of the integrated circuit does not include a thick metallization layer; and at least part of the power distribution... Altera Corporation

04/27/17 / #20170115958

Methods and performing product series operations in multiplier accumulator blocks

A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic... Altera Corporation

04/27/17 / #20170117250

Integrated circuit packages with detachable interconnect structures

An integrated circuit package may include a first integrated circuit die having a first bump structure, a second integrated circuit die having a second bump structure, and a detachable interconnect structure having first and second conductive structures that is positioned between the first and second integrated circuit dies. In order... Altera Corporation

04/27/17 / #20170117899

Systems and methods for configuring an sopc without a need to use an external memory

Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.... Altera Corporation

04/13/17 / #20170103157

State visibility and manipulation in integrated circuits

In a first mode, a control circuit generates a circuit design implementation with storage circuits in an integrated circuit by programming configuration memory bits via configuration resources. The storage circuits can be accessed for read and write operations during the execution of the circuit design implementation with the integrated circuit.... Altera Corporation

04/13/17 / #20170103298

Method and designing and implementing a convolution neural net accelerator

A method for implementing a convolutional neural network (CNN) accelerator on a target includes identifying characteristics and parameters for the CNN accelerator. Resources on the target are identified. A design for the CNN accelerator is generated in response to the characteristics and parameters of the CNN accelerator and the resources... Altera Corporation

04/13/17 / #20170103299

Method and implementing layers on a convolutional neural network accelerator

A method for implementing a convolutional neural network (CNN) accelerator on a target includes utilizing one or more processing elements to implement a standard convolution layer. A configuration of the CNN accelerator is modified to change a data flow between components on the CNN accelerator. The one or more processing... Altera Corporation

04/06/17 / #20170097810

Methods and sequencing multiply-accumulate operations

An integrated circuit may have specialized processing blocks that are configurable to operate as arithmetic operators that may implement, amongst other functions, multiplication and multiply-accumulation operations in a first mode. In a second mode, a sequencer circuit may provide data signals and control signals to the specialized processing blocks such... Altera Corporation

04/06/17 / #20170097840

Efficient virtual i/o address translation

A method includes using a network interface controller to monitor a transmit ring, wherein the transmit ring comprises a circular ring data structure that stores descriptors, wherein a descriptor describes data and comprises a guest bus address that provides a virtual memory location of the data. The method also includes... Altera Corporation

04/06/17 / #20170098026

Control block size reduction through ip migration in an integrated circuit device

Methods for control block size reduction of a controller of an integrated circuit (IC) device through intellectual property (IP) migration in the IC device are disclosed. A disclosed method includes receiving configuration data for the IC device and determining whether IP construction data is defined in the configuration data. The... Altera Corporation

04/06/17 / #20170099053

Programmable logic device virtualization

A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area... Altera Corporation

03/30/17 / #20170092586

Multi-level signaling for on-package chip-to-chip interconnect through silicon bridge

One embodiment relates to an apparatus for data communication between at least two in-package semiconductor dies. On the first semiconductor die in a package, a digital-to-analog converter (DAC) converts a plurality of binary signals to an analog signal. The analog signal is transmitted through a silicon bridge to a second... Altera Corporation

03/23/17 / #20170082689

Systems and methods for particle detection and error correction in an integrated circuit

An integrated circuit for detecting and correcting error events associated with atomic particles includes error detection circuitry connected to monitoring circuitry. The error detection circuitry may include a particle sensing circuit (e.g., a diode circuit) embedded below a substrate surface of the integrated circuit, and a particle validation circuit (e.g.,... Altera Corporation

03/23/17 / #20170084553

Tranmission line bridge interconnects

In one embodiment, an integrated circuit package includes a package substrate, a printed circuit board, an interposer structure and a transmission line bridge interconnect within the interposer. The interposer structure, which includes multiple interposer layers, may be formed on a top surface of the package substrate. The printed circuit board... Altera Corporation

03/16/17 / #20170077814

Asymmetric power flow controller for a power converter and operating the same

A controller for a power converter formed with a plurality of converter stages, and method of operating the same. In one embodiment, the controller includes a power system controller configured to determine an unequal current allocation among the plurality of converter stages based on an operation of the power converter.... Altera Corporation

Patent Packs
03/09/17 / #20170068638

Distributed multi-die protocol application interface

Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies... Altera Corporation

03/09/17 / #20170068765

Incremental register retiming of an integrated circuit design

A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a... Altera Corporation

03/09/17 / #20170068768

Method and performing parallel routing using a multi-threaded routing procedure

A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of... Altera Corporation

03/02/17 / #20170061055

Efficient integrated circuits configuration data management

Circuitry for efficient configuration data management is presented. The circuitry may include an encoding circuit that compares the configuration data of a circuit design with the base configuration data of a base circuit design. The encoding circuit may compress the difference between the configuration data and the base configuration data... Altera Corporation

03/02/17 / #20170061162

Systems and methods for multiport to multiport cryptography

Systems and methods are discussed herein for reusing hardware for encryption and authentication, where the hardware has a fixed input bandwidth, and where the hardware has the same bandwidth for a different input bandwidth. In order to accomplish this mechanism, systems and methods are provided herein for processing invalid data... Altera Corporation

02/16/17 / #20170046179

Application-based dynamic heterogeneous many-core systems and methods

A method for dynamically configuring multiple processors based on needs of applications includes receiving, from an application, an acceleration request message including a task to be accelerated. The method further includes determining a type of the task and searching a database of available accelerators to dynamically select a first accelerator... Altera Corporation

02/16/17 / #20170046455

Method and implementing a system-level design tool for design planning and architecture exploration

A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.... Altera Corporation

02/09/17 / #20170041249

Programmable logic device with integrated network-on-chip

Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a... Altera Corporation

01/26/17 / #20170024355

Hybrid programmable many-core device with on-chip interconnect

The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may... Altera Corporation

01/05/17 / #20170005661

Programmable high-speed i/o interface

Methods and apparatus for providing either high-speed, Or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and... Altera Corporation

01/05/17 / #20170005662

Programmable high-speed i/o interface

Methods and apparatus for providing either high-speed, Or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and... Altera Corporation








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