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Arm Limited patents


Recent patent applications related to Arm Limited. Arm Limited is listed as an Agent/Assignee. Note: Arm Limited may have other listings under different names/spellings. We're not affiliated with Arm Limited, we're just tracking patents.

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 new patent  Apparatus and maintaining address translation data within an address translation cache

An apparatus and method are provided for maintaining address translation data within an address translation cache. The address translation cache has a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system.... Arm Limited

 new patent  Eviction control for an address translation cache

A data processing system 2 includes an address translation cache 12 to store a plurality of address translation entries. Eviction control circuitry 10 selects a victim entry for eviction from address translation cache 12 using an eviction control parameter. The address translation cache 12 can store multiple different types of... Arm Limited

 new patent  Graphics processing systems

A graphics processing pipeline (30) includes a programmable fragment shader (40) that is operable to, in response to a “test” instruction included in a fragment shader program that it is executing, trigger, if appropriate, the performance of an alpha-to-coverage operation (41), a late stencil test (42), and a late depth... Arm Limited

Apparatus and maintaining address translation data within an address translation cache

An apparatus and method are provided for maintaining address translation data within an address translation cache. Each entry of the address translation cache is arranged to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to... Arm Limited

Controlling transitions of devices between normal state and quiescent state

A data processing apparatus (2) has a number of devices (4) having a normal state and a quiescent state. Transition sequencing circuitry (70) controls a sequential state transition process for transitioning each of the devices (4) in turn between the normal state and the quiescent state. For each device, the... Arm Limited

Display controllers

In a display controller of a data processing system, when composing two or more input surfaces to generate a composited surface comprising the two or more input surfaces, data indicating a border between different input surfaces in the composited surface is associated with the composited surface. The data indicative of... Arm Limited

Display controllers

In a display controller, output surface data from a composition processing stage 22 is received by and stored in a local latency hiding buffer 40 of a memory write subsystem 31 before being written out to an external memory. The local buffer 40 of the memory write subsystem 31 signals... Arm Limited

Instruction predecoding

An apparatus comprises processing circuitry, an instruction cache, decoding circuitry to decode program instructions fetched from the cache to generate macro-operations to be processed by the processing circuitry, and predecoding circuitry to perform a predecoding operation on a block of program instructions fetched from a data store to generate predecode... Arm Limited

Queuing memory access requests

A data processing apparatus is provided including queue circuitry to respond to control signals each associated with a memory access instruction, and to queue a plurality of requests for data, each associated with a reference to a storage location. Resolution circuitry acquires a request for data, and issues the request... Arm Limited

Integrated circuit using shaping and timing circuitries

Various implementations described herein may refer to and may be directed to an integrated circuit using shaping and timing circuitries. In one implementation, an integrated circuit may include memory that is accessed based on a voltage level on a first control line, and may include a control driver circuitry coupled... Arm Limited

Selecting encoding options

A set of encoding options to use when encoding an array of data elements is selected based on a bit count value and a distortion value for that set of encoding options. The distortion value is determined from a set of error values that represents the difference between a set... Arm Limited

Instruction issue according to in-order or out-of-order execution modes

Apparatus for processing data (2) includes issue circuitry (22) for issuing program instructions (processing operations) to execute either within real time execution circuitry (32) or non real time execution circuitry (24, 26, 28, 30). Registers within a register file (18) are marked as non real time dependent registers if they... Arm Limited

Apparatus, memory controller, memory module and controlling data transfer

An apparatus, memory controller, memory module and method are provided for controlling data transfer in memory. The apparatus comprises a memory controller and a plurality of memory modules. The memory controller is arranged to orchestrate direct data transfer by transmitting a first direct transfer command to a first memory module... Arm Limited

Error detection in communication networks

Broadly speaking, embodiments of the present techniques provide apparatus and methods to identify and correct communication errors in a network formed of a plurality of nodes. In particular, the apparatus and methods identify synchronisation errors in a network which result in delayed propagation of messages through the network.... Arm Limited

Methods of and encoding data arrays

To perform motion estimation for a video frame block to be encoded, a difference measure is determined for each of a plurality of reference frame block positions at a first, coarser resolution. The determined difference measures are then used estimate difference measures for reference frame blocks at positions at a... Arm Limited

Data item order restoration

An apparatus and a corresponding method for processing a sequence of received data items are disclosed. The processing is performed by multiple processing elements. A reorder buffer comprising multiple slots is used to maintain the order of the received data items, wherein a processing element reserves a next available slot... Arm Limited

Receiver circuitry and converting an input signal from a source voltage domain into an output signal for a destination voltage domain

The present invention provides a receiver circuit and method for receiving an input signal from a source voltage domain and converting the input signal into an output signal for a destination voltage domain. The source voltage domain operates from a supply voltage that exceeds a stressing threshold of components within... Arm Limited

Critical path architect

Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze... Arm Limited

Providing data in a shared memory

A data processing apparatus is provided, comprising controller circuitry. The controller circuitry includes processing circuitry that executes a stream of instructions. Communication circuitry obtains a command from shared storage circuitry to cause the processing circuitry to execute a subset of instructions in the stream of instructions, and proactively transmit additional... Arm Limited

Management of log data in electronic systems

The disclosed method comprises receiving operating environment data, such as resource availability data, from connected computing devices and services, analysing the data to create one or more policies governing log data storage and upload parameters, and sending the policies to the connected devices to enable them to limit resource consumption... Arm Limited

Comparator and memory region detection circuitry and methods

Comparator circuitry comprises carry-save-addition (CSA) circuitry to generate a set of partial sum bits and a set of carry bits in respect of corresponding bit positions in a first input value, a second input value, a carry-in value associated with the first and second input values, and a third input... Arm Limited

Cem switching device

Subject matter herein disclosed relates to a method for the manufacture of a switching device comprising a silicon-containing correlated electron material. In embodiments, processes are described for forming the silicon-containing correlated electron material. These processes may use comparatively lower temperatures as compared to those used for forming a correlated electron... Arm Limited

Cem switching device

Subject matter herein disclosed relates to a method for the manufacture of a CEM switching device providing that the CEM layer comprises a doped metal compound substantially free from metal wherein ions of the same metal element are present in different oxidation states. The method may provide a CEM layer... Arm Limited

Serial communication control

An apparatus 2 for performing serial data communication with a target device 4, such as an integrated circuit, utilizes serial transfer circuitry 16 to perform a serial transfer of data to a communication register 26 in the target device 4 and serial retrieval circuitry 18 to retrieve an acknowledge signal... Arm Limited

Floating point addition with early shifting

A floating point adder includes leading zero anticipation circuitry 18 to determine a number of leading zeros within a result significand value of a sum of a first floating point operand and a second floating point operand. This number of leading zeros is used to generate a mask which in... Arm Limited

Tracing processing activity

Data processing apparatus comprises a processing element having an instruction pipeline to execute instructions; and trace circuitry to generate items of trace data indicative of processing activities of the processing element; the trace circuitry being configured to generate items of event trace data in response to events initiated by execution... Arm Limited

Method for generating three-dimensional integrated circuit design

A method for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups... Arm Limited

Apparatus and fixed point to floating point conversion and negative power of two detector

A data processing system 2 supports conversion of fixed point numbers to floating point numbers. The result floating point numbers may be subnormal. A first shifter 28 shifts input signals representing the fixed point number by a first shift amount depending upon a leading zero count within an integer portion... Arm Limited

Memory dependence prediction

A data processing apparatus executes a stream of instructions. Memory access circuitry accesses a memory in response to control signals associated with a memory access instruction that is executed in the stream of instructions. Branch prediction circuitry predicts the outcome of branch instructions in the stream of instructions based on... Arm Limited

Interconnect circuitry and a operating such interconnect circuitry

An interconnect circuit, and method of operation of such an interconnect circuit, are provided. The interconnect circuitry has a first interface for coupling to a master device and a second interface for coupling to a slave device. Transactions are performed between the master device and the slave device, where each... Arm Limited

Data processing

Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of one or more data vectors each comprising an ordered plurality of data items at respective vector positions in the data vector, according to the state of respective predicate indicators associated with... Arm Limited

Data processing

Data processing apparatus comprises: processing circuitry to selectively apply vector processing operations to one or more data items of one or more data vectors each comprising a plurality of data items at respective vector positions in the data vector, according to the state of respective predicate indicators associated with the... Arm Limited

Power supply control

A data processing apparatus 2 includes processing circuitry 4 performing processing operations which move the processing circuitry 4 between logical states. Monitoring circuitry 18 monitors logical state variables of the processing circuitry and these are supplied to prediction circuitry 30 which detects predetermined patterns within the logical states which are... Arm Limited

Cache maintenance instruction

An apparatus (2) comprises processing circuitry (4) for performing data processing in response to instructions. The processing circuitry (4) supports a cache maintenance instruction (50) specifying a virtual page address (52) identifying a virtual page of a virtual address space. In response to the cache maintenance instruction, the processing circuitry... Arm Limited

Interface device for a data processing system

An interface device for a data processing system is provided. The interface device comprises first interface circuitry to receive incoming data and second interface circuitry to transmit processed data to a data store for storage. The interface device is provided with processing circuitry to generate the processed data from the... Arm Limited

02/01/18 / #20180033191

Graphics processing systems

In a graphics processing system, a bounding volume (20) representative of the volume of all or part of a scene to be rendered is defined. Then, when rendering an at least partially transparent object (21) that is within the bounding volume (20) in the scene, a rendering pass for part... Arm Limited

01/25/18 / #20180026799

A establishing trust between a device and an apparatus

There is disclosed a method of establishing trust between an agent device and a verification apparatus, the method comprising: obtaining, at the agent device, a trust credential, wherein the trust credential relates to an aspect of the agent device and comprises authentication information for identifying at least one party trusted... Arm Limited

01/18/18 / #20180018359

Datagram reassembly

Apparatus and a corresponding method for processing received datagram fragments are provided. Fragments are considered in fragments lists, which comprise a linked list of fragments. The fragments lists are referenced by corresponding entries stored in fragment list storage, where all received fragments from a given datagram will form part of... Arm Limited

01/18/18 / #20180018420

System and perforating redundant metal in self-aligned multiple patterning

A method for modifying metal portions of a layout data file associated with a self-aligned multiple patterning (SAMP) process. The method comprises receiving the layout data file that includes one or more active metal portions and layout information associated with an integrated circuit. The method also comprises converting the layout... Arm Limited

01/18/18 / #20180019951

Data item replay protection

Apparatus and a corresponding method for processing a received data item comprising a received sequence number are provided. A set of sequence number entries are stored as an array and data item processing circuitry performs an access to only a selected entry in the array in dependence on the received... Arm Limited

01/04/18 / #20180004278

Power control circuitry for controlling power domains

A data processing apparatus 2 includes a plurality of power domains controlled by respective power control signals PCS. Power control circuitry 22 includes mapping circuitry which maps a plurality of power status signals PSS indicative of the power status of respective power domains, and received from those power domains, to... Arm Limited

01/04/18 / #20180004443

Accessing encoded blocks of data in memory

A method of storing encoded blocks of data in memory comprises generating headers for the encoded blocks of data. The headers are stored in memory according to a tiled layout based on tiles of plural adjacent blocks of data elements of the array of data elements. Respective sets of the... Arm Limited

01/04/18 / #20180004500

Systems and methods for short range wireless data transfer

Systems and methods for application level authentication are provided for use with the low energy Bluetooth device and accessory. This includes receiving accessory credentials from a server, establishing a Bluetooth low energy connection with the accessory, authenticating with the accessory, and lastly transferring data to the accessory. The transferring of... Arm Limited

01/04/18 / #20180004663

Progressive fine to coarse grain snoop filter

A data processing system includes a snoop filter organized as a number of lines, each storing an address tag associated with the address of data stored in one or more caches of the system, a coherency state of the data, and presence data. A snoop controller sends snoop messages in... Arm Limited

01/04/18 / #20180004678

Apparatus and performing address translation

An apparatus, system, and method for address translation are provided. Physical address information corresponding to virtual addresses is prefetched and stored, where at least some sequences of the virtual addresses are in a predefined order. The physical address information is prefetched based on identification information provided by a data processing... Arm Limited

01/04/18 / #20180004704

Interface apparatus and method

An interface comprises routing circuitry configured to receive data items from a data source device and to route the received data items to a data sink device by either a first data path including a data buffer or a second data path, in response to an indication of a current... Arm Limited

01/04/18 / #20180005351

Data processing systems

In a data processing system, an input data array to be downscaled is split into plural parts along its horizontal extent and the different parts of the input data array are then provided to respective scalers of the data processing system and are respectively downscaled by those scalers to provide... Arm Limited

12/28/17 / #20170371560

An controlling access to a memory device, and a performing a maintenance operation within such an apparatus

A technique is described for performing a maintenance operation within an apparatus that is used to control access to a memory device. The apparatus has a storage device for storing access requests to be issued to the memory device, and maintenance circuitry for performing a maintenance operation on storage elements... Arm Limited

12/28/17 / #20170371793

Cache with compressed data and tag

Cache line data and metadata are compressed and stored in first and, optionally, second memory regions, the metadata including an address tag When the compressed data fit entirely within a primary block in the first memory region, both data and metadata are retrieved in a single memory access. Otherwise, overflow... Arm Limited

12/21/17 / #20170364461

Transferring data between memory system and buffer of a master device

A master device has a buffer for storing data transferred from, or to be transferred to, a memory system. Control circuitry issues from time to time a group of one or more transactions to request transfer of a block of data between the memory system and the buffer. Hardware or... Arm Limited

12/21/17 / #20170364710

Apparatus and obfuscating power consumption of a processor

An apparatus for obfuscating power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises counterbalance circuitry configured to provide a second power consumption to directly counterbalance the power consumption associated with the one or more operations of the logic circuitry. The second... Arm Limited

12/21/17 / #20170364817

Estimating a number of occupants in a region

A method for estimating a number of occupants in a region comprises receiving a time series of sensor values detected over a period of time by a motion sensor sensing motion in the region. A spread parameter indicative of the spread of the sensor values is determined. The number of... Arm Limited

12/21/17 / #20170365331

Boost circuit for memory

Various implementations described herein are directed to a device having a memory cell coupled to complementary bitlines. The memory cell may store at least one data bit value associated with complementary bitline signals received via the complementary bitlines. The device may include a pair of write drivers coupled to the... Arm Limited

12/21/17 / #20170365600

Using inter-tier vias in integrated circuits

Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled... Arm Limited

12/14/17 / #20170357570

Storing arrays of data in data processing systems

In a data processing system that comprises a memory 8 comprising N memory banks 11, a memory controller is configured to store one or more N data unit×N data unit arrays of data in the memory 8 such that each data unit in each row of each N×N data unit... Arm Limited

12/14/17 / #20170359338

Management of relationships between a device and a service provider

An authentication device is used to create a secure connection between an Internet of Things (IoT) device and a service provider, so that the IoT device is not limited to only the services of one specific provider or the specific services of the provider of the IoT device. In addition,... Arm Limited

12/14/17 / #20170359589

Video data processing system

A system for encoding and decoding a sequence of frames of video data. The system includes encoding processing circuitry configured to encode a sequence of source video frames using other source frames as reference frames. The encoding processing circuitry is also configured, when encoding a new source frame that has... Arm Limited

12/07/17 / #20170351319

Delegating component power control

An apparatus and a corresponding method of operating the apparatus are disclosed. A component of the apparatus is capable of operating in one of at least two power modes and component power control circuitry which is communicatively coupled to the component causes the component to operate in a selected power... Arm Limited

12/07/17 / #20170351488

Arithmetic operation input-output equality detection

Apparatus and a corresponding method are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the... Arm Limited

12/07/17 / #20170351517

Debugging data processing transactions

A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. Start of execution of a transaction may be detected and execution diverted to... Arm Limited

12/07/17 / #20170352165

Encoding and decoding arrays of data elements

A method of encoding a block of an array of data elements comprises selectively writing out an encoded version of the block either that is encoded using a first encoding scheme, which provides encoded blocks of non-fixed data size, or that is encoded using a second encoding scheme, which provides... Arm Limited

11/30/17 / #20170344342

Rounding circuitry and method

A data processing apparatus for performing rounding on an input value to produce a rounded form output value includes floor calculation circuitry that receives the input value in redundant-representation and generates two candidates of a floor of the input value in non-redundant representation. Ceiling calculation circuitry receives the input value... Arm Limited

11/30/17 / #20170344366

Method and scheduling in a non-uniform compute device

A data processing apparatus, and method of operation thereof, for executing instructions. The apparatus includes one or more host processors, each having a first processing unit, and a multi-level memory system. One or more levels of the memory system are tightly coupled to a corresponding second processing unit. At least... Arm Limited

11/30/17 / #20170344367

Method and reordering in a non-uniform compute device

A data processing apparatus includes a multi-level memory system, one or more first processing unit coupled to the memory system at a first level and one or more second processing units each coupled to the memory system at a second level. A first reorder buffer maintains data order during execution... Arm Limited

11/30/17 / #20170344480

Method and maintaining data coherence in a non-uniform compute device

A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes... Arm Limited

Patent Packs
11/30/17 / #20170344492

Address translation within a virtualised system background

A memory management unit 22, 34, 48 serves to use first stage of address translation and permission data S1 managed by a guest operating system and second stage of address translation and permission data S2 managed by a hypervisor. If there is a mismatch between the permissions (or other characteristics)... Arm Limited

11/30/17 / #20170346504

Apparatus and generating an error code for a block comprising a plurality of data bits and a plurality of address bits

An apparatus and method are provided for generating an error code for a block comprising a plurality of data bits and a plurality of address bits. The apparatus has block generation circuitry to generate a block comprising a plurality of data bits and a plurality of address bits, and error... Arm Limited

11/23/17 / #20170337115

Instruction sampling within transactions

A data processing apparatus (4) includes processing circuitry (6) for executing program instructions that form part of a transaction which executes to generate speculative updates and to commit the speculative updates if the transaction completes without a conflict. Instruction sampling circuitry (44) captures instruction diagnostic data (IDD) relating to execution... Arm Limited

11/23/17 / #20170337133

Cache entry replacement

A data processing system 2 incorporates a cache system 4 having a cache memory 6 and a cache controller 10, 12, 14, 16, 18. The cache controller selects for cache entry eviction using a primary eviction policy. This primary eviction policy may identify a plurality of candidates for eviction with... Arm Limited

11/23/17 / #20170338836

Logical interleaver

Various implementations described herein are directed to a memory device. The memory device may include a first interleaving circuit that receives data words and generates a first error correction code based on the received data words. The memory device may include a second interleaving circuit that receives the data words... Arm Limited

11/16/17 / #20170329395

Date processing systems

The graphics processor then reads the decoded graphics textures for use when generating its render outputs, such as output frames for display.... Arm Limited

11/16/17 / #20170329603

Conditional selection of data elements

An apparatus performs an operation on a register, and then conditionally selects either that register or a further register on which no operation has been performed. The apparatus includes a decoder that decodes a conditional select instruction that specifies a primary source register, a secondary source register, a destination register,... Arm Limited

11/16/17 / #20170329613

Method of and providing an output surface in a data processing system

An apparatus for compositing an output surface (10) from a plurality of input surfaces (1, 2, 3, 4) includes processing circuitry and a composition processor. The processing circuitry is configured to determine whether two or more input surfaces of the plurality of input surfaces (1, 2, 3, 4) can be... Arm Limited

11/16/17 / #20170329626

Apparatus with at least one resource having thread mode and transaction mode, and method

An apparatus (2) has processing circuitry (6) having access to a first processing resource (20-0) and a second processing resource (20-3). A first thread can be processed using the first processing resource. In a thread mode the second processing resource (20-3) can be used to process a second thread while... Arm Limited

11/16/17 / #20170329627

Monitoring utilization of transactional processing resource

An apparatus (2) may have a processing element (4) for performing data access operations to access data from at least one storage device (10, 12, 14). The processing element may have at least one transactional processing resource (10, 18) supporting processing of a transaction in which data accesses are performed... Arm Limited

11/16/17 / #20170330372

Graphics processing systems

A graphics processing pipeline comprises vertex shading circuitry that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline, to generate, inter alia, a separate vertex shaded position attribute value for each view of the plural different views. Tiling... Arm Limited

11/16/17 / #20170331465

General purpose receiver

Various implementations described herein are directed to circuit. The circuit may include a first input stage having first devices and a first path for slow slew input detection. The circuit may include a second input stage having second devices and a second path for fast slew input detection. The circuit... Arm Limited

11/02/17 / #20170315805

Atomic add with carry instruction

Processing circuitry performs processing operations specified by program instructions. An instruction decoder decodes an atomic-add-with-carry instruction AAD-DC to control the processing circuitry to perform an atomic operation of an add of an addend operand value and a data value stored in a memory to generate a result value stored in... Arm Limited

11/02/17 / #20170315947

Switching device using buffering

A crossbar switch comprises two or more data inputs 10, two or more data outputs 100, a buffer 30 between the inputs and the outputs, an arbiter 52 associated with each output and configured to select data from one of the inputs when there is contention at the output, a... Arm Limited

11/02/17 / #20170316601

Graphics processing systems

The geometry for the scene is processed and sorted into lists for respective rendering tiles of the images being rendered only once, to provide a single set of tile geometry lists that are then used in common when rendering each respective resolution image.... Arm Limited

Patent Packs
11/02/17 / #20170317672

Power-on-reset circuit

Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined... Arm Limited

10/26/17 / #20170308478

Caching data from a non-volatile memory

A data processing system 2 includes interconnect circuitry 10 providing a plurality of memory transaction paths between one or more transaction masters, including a processor 4, debugging circuitry 6 and a DMA unit 8, and one or more transaction slaves including a non-volatile memory 12, a DRAM memory 18 and... Arm Limited

10/26/17 / #20170308491

Apparatus and combining trace data from a plurality of trace sources

An apparatus and method are provided for combining trace data from a plurality of trace sources. The apparatus has an input interface to receive trace data from the plurality of trace sources, and an output interface from which to issue a trace stream incorporating the trace data from each of... Arm Limited

10/26/17 / #20170309027

Method and processing graphics

A graphics processing system sorts graphics primitives for rendering into lists corresponding to different sub-regions of a render output to be generated, each list indicating primitives to be processed for the render output. A primitive list building unit divides a render target into various sub-regions, determines which sub-regions a primitive... Arm Limited

10/19/17 / #20170301319

Data processing systems

A display controller of a data processing system fetches data for surfaces to be displayed from memory of the data processing system into a local buffer or buffers of the display controller and provides that data from the local buffer or buffers of the display controller to a display for... Arm Limited

10/12/17 / #20170293467

Apparatus and supporting a conversion instruction

A data processing system 2 includes instruction decoder circuitry 12 responsive to a conversion instruction FCVTJS to convert a double precision floating point number into a 32-bit integer number. Right shifting circuitry 28 performs a right shift upon at least part of the input number and left shifting circuitry 32... Arm Limited

10/12/17 / #20170293541

Self-testing in a processor core

Apparatus and a method for processor core self-testing are disclosed. The apparatus comprises processor core circuitry to perform data processing operations by executing data processing instructions. Separate self-test control circuitry causes the processor core circuitry to temporarily switch from a first state of executing the data processing instructions to a... Arm Limited

10/12/17 / #20170293567

Proxy identifier for data access operation

An apparatus comprises processing circuitry to process data access operations specifying a virtual address of data to be loaded from or stored to a data store, and proxy identifier determining circuitry to determine a proxy identifier for a data access operation to be processed by the data access circuitry, the... Arm Limited

10/12/17 / #20170294222

Storage bitcell with isolation

A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell... Arm Limited

10/05/17 / #20170285725

Data processing

A data processing apparatus comprises processing circuitry configured to predict whether a region of output data to be generated by the apparatus for a current set of output data will be similar to a region of output data generated and stored in memory for a previous set of output data.... Arm Limited

10/05/17 / #20170285955

Data processing systems

For each block, it is determined whether all the data positions for the block have the same data value associated with them, and, if so, an indication that all of the data positions within the block have the same data value associated with them, and an indication of the same... Arm Limited

10/05/17 / #20170286107

Shared resources in a data processing executing a plurality of threads

A data processing apparatus (100) executes threads and includes a general program counter (PC) (120) identifying an instruction to be executed for at least a subset of the threads. Each thread has a thread PC (184). The subset of threads has at least one lock parameter (188, 500-504) for tracking... Arm Limited

10/05/17 / #20170286116

Instruction prefetching

A data processing apparatus has prefetch circuitry for prefetching instructions from a data store into an instruction queue. Branch prediction circuitry is provided for predicting outcomes of branch instructions and the prefetch circuitry may prefetch instructions subsequent to the branch based on the predicted outcome. Instruction identifying circuitry identifies whether... Arm Limited

10/05/17 / #20170286421

Indexing entries of a storage structure shared between multiple threads

An apparatus has processing circuitry for processing instructions from multiple threads. A storage structure is shared between the threads and has a number of entries. Indexing circuitry generates a target index value identifying an entry of the storage structure to be accessed in response to a request from the processing... Arm Limited

10/05/17 / #20170287101

Graphics processing systems

A tile-based graphics processing pipeline includes rendering circuitry for rendering graphics fragments to generate rendered fragment data. Each graphics fragment has associated with it a set of sampling positions to be rendered. The pipeline also includes a tile buffer configured to store rendered fragment data for sampling positions prior to... Arm Limited

09/28/17 / #20170277537

Processing mixed-scalar-vector instructions

Processing circuitry supports overlapped execution of vector instructions when at least one beat of a first vector instruction is performed in parallel with at least one beat of a second vector instruction. The processing circuitry also supports mixed-scalar-vector instructions for which one of a destination register and one or more... Arm Limited

09/28/17 / #20170277817

Computer implemented reducing failure in time soft errors of a circuit design

A computer implemented system and method is provided for reducing failure in time (FIT) errors associated with one or more sequential devices of a circuit design for a process technology. The method comprises receiving an input data file that includes register transfer level (RTL) data of the circuit design. The... Arm Limited

09/28/17 / #20170280307

Apparatus and tracking call paths

A data processing apparatus is provided. Call path storage circuitry stores an identifier of a call path and processing circuitry executes a current group of instructions from a plurality of groups of instructions. The processing circuitry is responsive to a calling instruction to firstly cause the processing circuitry to start... Arm Limited

09/21/17 / #20170269657

Combination of control interfaces for multiple communicating domains

Various implementations described herein are directed to a method and apparatus for a low power interface combiner for controlling a cross domain component in a system of two or more power domain controls. The combiner may include a first state for requesting cross domain component quiescence when a first control... Arm Limited

09/21/17 / #20170269960

Apparatus with shared transactional processing resource, and data processing method

An apparatus (2) with multiple processing elements (4, 6, 8) has shared transactional processing resources (10, 50, 75) for supporting processing of transactions, which comprise operations performed speculatively following a transaction start event whose results are committed following a transaction end event. The transactional processing resources may have a significant... Arm Limited

09/21/17 / #20170272271

Apparatus and filtering transactions

An apparatus and method are provided for filtering transactions performed between a master device and a slave device, where each transaction comprises one or more transfers. The apparatus has a first interface for coupling to the master device and a second interface for coupling to the slave device. Routing circuitry... Arm Limited

09/21/17 / #20170272774

Video data processing system

An apparatus for decoding a sequence of frames of encoded video data includes parsing circuitry configured to parse the encoded video image data for a frame to derive encoding information for each block of the frame. The apparatus also includes feedback circuitry configured to feed back, to the parsing circuitry,... Arm Limited








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