Real Time Touch



new TOP 200 Companies filing patents this week

new Companies with the Most Patent Filings (2010+)




Real Time Touch

Similar
Filing Names

Arm Limited
Arm Limited_20100107
Arm Limited_20100114
Arm Limited_20100128
Arm Limited_20131212

Arm Limited patents


Recent patent applications related to Arm Limited. Arm Limited is listed as an Agent/Assignee. Note: Arm Limited may have other listings under different names/spellings. We're not affiliated with Arm Limited, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "A" | Arm Limited-related inventors


 new patent  Datagram reassembly

Apparatus and a corresponding method for processing received datagram fragments are provided. Fragments are considered in fragments lists, which comprise a linked list of fragments. The fragments lists are referenced by corresponding entries stored in fragment list storage, where all received fragments from a given datagram will form part of... Arm Limited

 new patent  System and perforating redundant metal in self-aligned multiple patterning

A method for modifying metal portions of a layout data file associated with a self-aligned multiple patterning (SAMP) process. The method comprises receiving the layout data file that includes one or more active metal portions and layout information associated with an integrated circuit. The method also comprises converting the layout... Arm Limited

 new patent  Data item replay protection

Apparatus and a corresponding method for processing a received data item comprising a received sequence number are provided. A set of sequence number entries are stored as an array and data item processing circuitry performs an access to only a selected entry in the array in dependence on the received... Arm Limited

Power control circuitry for controlling power domains

A data processing apparatus 2 includes a plurality of power domains controlled by respective power control signals PCS. Power control circuitry 22 includes mapping circuitry which maps a plurality of power status signals PSS indicative of the power status of respective power domains, and received from those power domains, to... Arm Limited

Accessing encoded blocks of data in memory

A method of storing encoded blocks of data in memory comprises generating headers for the encoded blocks of data. The headers are stored in memory according to a tiled layout based on tiles of plural adjacent blocks of data elements of the array of data elements. Respective sets of the... Arm Limited

Systems and methods for short range wireless data transfer

Systems and methods for application level authentication are provided for use with the low energy Bluetooth device and accessory. This includes receiving accessory credentials from a server, establishing a Bluetooth low energy connection with the accessory, authenticating with the accessory, and lastly transferring data to the accessory. The transferring of... Arm Limited

Progressive fine to coarse grain snoop filter

A data processing system includes a snoop filter organized as a number of lines, each storing an address tag associated with the address of data stored in one or more caches of the system, a coherency state of the data, and presence data. A snoop controller sends snoop messages in... Arm Limited

Apparatus and performing address translation

An apparatus, system, and method for address translation are provided. Physical address information corresponding to virtual addresses is prefetched and stored, where at least some sequences of the virtual addresses are in a predefined order. The physical address information is prefetched based on identification information provided by a data processing... Arm Limited

Interface apparatus and method

An interface comprises routing circuitry configured to receive data items from a data source device and to route the received data items to a data sink device by either a first data path including a data buffer or a second data path, in response to an indication of a current... Arm Limited

Data processing systems

In a data processing system, an input data array to be downscaled is split into plural parts along its horizontal extent and the different parts of the input data array are then provided to respective scalers of the data processing system and are respectively downscaled by those scalers to provide... Arm Limited

An controlling access to a memory device, and a performing a maintenance operation within such an apparatus

A technique is described for performing a maintenance operation within an apparatus that is used to control access to a memory device. The apparatus has a storage device for storing access requests to be issued to the memory device, and maintenance circuitry for performing a maintenance operation on storage elements... Arm Limited

Cache with compressed data and tag

Cache line data and metadata are compressed and stored in first and, optionally, second memory regions, the metadata including an address tag When the compressed data fit entirely within a primary block in the first memory region, both data and metadata are retrieved in a single memory access. Otherwise, overflow... Arm Limited

Transferring data between memory system and buffer of a master device

A master device has a buffer for storing data transferred from, or to be transferred to, a memory system. Control circuitry issues from time to time a group of one or more transactions to request transfer of a block of data between the memory system and the buffer. Hardware or... Arm Limited

Apparatus and obfuscating power consumption of a processor

An apparatus for obfuscating power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises counterbalance circuitry configured to provide a second power consumption to directly counterbalance the power consumption associated with the one or more operations of the logic circuitry. The second... Arm Limited

Estimating a number of occupants in a region

A method for estimating a number of occupants in a region comprises receiving a time series of sensor values detected over a period of time by a motion sensor sensing motion in the region. A spread parameter indicative of the spread of the sensor values is determined. The number of... Arm Limited

Boost circuit for memory

Various implementations described herein are directed to a device having a memory cell coupled to complementary bitlines. The memory cell may store at least one data bit value associated with complementary bitline signals received via the complementary bitlines. The device may include a pair of write drivers coupled to the... Arm Limited

Using inter-tier vias in integrated circuits

Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled... Arm Limited

Storing arrays of data in data processing systems

In a data processing system that comprises a memory 8 comprising N memory banks 11, a memory controller is configured to store one or more N data unit×N data unit arrays of data in the memory 8 such that each data unit in each row of each N×N data unit... Arm Limited

Management of relationships between a device and a service provider

An authentication device is used to create a secure connection between an Internet of Things (IoT) device and a service provider, so that the IoT device is not limited to only the services of one specific provider or the specific services of the provider of the IoT device. In addition,... Arm Limited

Video data processing system

A system for encoding and decoding a sequence of frames of video data. The system includes encoding processing circuitry configured to encode a sequence of source video frames using other source frames as reference frames. The encoding processing circuitry is also configured, when encoding a new source frame that has... Arm Limited

Delegating component power control

An apparatus and a corresponding method of operating the apparatus are disclosed. A component of the apparatus is capable of operating in one of at least two power modes and component power control circuitry which is communicatively coupled to the component causes the component to operate in a selected power... Arm Limited

Arithmetic operation input-output equality detection

Apparatus and a corresponding method are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the... Arm Limited

Debugging data processing transactions

A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. Start of execution of a transaction may be detected and execution diverted to... Arm Limited

Encoding and decoding arrays of data elements

A method of encoding a block of an array of data elements comprises selectively writing out an encoded version of the block either that is encoded using a first encoding scheme, which provides encoded blocks of non-fixed data size, or that is encoded using a second encoding scheme, which provides... Arm Limited

Rounding circuitry and method

A data processing apparatus for performing rounding on an input value to produce a rounded form output value includes floor calculation circuitry that receives the input value in redundant-representation and generates two candidates of a floor of the input value in non-redundant representation. Ceiling calculation circuitry receives the input value... Arm Limited

Method and scheduling in a non-uniform compute device

A data processing apparatus, and method of operation thereof, for executing instructions. The apparatus includes one or more host processors, each having a first processing unit, and a multi-level memory system. One or more levels of the memory system are tightly coupled to a corresponding second processing unit. At least... Arm Limited

Method and reordering in a non-uniform compute device

A data processing apparatus includes a multi-level memory system, one or more first processing unit coupled to the memory system at a first level and one or more second processing units each coupled to the memory system at a second level. A first reorder buffer maintains data order during execution... Arm Limited

Method and maintaining data coherence in a non-uniform compute device

A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes... Arm Limited

Address translation within a virtualised system background

A memory management unit 22, 34, 48 serves to use first stage of address translation and permission data S1 managed by a guest operating system and second stage of address translation and permission data S2 managed by a hypervisor. If there is a mismatch between the permissions (or other characteristics)... Arm Limited

Apparatus and generating an error code for a block comprising a plurality of data bits and a plurality of address bits

An apparatus and method are provided for generating an error code for a block comprising a plurality of data bits and a plurality of address bits. The apparatus has block generation circuitry to generate a block comprising a plurality of data bits and a plurality of address bits, and error... Arm Limited

Instruction sampling within transactions

A data processing apparatus (4) includes processing circuitry (6) for executing program instructions that form part of a transaction which executes to generate speculative updates and to commit the speculative updates if the transaction completes without a conflict. Instruction sampling circuitry (44) captures instruction diagnostic data (IDD) relating to execution... Arm Limited

Cache entry replacement

A data processing system 2 incorporates a cache system 4 having a cache memory 6 and a cache controller 10, 12, 14, 16, 18. The cache controller selects for cache entry eviction using a primary eviction policy. This primary eviction policy may identify a plurality of candidates for eviction with... Arm Limited

Logical interleaver

Various implementations described herein are directed to a memory device. The memory device may include a first interleaving circuit that receives data words and generates a first error correction code based on the received data words. The memory device may include a second interleaving circuit that receives the data words... Arm Limited

Date processing systems

The graphics processor then reads the decoded graphics textures for use when generating its render outputs, such as output frames for display.... Arm Limited

Conditional selection of data elements

An apparatus performs an operation on a register, and then conditionally selects either that register or a further register on which no operation has been performed. The apparatus includes a decoder that decodes a conditional select instruction that specifies a primary source register, a secondary source register, a destination register,... Arm Limited

11/16/17 / #20170329613

Method of and providing an output surface in a data processing system

An apparatus for compositing an output surface (10) from a plurality of input surfaces (1, 2, 3, 4) includes processing circuitry and a composition processor. The processing circuitry is configured to determine whether two or more input surfaces of the plurality of input surfaces (1, 2, 3, 4) can be... Arm Limited

11/16/17 / #20170329626

Apparatus with at least one resource having thread mode and transaction mode, and method

An apparatus (2) has processing circuitry (6) having access to a first processing resource (20-0) and a second processing resource (20-3). A first thread can be processed using the first processing resource. In a thread mode the second processing resource (20-3) can be used to process a second thread while... Arm Limited

11/16/17 / #20170329627

Monitoring utilization of transactional processing resource

An apparatus (2) may have a processing element (4) for performing data access operations to access data from at least one storage device (10, 12, 14). The processing element may have at least one transactional processing resource (10, 18) supporting processing of a transaction in which data accesses are performed... Arm Limited

11/16/17 / #20170330372

Graphics processing systems

A graphics processing pipeline comprises vertex shading circuitry that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline, to generate, inter alia, a separate vertex shaded position attribute value for each view of the plural different views. Tiling... Arm Limited

11/16/17 / #20170331465

General purpose receiver

Various implementations described herein are directed to circuit. The circuit may include a first input stage having first devices and a first path for slow slew input detection. The circuit may include a second input stage having second devices and a second path for fast slew input detection. The circuit... Arm Limited

11/02/17 / #20170315805

Atomic add with carry instruction

Processing circuitry performs processing operations specified by program instructions. An instruction decoder decodes an atomic-add-with-carry instruction AAD-DC to control the processing circuitry to perform an atomic operation of an add of an addend operand value and a data value stored in a memory to generate a result value stored in... Arm Limited

11/02/17 / #20170315947

Switching device using buffering

A crossbar switch comprises two or more data inputs 10, two or more data outputs 100, a buffer 30 between the inputs and the outputs, an arbiter 52 associated with each output and configured to select data from one of the inputs when there is contention at the output, a... Arm Limited

11/02/17 / #20170316601

Graphics processing systems

The geometry for the scene is processed and sorted into lists for respective rendering tiles of the images being rendered only once, to provide a single set of tile geometry lists that are then used in common when rendering each respective resolution image.... Arm Limited

11/02/17 / #20170317672

Power-on-reset circuit

Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined... Arm Limited

10/26/17 / #20170308478

Caching data from a non-volatile memory

A data processing system 2 includes interconnect circuitry 10 providing a plurality of memory transaction paths between one or more transaction masters, including a processor 4, debugging circuitry 6 and a DMA unit 8, and one or more transaction slaves including a non-volatile memory 12, a DRAM memory 18 and... Arm Limited

10/26/17 / #20170308491

Apparatus and combining trace data from a plurality of trace sources

An apparatus and method are provided for combining trace data from a plurality of trace sources. The apparatus has an input interface to receive trace data from the plurality of trace sources, and an output interface from which to issue a trace stream incorporating the trace data from each of... Arm Limited

10/26/17 / #20170309027

Method and processing graphics

A graphics processing system sorts graphics primitives for rendering into lists corresponding to different sub-regions of a render output to be generated, each list indicating primitives to be processed for the render output. A primitive list building unit divides a render target into various sub-regions, determines which sub-regions a primitive... Arm Limited

10/19/17 / #20170301319

Data processing systems

A display controller of a data processing system fetches data for surfaces to be displayed from memory of the data processing system into a local buffer or buffers of the display controller and provides that data from the local buffer or buffers of the display controller to a display for... Arm Limited

10/12/17 / #20170293467

Apparatus and supporting a conversion instruction

A data processing system 2 includes instruction decoder circuitry 12 responsive to a conversion instruction FCVTJS to convert a double precision floating point number into a 32-bit integer number. Right shifting circuitry 28 performs a right shift upon at least part of the input number and left shifting circuitry 32... Arm Limited

10/12/17 / #20170293541

Self-testing in a processor core

Apparatus and a method for processor core self-testing are disclosed. The apparatus comprises processor core circuitry to perform data processing operations by executing data processing instructions. Separate self-test control circuitry causes the processor core circuitry to temporarily switch from a first state of executing the data processing instructions to a... Arm Limited

10/12/17 / #20170293567

Proxy identifier for data access operation

An apparatus comprises processing circuitry to process data access operations specifying a virtual address of data to be loaded from or stored to a data store, and proxy identifier determining circuitry to determine a proxy identifier for a data access operation to be processed by the data access circuitry, the... Arm Limited

10/12/17 / #20170294222

Storage bitcell with isolation

A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell... Arm Limited

10/05/17 / #20170285725

Data processing

A data processing apparatus comprises processing circuitry configured to predict whether a region of output data to be generated by the apparatus for a current set of output data will be similar to a region of output data generated and stored in memory for a previous set of output data.... Arm Limited

10/05/17 / #20170285955

Data processing systems

For each block, it is determined whether all the data positions for the block have the same data value associated with them, and, if so, an indication that all of the data positions within the block have the same data value associated with them, and an indication of the same... Arm Limited

10/05/17 / #20170286107

Shared resources in a data processing executing a plurality of threads

A data processing apparatus (100) executes threads and includes a general program counter (PC) (120) identifying an instruction to be executed for at least a subset of the threads. Each thread has a thread PC (184). The subset of threads has at least one lock parameter (188, 500-504) for tracking... Arm Limited

10/05/17 / #20170286116

Instruction prefetching

A data processing apparatus has prefetch circuitry for prefetching instructions from a data store into an instruction queue. Branch prediction circuitry is provided for predicting outcomes of branch instructions and the prefetch circuitry may prefetch instructions subsequent to the branch based on the predicted outcome. Instruction identifying circuitry identifies whether... Arm Limited

10/05/17 / #20170286421

Indexing entries of a storage structure shared between multiple threads

An apparatus has processing circuitry for processing instructions from multiple threads. A storage structure is shared between the threads and has a number of entries. Indexing circuitry generates a target index value identifying an entry of the storage structure to be accessed in response to a request from the processing... Arm Limited

10/05/17 / #20170287101

Graphics processing systems

A tile-based graphics processing pipeline includes rendering circuitry for rendering graphics fragments to generate rendered fragment data. Each graphics fragment has associated with it a set of sampling positions to be rendered. The pipeline also includes a tile buffer configured to store rendered fragment data for sampling positions prior to... Arm Limited

09/28/17 / #20170277537

Processing mixed-scalar-vector instructions

Processing circuitry supports overlapped execution of vector instructions when at least one beat of a first vector instruction is performed in parallel with at least one beat of a second vector instruction. The processing circuitry also supports mixed-scalar-vector instructions for which one of a destination register and one or more... Arm Limited

09/28/17 / #20170277817

Computer implemented reducing failure in time soft errors of a circuit design

A computer implemented system and method is provided for reducing failure in time (FIT) errors associated with one or more sequential devices of a circuit design for a process technology. The method comprises receiving an input data file that includes register transfer level (RTL) data of the circuit design. The... Arm Limited

09/28/17 / #20170280307

Apparatus and tracking call paths

A data processing apparatus is provided. Call path storage circuitry stores an identifier of a call path and processing circuitry executes a current group of instructions from a plurality of groups of instructions. The processing circuitry is responsive to a calling instruction to firstly cause the processing circuitry to start... Arm Limited

09/21/17 / #20170269657

Combination of control interfaces for multiple communicating domains

Various implementations described herein are directed to a method and apparatus for a low power interface combiner for controlling a cross domain component in a system of two or more power domain controls. The combiner may include a first state for requesting cross domain component quiescence when a first control... Arm Limited

09/21/17 / #20170269960

Apparatus with shared transactional processing resource, and data processing method

An apparatus (2) with multiple processing elements (4, 6, 8) has shared transactional processing resources (10, 50, 75) for supporting processing of transactions, which comprise operations performed speculatively following a transaction start event whose results are committed following a transaction end event. The transactional processing resources may have a significant... Arm Limited

09/21/17 / #20170272271

Apparatus and filtering transactions

An apparatus and method are provided for filtering transactions performed between a master device and a slave device, where each transaction comprises one or more transfers. The apparatus has a first interface for coupling to the master device and a second interface for coupling to the slave device. Routing circuitry... Arm Limited

09/21/17 / #20170272774

Video data processing system

An apparatus for decoding a sequence of frames of encoded video data includes parsing circuitry configured to parse the encoded video image data for a frame to derive encoding information for each block of the frame. The apparatus also includes feedback circuitry configured to feed back, to the parsing circuitry,... Arm Limited

Patent Packs
09/14/17 / #20170262381

Multi-range lookup in translation lookaside buffer

There is described a method and data processing apparatus configured to translate a virtual address into a physical address, the virtual address comprising an offset for a memory page, an index and a tag with the memory page having a variable size.... Arm Limited

09/14/17 / #20170262954

Graphics processing systems

An input set of indices, which contains primitive restarts, is input into splitter stage, where it is split into blocks of index positions. Each of these blocks is processed by scanner stages and scan combiner stage, to determine for each index position, the index position of the end of the... Arm Limited

09/07/17 / #20170255248

Cache power management

A method of operating a cache and corresponding apparatus are provided. The cache is capable of being only partially powered, and a decision to reduce the proportion of the cache which is currently powered is made based on calculating a memory bandwidth equivalent of expending the current active cache leakage... Arm Limited

09/07/17 / #20170255734

Computer implemented generating a layout of a cell defining a circuit component

The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input,... Arm Limited

09/07/17 / #20170256027

Data processing systems

A method of operating a data processing system 4 comprises a first processing stage 11, 12 of the data processing system producing data according to a first pattern, and a second processing stage 20 of the data processing system using the data produced by the first processing stage 11, 12... Arm Limited

08/31/17 / #20170249085

Data storage

Data storage apparatus comprises detection circuitry configured to detect a match between a multi-bit reference memory address and a test address, the test address being a combination of a multi-bit base address and a multi-bit address offset, the detection circuitry comprising: a comparator configured to compare, as a first comparison,... Arm Limited

08/24/17 / #20170243323

Method of and processing a frame

A method of processing a frame in a data processing system is provided, in which the frame comprises one or more frame regions that together form the frame, and each frame region is represented as one or more data values, with each data value being represented by a set of... Arm Limited

08/17/17 / #20170236243

Graphics processing

A graphics processing system comprises a memory that stores graphics data. The graphics data stored in the memory is accessible using virtual memory addresses that map to physical memory addresses in the memory. The graphics processing system further comprises page merging circuitry configured to use metadata provided for a set... Arm Limited

08/17/17 / #20170236244

Graphics processing systems

A graphics processing system comprises a pair of graphics processing units that are connected to each other via communications bridges that can allow communication between the connected graphics processing units. One of the graphics processing units is operable to act as a master graphics processing unit controlling graphics processing operations... Arm Limited

08/10/17 / #20170228318

Apparatus and supporting multiple cache features

An apparatus and method are provided for supporting multiple cache features. The apparatus provides cache storage comprising a plurality of cache ways and organised as a plurality of ways groups, where each way group comprises multiple cache ways from the plurality of cache ways. First cache feature circuitry is provided... Arm Limited

08/10/17 / #20170228493

Integrated circuit manufacture using direct write lithography

Integrated circuits are manufactured using a direct write lithography step to at least partially form at least one layer within the integrated circuit. The performance characteristics of an at least partially formed integrated circuit are measured and then the layout design to be applied with a direct write lithography step... Arm Limited

08/03/17 / #20170220478

Write operations to non-volatile memory

An apparatus for processing data and a method of data processing are provided. A processor core in the apparatus performs data processing operations in response to a sequence of instructions, including write operations which write data items to a non-volatile memory. A write-back cache stores local copies of the data... Arm Limited

08/03/17 / #20170222602

Integrated oscillator circuitry

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a comparator stage, a resistor, a capacitor, and active switches arranged to provide a clock signal having a time period that is independent of a first source voltage. Independence may be achieved by using a... Arm Limited

07/27/17 / #20170212758

Encoding instructions identifying first and second architectural register numbers

Various encoding schemes are discussed for more efficiently encoding instructions which identify first and second architectural register numbers. In the first example, by constraining the first architectural register number to be greater than the second architectural register number, this frees up encodings for use in encoding other operations. In a... Arm Limited

07/27/17 / #20170212761

Controlling processing of instructions in a processing pipeline

In a pipeline where first and second instruction slots process first and second instructions in parallel and a duplicated processing resource is provided at both first and second pipeline stages, a second instruction in the second instruction slot requiring the duplicated processing resource is controlled to use the duplicated processing... Arm Limited

Patent Packs
07/27/17 / #20170212764

Controlling processing of instructions in a processing pipeline

In a processing pipeline, hazards involving conditional instructions may be ignored when the conditional instruction would fail its test condition and there are no earlier instructions than the conditional instruction remaining which could potentially update the condition status information used to evaluate the test condition.... Arm Limited

07/27/17 / #20170212844

Measuring address translation latency

An apparatus includes processing circuitry to process instructions, some of which may require addresses to be translated. The apparatus also includes address translation circuitry to translate addresses in response to instruction processed by the processing circuitry. Furthermore, the apparatus also includes translation latency measuring circuitry to measure a latency of... Arm Limited

07/27/17 / #20170212975

Physical placement control

Various implementations described herein are directed to systems and methods for controlling physical placement of a circuit design. The systems and methods may extract state groups of the circuit design by deriving state groups from each logical hierarchy of the circuit design. At each level, available state points may be... Arm Limited

07/27/17 / #20170213814

Implant structure for area reduction

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a cell having a first region designated for a first type of implant and a second region designated for a second type of implant that is different than the first type of implant. The integrated... Arm Limited

07/20/17 / #20170206698

Data processing systems

A graphics processing unit comprises a programmable execution unit executing graphics processing programs for execution threads to perform graphics processing operations, a local register memory comprising one or more registers, where registers of the register memory are assignable to store data associated with an individual execution thread that is being... Arm Limited

07/20/17 / #20170207909

Correlation determination early termination

Correlation circuitry (2) includes selection circuitry (4) for selecting a sequence of symbol subsets comprising proper subsets of a candidate sequence of symbols and corresponding proper subsets of a target sequence of symbols. Correlation value determining circuitry (6) determines partial correlation values for these proper subsets which are then combined... Arm Limited

07/13/17 / #20170199723

Circuitry and performing division

A data processing apparatus comprises signal receiving circuitry to receive a signal corresponding to a divide instruction that identifies a dividend x and a divisor d. Processing circuitry performs, in response to said divide instruction, a radix-N division algorithm to generate a result value q=x/d, where N is an integer... Arm Limited

07/13/17 / #20170199738

Data processing

Data processing circuitry comprises allocation circuitry to allocate one or more source and destination processor registers, of a set of processor registers each defined by a respective register index, to a processor instruction for use in execution of that processor instruction and to associate, with the processor instruction, information to... Arm Limited

07/13/17 / #20170201099

Harvesting power from ambient energy in an electronic device

An electronic device 50 has at least one harvesting unit 52 for harvesting power from ambient energy. At least one circuit 54, including processing circuitry 56, is supplied with power from the harvesting unit 52. Control circuitry 60 is provided to adjust at least one property of the processing circuitry... Arm Limited

07/06/17 / #20170192900

Cache memory

A cache memory, such as a translation lookaside buffer cache 16, includes a plurality of blocks of bit storage circuits 26 which can operate in either a first mode to store a plurality of shared-tagged data values having a shared tag, which his stored in a tag memory 24, or... Arm Limited

07/06/17 / #20170192915

Handling interrupts in a multi-processor system

A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared... Arm Limited

07/06/17 / #20170193691

Graphics processing

A graphics processing pipeline includes position shading circuitry, a tiler, varying-only vertex shading circuitry and fragment (frontend) shading circuitry. The tiler reads a list of indices defining a set of vertices to be processed by the graphics processing pipeline and determines whether or not vertex shading is required for the... Arm Limited

07/06/17 / #20170194046

Port modes for use with memory

Various implementations described herein may refer to and may be directed to using port modes with memory. In one implementation, a memory device may include access control circuitry used to selectively activate one of a plurality of first word-lines based on first address signals from a first access port, and... Arm Limited

06/29/17 / #20170185410

Handling move instructions using register renaming

An apparatus has processing circuitry, register rename circuitry and control circuitry which selects one of first and second move handling techniques for handling a move instruction specifying a source logical register and a destination logical register. In the first technique, the register rename circuitry maps the destination logical register of... Arm Limited

06/29/17 / #20170185516

Snoop optimization for multi-ported nodes of a data processing system

A data processing apparatus having an interconnect circuit operable to transfer snoop messages between a plurality of connected devices, at least one of which has multiple ports each coupled to a local cache. The interconnect circuit has decode logic that identifies, from an address in a snoop message, which port... Arm Limited

06/29/17 / #20170185528

A data processing apparatus, and a handling address translation within a data processing apparatus

A data processing apparatus and method are provided for performing address translation in response to a memory access request issued by processing circuitry of the data processing apparatus and specifying a virtual address for a data item. Address translation circuitry performs an address translation process with reference to at least... Arm Limited

06/29/17 / #20170185542

Arbitration of requests requiring a variable number of resources

Arbitration circuitry is provided for arbitrating between requests awaiting servicing. The requests require variable numbers of resources and the arbitration circuitry permits the request to be serviced in a different order to the order in which they were received. Checking circuitry prevents a given request other than a oldest request... Arm Limited

06/29/17 / #20170185709

Method and adjusting a timing derate for static timing analysis

A static timing analysis method and apparatus that determine an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design... Arm Limited

06/29/17 / #20170186745

Resistance mitigation in physical design

Various implementations described herein are directed to an integrated circuit with mitigated resistance. The integrated circuit may include a cell having a plurality of transistors including a first transistor of a first type and a second transistor of a second type that is different from the first type. The integrated... Arm Limited

06/22/17 / #20170177055

Clock frequency reduction for an electronic device

An electronic device (20) has a clock path (24) for propagating a clock signal and a clock propagating element (26) on the clock path. An analogue element (30) coupled to the clock path (24) varies, in dependence on an analogue level of a first signal (32), a switching delay for... Arm Limited

06/22/17 / #20170177269

Memory synchronization filter

Data synchronization between memories of a data processing system is achieved by transferring the data blocks from a first memory to a second memory, forming a hash list from addresses of data blocks that are written to the second memory or modified in the second memory. The hash list may... Arm Limited

06/22/17 / #20170177785

Computer implemented modifying a layout of standard cells defining a circuit component

A computer implemented system and method is provided for modifying a layout of one or more standard cells defining a circuit component, the layout providing a layout pattern for a process technology. The method comprises receiving, after completion of one or more initial place and route operations, an input data... Arm Limited

06/22/17 / #20170178279

Graphics processing systems

In a graphics processing system, when rendering plural views of the same scene (step 43), such as for stereoscopic rendering, the vertex shading operation is configured so that rather than executing the vertex shader program separately for each view that is being rendered, a single vertex shading program is executed... Arm Limited

06/22/17 / #20170178700

Integrated circuit using topology configurations

Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices... Arm Limited








ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009



###

This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Arm Limited in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Arm Limited with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

###