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Arteris Inc patents


Recent patent applications related to Arteris Inc. Arteris Inc is listed as an Agent/Assignee. Note: Arteris Inc may have other listings under different names/spellings. We're not affiliated with Arteris Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "A" | Arteris Inc-related inventors


System and reducing ecc overhead and memory access bandwidth

A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth. The invention can be implemented in any chip, system, method, or HDL code... Arteris Inc

Victim buffer for cache coherent systems

In accordance with various aspects of the invention, a recall transaction is issued if a tag filter entry needs to be freed up for an incoming transaction. Directory entries chosen for a recall transaction are pushed into a fully associative structure called victim buffer. If this structure gets full, then... Arteris Inc

Estimation of chip floorplan activity distribution

Simulation or calculation to estimate activity per unit in a chip design, combined with estimation of the specific location or region in which the unit logic will be finally placed, provides for calculation of an estimation of the activity distribution within the floorplan. Activity distribution estimation can be performed with... Arteris Inc

Isolation mode in a cache coherent system

The invention involves isolating a cache coherence controller from agents or units. The term unit as used herein may refer to one or more circuits, components, registers, processors, software subroutines, or any combination thereof. The separate units communicate with each other and are logically coupled.... Arteris Inc

Directory storage control for commonly used patterns

A system and method are disclosed with the ability to track usage of information and determine commonly used patterns to be stored and updated in a directory. The information includes counter values that represent the frequency of occurrence of a pattern that is committed to the directory. Thus, allows the... Arteris Inc

System to reduce directory information storage

A system and method are disclosed with the ability to track usage of information, which patterns, and determine the most frequently used patterns to be stored and updated in a directory, thereby controlling and reducing the size allocated to storing information in the directory. The size is reduced by limiting... Arteris Inc

Prioritization of order ids in dram scheduling

A DRAM scheduler that prioritizes pending transactions based on their order ID value. The order of prioritization of ID values changes from time to time. Changes affecting any particular pending ID value occur only when no requests of that ID value are pending.... Arteris Inc

Control and address redundancy in storage buffer

A system and method for detecting writes of data to errant locations in storage arrays. Address information and information redundant with address information is encoded and stored in proximity with data. Upon reading the stored data, the corresponding address information is decoded and compared to the address of the intended... Arteris Inc

Proxy cache conditional allocation

A system and method are disclosed that include a bridge that translates non-coherent transactions, which are received from a non-coherent subsystem, into one or more coherent transactions to be issued to a coherent subsystem. The bridge also buffers data coherently in an internal cache, also known as a proxy cache,... Arteris Inc

Dynamic link serialization in network-on-chip

A Network-on-Chip (NoC) link with an upstream bypassable narrowing serialization adapter and a downstream bypassable widening serialization adapter. The serialization adapters are normally bypassed. To avoid sending information on broken wires, bypassing is disabled so that information is serialized to only a portion of the link. Serialization can be applied... Arteris Inc

Protection scheme conversion

Systems-on-chip are designed with different IPs that use different data protection schemes. Modules are used between the IPs, and the modules convert between protection schemes. Protection schemes can be per-byte, word, packet, flit, or burst. Conversion can involve splitting, merging, encapsulation, conversion, and generation of redundant information. Encoding of redundancy... Arteris Inc

Editing a noc topology on top of a floorplan

A NoC topology is represented on top of a physical view of a chip's floorplan. The NoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of switches within the floorplan is automatically computed. Locations can also be edited... Arteris Inc

Automatic architecture placement guidance

On-chip data transport network architectural units are assigned preferred placement locations based on architecture-level constraints. The preferred placement locations are used to generate placement constraints for a place and route tool. The placement constraints are applied to cells that are synthesized from each architectural unit. Constraints are blockages, fences, regions,... Arteris Inc

System and adaptation of coherence models between agents

A system and method are disclosed for multiple coherent caches supporting agents that use different, incompatible coherence models. Compatibility is implemented by translators that accept coherency requests and snoop responses from an agent and accept snoop requests and coherency responses from a coherence controller. The translators issue corresponding coherency requests... Arteris Inc








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