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Atrenta Inc patents

Recent patent applications related to Atrenta Inc. Atrenta Inc is listed as an Agent/Assignee. Note: Atrenta Inc may have other listings under different names/spellings. We're not affiliated with Atrenta Inc, we're just tracking patents.

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Date Atrenta Inc patents (updated weekly) - BOOKMARK this page
12/31/15System and viewing and modifying configurable rtl modules
12/31/15System and grading and selecting simulation tests using property coverage
12/10/15System and reducing power of a circuit using critical signal analysis
08/20/15Method and apparatus using formal methods for checking generated-clock timing definitions
08/20/15System and abstraction of a circuit portion of an integrated circuit
05/21/15Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline design
10/02/14Method of global design closure at top level and driving of downstream implementation flow
09/18/14System and a hybrid clock domain crossing verification
09/18/14System and filtration of error reports respective of static and quasi-static signals within an integrated circuit design
09/18/14System and altering circuit design hierarchy to optimize routing and power distribution
09/18/14System and strengthening of a circuit element to reduce an integrated circuit's power consumption
09/04/14Method for measuring assertion density in a system of verifying integrated circuit design
04/10/14Computer system for generating an integrated and unified view of ip-cores for hierarchical analysis of a system on chip (soc) design
03/27/14Characterization based buffering and sizing for system performance optimization
02/13/14System and inferring higher level descriptions from rtl topology based on naming similarities and dependency
02/06/14Apparatus and method thereof for hybrid timing exception verification of an integrated circuit design
01/30/14Systems and methods for generating a higher level description of a circuit design based on connectivity strengths
10/31/13System and methods for inferring higher level descriptions from rtl topology based on connectivity propagation
09/19/13System and metastability verification of circuits of an integrated circuit
09/12/13Hierarchical bottom-up clock domain crossing verification
08/15/13Method and system thereof for optimization of power consumption of scan chains of an integrated circuit for test
07/18/13System and inferring higher level descriptions from rti topology based on naming similarities and dependency
01/10/13Computer-aided design system and methods thereof for merging design constraint files across operational modes
07/12/12System and metastability verification of circuits of an integrated circuit
02/16/12Apparatus and method thereof for hybrid timing exception verification of an integrated circuit design
11/24/11Method and system for equivalence checking
04/28/11Method and system thereof for optimization of power consumption of scan chains of an integrated circuit for test
03/11/10Method for compaction of timing exception paths







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