| Symbol |
Company |
Application # |
Date |
Title |
| CDNS | Cadence Design Systems | 20120102440 | 20120426 | Method and system for implementing controlled breaks between features using sub-resolution assist features |
| CDNS | Cadence Design Systems | 20120096414 | 20120419 | Method and system for implementing controlled breaks between features using sub-resolution assist features |
| CDNS | Cadence Design Systems | 20120089954 | 20120412 | Methods, systems, and computer program product for parallelizing tasks in processing an electronic circuit design |
| CDNS | Cadence Design Systems | 20120089879 | 20120412 | Method and system for identifying power defects using test pattern switching activity |
| CDNS | Cadence Design Systems | 20120089872 | 20120412 | Method and system for subnet defect diagnostics through fault compositing |
| CDNS | Cadence Design Systems | 20120047434 | 20120223 | Method to preview an undo/redo list |
| CDNS | Cadence Design Systems | 20120038648 | 20120216 | Method and system for implementing, controlling, and interfacing with circuit simulators |
| CDNS | Cadence Design Systems | 20120030644 | 20120202 | Method and system for implementing stacked vias |
| CDNS | Cadence Design Systems | 20120023471 | 20120126 | Method, apparatus, and article of manufacture for providing in situ, customizable information in designing electronic circuits with electrical awareness |
| CDNS | Cadence Design Systems | 20120023467 | 20120126 | Methods, systems, and articles of manufacture for implementing electronic circuit designs with electrical awareness |
| CDNS | Cadence Design Systems | 20120023465 | 20120126 | Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awareness |
| CDNS | Cadence Design Systems | 20120022846 | 20120126 | Methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness |
| CDNS | Cadence Design Systems | 20110314432 | 20111222 | Method and system for implementing efficient locking to facilitate parallel processing of ic designs |
| CDNS | Cadence Design Systems | 20110276908 | 20111110 | System and method for management of controls in a graphical user interface |
| CDNS | Cadence Design Systems | 20110270556 | 20111103 | Method and system for implementing circuit simulators |
| CDNS | Cadence Design Systems | 20110252389 | 20111013 | Reducing critical cycle delay in an integrated circuit design through use of sequential slack |
| CDNS | Cadence Design Systems | 20110239177 | 20110929 | Method and system for approximate placement in electronic designs |
| CDNS | Cadence Design Systems | 20110239168 | 20110929 | Intelligent pattern signature based on lithography effects |
| CDNS | Cadence Design Systems | 20110219320 | 20110908 | Method and system for searching for graphical objects of a design |
| CDNS | Cadence Design Systems | 20110219341 | 20110908 | Method, system, and program product for interactive checking for double pattern lithography violations |
| CDNS | Cadence Design Systems | 20110219352 | 20110908 | Method and system for searching and replacing graphical objects of a design |
| CDNS | Cadence Design Systems | 20110192994 | 20110811 | System and method of electron beam writing |
| CDNS | Cadence Design Systems | 20110173582 | 20110714 | Method and apparatus for rule-based automatic layout parasitic extraction in a multi-technology environment |
| CDNS | Cadence Design Systems | 20110167400 | 20110707 | Method and mechanism for extraction and recognition of polygons in an ic design |
| CDNS | Cadence Design Systems | 20110161899 | 20110630 | Method, system, and computer program product for implementing multi-power domain digital / mixed-signal verification and low power simulation |
| CDNS | Cadence Design Systems | 20110161900 | 20110630 | Method, system, and computer program product for implementing multi-power domain digital / mixed signal verification and low power simulation |
| CDNS | Cadence Design Systems | 20110154276 | 20110623 | Method and system for optimally placing and assigning interfaces in a cross-fabric design environment |
| CDNS | Cadence Design Systems | 20110153289 | 20110623 | Method and system for specifying system level constraints in a cross-fabric design environment |
| CDNS | Cadence Design Systems | 20110153288 | 20110623 | Method and system for optimally connecting interfaces across mutiple fabrics |
| CDNS | Cadence Design Systems | 20110153272 | 20110623 | Methods and systems for high sigma yield estimation using reduced dimensionality |
| CDNS | Cadence Design Systems | 20110153271 | 20110623 | Methods and systems for high sigma yield estimation |
| CDNS | Cadence Design Systems | 20110133806 | 20110609 | Integrated clock gating cell for circuits with double edge triggered flip-flops |
| CDNS | Cadence Design Systems | 20110131544 | 20110602 | Visualization and information display for shapes in displayed graphical images based on a cursor |
| CDNS | Cadence Design Systems | 20110131543 | 20110602 | Visualization and information display for shapes in displayed graphical images |
| CDNS | Cadence Design Systems | 20110131525 | 20110602 | Visualization and information display for shapes in displayed graphical images based on user zone of focus |
| CDNS | Cadence Design Systems | 20110113393 | 20110512 | Method, system, and program product for routing an integrated circuit to be manufactured by sidewall-image transfer |
| CDNS | Cadence Design Systems | 20110099530 | 20110428 | Spine selection mode for layout editing |
| CDNS | Cadence Design Systems | 20110093826 | 20110421 | Method and system for model-based routing of an integrated circuit |
| CDNS | Cadence Design Systems | 20110083114 | 20110407 | Method and system for re-using digital assertions in a mixed signal design |
| CDNS | Cadence Design Systems | 20110078651 | 20110331 | Method and system for test reduction and analysis |
| CDNS | Cadence Design Systems | 20110066997 | 20110317 | Modeling and simulating device mismatch for designing integrated circuits |
| CDNS | Cadence Design Systems | 20110066995 | 20110317 | Annotation management for hierarchical designs of integrated circuits |
| CDNS | Cadence Design Systems | 20110061034 | 20110310 | Method and system for implementing graphically editable parameterized cells |
| CDNS | Cadence Design Systems | 20100287493 | 20101111 | Method and system for viewing and editing an image in a magnified view |
| CDNS | Cadence Design Systems | 20100205575 | 20100812 | Methods, systems, and computer-program products for item selection and positioning suitable for high-altitude and context sensitive editing of electrical circuits |
| CDNS | Cadence Design Systems | 20100205572 | 20100812 | Adaptive mesh resolution in electric circuit simulation and analysis |
| CDNS | Cadence Design Systems | 20100083289 | 20100401 | Method and apparatus for implementing a task-based interface in a logic verification system |
| CDNS | Cadence Design Systems | 20100064271 | 20100311 | Method and system for simulating state retention of an rtl design |
| CDNS | Cadence Design Systems | 20100049935 | 20100225 | Management of very large streaming data sets for efficient writes and reads to and from persistent storage |
| CDNS | Cadence Design Systems | 20100004902 | 20100107 | Spine selection mode for layout editing |
