Real Time Touch



new TOP 200 Companies filing patents this week

new Companies with the Most Patent Filings (2010+)




Real Time Touch

Cavium Inc patents


Recent patent applications related to Cavium Inc. Cavium Inc is listed as an Agent/Assignee. Note: Cavium Inc may have other listings under different names/spellings. We're not affiliated with Cavium Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "C" | Cavium Inc-related inventors


Protocol independent programmable switch (pips) for software defined data center networks

A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters... Cavium Inc

Session based packet mirroring in a network asic

A forwarding pipeline of a forwarding engine includes a mirror bit mask vector with one bit per supported independent mirror session. Each bit in the mirror bit mask vector can be set at any point in the forwarding pipeline when the forwarding engine determines that conditions for a corresponding mirror... Cavium Inc

Engine architecture for processing finite automata

An engine architecture for processing finite automata includes a hyper non-deterministic automata (HNA) processor specialized for non-deterministic finite automata (NFA) processing. The HNA processor includes a plurality of super-clusters and an HNA scheduler. Each super-cluster includes a plurality of clusters. Each cluster of the plurality of clusters includes a plurality... Cavium Inc

Managing virtual-address caches for multiple memory page sizes

A translation lookaside buffer stores information indicating respective page sizes for different translations. A virtual-address cache module manages entries, where each entry stores a memory block in association with a virtual address and a code representing at least one page size of a memory page on which the memory block... Cavium Inc

Method and table aging in a network switch

Embodiments of the present invention relate to a centralized table aging module that efficiently and flexibly utilizes an embedded memory resource, and that enables and facilitates separate network controllers. The centralized table aging module performs aging of tables in parallel using the embedded memory resource. The table aging module performs... Cavium Inc

Systems and methods for vectorized fft for multi-dimensional convolution operations

A new approach is proposed to support efficient convolution for deep learning by vectorizing multi-dimensional input data for multi-dimensional fast Fourier transform (FFT) and direct memory access (DMA) for data transfer. Specifically, a deep learning processor (DLP) includes a plurality of tensor engines each configured to perform convolution operations by... Cavium Inc

Process-compensated level-up shifter circuit

A level-up shifter circuit is suitable for high speed and low power applications. The circuit dissipates almost no static power, or leakage current, compared to conventional designs and can preserve the signal's duty cycle even at high data rates. This circuit can be used with a wide range of power... Cavium Inc

Method and efficient and flexible direct memory access

Method and system embodying the method for a direct memory access between a data storage and a data processing device via one or more direct memory access units, comprising transferring data between the data storage and a first direct memory access engine of a respective one or more direct memory... Cavium Inc

Methods and frequency offset estimation

Methods and apparatus for frequency offset estimation are disclosed. In an exemplary embodiment, a method includes determining a demodulation reference signal (DMRS) frequency offset estimate from DMRS symbols in a received signal, and determining a cyclic prefix (CP) frequency offset estimate from cyclic prefix values in the received signal. The... Cavium Inc

Systems and methods for virtio based optimization of data packet paths between a virtual machine and a network device for live virtual machine migration

A new approach is proposed that contemplates systems and methods to support virtio-based data packet path optimization for live virtual machine (VM) migration for Linux. Specifically, a data packet receiving (Rx) path and a data packet transmitting (Tx) path between a VM running on a host and a virtual function... Cavium Inc

Managing memory access requests with prefetch for streams

Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks in a main memory includes: storing stream information identifying recognized streams that were recognized based on previously received memory access requests, where one or... Cavium Inc

Admission control for memory access requests

Managing memory access requests for a plurality of processor cores includes: storing admission control information for determining whether or not to admit a predetermined type of memory access request into a shared resource that is shared among the processor cores and includes one or more cache levels of a hierarchical... Cavium Inc

Method of dynamically renumbering ports and an apparatus thereof

Embodiments of the apparatus of dynamically renumbering ports relate to a network chip that minimizes the total logic on the network chip by limiting the number of states that needs to be preserved for all ports on the network chip. Each pipe on the network chip implements a dynamic port... Cavium Inc

Voltage regulator with adaptive bias network

A low drop-out voltage regulator includes an error amplifier that generates an amplified error voltage, the error amplifier including a first input for receiving a reference voltage, a second input for receiving a feedback voltage, a bias terminal for receiving an adaptive bias current, and an output. A pass gate... Cavium Inc

Systems and methods for text analytics processor

A hardware-based programmable text analytics processor has a plurality of components including at least a tokenizer, a tagger, a parser, and a classifier. The tokenizer processes an input stream of unstructured text data and identifies a sequence of tokens along with their associated token ids. The tagger assigns a tag... Cavium Inc

Systems and methods for deep learning processor

A hardware-based programmable deep learning processor (DLP) is proposed, wherein the DLP comprises with a plurality of accelerators dedicated for deep learning processing. Specifically, the DLP includes a plurality of tensor engines configured to perform operations for pattern recognition and classification based on a neural network. Each tensor engine includes... Cavium Inc

Apparatus and enabling flexible key in a network switch

A network switch to support flexible lookup key generation comprises a control CPU configured to run a network switch control stack. The network switch control stacks is configured to manage and control operations of a switching logic circuitry, provide a flexible key having a plurality of possible fields that constitute... Cavium Inc

Method and dynamic virtual system on chip

A processor device comprises a plurality of virtual systems on chip, configured to utilize resources of a plurality of resources in accordance with a resource alignment between the plurality of virtual systems on chip and the plurality of resources. The processor device may further comprises a resource aligning unit configured... Cavium Inc

Method and shared multi-port memory access

Method and system embodying the method for a general address transformation for an access to a shared memory comprising at least one tile and each tile comprising at least one memory bank, comprising selecting a mode of a general address transformation; providing a general address comprising a plurality of bits... Cavium Inc

Managing synonyms in virtual-address caches

A virtual-address cache module receives at least a portion of a virtual address and in response indicates a hit or a miss. A first cache structure stores only memory blocks with virtual addresses that are members of a set of multiple synonym virtual addresses that have all been previously received... Cavium Inc

Managing translation invalidation

Managing translation invalidation includes: in response to determining that a first invalidation message (IM) applies to a subset of virtual addresses (VAs) consisting of fewer than all VAs associated with a first set of translation context (TC) values, searching VA-indexed structure(s) to find and invalidate any entries that correspond to... Cavium Inc

Method and system for compressing data for a translation look aside buffer (tlb)

An embodiment of the present disclosure includes a method for compressing data for a translation look aside buffer (TLB). The method includes: receiving an identifier at a content addressable memory (CAM), the identifier having a first bit length; compressing the identifier based on a location within the CAM the identifier... Cavium Inc

Multiple ethernet ports and port types using a shared data path

In an embodiment an interface unit includes a transmit pipeline configured to transmit egress data, and a receive pipeline configured to receive ingress data. At least one of the transmit pipeline and the receive pipeline being may be configured to provide shared resources to a plurality of ports. The shared... Cavium Inc

Method of using bit vectors to allow expasion and collapse of header layers within packets for enabling flexible modifications and an apparatus thereof

Embodiments of the apparatus for modifying packet headers relate to a use of bit vectors to allow expansion and collapse of protocol headers within packets for enabling flexible modification. A rewrite engine expands each protocol header into a generic format and applies various commands to modify the generalized protocol header.... Cavium Inc

Method and system for reconfigurable parallel lookups using multiple shared memories

Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles.... Cavium Inc

Method and system for reconfigurable parallel lookups using multiple shared memories

Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles.... Cavium Inc

Apparatus and optimized n-write/1-read port memory design

An optimized design of n-write/1-read port memory comprises a memory unit including a plurality of memory banks each having one write port and one read port configured to write data to and read data from the memory banks, respectively. The memory further comprises a plurality of write interfaces configured to... Cavium Inc

Apparatus and supporting multiple virtual switch instances on a network switch

A network switch to support multiple virtual switch instances comprises a control CPU configured to run a plurality of network switch control stacks, wherein each of the network switch control stacks is configured to manage and control operations of one or more virtual switch instances of a switching logic circuitry... Cavium Inc

Method and managing global chip power on a multicore system on chip

According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is... Cavium Inc

Method and virtualization

A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurality of virtual systems on chip and a configuring... Cavium Inc

Method and determining metric for selective caching

System and method determining metric for selective caching, comprising determining a result of an access to a cache for at least one tracked attribute; determining a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance... Cavium Inc

Methods and providing an fft engine using a reconfigurable single delay feedback architecture

Methods and apparatus for providing an FFT engine using a reconfigurable single delay feedback architecture. In one aspect, an apparatus includes a radix-2 (R2) single delay feedback (SDF) stage that generates a radix-2 output and a radix-3 (R3) SDF stage that generates a radix-3 output. The apparatus also includes one... Cavium Inc

Packet processing system, utilizing memory sharing

A packet processing system having a control path memory of a control path subsystem and a datapath memory of a datapath subsystem. The datapath subsystem stores packet data of incoming packets and the control path subsystem performs matches of a subset of packet data, or a hash of the packet... Cavium Inc

Collapsed address translation with multiple page sizes

A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer... Cavium Inc

07/06/17 / #20170192935

Methods and a vector memory subsystem for use with a programmable mixed-radix dft/idft processor

A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data... Cavium Inc

07/06/17 / #20170192936

Methods and providing a programmable mixed-radix dft/idft processor using vector engines

A programmable vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values is disclosed. In an exemplary embodiment, an apparatus includes a memory bank and a vector data path pipeline coupled to the memory bank. The apparatus also includes a configurable mixed radix engine coupled to the vector data... Cavium Inc

07/06/17 / #20170195281

Methods and twiddle factor generation for use with a programmable mixed-radix dft/idft processor

Twiddle factor generation for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes look-up table logic that receives twiddle control factors and outputs a selected twiddle factor scaler value (TFSV), a base vector generator that generates... Cavium Inc

07/06/17 / #20170195900

Methods and configuring a front end to process multiple sectors with multiple radio frequency frames

Methods and apparatus for configuring a front end to process multiple sectors with multiple radio frequency frames. In an exemplary embodiment, a method includes decoding instructions included in a job description list, and configuring one or more processing functions of a transceiver to process a radio signal associated with a... Cavium Inc

06/29/17 / #20170187623

Method of identifying internal destinations of network packets and an apparatus thereof

Embodiments of the apparatus of identifying internal destinations of network packets relate to a network chip that allows flexibility in handling packets. The handling of packets can be a function of what the packet contents are or where the packets are from. The handling of packets can also be a... Cavium Inc

06/15/17 / #20170170930

Methods and providing soft and blind combining for pusch acknowledgement (ack) processing

Methods and apparatus for providing soft and blind combining for PUSCH acknowledgement (ACK) processing. In an exemplary embodiment, a method includes soft-combining acknowledgement (ACK) bits received from a UE that are contained in a received sub-frame of symbols. The ACK bits are soft-combined using a plurality of scrambling sequences to... Cavium Inc

06/15/17 / #20170171854

Methods and providing soft and blind combining for pusch cqi processing

Methods and apparatuses for providing soft and blind combining for PUSCH CQI processing are disclosed. In an exemplary embodiment, a method includes generating a plurality of hypothetical rank indicator (RI) values associated with a user equipment (UE), and concurrently soft-combining channel quality information (CQI) and RI information associated with the... Cavium Inc

06/08/17 / #20170161215

Packet processing system, utilizing a port client chain

A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the... Cavium Inc

06/08/17 / #20170161402

Systems and methods for dynamic regression test generation using coverage-based clustering

A new approach is proposed that contemplates systems and methods to support dynamic regression test generation for an IC design based upon coverage-based clustering of RTL modules in the design. First, coverage data for code coverage by a plurality of RTL modules in the IC design are collected and a... Cavium Inc

04/06/17 / #20170097895

Input output value prediction with physical or virtual addressing for virtual environment

Method and system embodying the method for input/output value determination at a processor core, comprising generating an I/O instruction comprising at least a physical or a virtual address; comparing the address with a relevant database of I/O devices addresses. When the comparing is successful determining the I/O device or a... Cavium Inc

03/16/17 / #20170075754

Apparatus and parallel crc units for variably-sized data frames

A cyclic redundancy check (CRC) device configured to support parallel calculation of a CRC value for a data frame comprises a plurality of CRC processing units each configured to accept one of a plurality of data segments of the data frame of a variable size that can be unknown to... Cavium Inc

03/16/17 / #20170075845

Systems and methods for offloading link aggregation to a host bus adapter (hba) in single root i/o virtualization (sriov) mode

A new approach is proposed to offload of link aggregation from a host to a HBA in SRIOV mode. The HBA first creates one or more link aggregation offload engines each having one or more physical ports and to establish a first link between a VM running on the host... Cavium Inc

03/02/17 / #20170063692

Method and providing a low latency transmission system using adaptive buffering estimation

One aspect of the present invention discloses a network system capable of transmitting and processing audio video (“A/V”) data with enhanced quality of service (“QoS”). The network system includes a transmitter, a transmission channel, an adjustable decoder buffer, and a decoder. The transmitter contains an encoder able to encode A/V... Cavium Inc

03/02/17 / #20170063808

Systems and methods for offloading ipsec processing to an embedded networking device

A new approach is proposed that contemplates systems and methods to support a mechanism to offload IPSec/IKE processing of virtual machines (VMs) running on a host to an embedded networking device, which serves as a hardware accelerator for the VMs that need to have secured communication with a remote device/server... Cavium Inc

03/02/17 / #20170063959

Method and providing a low latency transmission system using adjustable buffers

One aspect of the present invention discloses a network system capable of transmitting and processing audio video (“A/V”) data with enhanced quality of service (“QoS”). The network system includes a transmitter, a transmission channel, an adjustable decoder buffer, and a decoder. The transmitter contains an encoder able to encode A/V... Cavium Inc

01/26/17 / #20170024159

Method and virtualization

A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurality of virtual systems on chip and a configuring... Cavium Inc

01/26/17 / #20170024346

Apparatus and on-chip crossbar design in a network switch using benes network

An on-chip crossbar of a network switch comprising a central arbitration component configured to allocate packet data requests received from destination port groups to memory banks. The on-chip crossbar further comprises a Benes routing network comprising a forward network having a plurality of pipelined forward routing stages and a reverse... Cavium Inc

01/05/17 / #20170003905

Local instruction ordering

A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.... Cavium Inc








ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009



###

This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Cavium Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Cavium Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

###