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Cavium Inc patents

Recent patent applications related to Cavium Inc. Cavium Inc is listed as an Agent/Assignee. Note: Cavium Inc may have other listings under different names/spellings. We're not affiliated with Cavium Inc, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "C" | Cavium Inc-related inventors




Date Cavium Inc patents (updated weekly) - BOOKMARK this page
04/06/17Input output value prediction with physical or virtual addressing for virtual environment
03/16/17Apparatus and parallel crc units for variably-sized data frames
03/16/17Systems and methods for offloading link aggregation to a host bus adapter (hba) in single root i/o virtualization (sriov) mode
03/02/17Method and providing a low latency transmission system using adaptive buffering estimation
03/02/17Systems and methods for offloading ipsec processing to an embedded networking device
03/02/17Method and providing a low latency transmission system using adjustable buffers
01/26/17Method and virtualization
01/26/17Apparatus and on-chip crossbar design in a network switch using benes network
01/05/17Local instruction ordering
12/01/16Systems and methods for offloading inline ssl processing to an embedded networking device
10/27/16Method for work scheduling in a multi-chip system
10/27/16Hierarchical statisically multiplexed counters and a method thereof
10/06/16Method and handling modified constellation mapping using a soft demapper
10/06/16Method and discarding unused points from constellation mapping rule using transceiver processing hardware ("tph")
10/06/16Systems and methods for timing adjustment of metadata paths in a network switch under timing constraints
09/22/16Managing address-independent page attributes
09/22/16Apparatus and generating lookups and making decisions for packet modifying and forwarding in a software-defined network engine
09/15/16System and configuring a plurality of registers with soft error detection and low wiring complexity
09/15/16Systems and methods for live upgrade and update of firmware on an embedded networking device
09/15/16Design and verification of a multichip coherence protocol
09/08/16Communication and control topology for efficient testing of sets of devices
09/08/16Managing reuse information in caches
09/08/16Managing reuse information for memory pages
09/08/16Managing reuse information with multiple translation stages
09/01/16Apparatus and collecting responses to a plurality of parallel lookup queries from a flow of packets at a network switch
08/25/16Method and generating parallel lookup requests utilizing a super key
08/25/16System and rule matching in a processor
08/11/16Reconfigurable interconnect element with local lookup tables shared by multiple packet processing engines
08/11/16Content search mechanism using finite automata
07/07/16Protocol independent programmable switch (pips) software defined data center networks
06/23/16Network switching with layer 2 switch coupled co-resident data-plane and network interface controllers
06/09/16Systems and methods for enabling access to elastic storage over a network as local storage via a logical storage controller
06/09/16Systems and methods for hardware accelerated metering for openflow protocol
05/26/16Systems and methods for hardware accelerated timer implementation for openflow protocol
05/26/16Systems and methods for cloud-based web service security management basedon hardware security module
05/19/16Testing semiconductor devices
05/19/16Debug interface for multiple cpu cores
05/19/16Automatic data rate matching
05/19/16Distributed timer subsystem across multiple devices
05/19/16Independent ordering of independent transactions
05/19/16Programmable ordering and prefetch
05/19/16High performance shifter circuit
05/19/16Bypass fifo for multiple virtual channels
05/19/16Distributing resource requests in a computing system
05/19/16Carry chain for simd operations
05/19/16Managing history information for branch prediction
05/19/16Sharing resources in a multi-context computing system
05/19/16Apparatus and distributed instruction trace in a processor system
05/19/16Filtering translation lookaside buffer invalidations
05/19/16Instruction cache translation management
05/19/16Instruction ordering for in-progress operations
05/19/16Translation lookaside buffer management
05/19/16Caching tlb translations using a unified page table walker cache
05/19/16Method and system for compressing data for a translation look aside buffer (tlb)
05/19/16Translation lookaside buffer invalidation suppression
05/19/16Multiple memory management units
05/19/16Managing buffered communication between sockets
05/19/16Managing buffered communication between cores
05/19/16Distributed interrupt scheme in a multi-processor system
05/19/16Register access control among multiple devices
05/19/16Distributed timer subsystem
05/19/16Arbitrated access to resources among multiple devices
05/19/16Programmable validation of transaction requests
05/19/16Implementing 128-bit simd operations on a 64-bit datapath
05/19/16Method to measure edge-rate timing penalty of digital integrated circuits
Patent Packs
05/19/16Managing skew in data signals
05/19/16Managing skew in data signals with adjustable strobe
05/19/16Controlled multi-step de-alignment of clocks
05/19/16Controlled dynamic de-alignment of clocks
05/19/16Managing skew in data signals with multiple modes
05/19/16Frequency division clock alignment
05/19/16Frequency division clock alignment using pattern selection
05/19/16Apparatus and scalable and flexible table search in a network switch
05/19/16Management of an over-subscribed shared buffer
05/19/16Method and system for improved load balancing of received network traffic
05/19/16Apparatus and a multi-entity secure software transfer
05/19/16Network switching with co-resident data-plane and network interface controllers
05/12/16Adder decoder
05/12/16Hybrid wildcard match table
04/21/16Flexible instruction execution in a processor pipeline
Patent Packs
04/21/16Flexible instruction execution in a processor pipeline
04/21/16Systems and methods for allowing flexible chip configuration by external entity while maintaining secured boot environment
03/24/16Method and improving data integrity using compressed soft information
03/24/16Method and quantizing soft information using non-linear llr quantization
03/24/16Method and quantizing soft information using linear quantization
03/17/16Systems and methods for enabling local caching for remote storage devices over a network via nvme controller
03/10/16Anchored patterns
03/10/16Scope in decision trees
02/04/16Method and an co-processor data plane virtualization
01/28/16Systems and methods for hardware security module as certificate authority for network-enabled devices
01/21/16Reverse nfa generation and processing
01/21/16Reverse nfa generation and processing
01/14/16Managing instruction order in a processor pipeline
01/14/16Managing instruction order in a processor pipeline
12/17/15Qos based dynamic execution engine selection
12/10/15Systems and methods for secured backup of hardware security modules for cloud-based web services
12/10/15Systems and methods for secured hardware security module communication with web service hosts
12/10/15Systems and methods for secured key management via hardware security module for cloud-based web services
12/10/15Systems and methods for high availability of hardware security modules for cloud-based web services
12/10/15Systems and methods for secured communication hardware security module and network-enabled devices
11/05/15Systems and methods for nvme controller virtualization to support multiple virtual machines running on a host
11/05/15Systems and methods for enabling local caching for remote storage devices over a network via nvme controller
11/05/15Systems and methods for enabling value added services for extensible storage devices over a network via nvme controller
11/05/15Systems and methods for supporting migration of virtual machines accessing remote storage devices over network via nvme controllers
11/05/15Systems and methods for enabling access to extensible storage devices over a network as local storage via nvme controller
11/05/15Systems and methods for supporting hot plugging of remote storage devices accessed over a network via nvme controller
10/22/15Systems and methods for automated functional coverage generation and management for ic design protocols
10/15/15Processing of finite automata based on memory hierarchy
10/15/15Compilation of finite automata based on memory hierarchy
10/15/15Processing of finite automata based on a node cache
Social Network Patent Pack
10/08/15Messaging with flexible transmit ordering
10/08/15Phased bucket pre-fetch in a network processor
09/17/15Method and low latency exchange of data between a processor and coprocessor
09/10/15Method and memory allocation in a multi-node system
09/10/15Method and system for work scheduling in a multi-chip system
09/10/15Multi-core network processor interconnect with multi-node connection
09/10/15Inter-chip interconnect protocol for a multi-chip system
09/10/15Method and system for ordering i/o access in a multi-node environment
09/03/15Method and power gating hardware components in a chip device
09/03/15Partitioned error code computation
Patent Packs
09/03/15System on chip link layer protocol
09/03/15Packet output processing
09/03/15Packet scheduling in a network processor
09/03/15Packet shaping in a network processor
08/27/15Apparatus and software enabled access to protected hardware resources
08/27/15Independent ordering of independent threads
08/27/15Cdr voter with improved frequency offset tolerance
08/27/15Multiple ethernet ports and port types using a shared data path
08/06/15Method and an pre-fetching and processing work for procesor cores in a network processor
08/06/15Finite automata processing based on a top of stack (tos) memory
08/06/15Method and optimizing finite automata processing
08/06/15Method and an work packet queuing, scheduling, and ordering with conflict queuing
08/06/15Method and an work request arbitration in a network processor
07/23/15Work request processor
07/16/15Block mask register
07/09/15Condition code approach for comparing rule and key data that are provided in portions
07/09/15Method and compiling search trees for processing request keys based on a key size supported by underlying processing elements
07/09/15Lookup cluster complex
07/09/15Processing request keys based on a key size supported by underlying processing elements
07/09/15Methods and systems for single instruction multiple data programmable packet parsers
07/09/15Packet parsing engine
07/09/15Methods and systems for distribution of packets among parsing clusters
07/09/15Methods and systems for resource management in a single instruction multiple data packet parsing cluster
07/09/15Methods and systems for flexible packet classification
07/09/15Floating mask generation for network packet flow
07/02/15Method and an converting interrupts into scheduled events
07/02/15Method and an interupt collecting and reporting
07/02/15Method and system for skipping over group(s) of rules based on skip group rule
07/02/15Method and processing of finite automata
07/02/15Multi-function delay locked loop
Patent Packs
07/02/15Look-aside processor unit with internal and external access for multicore processors
07/02/15Multi-rule approach to encoding a group of rules
06/25/15Method and an memory address allignment
06/25/15System and a a remote direct memory access over converged ethernet
06/25/15Method and an virtualization of a quality-of-service
06/18/15Dram address protection
06/18/15Virtualized network interface for remote direct memory access over converged ethernet
06/18/15Virtualized network interface for lockdown and overlay of data in transmitted packets
06/04/15Systems and methods for specifying. modeling, implementing and verifying ic design protocols
05/21/15Virtualized network interface for tcp reassembly buffer allocation
05/21/15On-chip memory (ocm) physical bank parallelism
05/14/15Method and apparatus to represent a processor context with fewer bits
04/30/15Packet classification
04/30/15Method and managing processing thread migration between clusters within a processor
04/09/15Data strobe generation
04/09/15Method and conditional storing of data using a compare-and-swap based approach
04/09/15Method and supporting wide operations using atomic sequences
04/09/15Method and aligning signals
04/02/15Clock multiplexing and repeater network
04/02/15Method and reference voltage calibration in a single-ended receiver
Social Network Patent Pack
04/02/15Dynamically adjusting supply voltage based on monitored chip temperature
04/02/15Method and amplifier offset calibration
04/02/15Method and calibrating an input interface
04/02/15Protocol switching over multi-network interface
04/02/15Auto-blow memory repair
03/26/15Semiconductor with virtualized computation and switch resources
03/26/15Memory interface with integrated tester
03/26/15Merged tlb structure for multiple sequential address translations
03/26/15Maintenance of cache and tags in a translation lookaside buffer
03/26/15Translation bypass in multi-stage address translation
03/26/15Collapsed address translation with multiple page sizes
03/26/15Method and managing global chip power on a multicore system on chip
03/05/15Scannable flop with a single storage element
03/05/15Multiplexer flop
03/05/15Clock gated delay line based on setting value
03/05/15Generating a non-deterministic finite automata (nfa) graph for regular expression patterns with advanced features
03/05/15Traversal with arc configuration information
03/05/15Engine architecture for processing finite automata
03/05/15Memory management for finite automata processing
03/05/15Distributed delay locked loop
Social Network Patent Pack
03/05/15Method and compilation of finite automata
03/05/15System and method to traverse a non-deterministic finite automata (nfa) graph generated for regular expression patterns with advanced features
03/05/15Method and processing finite automata
01/29/15Network interface card with virtual switch and traffic flow policy enforcement
01/15/15Word boundary lock
01/08/15Method and power control
12/25/14Low latency rate control system and method
12/18/14System and method to provide non-coherent access to a coherent memory system
10/30/14Video encoder bit estimator for macroblock encoding
10/23/14Method and managing write back cache
09/18/14Apparatus and providing sort offload
09/18/14Apparatus and media access control scheduling with a sort hardware coprocessor
09/18/14Apparatus and media access control scheduling with a priority calculation hardware coprocessor
09/18/14Scheduling scheduling rule matching in a processor
09/18/14Method and an accumulator scoreboard for out-of-order rule response handling
09/18/14Batch incremental update
09/18/14Nsp manager
09/18/14Merging independent writes, separating dependent and independent writes, and error roll back
09/18/14Method and data integrity checking in a processor
07/31/14Work migration in a processor
07/03/14System and optimizing use of channel state information
07/03/14Lookup front end packet output processor
05/01/14Lookup front end packet input processor
03/27/14Level-up shifter circuit
03/20/14Messaging with flexible transmit ordering
02/27/14Multiple core session initiation protocol (sip)
01/30/14Content search mechanism that uses a deterministic finite automata (dfa) graph, a dfa state machine, and a walker process
11/28/13High speed variable bandwidth ring-based system
09/26/13System and compression and decompression
09/26/13Lookup cluster complex
Social Network Patent Pack
09/26/13Hardware and software association and authentication
09/12/13Phased bucket pre-fetch in a network processor
09/05/13Duplication in decision trees
08/22/13Rule modification in decision trees
05/23/13Reverse nfa generation and processing
05/02/13Packet traffic control in a network processor
05/02/13Work request processor
05/02/13Network processor with distributed trace buffers
05/02/13Multi-core interconnect in a network processor
04/25/13Packet priority in a network processor
04/25/13Multi-protocol serdes phy apparatus
04/25/13Word boundary lock
04/25/13Polarity detection
04/25/13Input output bridging
04/25/13System and method to reduce memory access latencies using selective replication across multiple memory ports
04/25/13System and method to provide non-coherent access to a coherent memory system
04/25/13Bit error rate impact reduction
04/25/13Method and power control
04/18/13Qos based dynamic execution engine selection
04/18/13Processor with dedicated virtual functions and dynamic assignment of functional resources
04/18/13Processor with efficient work queuing
04/04/13Decision tree level merging
03/14/13Method and multiple access of plural memory banks
03/07/13Lookup front end packet input processor
03/07/13Identifying duplication in decision trees
02/14/13Packet classification
02/07/13Lookup front end packet input processor
02/07/13Lookup cluster complex
02/07/13System and storing lookup request rules in multiple memories







ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009



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