Real Time Touch



new TOP 200 Companies filing patents this week

new Companies with the Most Patent Filings (2010+)




Real Time Touch

Chipmos Technologies Inc patents


Recent patent applications related to Chipmos Technologies Inc. Chipmos Technologies Inc is listed as an Agent/Assignee. Note: Chipmos Technologies Inc may have other listings under different names/spellings. We're not affiliated with Chipmos Technologies Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "C" | Chipmos Technologies Inc-related inventors


Semiconductor package and manufacturing method thereof

A semiconductor package includes a first chip, a second chip, a plurality of first conductive bumps, a plurality of second conductive bumps and an underfill. The first chip includes a first active surface having a chip bonding zone, a plurality of first inner pads in the chip bonding zone and a plurality of first outer pads out of the chip bonding zone. ... Chipmos Technologies Inc

Semiconductor device

Provided is a semiconductor device including a substrate, a pad, a protective layer, a plurality of convex patterns, a redistribution layer (rdl), and a bump. The pad is disposed on the substrate. ... Chipmos Technologies Inc

Semicondcutor light-emitting device and fabricating method thereof

A semiconductor light-emitting device including a light-emitting diode chip and an electrode disposed thereon is provided. The electrode at least includes a plated silver alloy (ag1-xyx) layer, wherein the y of the ag1-xyx layer includes metals forming a complete solid solution with ag at arbitrary weight percentage, and the x of the ag1-xyx layer is in a range from about 0.02 to 0.15. ... Chipmos Technologies Inc

Multi-chip package structure manufacturing process and wafer level chip package structure manufacturing process

A wafer level chip package manufacturing process is provided. A wafer includes a plurality of first chips and a circuit layer disposed on the first chips, wherein each of the first chips has a chip bonding region, a plurality of first inner pads located in the chip bonding region and a plurality of first outer pads located outside the chip bonding region, the circuit layer includes a plurality of insulating layers, the insulating layers have at least one groove, the groove is disposed between the first inner pads and the first outer pads, and the groove surrounds the first inner pads. ... Chipmos Technologies Inc

Multi-chip package structure, wafer level chip package structure and manufacturing process thereof

A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. ... Chipmos Technologies Inc








ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009



###

This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Chipmos Technologies Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Chipmos Technologies Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

###