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Conversant Intellectual Property Management Inc
Conversant Intellectual Property Management Incorporated
  

Conversant Intellectual Property Management Inc patents

Recent patent applications related to Conversant Intellectual Property Management Inc. Conversant Intellectual Property Management Inc is listed as an Agent/Assignee. Note: Conversant Intellectual Property Management Inc may have other listings under different names/spellings. We're not affiliated with Conversant Intellectual Property Management Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "C" | Conversant Intellectual Property Management Inc-related inventors




Date Conversant Intellectual Property Management Inc patents (updated weekly) - BOOKMARK this page
12/03/15Methods and devices for creating a shared music station
10/01/15Apparatus, system, and connecting devices
10/01/15Scheduling wireless networks
08/27/15System and controlling a wireless network
03/19/15Power saving in wireless network entities
01/29/15Frequency division multiplexing system with selectable rate
01/15/15Port packet queuing
11/20/14Clock reproducing and timing method in a system having a plurality of devices
10/30/14Method and system for providing dc power on local telephone lines
09/11/14Telephone outlet with packet telephony adapter, and a network using same
08/28/14Position determination of mobile stations in a wireless network
07/31/14Trunking in a matrix
07/24/14Power saving in wireless network entities
11/09/17Clock mode determination in a memory system
10/26/17Non-volatile semiconductor memory having multiple external power supplies
10/05/17Power managers for an integrated circuit
09/21/17Wide frequency range delay locked loop
08/10/17Nand flash memory having multiple cell substrates
07/20/17Flash memory system
06/29/17Non-volatile memory serial core architecture
06/08/17Clock mode determination in a memory system
05/25/17U-shaped common-body type cell string
05/18/17Memory device with manufacturable cylindrical storage node
04/27/17Non-volatile semiconductor memory having multiple external power supplies
04/20/17Method and system for accessing a flash memory device
03/16/17Memory with output control
01/05/17Multipage program scheme for flash memory
12/08/16Circuit for clamping current in a charge pump
11/03/16Dynamic random access memory with fully independent partial array refresh function
10/27/16Low leakage and data retention circuitry
10/06/16Clock mode determination in a memory system
09/22/16Dynamic impedance control for input/output buffers
08/11/16Access transistor of a nonvolatile memory device and fabricating same
07/28/16Frequency division multiplexing system with selectable rate
07/21/16Memory with output control
07/07/16Method and system for accessing a flash memory device
06/16/16Polymer memory
06/02/16Memory device with manufacturable cylindrical storage node
05/19/16Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage
04/07/16Non-volatile semiconductor memory having multiple external power supplies
04/07/16Using interrupted through-silicon-vias in integrated circuits adapted for stacking
03/24/16Structure and manufacture of memory device with thin silicon body
03/24/16Power managers for an integrated circuit
03/10/16Memory system and method using stacked memory device dice
03/03/16U-shaped common-body type cell string
02/18/16Vertical gate stacked nand and row decoder for erase operation
02/04/16Dynamic random access memory and boosted voltage producer therefor
02/04/16Relay wireless networks
01/21/16System and frequency synchronization of doppler-shifted subcarriers
01/07/16Non-volatile memory device having configurable page size
12/17/15Nand flash memory having multiple cell substrates
12/17/15Method and reducing pool starvation in a shared memory switch
10/29/15Composite semiconductor memory device with error correction
10/22/15Lithography-friendly local read circuit for nand flash memory devices and manufacturing method thereof
09/10/15Clock mode determination in a memory system
08/06/15Dram memory device with manufacturable capacitor
07/30/15Three dimensional non-volatile memory with charge storage node isolation
07/09/15Circuit, selectively turning off internal clock drivers
07/02/15Semiconductor device having metal lines with slits
06/11/15System and operation for high capacity solid-state drive
06/11/15Semiconductor memory device with plural memory die and controller die
05/14/15Three dimensional nonvolatile memory cell structure with upper body connection
04/30/15Split block decoder for a nonvolatile memory device
04/16/15Cost effective forming embedded dram capacitor
04/02/15Method and testing surface mounted devices
Patent Packs
03/19/15High bandwidth memory interface
03/19/15Method and starting an engine in a hybrid vehicle
03/19/15Memory controller with flexible data alignment to clock
02/19/15Structure and manufacturing a stacked memory array for junction-free cell transistors
02/19/15Structure and manufacturing a stacked memory array for junction-free cell transistors
02/19/15Phase change memory word line driver
02/19/15Non-volatile memory serial core architecture
02/12/15System and page buffer operation for memory devices
02/05/15Memory system and method using stacked memory device dice
01/29/15Circuit for clamping current in a charge pump
01/22/15Through semiconductor via structure with reduced stress proximity effect
01/15/15Error detection method and a system including one or more memory device
01/08/15Apparatus and delivering power in a hybrid vehicle
01/08/15Dynamic impedance control for input/output buffers
01/08/15Partial block erase architecture for flash memory
Patent Packs
01/08/15Clock mode determination in a memory system
01/01/15Network architecture for data communication
12/25/14Low leakage and data retention circuitry
09/18/14Structure and manufacture of memory device with thin silicon body
09/11/14Method, apparatus, signals, and medium for managing power in a hybrid vehicle
08/28/14Bridge device architecture for connecting discrete memory devices to a system
08/21/14Dynamic random access memory with fully independent partial array refresh function
08/14/14Using interrupted through-silicon-vias in integrated circuits adapted for stacking
08/14/14Delay locked loop circuit and method
05/01/14Method and sharing internal power supplies in integrated circuit devices







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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