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Cryptography Research Inc patents


Recent patent applications related to Cryptography Research Inc. Cryptography Research Inc is listed as an Agent/Assignee. Note: Cryptography Research Inc may have other listings under different names/spellings. We're not affiliated with Cryptography Research Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "C" | Cryptography Research Inc-related inventors


Hardware masked substitution box for the data encryption standard

An integrated circuit may implement a masked substitution box that includes a counter that generates counter values. An input mask component may generate unmasked input values based on a combination of respective counter values and an input mask value. ... Cryptography Research Inc

Protecting block cipher computation operations from external monitoring attacks

Systems and methods for protecting block cipher computation operations, from external monitoring attacks. An example apparatus for implementing a block cipher may comprise: a first register configured to store a first pre-computed mask value represented by a combination of a first random value and a second random value; a second register configured to store an output mask value, wherein the output mask value is an inverse permutation function of the first random value; a third register configured to store a second pre-computed mask value represented by a combination the first pre-computed mask value and a permutation function of the output mask value; a fourth register configured to store an input mask value, wherein the input mask value is a combination of an expansion function of the first random value and a key mask value; a non-linear transformation circuit configured to apply the expansion function to a masked round state, perform a non-linear transformation of a combination of a masked key with an output of the expansion function, and apply the permutation function to the output of the non-linear transformation, wherein the non-linear transformation is defined using the input mask value stored in the fourth register and the output mask value stored in the second register; and two round feedback circuits configured to swap the masked round state produced by the non-linear transformation and combine the masked round state with the first pre-computed mask value stored in the first register and the second pre-computed mask value stored in the third register.. ... Cryptography Research Inc

Protecting polynomial hash functions from external monitoring attacks

Systems and methods for protecting from external monitoring attacks cryptographic data processing operations involving computation of a universal polynomial hash function, such as ghash function. An example method may comprise: receiving an input data block, an iteration result value, and a mask value; performing a non-linear operation to produce a masked result value, wherein a first operand of the non-linear operation is represented by a combination of the iteration result value and the input data block, and the second operand of the non-linear operation is represented by a secret hash value, and wherein one of the first operand or the second operand is masked using a mask value; determining, based on the mask value, a mask correction value; and producing a new iteration result value by applying the mask correction value to the masked result value.. ... Cryptography Research Inc

Secure boot with resistance to differential power analysis and other external monitoring attacks

A method for device authentication comprises receiving, by processing hardware of a first device, a message from a second device to authenticate the first device. The processing hardware retrieves a secret value from secure storage hardware operatively coupled to the processing hardware. ... Cryptography Research Inc

Memory optimization for nested hash operations

A first hash value is calculated by using a first input value that is stored in a first set of registers. The first hash value is then stored in a second set of registers. ... Cryptography Research Inc

Providing access to a hardware resource based on a canary value

A container corresponding to executable code may be received. In response receiving the container, an assertion value may be stored in an assertion register. ... Cryptography Research Inc

Self-timed random number generator

The embodiments described herein describe a chain of pattern generators organized in a ring topology. Each of the pattern generators in the chain includes asynchronous digital logic and implements an update rule that generates a bidirectional pattern within the chain of pattern generators. ... Cryptography Research Inc

Non-volatile memory for secure storage of authentication data

A first non-volatile memory may store first data and a second non-volatile memory may store second data. An authentication component may be coupled with the first non-volatile memory and the second non-volatile memory and may receive a request to perform an authentication operation. ... Cryptography Research Inc

Exponent splitting for cryptographic operations

A first share value and a second share value may be received. A combination of the first share value and the second share value may correspond to an exponent value. ... Cryptography Research Inc

Generating a device identification key from a base key for authentication with a network

A base key that is stored at a device may be received. A network identification may further be received. ... Cryptography Research Inc

Managing privileges of different entities for an integrated circuit

A request associated with one or more privileges assigned to a first entity may be received. Each of the one or more privileges may correspond to an operation of an integrated circuit. ... Cryptography Research Inc

Diversifying a base symmetric key based on a public key

A symmetric key that is stored at a device may be received. A public key from a remote entity may also be received at the device. ... Cryptography Research Inc

Secure boot with resistance to differential power analysis and other external monitoring attacks

A computing device includes a secure storage hardware to store a secret value and processing hardware comprising at least one of a cache or a memory. During a secure boot process the processing hardware loads untrusted data into at least one of the cache or the memory of the processing hardware, the untrusted data comprising an encrypted data segment and a validator, retrieves the secret value from the secure storage hardware, derives an initial key based at least in part on an identifier associated with the encrypted data segment and the secret value, verifies, using the validator, whether the encrypted data segment has been modified, and decrypts the encrypted data segment using a first decryption key derived from the initial key to produce a decrypted data segment responsive to verifying that the encrypted data segment has not been modified.. ... Cryptography Research Inc

Preemption of a container in a secure computation environment

A container corresponding to executable code may be received. The container may be executed in a secure computation environment by performing one or more operations specified by the executable code of the container. ... Cryptography Research Inc

06/01/17 / #20170154193

Gate-level masking

A method of and system for gate-level masking of secret data during a cryptographic process is described. A mask share is determined, wherein a first portion of the mask share includes a first number of zero-values and a second number of one-values, and a second portion of the mask share includes the first number of one-values and the second number of zero-values. ... Cryptography Research Inc

05/18/17 / #20170142083

Secure data provisioning

A first instruction to store an entity identification (id) in a memory of a device may be received. The entity id may be stored in the memory in response to receiving the first instruction. ... Cryptography Research Inc

03/23/17 / #20170085368

Performing cryptographic data processing operations in a manner resistant to external monitoring attacks

Systems and methods for performing cryptographic data processing operations in a manner resistant to external monitoring attacks. An example method may comprise: executing, by a processing device, a first data manipulation instruction, the first data manipulation instruction affecting an internal state of the processing device; executing a second data manipulation instruction, the second data manipulation instruction interacting with said internal state; and breaking a detectable interaction of the first data manipulation instruction and the second data manipulation instruction by executing a third data manipulation instruction utilizing an unpredictable data item.. ... Cryptography Research Inc

03/09/17 / #20170070485

Location aware cryptography

Encrypted data transmitted from a second entity to a first entity may be received. The encrypted data may be encrypted by a location based public key based on a public key and a location associated with the second entity. ... Cryptography Research Inc

03/02/17 / #20170061121

Low overhead random pre-charge countermeasure for side-channel attacks

A side-channel attack resistant circuit topology for performing logic functions. This topology includes combinatorial logic to perform the at least one logic function. ... Cryptography Research Inc

01/26/17 / #20170025187

System including hierarchical memory modules having different types of integrated circuit memory devices

Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. ... Cryptography Research Inc

01/12/17 / #20170011394

Cryptographic security for mobile payments

A base key that is stored at a mobile device may be received. A first dynamic key that is based on the base key may be generated. ... Cryptography Research Inc








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