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Csmc Technologies Fab1 Co Ltd patents


Recent patent applications related to Csmc Technologies Fab1 Co Ltd. Csmc Technologies Fab1 Co Ltd is listed as an Agent/Assignee. Note: Csmc Technologies Fab1 Co Ltd may have other listings under different names/spellings. We're not affiliated with Csmc Technologies Fab1 Co Ltd, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "C" | Csmc Technologies Fab1 Co Ltd-related inventors


Method for manufacturing laterally insulated-gate bipolar transistor

The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature... Csmc Technologies Fab1 Co Ltd

Semiconductor rectifier and manufacturing method thereof

A semiconductor rectifying device and a method of manufacturing the same. The semiconductor rectifying device includes: a substrate of a first conductivity type (100), an epitaxial layer of a first conductivity type (200) formed on the substrate of the first conductivity type (100), wherein the epitaxial layer of the first... Csmc Technologies Fab1 Co Ltd

Lateral insulated-gate bipolar transistor

A lateral insulated gate bipolar transistor comprises a substrate (10); an anode terminal located on the substrate, comprising: an N-type buffer region (51) located on the substrate (10); a P well (53) located in the N-type buffer region; an N-region (55) located in the P well (53); two P+ shallow... Csmc Technologies Fab1 Co Ltd

N-type lateral double-diffused metal-oxide-semiconductor field-effect transistor

An N type lateral double-diffused metal oxide semiconductor field effect transistor (200) includes a substrate (202); a first N well (204) formed on the substrate; a second N well (206), a first P well (208), a third N well (210) and a fourth N well (212); a source lead-out region... Csmc Technologies Fab1 Co Ltd

Semiconductor device and manufacturing method therefor

A manufacturing method for a semiconductor device is provided. The method comprises: providing a semiconductor substrate (200); sequentially forming an oxide layer (201) and a silicon nitride layer (202) on the semiconductor substrate (200); annealing the silicon nitride layer (202), and then etching an active region (401) by using the... Csmc Technologies Fab1 Co Ltd

Low drop-out regulator circuit, chip and electronic device

A low dropout linear regulator circuit comprises a voltage reference source module (100), an error amplifier (200), a reference voltage determining module (300), a power transmission device (400) and a feedback module (500); wherein the voltage reference source module (100) provides a reference voltage for the error amplifier (200), the... Csmc Technologies Fab1 Co Ltd

Method for manufacturing mems double-layer suspension microstructure, and mems infrared detector

A method for manufacturing a MEMS double-layer suspension microstructure comprises steps of: forming a first film body on a substrate, and a cantilever beam connected to the substrate and the first film body; forming a sacrificial layer on the first film body and the cantilever beam; patterning the sacrificial layer... Csmc Technologies Fab1 Co Ltd

Brown out detector having sequential control function

A brown-out detection circuit having a time sequence control function comprises: a voltage divider (110), a reference voltage source (120), a comparator (130) and a time sequence control module (140); wherein one terminal of the voltage divider (110) is connected to an external power supply, the other terminal of the... Csmc Technologies Fab1 Co Ltd

Method for manufacturing ldmos device

A method for manufacturing an LDMOS device includes: providing a semiconductor substrate (200), forming a drift region (201) in the semiconductor substrate (200), forming a gate material layer on the semiconductor substrate (200), and forming a negative photoresist layer (204) on the gate material layer; patterning the negative photoresist layer... Csmc Technologies Fab1 Co Ltd

Method for manufacturing mems torsional electrostatic actuator

A method for manufacturing an MEMS torsional electrostatic actuator comprises: providing a substrate, wherein the substrate comprises a first silicon layer, a buried oxide layer and a second silicon layer that are laminated sequentially; patterning the first silicon layer and exposing the buried oxide layer to form a rectangular upper... Csmc Technologies Fab1 Co Ltd

Direct digital synthesizing method and direct digital synthesizer

A direct digital frequency synthesis method comprises the following steps: calculating, by a phase accumulation module, a first phase according to a frequency synthesis word (S101); finding an amplitude value by a preset sinusoidal lookup table according to the first phase (S102); finding a second phase by a preset phase... Csmc Technologies Fab1 Co Ltd

Method and system for correcting driving amplitude of gyro sensor

A method for correcting the driving amplitude of a gyro sensor, mainly comprises adjusting the size of a driving signal (a preset amplitude value) through feedback of a sensor response amplitude signal (an average amplitude value) in a resonance maintaining time period, so that the response amplitude of the resonance... Csmc Technologies Fab1 Co Ltd

Junction field effect transistor and manufacturing method therefor

The present invention relates to a junction field effect transistor. The junction field effect transistor comprises a substrate (10), a buried layer in the substrate, a first well region (32) and a second well region (34) that are on the buried layer, a source lead-out region (50), a drain lead-out... Csmc Technologies Fab1 Co Ltd

Manufacturing mems chip

A method of manufacturing a MEMS chip includes: providing a silicon substrate layer, the silicon substrate layer comprising a front surface configured to perform a MEMS process and a rear surface opposite to the front surface; growing a first oxidation layer mainly made of SiO2 on the rear surface of... Csmc Technologies Fab1 Co Ltd

Positioning method in microprocessing process of bulk silicon

A positioning method in a microprocessing process of bulk silicon comprises the steps of: fabricating, on a first surface of a first substrate (10), a first pattern (100), a stepper photo-etching machine alignment mark (200) for positioning the first pattern, and a double-sided photo-etching machine first alignment mark (300) for... Csmc Technologies Fab1 Co Ltd

Mems-based manufacturing sensor

An MEMS-based method for manufacturing a sensor comprises the steps of: forming a shallow channel (120) and a support beam (140) on a front surface of a substrate (100); forming a first epitaxial layer (200) on the front surface of the substrate (100) to seal the shallow channel (120); forming... Csmc Technologies Fab1 Co Ltd

Mems microphone

A MEMS microphone includes a substrate (100), a supporting part (200), an upper polar plate (300) and a lower polar plate (400). The substrate (100) is provided with an opening (120) penetrating the middle thereof; the lower polar plate (400) straddles the opening (120); the supporting part (200) is fixed... Csmc Technologies Fab1 Co Ltd

Semiconductor device having esd protection structure

The present disclosure relates to a semiconductor device with an ESD protection structure. The semiconductor device includes a high-voltage power device 101, the ESD protection structure is a NMOS transistor 102, a drain of the NMOS transistor is shared by a source of the power device as a common-drain-source structure... Csmc Technologies Fab1 Co Ltd

Laterally diffused metal oxide semiconductor device and manufacturing method therefor

A laterally diffused metal oxide semiconductor device includes: a substrate (10); a buried layer region (32) in the substrate; a well region (34) on the buried layer region (32); a gate region on the well region; a source region (41) and a drain region (43) which are located at two... Csmc Technologies Fab1 Co Ltd

High-voltage device simulation model and modeling method therefor

A high-voltage device simulation model and a modeling method thereof are provided. The simulation model comprises: a core transistor (101), a drain terminal resistor (102) and a source terminal resistor (103), wherein a first terminal of the drain terminal resistor (102) is electrically connected to a drain (d1) of the... Csmc Technologies Fab1 Co Ltd

Silicon-on-insulator device and intermetallic dielectric layer structure thereof and manufacturing method

Provided is an intermetallic dielectric layer structure of a silicon-on-insulator device, comprising a silicon-rich oxide layer (54) covering a metal interconnect, a fluorine-silicon glass layer on the silicon-rich oxide layer, and a non-doped silicate glass layer on the fluorine-silicon glass layer; the thickness of the silicon-rich oxide layer (54) is... Csmc Technologies Fab1 Co Ltd








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