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Cypress Semiconductor Corporation patents


Recent patent applications related to Cypress Semiconductor Corporation. Cypress Semiconductor Corporation is listed as an Agent/Assignee. Note: Cypress Semiconductor Corporation may have other listings under different names/spellings. We're not affiliated with Cypress Semiconductor Corporation, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "C" | Cypress Semiconductor Corporation-related inventors


 new patent  Phase controller apparatus and methods

A phase controller includes a plurality of pulse width modulation (pwm) circuits, a plurality of switching devices, a computing unit, and a latency generator. The plurality of pwm circuits output pulse signals. ... Cypress Semiconductor Corporation

 new patent  Split-gate flash cell formed on recessed substrate

A semiconductor device and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed in a first region of a substrate, and a non-volatile memory (nvm) cell including a select gate and a memory gate formed in a first recess in a second region of the same substrate, wherein the recess is recessed relative to a first surface of the substrate. ... Cypress Semiconductor Corporation

 new patent  Integration of a memory transistor into high-k, metal gate cmos process flow

A memory device that includes a non-volatile memory (nvm) transistor disposed in a first region of a substrate. The nvm transistor includes a first gate including a first type of conductor material. ... Cypress Semiconductor Corporation

 new patent  Self-aligned trench isolation in integrated circuits

A method for fabricating an integrated circuit (ic) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. ... Cypress Semiconductor Corporation

 new patent  Non-volatile memory array with memory gate line and source line scrambling

A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (nvm) cells coupled in the same column of the memory array, in which each nvm cell may include a memory gate. ... Cypress Semiconductor Corporation

 new patent  Capacitive sensing with multi-pattern scan

The sensing circuit includes including first input of a first electrode, a first set of inputs of a first set of two or more electrodes forming a first intersection and a second intersection, and a second set of inputs of a second set of two or more electrodes forming the second intersection and a third intersection. The sensing circuit includes a scan control circuit, coupled to the touch panel of electrodes, to concurrently select the sets of electrodes via a multiplexer. ... Cypress Semiconductor Corporation

 new patent  Multi-phase self-capacitance scanning of sensors arrays

Techniques for multi-phase self-capacitance (mpsc) scanning of a sensor array are described herein. In an example embodiment, a device comprises a sensor logic coupled to a processing logic. ... Cypress Semiconductor Corporation

 new patent  Detect and differentiate touches from different size conductive objects on a capacitive button

Apparatuses and methods of distinguishing between a finger and stylus proximate to a touch surface are described. One apparatus includes a first circuit to obtain capacitance measurements of sense elements when a conductive object is proximate to a touch surface. ... Cypress Semiconductor Corporation

 new patent  Input/output multiplexer bus

One embodiment includes and i/0 bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding i/0 port to the signal line. Switch logic coupled to the i/0 bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective i/0 port.. ... Cypress Semiconductor Corporation

Memory transistor with multiple charge storing layers and a high work function gate electrode

Semiconductor devices including non-volatile memory devices and methods of fabricating the same are provided. Generally, the memory device includes a gate structure, a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. ... Cypress Semiconductor Corporation

Encryption for xip and mmio external memories

Techniques for multiplexing between an execute-in-place (xip) mode and a memory-mapped input/output (mmio) mode for access to external memory devices are described herein. In an example embodiment, an ic device comprises a serial interface and a controller that is configured to communicate with external memory devices over the serial interface. ... Cypress Semiconductor Corporation

Microcontroller energy profiler

A method is disclosed to estimate energy consumed by a component in a microcontroller during operation including identifying “event” activities, where the energy consumed by the component may be determined by the number of events executed by the component, and “duration” activities, where the energy consumed may be determined by the duration of time required to execute of the activity, and determining the energy consumed by the component based on the number of events/duration of time and an energy coefficient which corresponds to the amount of energy consumed by the component to execute the activity, under given operating conditions. In an embodiment, data transfers at a bus interface may represent event activities. ... Cypress Semiconductor Corporation

Methods, circuits, devices and systems for comparing signals

Disclosed is a method of comparing two or more signals which may include: for each of the two or more signals, charging to a fixed voltage a compensation capacitor associated with a sense path of the signal, discharging each of the charged capacitors to a threshold voltage of a transistor in its respective sense path and integrating a discharge current from each capacitor with the signal sensed on the respective sense path.. . ... Cypress Semiconductor Corporation

Fast ramp low supply charge pump circuits

Techniques for fast ramp, low supply charge-pump circuits are described herein. In an example embodiment, a non-volatile memory device comprises a flash memory array coupled to a fast charge-pump circuit. ... Cypress Semiconductor Corporation

04/05/18 / #20180098397

Stochastic signal density modulation for optical transducer control

A controller for optical transducers uses stochastic signal density modulation to reduce electromagnetic interference.. . ... Cypress Semiconductor Corporation

04/05/18 / #20180097445

Low quiescent current dc-to-dc converter

Systems and methods for driving a low quiescent current dcdc converter are disclosed. An error threshold compensation circuit of the dcdc converter is configured to detect an output voltage of the dcdc converter, compare the output voltage to a target voltage, and modify a first threshold voltage of the hysteresis control circuit based on the comparison.. ... Cypress Semiconductor Corporation

04/05/18 / #20180095678

Systems, methods, and devices for user configurable wear leveling of non-volatile memory

Disclosed herein are systems, methods, and devices for user configurable wear leveling of non-volatile memory devices. Devices include a non-volatile memory including a plurality of physical memory portions, where each of the plurality of physical memory portions is configured to be mapped to a logical memory portion of a plurality of logical memory portions. ... Cypress Semiconductor Corporation

04/05/18 / #20180095558

Mutual capacitance sensing array

A method and apparatus for sensing a conductive object by a mutual capacitance sensing array is described according to an embodiment of the present invention. The mutual capacitance sensing array comprises one or more sensor elements. ... Cypress Semiconductor Corporation

04/05/18 / #20180095511

Low-power type-c receiver with high idle noise and dc-level rejection

Techniques for low-power usb type-c receivers with high dc-level shift tolerance are described herein. In an example embodiment, a usb-enabled device comprises a receiver circuit coupled to a configuration channel (cc) line of a usb type-c subsystem. ... Cypress Semiconductor Corporation

03/29/18 / #20180088912

Techniques for generating microcontroller configuration information

An example includes accessing multiple configurations stored in a memory, where each configuration is associated with a corresponding circuit function implementable by an electronic device and associated with a corresponding set of resources of the electronic device. The example includes determining that one or more sets of resources of the electronic device are available for use by one or more configurations of the multiple configurations. ... Cypress Semiconductor Corporation

03/22/18 / #20180083650

Ratio-metric self-capacitance-to-code convertor

A circuit, system, and method for converting self capacitance to a digital value may include a pair of charge transfer circuits, each including a switch network, a sensor capacitor or modulation capacitor, and an integration capacitor may be coupled to a comparator to produce a data signal representative of the capacitance of the sensor capacitor of one of the charge transfer circuits. The data signal may be used to indicate a capacitance value of the self capacitance through conversion by a circuit.. ... Cypress Semiconductor Corporation

03/22/18 / #20180083024

Method of ono stack formation

A method of controlling the thickness of gate oxides in an integrated cmos process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the nv gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (mos) transistor in the second region, wherein the gate oxide of the at least one mos transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.. . ... Cypress Semiconductor Corporation

03/22/18 / #20180082746

Systems, methods, and apparatus for memory cells with common source lines

A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other embodiments are also described.. ... Cypress Semiconductor Corporation

03/22/18 / #20180081697

System for re-enumeration of usb 3.0 compatible peripheral devices

Described herein is a system comprising a peripheral device that is connected to a host device over a bus compatible with usb 3.0. The host device comprises a reduced functionality usb host controller configured to perform a set of one or more preprogrammed functions from the usb 3.0 specification, and a universal asynchronous receiver and transmitter (uart) configured to sample usb response data received from the peripheral device over the bus.. ... Cypress Semiconductor Corporation

03/22/18 / #20180081564

Memory subsystem with wrapped-to-continuous read

Disclosed herein are system, method, and computer program product embodiments for accessing data of a memory. A method embodiment operates by receiving one or more requests for data stored across at least a first memory area and a second memory area of a memory. ... Cypress Semiconductor Corporation

03/22/18 / #20180081479

Force sensing

An apparatus including a first signal generator of a force sensing circuit to output a first excitation (tx) signal on a first terminal and a second tx signal on a second terminal. The first terminal and the second terminal are configured to couple to a first force sensor and a reference sensor. ... Cypress Semiconductor Corporation

03/08/18 / #20180068735

Method to reduce program disturbs in non-volatile memory cells

A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (vneg) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. ... Cypress Semiconductor Corporation

02/22/18 / #20180053657

Sonos stack with split nitride memory layer

A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. ... Cypress Semiconductor Corporation

02/08/18 / #20180040625

Complementary sonos integration into cmos flow

Methods of integrating complementary sonos devices into a cmos process flow are described. The method begins with depositing and patterning a first photoresist mask over a surface of a substrate to expose a n-sonos region, and implanting a channel for a nsonos device through a first pad oxide, followed by depositing and patterning a second photoresist mask to expose a p-sonos region, and implanting a channel for a psonos device through a second pad oxide. ... Cypress Semiconductor Corporation

01/25/18 / #20180025202

Anti-spoofing protection for fingerprint controllers

A method for detecting fingerprint spoof objects includes detecting a presence of the object at a fingerprint sensor and, in response to detecting the presence of the object, measuring a set of physical properties of the object based on one or more signals from a set of electrodes of the fingerprint sensor. The set of physical properties includes at least one of a subdermal compliance of the object and a surface adhesiveness of the object. ... Cypress Semiconductor Corporation

01/25/18 / #20180025199

Non-finger object rejection for fingerprint sensors

A method for detecting a finger at a fingerprint sensor includes detecting a presence of an object at a fingerprint sensor and, in response to detecting the presence of the object, acquiring image data for the object based on signals from the fingerprint sensor. The method further includes, for each subset of one or more subsets of the image data, calculating a magnitude value for a spatial frequency of the subset, and identifying the object as a finger based on comparing the magnitude value to a threshold.. ... Cypress Semiconductor Corporation

01/25/18 / #20180024945

Context-based protection system

A context-based protection system uses tiered protection structures including master protection units, shared memory protection units, a peripheral protection units to provide security to bus transfer operations between central processing units (cpus), memory array or portions of arrays, and peripherals.. . ... Cypress Semiconductor Corporation

01/11/18 / #20180012055

Fingerprint sensor pattern

An example system drives one or more transmit signals on first electrodes disposed in a first layer and propagating electrodes disposed in a second layer. The system measures a capacitance of sensors through a of second electrodes. ... Cypress Semiconductor Corporation

01/11/18 / #20180011718

Re-enumeration of usb 3.0 compatible devices

A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. ... Cypress Semiconductor Corporation

01/04/18 / #20180006132

Varied silicon richness silicon nitride formation

A method to fabricate a non-planar memory device including forming a multi-layer silicon nitride structure substantially perpendicular to a top surface of the substrate. There may be multiple non-stoichiometric silicon nitride layers, each including a different or same silicon richness value from one another.. ... Cypress Semiconductor Corporation

01/04/18 / #20180003752

Detect and differentiate touches from different size conductive objects on a capacitive button

Apparatuses and methods of distinguishing between a finger and stylus proximate to a touch surface are described. One apparatus includes a first circuit to obtain capacitance measurements of sense elements when a conductive object is proximate to a touch surface. ... Cypress Semiconductor Corporation

12/28/17 / #20170371992

Integrated circuit including parametric analog elements

A design system is provided. In one embodiment the design system includes an input module to receive specification data for a designed circuit including a configurable integrated circuit (ic). ... Cypress Semiconductor Corporation

12/28/17 / #20170371824

Bus sharing scheme

A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of 10 pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the pads to each other.. . ... Cypress Semiconductor Corporation

12/28/17 / #20170371451

Providing a baseline capacitance for a capacitance sensing channel

A capacitance-sensing circuit may include a channel input associated with measuring a capacitance of a unit cell of a capacitive sense array. The capacitance-sensing circuit may also include a capacitive hardware baseliner that is coupled to the channel input. ... Cypress Semiconductor Corporation

12/21/17 / #20170365346

High voltage architecture for non-volatile memory

A method of erasing, during an erase operation, a non-volatile memory (nvm) cell of a memory device is disclosed. The erasing includes applying a first hv signal (vpos) to a common source line (csl). ... Cypress Semiconductor Corporation

12/21/17 / #20170365300

Methods and devices for reading data from non-volatile memory cells

Disclosed is a method for responding to a single user read command of a complementary cell array including one or more complementary cell pairs, the method including: determining if a first group of cells out of a data word is in an erased state or in a programmed state, and outputting a data word so that (a) if the first group of cells is determined to be erased a logical “one” is output for each bit of the data word and (b) if the first group of cells is determined to be programmed the result of a complementary read is output for each bit of the data word.. . ... Cypress Semiconductor Corporation

12/14/17 / #20170358367

Methods and devices for reducing program disturb in non-volatile memory cell arrays

A memory device that includes a pair of non-volatile memory cells, a first memory cell including a first memory gate and a first select gate, and a second memory cell including a second memory gate and a second select gate. The first and second memory cells share a source line, and the first and second memory gates are not connected to one another.. ... Cypress Semiconductor Corporation

12/07/17 / #20170352732

Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region

A memory is described. Generally, the memory includes a number of non-planar multigate transistors, each including a channel of semiconducting material overlying a surface of a substrate and electrically connecting a source and a drain, a tunnel dielectric layer overlying the channel on at least three sides thereof, and a multi-layer charge-trapping region overlying the tunnel dielectric layer. ... Cypress Semiconductor Corporation

12/07/17 / #20170351897

Methods and sensors for multiphase scanning in the fingerprint and touch applications

Techniques for multi-phase scanning based on pseudo-random sequences in capacitive fingerprint applications are described herein. In an example embodiment, a method performed by a processing device comprises: receiving measurements that are representative of a portion of a finger on a capacitive fingerprint sensor array, where the measurements are obtained from sensor elements of the capacitive fingerprint sensor array that are scanned in a multi-phase mode based on an excitation vector generated from a pseudo-random sequence; and generating a fingerprint image for the portion of the finger based on the measurements.. ... Cypress Semiconductor Corporation

12/07/17 / #20170351320

Configurable and power-optimized integrated gate-driver for usb power-delivery and type-c socs

Techniques for power field effect transistor (power-fet) gate drivers are described herein. In an example embodiment, a usb-enabled system comprises a first and second power paths and an ic controller coupled to control the first and second power paths, where the first and second power paths are external to the ic controller and the ic controller is configured to operate both an n-channel power-fet in the first power path and a p-channel power-fet in the second power path.. ... Cypress Semiconductor Corporation

11/16/17 / #20170331270

Adjustable over-current detector circuit for universal serial bus (usb) devices

A current detector circuit includes a current sense amplifier, coupled to a sense resistor, to receive a pair of input voltages and to output a first indicator signal responsive to a sensed input voltage difference produced by a sensed current passing through the sense resistor. The current detector circuit includes a comparator coupled to the current sense amplifier, the comparator to compare the first indicator signal to a reference voltage signal and output an interrupt signal responsive to the first indicator signal exceeding the reference voltage signal; and a reference voltage generator circuit coupled to the comparator, the reference voltage generator circuit to select the reference voltage signal from a plurality of reference voltages according to a first selector signal received from a configuration channel of a serial bus connector device.. ... Cypress Semiconductor Corporation

11/09/17 / #20170322649

Contact detection mode switching in a touchscreen device

A method is disclosed for determining detecting a conductive object and determining the type of object and the type of contact that object has with a touch sensitive surface, the method comprising measuring capacitance on a plurality of mutual capacitance sensors, each mutual capacitance sensor corresponding to a unit cell in an array of unit cells. After mutual capacitance is measured a peak unit cell is identified based on the measured capacitances and a matrix sum of a plurality of unit cells surround the peak unit cell is calculated. ... Cypress Semiconductor Corporation

10/05/17 / #20170287366

Systems and methods for downloading code and data into a secure non-volatile memory

An example secure embedded device includes a secure non-volatile memory coupled to a processor. The processor provides a scramble or cipher key and uses a scramble algorithm or a cipher algorithm to scramble or cipher information received from an external device into transformed information. ... Cypress Semiconductor Corporation

10/05/17 / #20170286344

Dynamically reconfigurable analog routing and multiplexing architecture on a system on a chip

An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.. . ... Cypress Semiconductor Corporation

09/28/17 / #20170278853

Integration of a memory transistor into high-k, metal gate cmos process flow

Memory cells including embedded sonos based non-volatile memory (nvm) and mos transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a nvm transistor in a nvm region of a substrate including the nvm region and a plurality of mos regions; and depositing a high-k dielectric material over the gate stack of the nvm transistor and the plurality of mos regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the nvm transistor and high-k gate dielectrics in the plurality of mos regions. ... Cypress Semiconductor Corporation

09/28/17 / #20170278573

Systems, methods, and apparatus for memory cells with common source lines

Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. ... Cypress Semiconductor Corporation

09/28/17 / #20170277241

Low-power touch button sensing system

A method for operating a sensing system includes receiving, from a processing device, control information for configuring a capacitance sensing circuit, configuring the capacitance sensing circuit with the control information in response to receiving the control information, and controlling power consumption of the processing device based on the control information and based on a capacitance measured by the capacitance sensing circuit.. . ... Cypress Semiconductor Corporation

09/14/17 / #20170264376

Transceiver for communication and method for controlling communication

An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.. . ... Cypress Semiconductor Corporation

09/14/17 / #20170263623

Memory device with multi-layer channel and charge trapping layer

A 3-d/vertical non-volatile (nv) memory device such as 3-d nand flash memory and fabrication method thereof, the nv memory device includes vertical openings disposed in a stack of alternating stack layers of first stack layers and second stack layers over a wafer, a multi-layer dielectric disposed over an inner sidewall of each opening, a first channel layer disposed over the multi-layer dielectric, and a second channel layer disposed over the first channel layer, in which at least one of the first or second channel layers includes polycrystalline germanium or silicon-germanium.. . ... Cypress Semiconductor Corporation

09/14/17 / #20170263622

Embedded sonos based memory cells

Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (nvm) transistor formed in a first region of a substrate, the nvm transistor comprising a channel and a gate stack on the substrate overlying the channel. ... Cypress Semiconductor Corporation

09/14/17 / #20170263459

Multi-layer inter-gate dielectric structure and method of manufacturing thereof

A semiconductor device having a first gate stack on a substrate is disclosed. The first gate stack may include a first gate conductor over a first gate dielectric structure. ... Cypress Semiconductor Corporation

09/14/17 / #20170263309

10-transistor non-volatile static random-access memory using a single non-volatile memory element and method of operation thereof

A memory including an array of nvram cells and method of operating the same are provided. Each nvram cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including a solitary non-volatile memory (nvm) device, a first transistor coupled to the nvm device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the nvm device through which a compliment of the data is coupled to the volatile charge storage circuit and a third transistor through which the nvm device is coupled to a positive voltage supply line (vcct). ... Cypress Semiconductor Corporation

09/14/17 / #20170262685

Fingerprint sensor-compatible overlay material

A fingerprint sensor-compatible overlay material which uses anisotropic conductive material to enable accurate imaging of a fingerprint through an overlay is disclosed. The anisotropic conductive material has increased conductivity in a direction orthogonal to the fingerprint sensor, increasing the capacitive coupling of the fingerprint to the sensor surface, allowing the fingerprint sensor to accurately image the fingerprint through the overlay. ... Cypress Semiconductor Corporation

09/14/17 / #20170262097

Single layer sensor pattern

A capacitive sensor array comprises large sensor electrodes and small sensor electrodes formed from a single layer of conductive material. Each sensor electrode of a first set of small sensor electrodes is electrically connected to a first pad. ... Cypress Semiconductor Corporation

09/14/17 / #20170262094

Sensor array with edge pattern

A capacitive sensor array may include a first set of sensor electrodes and a second set of sensor electrodes. Each of the second set of sensor electrodes may intersect each of the first set of sensor electrodes to form a plurality of unit cells each corresponding to a pair of sensor electrodes including one of the first set of sensor electrodes and one of the second set of sensor electrodes. ... Cypress Semiconductor Corporation

09/14/17 / #20170262035

Type-c connector subsystem

A universal serial bus (usb) type-c connector subsystem is described herein. An integrated circuit (ic) chip device includes a universal serial bus (usb) type-c subsystem. ... Cypress Semiconductor Corporation

09/07/17 / #20170255297

Capacitive sensing button on chip

A method and apparatus include a plurality of sensor elements arranged within an integrated circuit package and a controller arranged within the integrated circuit package and coupled to the plurality of sensor elements. The controller is configured to apply a transmit signal to a first sensor element of the plurality of sensor elements and receive a receive signal from a second sensor element of the plurality of sensor elements. ... Cypress Semiconductor Corporation

08/31/17 / #20170250192

Non-volatile memory with silicided bit line contacts

An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ono) nitride edges. ... Cypress Semiconductor Corporation

08/31/17 / #20170249978

Systems, methods, and devices for parallel read and write operations

Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. ... Cypress Semiconductor Corporation

08/03/17 / #20170221768

Manufacturing of fet devices having lightly doped drain and source regions

Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. ... Cypress Semiconductor Corporation

07/20/17 / #20170205453

Quasi-differential mutual capacitance measurement

A circuit, system, and method for converting mutual capacitance to a digital value is described. Charge packets are transferred from a mutual capacitance to a pair of integration capacitors during alternate charge and discharge cycles. ... Cypress Semiconductor Corporation

07/13/17 / #20170201266

Configurable capacitor arrays and switched capacitor circuits

Methods and apparatus include and amplifier circuit and a first capacitor branch including a first plurality of capacitors. The first capacitor branch couples to an input signal and to an input of the amplifier circuit. ... Cypress Semiconductor Corporation

07/13/17 / #20170199840

Asynchronous transceiver for on-vehicle electronic device

An on-vehicle electronic device has a generating unit configured to generate a first clock for data communication with another on-vehicle electronic device through a cxpi communication network; and an adjusting unit configured to adjust a duty width of the first clock.. . ... Cypress Semiconductor Corporation

07/06/17 / #20170194963

Programmable input/output circuit

A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two io pads, and a reference buffer coupled to both the input buffer and the second of the io pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the io pads.. . ... Cypress Semiconductor Corporation

07/06/17 / #20170194343

Split gate charge trapping memory cells having different select gate and memory gate heights

A semiconductor device that has a split gate charge trapping memory cell having select and memory gates of different heights is presented herein. In an embodiment, the semiconductor device also has a low voltage transistor and a high voltage transistor. ... Cypress Semiconductor Corporation

06/29/17 / #20170186883

Memory transistor with multiple charge storing layers and a high work function gate electrode

Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ono) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ono stack. ... Cypress Semiconductor Corporation

06/29/17 / #20170185558

Microcontroller programmable system on a chip

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. ... Cypress Semiconductor Corporation

06/22/17 / #20170177920

Capacitive fingerprint sensor with quadrature demodulator and multiphase scanning

A fingerprint sensing circuit, system, and method is disclosed. The fingerprint sensor maybe include a plurality of inputs coupled to a plurality of fingerprint sensing electrodes and to an analog front end. ... Cypress Semiconductor Corporation

06/22/17 / #20170177536

Microcontroller programmable system on a chip

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. ... Cypress Semiconductor Corporation

06/15/17 / #20170170187

Gate fringing effect based channel formation for semiconductor device

A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. ... Cypress Semiconductor Corporation

06/15/17 / #20170169888

Asymmetric pass field-effect transistor for nonvolatile memory

A method of performing an operation on a non-volatile memory (nvm) cell of a memory device is disclosed. The pass transistor of the nvm cell is an asymmetric transistor including a source with a halo implant. ... Cypress Semiconductor Corporation

06/08/17 / #20170162586

Split-gate semiconductor device with l-shaped gate

A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. ... Cypress Semiconductor Corporation

06/08/17 / #20170162249

Method for fabricating ferroelectric random-access memory on pre-patterned bottom electrode and oxidation barrier

Structure and method of fabrication of f-ram cells are described. The f-ram cell include ferroelectric capacitors forming over and with a pre-patterned barrier structure which has a planarized/chemically and/or mechanically polished top surface. ... Cypress Semiconductor Corporation

05/18/17 / #20170141787

Delta modulator receive channel for capacitance measurement circuits

A circuit, system, and method for measuring capacitance are described. A current may be received at an input of a conversion circuit. ... Cypress Semiconductor Corporation

05/18/17 / #20170141201

Memory first process flow and device

A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. ... Cypress Semiconductor Corporation

05/18/17 / #20170140196

Fingerprint sensor-compatible overlay material

A fingerprint sensor-compatible overlay material which uses anisotropic conductive material to enable accurate imaging of a fingerprint through an overlay is disclosed. The anisotropic conductive material has increased conductivity in a direction orthogonal to the fingerprint sensor, increasing the capacitive coupling of the fingerprint to the sensor surface, allowing the fingerprint sensor to accurately image the fingerprint through the overlay. ... Cypress Semiconductor Corporation

04/13/17 / #20170103240

Integrated circuit to convert no-wire signals to one-wire signals

A radio frequency identification (rfid) integrated circuit includes a transceiver and a processing device. The transceiver may to transmit a first continuous wave radio frequency (rf) signal to a bridge in a no-wire format via an antenna, where the transceiver is to start transmitting the modulated or continuous wave rf signal at a first amplitude value and increase an amplitude of the modulated or continuous wave rf signal to a second amplitude value at which an acknowledge (ack) pulse is detected. ... Cypress Semiconductor Corporation

04/06/17 / #20170098933

Protecting circuit and integrated circuit

A protecting circuit includes: a discharge switch configured to connect to a first terminal and a second terminal; a trigger circuit comprising load devices configured to be connected in series between the first terminal and the second terminal, each of the load devices being configured to consume power; and a shunt circuit comprising, between the trigger circuit and the first terminal or the second terminal, at least one shunt pathway configured to be capable of bypassing at least one of the load devices. The trigger circuit is configured to turn on the discharge switch when a voltage between the first terminal and the second terminal is higher than a first voltage value, and the shunt circuit is configured to electrically connect the shunt pathway when the voltage is higher than a second voltage value that is greater than the first voltage value.. ... Cypress Semiconductor Corporation

04/06/17 / #20170098468

Low standby power with fast turn on for non-volatile memory devices

Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. ... Cypress Semiconductor Corporation

03/30/17 / #20170093385

Valley detection circuit and drive circuit

A technique for detecting a valley timing at lower cost is described. A drive circuit comprises a peak voltage holder, a valley voltage holder, a center voltage generator, a monitor, and a detector. ... Cypress Semiconductor Corporation

03/30/17 / #20170092781

Nonvolatile charge trap memory device having a high dielectric constant blocking region

An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. ... Cypress Semiconductor Corporation

03/30/17 / #20170092729

Method of manufacturing for memory transistor with multiple charge storing layers and a high work function gate electrode

A semiconductor devices including non-volatile memories and methods of fabricating the same to improve performance thereof are provided. Generally, the device includes a memory transistor comprising a polysilicon channel region electrically connecting a source region and a drain region formed in a substrate, an oxide-nitride-nitride-oxide (onno) stack disposed above the channel region, and a high work function gate electrode formed over a surface of the onno stack. ... Cypress Semiconductor Corporation

03/30/17 / #20170092606

Semiconductor device and method of manufacturing the same

A semiconductor device includes a semiconductor chip, a bump contact, and encapsulating layer, an insulating layer and a connection terminal.. . ... Cypress Semiconductor Corporation

03/30/17 / #20170092577

Memory device interconnects and method of manufacture

A method of fabricating an integrated circuit memory device including forming a first and second inter-level dielectric layer, an anti-reflective coating layer, and a plurality of electrical connections is disclosed.. . ... Cypress Semiconductor Corporation

03/30/17 / #20170092367

Asymmetric pass field-effect transistor for non-volatile memory

A method of performing an operation on a non-volatile memory (nvm) cell of a memory device is disclosed. The pass transistor of the nvm cell is an asymmetric transistor including a source with a halo implant. ... Cypress Semiconductor Corporation

03/30/17 / #20170090781

Method for providing read data flow control or error reporting using a read data strobe

Disclosed herein are system, apparatus, methods and/or combinations and sub-combinations thereof, for using a read data strobe signal received at a host device from a peripheral device to convey variable latency (flow) control or report an error in the data content read from the peripheral device. Reception of the read data strobe signal before a predetermined maximum latency time, provides variable latency control back to the host by indicating when valid data is available for capture. ... Cypress Semiconductor Corporation

03/30/17 / #20170090626

Technique for increasing the sensitivity of capacitive sense arrays

A technique for operating a capacitive sensor array is described. The technique includes measuring a first capacitance of a first set of electrodes at a first time, measuring a second capacitance of a second set of electrodes at a second time, and calculating a position of a conductive object based on a relative magnitude of the first capacitance and the second capacitance. ... Cypress Semiconductor Corporation

03/23/17 / #20170085268

Integrated circuit device with programmable analog subsystem

An integrated circuit (ic) device can include a plurality of analog blocks, including at least one fixed function analog circuit, a plurality of reconfigurable analog circuit blocks, at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; and a digital section comprising digital circuits; wherein each analog block includes dedicated of signal lines coupled to the at least one analog routing block.. . ... Cypress Semiconductor Corporation

03/23/17 / #20170084465

Method of fabricating a charge-trapping gate stack using a cmos process flow

A method of fabricating a memory device is described. Generally, the method includes forming a channel from a semiconducting material overlying a surface of a substrate, and forming dielectric stack on the channel. ... Cypress Semiconductor Corporation

03/23/17 / #20170081940

Wellbore packer, method and tubing string

A wellbore packer for setting one or more packing elements in a borehole having an open hole section. The wellbore packer comprises a port-less mandrel configured with one or more packing elements and one or more setting mechanisms. ... Cypress Semiconductor Corporation

03/16/17 / #20170076766

Systems, methods, and devices for parallel read and write operations

Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. ... Cypress Semiconductor Corporation

03/16/17 / #20170076130

Fingerprint sensor pattern

An example sensor array includes a first electrode disposed in a first layer, multiple second electrodes disposed in a second layer, and multiple third electrodes disposed outside of the first layer. The second electrodes are galvanically isolated from the first electrode and the third electrodes. ... Cypress Semiconductor Corporation

03/09/17 / #20170068838

Multiphase fingerprint sensor layout and construction

A capacitive fingerprint sensor includes a set of capacitive sensor electrodes in a sensing area. The set of capacitive sensor electrodes includes a set of transmit (tx) sensor electrodes, a set of receive (rx) sensor electrodes, and a set of compensation electrodes. ... Cypress Semiconductor Corporation

03/09/17 / #20170068835

Half-bridge fingeprint sensing method

Fingerprint detection circuits with common mode noise rejection are described. The fingerprint detection circuit includes a half-bridge circuit coupled to a receive (rx) electrode of an array of fingerprint detection electrodes and to a buried capacitance that is unalterable by the presence of a conductive object on the array. ... Cypress Semiconductor Corporation

03/02/17 / #20170062456

Vertical division of three-dimensional memory device

A method of forming a vertical non-volatile (nv) memory device such as 3-d nand flash memory includes forming a vertical nv memory cell string within an opening disposed in a stack of alternating layers of a first layer and a second layer over a substrate, and dividing the vertical nv memory cell string into two halves with a first vertical deep trench and an isolation dielectric pillar formed in the first vertical deep trench, such that memory bit density of the divided vertical nv memory cell strings double the memory bits of the device.. . ... Cypress Semiconductor Corporation

03/02/17 / #20170061188

Baseline compensation for capacitive sensing

A capacitance sensing circuit may include a charge to digital converter, coupled to a signal receiver channel, to receive a signal from a capacitive sense array. The capacitance sensing circuit may also include a baseline compensation signal generator, coupled to the signal receiver channel, to provide a baseline compensation signal in an opposite phase of the signal to the signal receiver channel.. ... Cypress Semiconductor Corporation

03/02/17 / #20170060297

Differential sigma-delta capacitance sensing devices and methods

A capacitance sensing device can include a reference circuit configured to connect to a reference capacitance, and to generate an electrical reference signal that varies over time according to the reference capacitance and a compare signal; a sense circuit configured to connect to a sense capacitance, and to generate an electrical sense signal that varies over time according to a sense capacitance; a compare circuit having compare inputs coupled to receive the sense signal and the reference signal, and a compare output that provides the compare signal; and a value generation circuit configured to generate an output value corresponding to the compare signal over a predetermined time period.. . ... Cypress Semiconductor Corporation

02/23/17 / #20170053703

High voltage architecture for non-volatile memory

A method of erasing, during an erase operation, a non-volatile memory (nvm) cell of a memory device is disclosed. The erasing includes applying a first hv signal (vpos) to a common source line (csl). ... Cypress Semiconductor Corporation

02/23/17 / #20170052578

Low-power type-c receiver with high idle noise and dc-level rejection

Techniques for low-power usb type-c receivers with high dc-level shift tolerance and high noise rejection are described herein. In an example embodiment, a usb-enabled device comprises a receiver circuit coupled to a configuration channel (cc) line of a usb type-c subsystem. ... Cypress Semiconductor Corporation

02/16/17 / #20170047272

Tape chip on lead using paste die attach material

According to various embodiments, systems and methods for packaging a semiconductor device are provided. The disclosure discusses a semiconductor die having a top side and a bottom side that is disposed on a lead frame. ... Cypress Semiconductor Corporation

01/26/17 / #20170023995

Low-power touch button sensing system

A capacitance sensing circuit receives an application of a power supply. The capacitance sensing circuit controls a switch circuit to connect the power supply to a processing device responsive to the application of the power supply. ... Cypress Semiconductor Corporation

01/19/17 / #20170018621

Spacer formation with straight sidewall

Disclosed herein is a semiconductor device comprising a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. ... Cypress Semiconductor Corporation

01/19/17 / #20170018555

Nand memory cell string having a stacked select gate structure and process for for forming same

A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. ... Cypress Semiconductor Corporation

01/19/17 / #20170017496

Methods and physical computer-readable storage media for intiating re-enumeration of usb 3.0 compatible devices

Described herein is a system comprising a peripheral device that is connected to a host device over a bus compatible with usb 3.0. The host device comprises a reduced functionality usb host controller configured to perform a set of one or more preprogrammed functions from the usb 3.0 specification, and a universal asynchronous receiver and transmitter (uart) configured to sample usb response data received from the peripheral device over the bus.. ... Cypress Semiconductor Corporation

01/19/17 / #20170017347

Touch sensor pattern

An electronic system includes a processing device and a trellis pattern of conductors coupled to the processing device. The trellis pattern of conductors forms a multiple capacitors and the processing device is configured to sense a capacitance of each of the capacitors. ... Cypress Semiconductor Corporation

01/12/17 / #20170011807

Method to reduce program disturbs in non-volatile memory cells

A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (vneg) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. ... Cypress Semiconductor Corporation

01/12/17 / #20170011800

Systems, methods, and apparatus for memory cells with common source lines

Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. ... Cypress Semiconductor Corporation

01/12/17 / #20170011786

Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock domain

A system comprising a memory controller coupled to a memory device is described. The memory device is coupled to, and is external to, the memory controller. ... Cypress Semiconductor Corporation

01/05/17 / #20170005108

Oxide formation in a plasma process

A method of making and structural embodiments of a semiconductor structure are provided. The method includes forming a tunneling layer over a channel connecting a source and a drain formed in a surface of a substrate, forming a charge storage layer overlying the tunneling layer, and forming a blocking structure on the charge storage layer by plasma oxidation. ... Cypress Semiconductor Corporation








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