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Cypress Semiconductor Corporation
Cypress Semiconductor Corporation A Corporation Of The State Of Delaware
  

Cypress Semiconductor Corporation patents

Recent patent applications related to Cypress Semiconductor Corporation. Cypress Semiconductor Corporation is listed as an Agent/Assignee. Note: Cypress Semiconductor Corporation may have other listings under different names/spellings. We're not affiliated with Cypress Semiconductor Corporation, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "C" | Cypress Semiconductor Corporation-related inventors




Date Cypress Semiconductor Corporation patents (updated weekly) - BOOKMARK this page
10/05/17Dynamically reconfigurable analog routing and multiplexing architecture on a system on a chip
10/05/17Systems and methods for downloading code and data into a secure non-volatile memory
09/28/17Low-power touch button sensing system
09/28/17Systems, methods, and memory cells with common source lines
09/28/17Integration of a memory transistor into high-k, metal gate cmos process flow
09/14/17Type-c connector subsystem
09/14/17Sensor array with edge pattern
09/14/17Single layer sensor pattern
09/14/17Fingerprint sensor-compatible overlay material
09/14/1710-transistor non-volatile static random-access memory using a single non-volatile memory element and operation thereof
09/14/17Multi-layer inter-gate dielectric structure and manufacturing thereof
09/14/17Embedded sonos based memory cells
09/14/17Memory device with multi-layer channel and charge trapping layer
09/14/17Transceiver for communication and controlling communication
09/07/17Capacitive sensing button on chip
08/31/17Systems, methods, and devices for parallel read and write operations
08/31/17Non-volatile memory with silicided bit line contacts
08/03/17Manufacturing of fet devices having lightly doped drain and source regions
07/20/17Quasi-differential mutual capacitance measurement
07/13/17Asynchronous transceiver for on-vehicle electronic device
07/13/17Configurable capacitor arrays and switched capacitor circuits
07/06/17Split gate charge trapping memory cells having different select gate and memory gate heights
07/06/17Programmable input/output circuit
06/29/17Microcontroller programmable system on a chip
06/29/17Memory transistor with multiple charge storing layers and a high work function gate electrode
06/22/17Microcontroller programmable system on a chip
06/22/17Capacitive fingerprint sensor with quadrature demodulator and multiphase scanning
06/15/17Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock
06/15/17Asymmetric pass field-effect transistor for nonvolatile memory
06/15/17Gate fringing effect based channel formation for semiconductor device
06/08/17Method for fabricating ferroelectric random-access memory on pre-patterned bottom electrode and oxidation barrier
06/08/17Split-gate semiconductor device with l-shaped gate
05/25/17Sensor-compatible overlay
05/18/17Fingerprint sensor-compatible overlay material
05/18/17Memory first process flow and device
05/18/17Delta modulator receive channel for capacitance measurement circuits
04/13/17Integrated circuit to convert no-wire signals to one-wire signals
04/06/17Low standby power with fast turn on for non-volatile memory devices
04/06/17Protecting circuit and integrated circuit
03/30/17Technique for increasing the sensitivity of capacitive sense arrays
03/30/17Method for providing read data flow control or error reporting using a read data strobe
03/30/17Asymmetric pass field-effect transistor for non-volatile memory
03/30/17Memory device interconnects and manufacture
03/30/17Semiconductor device and manufacturing the same
03/30/17Method of manufacturing for memory transistor with multiple charge storing layers and a high work function gate electrode
03/30/17Nonvolatile charge trap memory device having a high dielectric constant blocking region
03/30/17Valley detection circuit and drive circuit
03/23/17Wellbore packer, method and tubing string
03/23/17Method of fabricating a charge-trapping gate stack using a cmos process flow
03/23/17Integrated circuit device with programmable analog subsystem
03/16/17Fingerprint sensor pattern
03/16/17Systems, methods, and devices for parallel read and write operations
03/09/17Half-bridge fingeprint sensing method
03/09/17Multiphase fingerprint sensor layout and construction
03/02/17Differential sigma-delta capacitance sensing devices and methods
03/02/17Baseline compensation for capacitive sensing
03/02/17Vertical division of three-dimensional memory device
02/23/17Low-power type-c receiver with high idle noise and dc-level rejection
02/23/17High voltage architecture for non-volatile memory
02/16/17Tape chip on lead using paste die attach material
01/26/17Low-power touch button sensing system
01/19/17Touch sensor pattern
01/19/17Methods and physical computer-readable storage media for intiating re-enumeration of usb 3.0 compatible devices
01/19/17Nand memory cell string having a stacked select gate structure and process for for forming same
01/19/17Spacer formation with straight sidewall
Patent Packs
01/12/17Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock domain
01/12/17Systems, methods, and memory cells with common source lines
01/12/17Method to reduce program disturbs in non-volatile memory cells
01/05/17Oxide formation in a plasma process
12/29/16Capacitive field sensor with sigma-delta modulator
12/29/16Method of forming controllably conductive oxide
12/22/16Automatic scheme to detect multi-standard charger types
12/22/16Switching circuit
12/22/16Analog-digital converter and control method
12/15/16Fingerprint sensing access for security and personalization in apps and devices
12/15/16Non-volatile static ram and operation thereof
12/15/16High speed, high voltage tolerant circuits in flash path
12/15/16Negative high voltage hot switching circuit
12/15/16Inter-bus communication interface device
12/01/16Ferroelectric random-access memory with pre-patterned oxygen barrier
Patent Packs
11/17/16Systems, methods, and devices for energy and power metering
11/17/16Protecting circuit and integrated circuit
11/17/16Phase controller apparatus and methods
11/10/16Integrated circuit device with programmable analog subsystem
10/27/16Asynchronous transceiver for on-vehicle electronic device
10/20/16Method and staggered start-up of a predefined, random, or dynamic number of flash memory devices
10/20/16Memory device with internal combination logic
10/20/16Three-dimensional charge trapping nand cell with discrete charge trapping film
10/20/16Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
10/20/16Oxide-nitride-oxide stack having multiple oxynitride layers
10/13/16Oxide-nitride-oxide stack having multiple oxynitride layers
10/13/16Buried hard mask for embedded semiconductor device patterning
10/13/16Sonos ono stack scaling
10/06/16Memory first process flow and device
09/29/16Capacitance sensor with sensor capacitance compensation
09/29/16Configurable capacitor arrays and switched capacitor circuits
09/08/16Embedded sonos based memory cells
08/25/16Drain extended mos transistors with split channel
08/04/16Detection of a conductive object during an initialization process of a touch-sensing device
07/28/16Split voltage non-volatile latch cell
07/28/16Integrated circuits with non-volatile memory and methods for manufacture
07/28/16Gate formation memory by planarization
07/21/16Data writing method and system
07/21/16Convex shaped thin-film transistor device having elongated channel over insulating layer
07/21/16Non-volatile memory with silicided bit line contacts
07/21/16Buried trench isolation in integrated circuits
07/14/16Semiconductor device and manufacturing the same
07/14/16Complimentary sonos integration into cmos flow
07/14/16Lateral charge storage region formation for semiconductor wordline
06/02/16Systems, methods, and devices for touch event and hover event detection
Social Network Patent Pack
05/26/16Methods and sensors for multiphase scanning in the fingerprint and touch applications
05/19/16Capacitive fingerprint sensor with quadrature demodulator and multiphase scanning
05/19/16Sonos stack with split nitride memory layer
05/12/16Semiconductor device and manufacturing the same
04/28/16High voltage, high-sensitivity self-capacitance sensing
04/28/16Background light detection for optical navigation systems
04/28/16Programmable switched capacitor block
04/28/16Low power capacitive sensor button
04/21/1610t non-volatile static random-access memory
04/21/16Charge trapping split gate embedded flash memory and associated methods
Patent Packs
04/21/16Psoc architecture
04/14/16Apparatus and reducing average scan rate to detect a conductive object on a sensing device
04/14/16Body position sensing for equipment
04/14/16Sonos type stacks for nonvolatile changetrap memory devices and methods to form the same
04/14/16Crystal oscillator start-up circuit
04/14/16System level interconnect with programmable switching
04/07/16Supply power dependent controllable write throughput for memory applications
04/07/16Method of integrating a charge-trapping gate stack into a cmos flow
04/07/16Dynamically switching communication modes in multi-standard wireless communication devices
03/31/16Computer system including reconfigurable arithmetic device with network of processor elements
03/24/16Force sensor baseline calibration
03/24/16Power-efficient voice activation
03/03/16Systems, methods, and devices for bootstrapped power circuits
03/03/16Integrated circuit device with programmable analog subsystem
02/25/16Providing a baseline capacitance for a capacitance sensing channel
02/18/16Integration of semiconductor memory cells and logic cells
02/04/16Split-gate semiconductor device with l-shaped gate
02/04/16Control apparatus, switching power supply and control method
01/28/16Generating a baseline compensation signal based on a capacitive circuit
01/28/16Multi-standard compliant usb battery charging scheme with detection of host disconnection in aca-dock mode
01/21/16Microcontroller programmable system on a chip with programmable interconnect
01/14/16Single layer sensor pattern
01/14/16Tool and refining a circuit including parametric analog elements
01/14/16Wireless locating and monitoring system
01/07/16Capacitance sensing circuits and methods
01/07/16Single layer sensor pattern
01/07/16Capacitance to code converter with sigma-delta modulator
01/07/16Barrier electrode driven by an excitation signal
01/07/16Memory architecture having two independently controlled voltage pumps
01/07/16Method of fabricating a charge-trapping gate stack using a cmos process flow
Patent Packs
01/07/16Load driver
01/07/16Programmable input/output circuit
12/24/15Encryption execute-in-place memories
12/10/15Mutual capacitance sensing array
12/03/15Programmable switched capacitor block
12/03/15Single layer touchscreen with ground insertion
10/15/15Capacitive sensing button on chip
10/15/15Method to reduce program disturbs in non-volatile memory cells
10/08/15Capacitive sensor array with pattern variation
10/08/15Methods and physical computer-readable storage media for initiating re-enumeration of usb 3.0 compatible devices
10/08/15Systems, methods, and memory cells with common source lines
10/08/15Methods to integrate sonos into cmos flow
10/08/15Use disposable gate cap to form transistors, and split gate charge trapping memory cells
10/08/15Cellular communication device with wireless pointing device function
09/03/15Barrier electrode driven by an excitation signal
07/23/15Method and reducing coupled noise influence in touch screen controllers
07/23/15Damascene oxygen barrier and hydrogen barrier for ferroelectric random-access memory
07/16/15Injected touch noise analysis
07/16/15Single layer touch sensor
07/16/15Esd clamp with a layout-alterable trigger voltage and a holding voltage above the supply voltage
Social Network Patent Pack
07/16/15Drain extended mos transistors with split channel
07/09/15Interleaving sense elements of a capacitive-sense array
07/09/15Accuracy in a capacitive sense array
07/09/15Lattice structure for capacitance sensing electrodes
07/09/15Method and data transmission via capacitance sensing device
07/09/15Detection of a conductive object during an initialization process of a touch-sensing device
07/02/15Compensation circuit for a tx-rx capacitive sensor
07/02/15Integrated circuit including parametric analog elements
07/02/15Radical oxidation process for fabricating a nonvolatile charge trap memory device
06/18/15Non-volatile memory and operating the same
06/18/15Complementary sonos integration into cmos flow
06/11/15Stylus tip shape
06/11/15Tunable baseline compensation scheme for touchscreen controllers
04/30/15Enhanced hydrogen barrier encapsulation the control of hydrogen induced degradation of ferroelectric capacitors in an f-ram process
04/30/15Multi-channel, multi-bank memory with wide data input/output
04/30/15Multi-channel physical interfaces and methods for static random access memory devices
04/23/15Virtual buttons for a touch interface
04/16/15Hover position calculation in a touchscreen device
04/16/15Techniques for generating microcontroller configuration information
04/09/15Multi-functional capacitance sensing circuit
Social Network Patent Pack
04/09/15Re-enumeration of usb 3.0 compatible devices
03/26/15Capacitive sensor arrangement
03/26/15High resolution capacitance to code converter
03/19/15Finger position sensing for handheld sports equipment
03/12/15Eliminating shorting between ferroelectric capacitors and metal contacts during ferroelectric random access memory fabrication
03/12/15Method of fabricating a ferroelectric capacitor
03/05/15Tail effect correction for slim pattern touch panels
03/05/15Active stylus to host data transmitting method
02/12/15Memory transistor with multiple charge storing layers and a high work function gate electrode
02/12/15Embedded sonos based memory cells
01/08/15Flipped cell sensor pattern
01/01/15Memory devices and methods for high random transaction rate
01/01/15Methods of fabricating an f-ram
12/25/14Sonos stack with split nitride memory layer
12/18/14Over-voltage tolerant circuit and method
12/18/14Systems and methods for providing high voltage to memory devices
11/20/14Access methods and circuits for memory devices having multiple banks
11/06/14Zero power metering circuits, systems and methods
10/23/14Uniform signals from non-uniform patterns of electrodes
10/23/14Hardware de-convolution block for multi-phase scanning
10/09/14Method to reduce program disturbs in non-volatile memory cells
10/02/14Memory devices and methods for high random transaction rate
09/25/14Oxide-nitride-oxide stack having multiple oxynitride layers
09/25/14Method and identification of touch panels
09/25/14Predictive touch surface scanning
09/18/14Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
09/18/14Memory transistor with multiple charge storing layers and a high work function gate electrode
09/18/14Nonvolatile memory cells and methods of making such cells
09/18/14Methods and circuits for measuring mutual and self capacitance
09/18/14Attenuator circuit of a capacitance-sensing circuit
Social Network Patent Pack
09/18/14Digital driving circuits, methods and systems for liquid crystal display devices
09/18/14Memory devices and systems including multi-speed access of memory modules
08/28/14Embedded sonos based memory cells
08/28/14Development, programming, and debugging environment
08/21/14Method of integrating a charge-trapping gate stack into a cmos flow
08/14/14Deuterated film encapsulation of nonvolatile charge trap memory device
07/31/14Touch sensor device
07/31/14Memory cell array latchup prevention
07/10/14System and controlling a light emitting diode fixture
07/10/14Touch identification for multi-touch technology
07/10/14Tail effect correction for slim pattern touch panels
07/10/14Stylus and related human interface devices with dynamic power control circuits
07/03/14Load driver
06/12/14Sensor mapping and creating gestures
04/17/14Sonos type stacks for nonvolatile changetrap memory devices and methods to form the same
04/10/14Memory cell array latchup prevention
04/03/14Method for fabricating a damascene self-aligned ferrorelectric random access memory (f-ram) having a ferroelectric capacitor aligned with a three dimensional transistor structure
04/03/14Development, programming, and debugging environment
04/03/14Microcontroller programmable system on a chip with programmable interconnect
03/27/14Capacitive stylus for a touch screen
03/27/14Method for fabricating a damascene self-aligned ferrorelectric random access memory (f-ram) with simultaneous formation of sidewall ferroelectric capacitors
03/20/14Method for improving scan time and sensitivity in touch sensitive user interface device
02/27/14Access methods and circuits for memory devices having multiple banks
02/13/14Dual scanning with automatic gain control
02/06/14Capacitance scanning proximity detection
01/23/14Gain correction for fast panel scanning
01/23/14Sensor array with edge pattern
01/23/14Hardware accelerator for touchscreen data processing
01/23/14Touchscreen data processing







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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