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Ememory Technology Inc
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Ememory Technology Inc patents


Recent patent applications related to Ememory Technology Inc. Ememory Technology Inc is listed as an Agent/Assignee. Note: Ememory Technology Inc may have other listings under different names/spellings. We're not affiliated with Ememory Technology Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "E" | Ememory Technology Inc-related inventors


Antifuse physically unclonable function unit and associated control method

An antifuse physically unclonable function (puf) unit includes a first sub-antifuse cell, a second sub-antifuse cell, a connection circuit, a first copying circuit and a first reading circuit. The first sub-antifuse cell includes a first antifuse transistor. ... Ememory Technology Inc

Electrostatic discharge circuit

An esd circuit is connected with a pad. The esd circuit includes a p-type transistor, an n-type transistor and a control circuit. ... Ememory Technology Inc

Non-volatile memory

A non-volatile memory including memory cells is provided. Each of the memory cells includes a substrate, a floating gate structure, a select gate structure, and a first doped region. ... Ememory Technology Inc

Control voltage searching method for non-volatile memory

A control voltage searching method is provided. Firstly, a control pulse with a preset control voltage and a preset pulse width is generated, and a control action on a memory cell. ... Ememory Technology Inc

Method of fabricating electrically erasable programmable non-volatile memory cell structure

A nvm cell structure includes a semiconductor substrate having a first conductivity type, a first well region having a second conductivity type, a floating gate transistor and an erase gate region. The first well region is disposed on a first od region of the semiconductor substrate. ... Ememory Technology Inc

Nonvolatile memory and fabrication method thereof

A nonvolatile memory cell includes a semiconductor substrate, a first od region, a second od region for forming an erase gate region, and a trench isolation region separating the first od region from the second od region. A select transistor is disposed on the first od region. ... Ememory Technology Inc

Uv-erasable memory device with uv transmitting window and fabrication method thereof

A uv-erasable memory device with a uv transmitting window is disclosed. The uv-erasable memory device includes a substrate, two serially connected pmos transistors on the substrate; an interlayer dielectric (ild) layer covering the two pmos transistors, a first intermetal dielectric (imd) layer on the ild layer, an intermediate layer on the first imd layer, a uv transmitting window in the intermediate layer, and a second intermetal dielectric (imd) layer on the first imd layer and in the uv transmitting window.. ... Ememory Technology Inc

Charge pump apparatus

A charge pump apparatus is provided. A two-phase clock signal and a four-phase clock signal for respectively driving a two-phase charge pump circuit and a four-phase charge pump circuit are generated according to delay signals of coupling nodes between delay circuits of a ring oscillator circuit.. ... Ememory Technology Inc

Charge pump circuit with a low reverse current

A charge pump circuit includes a first charge pump unit and a second charge pump unit. The first charge pump unit pumps an input voltage to output a first pumped voltage according to a first clock signal, a second clock signal and a third clock signal. ... Ememory Technology Inc

Charge pump circuit with low reverse current and low peak current

A charge pump circuit includes a voltage input port, a voltage output port, a plurality of charge pump units cascaded between the voltage input port and the voltage output port, a clock signal source, and n clock delay elements. The clock signal source generates a main clock signal and the n clock delay elements generate clock signals received by the charge pump units by delaying the main clock signal. ... Ememory Technology Inc

Non-volatile memory and method for programming and reading a memory array having the same

A non-volatile memory (nvm) includes a fin structure, a first fin field effect transistor (finfet), a second finfet, an antifuse structure, a third finfet, and a fourth finfet. The antifuse structure is formed on the fin structure and has a sharing gate, a single diffusion break (sdb) isolation structure, a first source/drain region, and a second source/drain region. ... Ememory Technology Inc

Memory system with low read power

A memory system includes a first memory bank, a first path selector, a second memory bank, a second path selector, and a sensing device. The first memory bank includes a plurality of first memory cells. ... Ememory Technology Inc

Electronic device with self-protection and anti-cloning capabilities and related method

An electronic device having anti-cloning function includes a first critical integrated circuit, which further includes a first security function block configured to authenticate an identity of a second critical integrated circuit in communication with the first critical integrated circuit, wherein the first security function block authenticates the identity of the second critical integrated circuit according to a chip identity of the second critical integrated circuit created using a non-volatile memory (nvm) physically unclonable function (puf).. . ... Ememory Technology Inc

Ememory Technology Inc.

. . ... Ememory Technology Inc

07/20/17 / #20170207773

Power-up sequence protection circuit for avoiding unexpected power-up voltage

A power-up sequence protection circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. First terminals of the first transistor, the second transistor, and the fourth transistor are coupled for receiving a program voltage. ... Ememory Technology Inc

07/20/17 / #20170207230

Single-poly nonvolatile memory cell structure having an erase device

A single-poly nonvolatile memory cell includes an soi substrate having a semiconductor layer, a first od region and a second od region on the semiconductor layer, an isolation region separating the first od region from the second od region, a pmos select transistor disposed on the first od region, and a pmos floating gate transistor disposed on the first od region. The pmos floating gate transistor is serially connected to the pmos select transistor. ... Ememory Technology Inc

07/20/17 / #20170206980

Method for programming antifuse-type one time programmable memory cell

A method for programming an antifuse-type otp memory cell is provided. Firstly, a first program voltage is provided to a gate terminal of an antifuse transistor. ... Ememory Technology Inc

07/20/17 / #20170206976

Power switch circuit

A power switch circuit includes a first transistor, a second transistor and a current source. A first source/drain terminal and a gate terminal of the first transistor receive a first supply voltage and a second supply voltage, respectively. ... Ememory Technology Inc

07/20/17 / #20170206975

Memory cell with low reading voltages

A memory cell includes a program select transistor, a program element, a read select transistor, a read element, and an erase element. The program select transistor is coupled to a program source line, a program select line, and a program control line. ... Ememory Technology Inc

07/20/17 / #20170206970

Memory array capable of performing byte erase operation

A memory array includes a plurality of memory pages, each memory page includes a plurality of memory bytes, each memory byte includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. Memory bytes of the same column are coupled to the same erase line, and memory bytes of different columns are coupled to different erase lines. ... Ememory Technology Inc

07/20/17 / #20170206969

Memory cell with high endurance for multiple program operations

A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. ... Ememory Technology Inc

07/20/17 / #20170206968

Memory array with one shared deep doped region

A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. ... Ememory Technology Inc

07/20/17 / #20170206965

Non-volatile memory

A non-volatile memory includes a memory array and a controlling circuit. The memory array includes plural word lines and plural bit lines. ... Ememory Technology Inc

07/20/17 / #20170206946

Self-timed reset pulse generator and memory device with self-timed reset pulse generator

A self-timed reset pulse generator includes a flip-flop, a tracking block, and a tracking circuit. The flip-flop receives an input signal and a feedback signal and outputting a reset signal. ... Ememory Technology Inc

07/20/17 / #20170206945

Memory device, peripheral circuit thereof and single-byte data write method thereof

A memory device, a peripheral circuit thereof and a single-byte data write method thereof are provided. The peripheral circuit includes a y decoder, a page buffer, and a write circuit. ... Ememory Technology Inc

07/20/17 / #20170206941

Driving circuit for non-volatile memory

A driving circuit includes a driving stage with a first level shifter and a second level shifter. The first level shifter includes an input terminal receiving a first control signal, an inverted input terminal receiving an inverted first control signal, a first output terminal, and a second output terminal. ... Ememory Technology Inc

07/20/17 / #20170206134

Memory architecture with ecc and method for operating memory with ecc

A circuit architecture for operating error-correction code (ecc) in a memory apparatus includes a control circuit and an ecc circuit. The ecc circuit is coupled with the control circuit. ... Ememory Technology Inc

06/22/17 / #20170178745

One time programmable non-volatile memory and read sensing method thereof

A read sensing method for an otp non-volatile memory is provided. The memory array is connected with plural bit lines. ... Ememory Technology Inc

05/04/17 / #20170125121

One time programmable non-volatile memory and read sensing method thereof

A read sensing method for an otp non-volatile memory is provided. The memory array is connected with plural bit line pairs. ... Ememory Technology Inc

04/27/17 / #20170117284

One-time programmable memory cell capable of reducing leakage current and preventing slow bit response, and method for programming a memory array comprising the same

A one time programmable (otp) memory cell includes a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal and a first source terminal. ... Ememory Technology Inc

04/20/17 / #20170110467

Single-poly nonvolatile memory device

A single-poly nvm cell includes a select transistor and a floating gate transistor serially connected to the select transistor. The select transistor includes a select gate, a select gate oxide layer, a source doping region, a first ldd region merged with the source doping region, a commonly-shared doping region, and a second ldd region merged with the commonly-shared doping region. ... Ememory Technology Inc

04/20/17 / #20170110195

Non-volatile memory cell and method of operating the same

A non-volatile memory cell includes a substrate, a select gate, a floating gate, and an assistant control gate. The substrate includes a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region. ... Ememory Technology Inc

03/16/17 / #20170077920

Power supply voltage switching circuit capable of preventing current leakage

A power supply voltage switching circuit includes a power selecting module, a level shifting module, and a supply switching module. The power selecting module receives a first supply signal and a second supply signal, and outputs an intermediate supply signal according to the first supply signal and the second supply signal. ... Ememory Technology Inc

03/16/17 / #20170076765

Memory apparatus capable of preventing leakage current

A memory apparatus includes a memory sector including n memory blocks and n local bit lines, a pre-charge circuit, and a program sector selector. Each of the n memory blocks includes a plurality of memory cells. ... Ememory Technology Inc

03/16/17 / #20170076757

One-time programmable memory array having small chip area

A memory cell includes a first select transistor, a first following gate transistor, an antifuse transistor, a second following gate transistor, and a second select transistor. The first select transistor has a first terminal coupled to a bit line, a second terminal, and a gate terminal coupled to a word line. ... Ememory Technology Inc

02/23/17 / #20170054300

Power system with detecting function

A power system with detecting function includes a power source, a power level detector, and a power floating detector. The power source includes multiple voltage sources for operations in multiple voltage domains, respectively. ... Ememory Technology Inc

02/23/17 / #20170053926

Antifuse-type one time programming memory cell and array structure with same

An antifuse-type otp memory cell has following structures. A first doped region, a second doped region, a third doped region and a fourth doped region are formed in a well region. ... Ememory Technology Inc

02/23/17 / #20170053925

Antifuse-type one time programming memory cell and array structure with same

An antifuse-type one time programming memory cell has following structures. A first doped region, a second doped region, a third doped region and a fourth doped region are formed in a well region. ... Ememory Technology Inc

02/23/17 / #20170053708

Code generating apparatus and one time programming block

The invention provides a code generating apparatus and an otp memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (otp) memory cells, a reference signal provider and a sense amplifier. ... Ememory Technology Inc

02/23/17 / #20170053707

Memory system with small size antifuse circuit capable of voltage boost

A memory system includes a control block, an antifuse voltage generator, an array voltage generator, and a memory array. The control block is used to output control signals to the memory array according to a memory control data signal. ... Ememory Technology Inc

02/09/17 / #a non-volatile memory including following elements is provided. the floating gate transistor, the select transistor and the stress-releasing transistor are disposed on the substrate and coupled in series with each other. the stress-releasing transistor is located between the floating gate transistor and the select transistor. the stress-releasing transistor has a stress release ratio represented by formula (1). a lower limit value of the stress release ratio is determined by a sustainable drain side voltage of the stress-releasing transistor of the non-volatile memory which is unselected when a program operation is performed. an upper limit value of the stress release ratio is determined by a readable drain current of the non-volatile memory which is selected when a read operation is performed.

Ememory Technology Inc.

. . ... Ememory Technology Inc








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