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Everspin Technologies Inc patents

Recent patent applications related to Everspin Technologies Inc. Everspin Technologies Inc is listed as an Agent/Assignee. Note: Everspin Technologies Inc may have other listings under different names/spellings. We're not affiliated with Everspin Technologies Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "E" | Everspin Technologies Inc-related inventors

Nonvolatile logic and security circuits

In some examples, a nonvolatile storage element may be configured to store a state or value during a low power or powered down period of a circuit. For example, the nonvolatile storage element may include a bridge of resistive elements that have a resistive state that may be configured by... Everspin Technologies Inc

Delayed write-back in memory

A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the... Everspin Technologies Inc

Self-referenced read with offset current in a memory

An apparatus used in a self-referenced read of a memory bit cell includes circuitry including a plurality of transistors that includes an NMOS-follower transistor for applying a read voltage to a first end of the bit cell. An offset current is applied by an offset current transistor. A transmission gate... Everspin Technologies Inc

Isolation of magnetic layers during etch in a magnetoresistive device

Methods for manufacturing magnetoresistive devices are presented in which isolation of magnetic layers in the magnetoresistive stack is achieved by oxidizing exposed sidewalls of the magnetic layers and then depositing additional encapsulating material prior to subsequent etching steps. Etching the magnetic layers using a non-reactive gas further prevents degradation of... Everspin Technologies Inc

Magnetoresistive device and manufacturing same

A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask over a selected portion of the third layer of ferromagnetic material, wherein the mask is a metal hard mask. Thereafter, etching through the... Everspin Technologies Inc

Write verify programming of a memory device

A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set... Everspin Technologies Inc

Sensing sensing current through a conductor and methods therefor

A sensing apparatus for characterizing current flow through a conductor includes a plurality of magnetic sensors. In some embodiments, the sensors are grouped in pairs to achieve common mode rejection of signals generated in response to magnetic fields not resulting from current flow through the conductor. Sensors having different levels... Everspin Technologies Inc

Word line auto-booting in a spin-torque magnetic memory having local source lines

In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a... Everspin Technologies Inc

Magnetoresistive structure having two dielectric layers, and manufacturing same

A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the... Everspin Technologies Inc

Redundant magnetic tunnel junctions in magnetoresistive memory

Memory cells in a spin-torque magnetic random access memory (MRAM) include at least two magnetic tunnel junctions within each memory cell, where each memory cell only stores a single data bit of information. Access circuitry coupled to the memory cells are able to read from and write to a memory... Everspin Technologies Inc

Memory device with shared read/write circuitry

In some examples, a memory device may be configured to use shared read circuitry to sample a voltage drop across both a bit cell and a resistive circuit in order to perform a comparison that produces an output corresponding to the bit stored in the bit cell. The shared read... Everspin Technologies Inc

Method of manufacturing a magnetoresistive stack/ structure using plurality of encapsulation layers

A method of manufacturing a magnetoresistive stack/structure comprising etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer; depositing a first encapsulation layer on the sidewalls of the second magnetic region and over the dielectric layer;... Everspin Technologies Inc

Magnetoresistive stack and fabricating same

A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first... Everspin Technologies Inc

Bias configuration for write operations in memory

Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both... Everspin Technologies Inc

Methods of manufacturing a magnetic field sensor

A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of... Everspin Technologies Inc

Method of integration of a magnetoresistive structure

A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via... Everspin Technologies Inc

Packages for integrated circuits and methods of packaging integrated circuits

An integrated circuit package including an integrated circuit die including a first side and a second side opposite the first side, the first side including at least one magnetoresistive device formed thereon. The integrated circuit package also may include a first magnetic shield disposed on or adjacent the first side... Everspin Technologies Inc

Ecc word configuration for system-level ecc compatibility

In some examples, a memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by... Everspin Technologies Inc

Circuit and controlling mram cell bias voltages

A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature,... Everspin Technologies Inc

Non-destructive write/read leveling

In some examples, a memory device is configured with non-volatile memory array(s) having one or more associated volatile memory arrays. The memory device may include a non-destructive write mode configured to prevent access to the non-volatile memory array(s) during an initiation or calibration sequence performed by the memory device or... Everspin Technologies Inc

Memory device with timing overlap mode

In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in... Everspin Technologies Inc

Bipolar chopping for 1/f noise and offset reduction in magnetic field sensors

A chopping technique, and associated structure, is implemented to cancel the magnetic 1/f noise contribution in a Tunneling Magnetoresistance (TMR) field sensor. The TMR field sensor comprises a first bridge circuit including multiple TMR elements to sense a magnetic field and a second circuit to apply a bipolar current pulse... Everspin Technologies Inc

Short detection and inversion

In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell... Everspin Technologies Inc

Memory device with page emulation mode

In some examples, a memory is configured to write multiple pages of an internal page size from a cache on the memory to a memory array on the memory in response to receiving a single precharge command when in a page emulation mode. When in the page emulation mode, the... Everspin Technologies Inc

Structures and methods for semiconductor packaging

A semiconductor package including a lead frame having a die pad and a plurality of leads arranged along at least a portion of a periphery of the semiconductor package, a semiconductor die secured to the die pad, wherein at least a portion of the semiconductor die extends beyond a periphery... Everspin Technologies Inc

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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Everspin Technologies Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Everspin Technologies Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by