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Freescale Semiconductor Inc
Freescale Semiconductor Inc A Corporation
Freescale Semiconductor Inc formerly Known As Sigmatel Inc
Freescale Semiconductor Inc Austin Texas
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Freescale Semiconductor Inc patents


Recent patent applications related to Freescale Semiconductor Inc. Freescale Semiconductor Inc is listed as an Agent/Assignee. Note: Freescale Semiconductor Inc may have other listings under different names/spellings. We're not affiliated with Freescale Semiconductor Inc, we're just tracking patents.

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 new patent  Breach detection in integrated circuits

An apparatus embodiment includes an integrated circuit (IC) and breach-detection circuitry. The IC includes data storage circuitry, a power grid configured to distribute power to the data storage circuitry, and a plurality of nodes distributed over at least one sensitive region of the IC. The breach-detection circuitry monitors power grid... Freescale Semiconductor Inc

 new patent  Memory controller for performing write transaction

A memory controller receives first and second write transactions from a processor and stores write data in a memory. The memory controller includes an address comparison circuit, a buffer, a level control circuit, a command generator, and a control circuit. The address comparison circuit compares second and third addresses and... Freescale Semiconductor Inc

 new patent  Sample-and-hold circuit

A sample-and-hold circuit, which includes a hold capacitor at its output terminal and at least one intermediate capacitor, intermittently receives an input voltage, and a first value of a switch enable signal causes the sample-and-hold circuit to sample the input voltage and to charge the at least one intermediate capacitor... Freescale Semiconductor Inc

 new patent  Systems and methods for non-volatile flip flops

A non-volatile flip flop integrated circuit includes a master latch circuit, a slave latch circuit coupled to the master latch circuit, and a non-volatile memory array coupled to the slave latch circuit. The non-volatile memory array includes a first pair of memory cells coupled to the slave latch circuit, and... Freescale Semiconductor Inc

 new patent  Scheduler for layer mapped code words

An eNode-B includes PUSH mapping hardware for improved performance. A scheduler schedules first and second code words of first and second respective user devices. A buffer receives and stores first and second identifiers. A de-multiplexer outputs a first code word number based on the first identifier and a second code... Freescale Semiconductor Inc

Vibration and shock robust gyroscope

A MEMS device includes a movable mass having a central region overlying a sense electrode and an opening in which a suspension structure and spring system are located. The suspension structure includes an anchor coupled to a substrate and rigid links extending from opposing sides of the anchor. The spring... Freescale Semiconductor Inc

Instruction pre-fetching

Pre-fetching instructions for tasks of an operating system (OS) is provided by calling a task scheduler that determines a load start time for a set of instructions for a particular task corresponding to a task switch condition. The OS calls, and in response to the load start time, a loader... Freescale Semiconductor Inc

Hardware controlled instruction pre-fetching

A task control circuit maintains, in response to task event information, a task information queue that includes task information for a plurality of tasks. Based upon the task information in the task information queue, a future task switch condition is identified as corresponding to a task switch time for a... Freescale Semiconductor Inc

Direct memory access (dma) unit with address alignment

Systems and methods for operating a DMA unit with address alignment are disclosed. These may include configuring a bandwidth control setting for a read job that includes a data transfer size corresponding to a first number of bytes. A second number of bytes to reach a read address alignment is... Freescale Semiconductor Inc

Packaged semiconductor device having a lead frame and inner and outer leads and forming

A method of making a packaged integrated circuit device includes forming a lead frame with leads that have an inner portion and an outer portion, the inner portion of the lead is between a periphery of a die pad and extends to one end of openings around the die pad.... Freescale Semiconductor Inc

Shielded package with integrated antenna

A semiconductor structure includes a packaged semiconductor device having at least one device, a conductive pillar, an encapsulant over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface to a second major surface of the encapsulant, and is exposed... Freescale Semiconductor Inc

Solid state microwave heating apparatus with stacked dielectric resonator antenna array, and methods of operation and manufacture

An embodiment of a microwave heating apparatus includes a solid state microwave energy source, a first dielectric resonator antenna that includes a first exciter dielectric resonator and a first feed structure in proximity to the first exciter dielectric resonator, one or more additional dielectric resonators stacked above the top surface... Freescale Semiconductor Inc

Solid state microwave heating apparatus with dielectric resonator antenna array, and methods of operation and manufacture

An embodiment of a microwave heating apparatus includes a solid state microwave energy source, a chamber, a dielectric resonator antenna with an exciter dielectric resonator and a feed structure, and one or more additional dielectric resonators each positioned within a distance of the exciter resonator to form a dielectric resonator... Freescale Semiconductor Inc

Controlled pulse generation methods and apparatuses for evaluating stiction in microelectromechanical systems devices

Methods and apparatuses are provided for evaluating or testing stiction in Microelectromechanical Systems (MEMS) devices utilizing a mechanized shock pulse generation approach. In one embodiment, the method includes the step or process of loading a MEMS device, such as a multi-axis MEMS accelerometer, into a socket provided on a Device-Under-Test... Freescale Semiconductor Inc

Esd protection structure

An ESD protection structure formed within a semiconductor substrate of an integrated circuit device. The ESD protection structure comprises a thyristor structure being formed from a first P-doped section forming an anode of the thyristor structure, a first N-doped section forming a collector node of the thyristor structure, a second... Freescale Semiconductor Inc

Clear channel assessment

Circuits and methods concerning signal detection are disclosed. In some example embodiments, an apparatus is configured to detect presence of a spreading sequence in a sample data sequence. Phase differences between samples in a sample sequence are determined. Presence of a spreading sequence in the sample sequence is detected by... Freescale Semiconductor Inc

Communication link adjustments in wireless networks based upon composite lqi measurements

Methods and systems are disclosed to adjust communication links within wireless networks based upon composite link quality indicators (LQIs). Packet communications are received by a network node through a communication link from a separate network node within a wireless network. The network node can also be configured to transmit packet... Freescale Semiconductor Inc

Conversion rate control for analog to digital conversion

A method, apparatus, and energy metering system obtains mains samples of a mains power line signal, performs non-white noise (NWN) filtering of the mains power line signal, obtains adjustable clock source samples of an adjustable clock signal of an adjustable clock oscillator, determines a difference based on the mains samples... Freescale Semiconductor Inc

Kernel based cluster fault analysis

A fault analysis method comprises: receiving fault data from wafer level testing that identifies locations and test results of a plurality of die; applying a kernel transform to the fault data to produce cluster data, where the kernel transform defines a fault impact distribution that defines fault contribution from the... Freescale Semiconductor Inc

Mass storage system and storing mass data

A mass storage system for storing mass data generated by a mass data source. The system includes a data buffer coupled to the mass data source, and a file system and command generator. The data buffer caches the mass data. The file system and command generator generates file system data... Freescale Semiconductor Inc

Method of wafer dicing for backside metallization

Method embodiments of wafer dicing for backside metallization are provided. One method includes: applying dicing tape to a front side of a semiconductor wafer, wherein the front side of the semiconductor wafer includes active circuitry; cutting a back side of the semiconductor wafer, the back side opposite the front side,... Freescale Semiconductor Inc

Method and performing distributed computation of precoding estimates

A method and apparatus for performing distributed computation of precoding estimates within a DAS. An RRH comprises a receiver component arranged to receive uplink signals from active user devices. The RRH further comprises a processing component arranged to perform channel estimation for each active user device m, based on the... Freescale Semiconductor Inc

Shielded and packaged electronic devices, electronic assemblies, and methods

Shielded and packaged electronic devices, electronic assemblies, and methods are disclosed herein. The shielded and packaged electronic devices include a packaged electronic device with a package surface and a plurality of electrically conductive package pads arranged on the package surface, a shielding dielectric layer extending in contact with the package... Freescale Semiconductor Inc

Mems gyroscope device

A microelectromechanical system (MEMS) gyroscope device includes a substrate having a surface parallel to a plane; first and second proof masses driven to slide back and forth past one another in a first directional axis of the plane, where the first and second proof masses respectively have a first and... Freescale Semiconductor Inc

Method and managing mismatches within a multi-threaded lockstep processing system

A processing system comprising a first processing domain and a second processing domain. Each of the first processing domain and the second processing domain comprises a multi-threaded processor core arranged to output a set of internal state signals representative of current states of internal components of the respective processor core.... Freescale Semiconductor Inc

Semiconductor device and making

A semiconductor device is disclosed that includes a first region of a first conductivity type that includes a drain, a region of a second conductivity type abutting the first region in a lateral direction and a vertical direction to form an interface between the first conductivity type and the second... Freescale Semiconductor Inc

Application specific low-power secure key

A key generator including a low-power key adjust circuit, and a high-power key adjust circuit. The low-power key adjust circuit including a storage location to store an original key, a shifter to shift the original key by a number of steps to shift to create a first key, and an... Freescale Semiconductor Inc

Angular rate sensor

A MEMS sensor for measuring rotational motion about a first axis includes a frame, a base structure under the frame, a drive mass mounted in the frame for rotational movement about a second axis perpendicular to the first axis, and a first drive paddle in the drive mass. A first... Freescale Semiconductor Inc

Systems and methods for non-volatile flip flops

An integrated circuit includes a first plurality of flip flops; a first bank of resistive memory cells, wherein each flip flop of the first plurality of flip flops uniquely corresponds to a resistive memory cell of the first bank of resistive memory cells; write circuitry configured to store data from... Freescale Semiconductor Inc

Integrated circuit package with solder balls on two sides

An integrated circuit package with solder balls on two major sides of the package and a method of making. The integrated circuit package includes at least one die encapsulated in an encapsulant. A work piece panel is formed with encapsulated die. Solder balls are attached to two major opposing sides... Freescale Semiconductor Inc

Sensing and detection of esd and other transient overstress events

An integrated circuit includes an I/O pad and a protection device coupled to the I/O pad and a first supply node. A transient event detector includes a latch; a first transistor having a first current electrode coupled to the I/O pad, a control electrode coupled to a first supply node,... Freescale Semiconductor Inc

Communicaton unit receiver, integrated circuit and adc dynamic range selection

A communication unit receiver comprising: a multi-section analogue to digital converter, ADC, configured to receive an analogue signal and convert at least a first portion of the analogue signal into a digital signal using a first ADC dynamic range. A modem, coupled to the multi-section ADC, is configured to: process... Freescale Semiconductor Inc

Communicaton unit, circuit for quadrature sampling error estimation and compensation and method therefor

A communication unit comprises a modem configured to generate a first and second test digital quadrature signal. The modem is configured to: estimate a first sampling error performance associated with a first quadrature path from the first received test digital quadrature signal; estimate a second sampling error performance associated with... Freescale Semiconductor Inc

Battery monitoring device

A battery monitoring device suitable for monitoring performance of one or more battery cells, such as with respect to a battery pack powering a vehicle. The battery monitoring device includes a signal injector configured to produce a replacement physical set that emulates one or more physical properties associated with the... Freescale Semiconductor Inc

Memory interleave system and method therefor

Methods and systems for accessing a memory are provided. One method of accessing a memory includes generating a memory access profile for accesses to a memory array. A memory controller coupled to the memory array is configured using the generated memory access profile. After configuring the memory controller, accesses to... Freescale Semiconductor Inc

11/23/17 / #20170337142

Compiler global memory access optimization in code regions using most appropriate base pointer registers

A processing device includes a target processor instruction memory to store a plurality of target processor instructions that include a plurality of global memory access instructions. The processing device further includes a compiler to communicate with the target processor instruction memory, the compiler including: a global variable candidate detection module... Freescale Semiconductor Inc

11/09/17 / #20170322098

Pressure sensor device and testing the pressure sensor device

A pressure sensor device and a method for testing the pressure sensor device is provided. The pressure sensor device includes a first pressure sensor cell having a first capacitance value, and a second pressure sensor cell having a second capacitance value, the second capacitance value being different from the first... Freescale Semiconductor Inc

11/09/17 / #20170322891

Device and secure data storage

A device for secure data storage has a host unit that obtains data stored on an external device at an external storage address; a user signal generator that generates a user defined security signal based on the external storage address of the data that indicates a security level of the... Freescale Semiconductor Inc

11/09/17 / #20170324377

Amplitude detection with compensation

A circuit including an amplitude detector. The amplitude detector includes an input to receive a signal having an amplitude voltage and a first pair of transistors configured in parallel. The input is coupled to the control terminal of at least one transistor of the first pair. The amplitude detector includes... Freescale Semiconductor Inc

11/09/17 / #20170324715

Light-weight key update mechanism with blacklisting based on secret sharing algorithm in wireless sensor networks

Various embodiments include a network manager for managing network keys in a network having a plurality of nodes, the device including: a memory; and a processor configured to: determine N nodes to blacklist, wherein N is an integer; select a polynomial function from a plurality of polynomial functions of degree... Freescale Semiconductor Inc

11/09/17 / #20170324716

Autonomous key update mechanism with blacklisting of compromised nodes for mesh networks

Various embodiments described herein relate to network key manager which is configured to manage keys in nodes in the network, wherein the network key manager including a memory configured to store an update data structure; a processor configured to: determine which nodes are blacklisted; generate the update data structure of... Freescale Semiconductor Inc

11/02/17 / #20170313573

Rough mems surface

A surface of a cavity of a MEMS device that is rough to reduce stiction. In some embodiments, the average roughness (Ra) of the surface is 5 nm or greater. In some embodiments, the rough surface is formed by forming one or more layers of a rough oxidizable material, then... Freescale Semiconductor Inc

10/26/17 / #20170307697

Magnetic field sensor with multiple axis sense capability

A sensor for sensing an external magnetic field along a sensing direction comprises a sensor bridge. The sensor bridge has a first sensor leg that includes a first magnetoresistive sense element and a second sensor leg that includes a second magnetoresistive sense element. The first and second sense elements have... Freescale Semiconductor Inc

10/26/17 / #20170308108

Voltage supply regulator with overshoot protection

A voltage supply regulator includes a first output resistor including a first terminal coupled to an output voltage of the voltage supply regulator and a second terminal; a first comparator including a first input coupled to a reference voltage, a second input coupled to the second terminal of the first... Freescale Semiconductor Inc

10/26/17 / #20170308404

Data processing system having a coherency interconnect

A processing system includes a first processor configured to issue a first request in a first format, an adapter configured to receive the first request in the first format and send the first request in a second format, and a memory coherency interconnect configured to receive the first request in... Freescale Semiconductor Inc

10/26/17 / #20170310307

Systems and methods for supplying different voltage levels with shared current

An integrated circuit includes a first portion of a stacked ring oscillator coupled between a first supply voltage node and a common node, wherein the first supply voltage node provides a local supply voltage for the first portion and the common node provides a local ground for the first portion.... Freescale Semiconductor Inc

10/19/17 / #20170301636

Electrostatic discharge protection for antenna using vias

An integrated circuit device is formed to include a plurality of vias that connect an antenna to a ground reference. This configuration of the integrated circuit device provides an electrical path from the antenna to ground, thereby preventing the buildup of charge at the antenna. The vias thereby reduce the... Freescale Semiconductor Inc

10/12/17 / #20170293001

Magnetic field sensor with permanent magnet biasing

A magnetic field sensor for sensing an external magnetic field along a sensing direction oriented perpendicular to a plane of the magnetic field sensor comprises a sensor bridge. The sensor bridge has a first sensor leg that includes a first magnetoresistive sense element and a second sensor leg that includes... Freescale Semiconductor Inc

10/12/17 / #20170292995

Multi-bit data flip-flop with scan initialization

Multi-bit data flip-flops are disclosed that provide bit initialization through propagation of scan bits. Input multiplexers are configured to select between input data bits and input scan bits based upon mode select signals. Master latches receive and latch outputs from the input multiplexers. Slave latches receive and latch outputs from... Freescale Semiconductor Inc

10/12/17 / #20170293375

Capacitive sensor device and operation

A capacitive sensor system includes a capacitive sensor device having a sense electrode that includes a first capacitor, a first supply voltage in , a first switch operable to couple the sense electrode to the first supply voltage during a first mode and an analog to digital converter during a... Freescale Semiconductor Inc

10/12/17 / #20170293516

Temporal relationship extension of state machine observer

A method includes receiving a first progress request from a first state machine associated with execution of a first thread on a processor. The method includes updating a current state of a temporal relationship state machine based on the current state, the first progress request, and a predetermined temporal relationship... Freescale Semiconductor Inc

10/12/17 / #20170294393

Pre-plated substrate for die attachment

A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to... Freescale Semiconductor Inc

10/12/17 / #20170294994

Common public radio interface, cpri, lane controller and operating thereof

The present application relates to a Common Public Radio Interface, CPRI, lane controller and a method of operating thereof. The CPRI lane controller comprises a transaction counter, a symbol counter and a comparator. The transaction counter is provided for maintaining a current aggregated transactions' size, Sizetrans, representative of an accumulated... Freescale Semiconductor Inc

10/12/17 / #20170295097

System and creating session entry

A system for creating a session entry and forwarding an IP packet includes memories that store session and session template tables, and first and second processors in communication with the memories. When the first processor receives the IP packet, it determines whether the session table includes a session entry corresponding... Freescale Semiconductor Inc

10/05/17 / #20170286587

Systems and methods for creating block constraints in integrated circuit designs

Methods for generating constraints associated with an integrated circuit design are provided. The method includes identifying, with a processor, a plurality of paths based on a floor-plan data set, each of the paths specifying a first block, a second block, and a first interconnect between the first block and the... Freescale Semiconductor Inc

10/05/17 / #20170289842

Method and system for processing lower nfft lte rates over cpri link

A method including receiving, by a radio equipment control (REC) device of a wireless communication system over an interface link, time domain compressed data from a radio equipment (RE) device at a first data transmission rate. The method further including transforming, by the REC device, the time domain compressed data... Freescale Semiconductor Inc

09/28/17 / #20170276738

Multiple axis magnetic sensor

A magnetic field sensor for sensing an external magnetic field along a sensing direction comprises a sensor bridge. The sensor bridge has a first sensor leg that includes a first magnetoresistive sense element and a second sensor leg that includes a second magnetoresistive sense element. The first and second sense... Freescale Semiconductor Inc

09/28/17 / #20170277647

Integrated circuit with pin level access to io pins

An integrated circuit (IC) having multiple cores controls write access to its input/output (I/O) pins. The IC includes a pin-control circuit, a memory, and a set of I/O pins. The pin-control circuit allows a core to independently control individual ones of the I/O pins. A set of pin-control values are... Freescale Semiconductor Inc

09/28/17 / #20170278763

Semiconductor device package and methods of manufacture thereof

A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface... Freescale Semiconductor Inc

09/28/17 / #20170278768

Packaged device with extended structure for forming an opening in the encapsualant

A packaged device includes an extended structure located at a major side of the packaged device. The extended structure defines an outer area that includes encapsulated material on the major side and an inner area where there is a lack of encapsulant over a portion of the device at the... Freescale Semiconductor Inc

09/28/17 / #20170278825

Apparatus and methods for multi-die packaging

A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers... Freescale Semiconductor Inc

09/28/17 / #20170278937

Split gate device with doped region and method therefor

A method of forming a semiconductor device using a substrate includes forming a first select gate over the substrate, a charge storage layer over the first select gate, over the second select gate, and over the substrate in a region between the first select gate and the second select gate,... Freescale Semiconductor Inc

09/28/17 / #20170278961

Semiconductor devices with an enhanced resistivity region and methods of fabrication therefor

Embodiments of a semiconductor device include a base substrate including an upper surface, a nucleation layer disposed over the upper surface of the base substrate, a first semiconductor layer disposed over the nucleation layer, a second semiconductor layer disposed over the first semiconductor layer, a channel within the second semiconductor... Freescale Semiconductor Inc

09/28/17 / #20170279268

Power switch module, smart grid power supply arrangement and method therefor

A power switch module comprising a control component. Upon an indicated operating condition fulfilling a protection condition, the control component is arranged to transition the power switch module from an ON state to a latched-OFF state in which the control component is arranged to configure the switching device to be... Freescale Semiconductor Inc

09/14/17 / #20170263324

Sector retirement for split-gate memory

A memory is provided. The memory includes an array of non-volatile memory (NVM) cells arranged in a plurality sectors. A control gate driver circuit has an output coupled to control gates of the NVM cells in a sector in the plurality of sectors. An address decoder is coupled to the... Freescale Semiconductor Inc

Patent Packs
09/14/17 / #20170263538

Packaged semiconductor device having bent leads and forming

A package device has a first lead frame having a first flag. A first integrated circuit is on the first flag. A first encapsulant is over the first integrated circuit. A first plurality of leads is electrically bonded to the first integrated circuit. A first lead of the first plurality... Freescale Semiconductor Inc

09/14/17 / #20170264124

Regulation circuit having analog and digital feedback and method therefor

A regulation circuit for powering a device while charging a battery is provided. The regulation circuit includes at least one analog feedback loop, and a digitally controlled feedback loop. The digitally controlled feedback loop includes first and second comparators. The first and second comparators compare an input power supply voltage... Freescale Semiconductor Inc

09/14/17 / #20170265228

Linear combination for rach detection

A method including receiving, by an antenna combiner of a wireless communication system, a set of Random Access Channel (RACH) sequences of a first RACH signal from a first antenna and a set of RACH sequences of a second RACH signal from a second antenna. The method further including selecting,... Freescale Semiconductor Inc

09/07/17 / #20170255485

Data processing system having dynamic thread control

A method for managing thread execution in a processing system is provided. The method includes setting a first watchpoint, and generating a first watchpoint trigger corresponding to the first watchpoint. In response to the first watchpoint trigger, execution of a first thread is controlled in accordance with a value stored... Freescale Semiconductor Inc

09/07/17 / #20170257466

System and adaptive learning time based network traffic manager

Data packets are received at a media access control interface. An arbitration policy at a traffic management controller adapts to changes in network traffic characteristics by implementing a learning phase during which processing time information based upon individual packets is updated. The processing time information includes first processing time information... Freescale Semiconductor Inc

08/31/17 / #20170247247

Integrated capacitive humidity sensor

A semiconductor device composed of a capacitive humidity sensor comprised of a moisture-sensitive polymer layer electrografted to an electrically conductive metal layer situated on an CMOS substrate or a combined MEMS and CMOS substrate, and exposed within an opening through a passivation layer, packages composed of the encapsulated device, and... Freescale Semiconductor Inc

08/31/17 / #20170249103

Data processing system having a write request network and a write data network

A data processing system includes a plurality of switch points interconnected by a write data network and a write request network. Each switch point includes write request switch circuitry having write request ingress ports and write request egress ports coupled to the write request network and arbitration circuitry configured to... Freescale Semiconductor Inc

08/31/17 / #20170249993

Memory repair system and method therefor

A memory system includes a main memory array, a redundant memory array, and a content addressable memory (CAM). The CAM includes a plurality of entries, wherein each entry includes a plurality of column address bits and a plurality of maskable row address bits. When an access address for a memory... Freescale Semiconductor Inc

08/31/17 / #20170250656

Multiple path amplifier with pre-cancellation

A device includes a first amplifier coupled to a first signal conduction path and a second amplifier coupled to a second signal conduction path. A first coupler is coupled to the first signal conduction path. The first coupler is configured to produce an output signal based on a first signal... Freescale Semiconductor Inc

08/31/17 / #20170250730

Passive equalizer capable of use in high-speed data communication

A passive equalizer is provided. The passive equalizer includes a first resistive element, a first inductive element, a second resistive element, and a first variable capacitor. The first resistive element is coupled between an input node and an output node. The first inductive element and the second resistive element are... Freescale Semiconductor Inc

08/24/17 / #20170244395

Circuit for reducing negative glitches in voltage regulator

A circuit that stabilizes an output signal of a voltage regulator includes a glitch amplifier, a pulse generator, and a transistor. The glitch amplifier amplifies glitches in the output signal and generates a glitch amplifier output signal. The pulse generator receives the glitch amplifier output signal and generates a control... Freescale Semiconductor Inc

08/24/17 / #20170244582

Fixed-point conjugate gradient digital pre-distortion (dpd) adaptation

A predistortion method and apparatus are provided which use a DPD actuator (225) to apply a memory polynomial formed with first DPD coefficients to a first input signal x[n], thereby generating a first pre-distorted input signal y[n] which is provided to the non-linear electronic device (253) to produce the output... Freescale Semiconductor Inc

08/10/17 / #20170227409

On-die temperature sensor for integrated circuit

An on-die temperature sensor measures temperature during a temperature-measurement session. A PTAT (proportional-to-absolute-temperature) generator generates an analog PTAT voltage that is dependent on temperature. A ramp generator generates a changing, analog ramp voltage whose rate of change is dependent on the PTAT voltage, such that the rate of change of... Freescale Semiconductor Inc

08/10/17 / #20170227982

Secure clock switch circuit

An integrated circuit (IC) having a clock switch that switches the system clock between an internal clock and an external clock based on whether or not the IC has finished downloading device configuration at boot and on whether or not the internal clock is functional. Further restrictions on the use... Freescale Semiconductor Inc

08/10/17 / #20170229444

Esd protection circuit

Electrostatic discharge (ESD) protection circuitry in an integrated circuit is provided. The protection circuitry includes a trigger circuit coupled between a first power supply bus and a second power supply bus. A delay circuit is coupled to receive an output signal from the trigger circuit. The delay circuit includes a... Freescale Semiconductor Inc

Patent Packs
08/10/17 / #20170230311

Buffer allocation and use for packet cloning and mangling

A method of cloning and mangling a received data packet in which an unused space of a receiving buffer can be used to accommodate at least some generated clone packets. Additional memory-use efficiencies can be realized by employing scatter-gather lists in the process of clone-packet generation when the size of... Freescale Semiconductor Inc

08/03/17 / #20170223152

Network application verification at a network processor

A network application is verified at a network processor by selecting network application functions based on a field of an ingress packet. The network application is composed of a set of network application functions, with each function carrying out a corresponding packet processing operation, such as packet parsing, statistical gathering,... Freescale Semiconductor Inc

08/03/17 / #20170220414

Multi-dimensional parity checker (mdpc) systems and related methods for external memories

Multi-dimensional parity checker (MDPC) systems and related methods are disclosed to check parity of data regions within external memories. In one embodiment, the MDPC system includes a control register and a parity checker. The parity checker receives data segments accessed from the data region. The parity checker generates and accumulates... Freescale Semiconductor Inc

08/03/17 / #20170220491

Direct interface between sram and non-volatile memory

A memory system comprises an SRAM array and a NVM array. The SRAM array and NVM array are both organized in rows and columns. The NVM array is directly coupled to the SRAM array. The memory system may also be coupled to a system bus of a data processing system.... Freescale Semiconductor Inc

08/03/17 / #20170223637

Receiver removal detection in wireless charging systems

A wireless charging system has a transmitter and a receiver. The transmitter has (i) a TX coil that wirelessly transfers power to the receiver and (ii) TX circuitry that powers the TX coil and detects receiver removal by comparing TX input power and TX power loss. The TX circuitry can... Freescale Semiconductor Inc

07/27/17 / #20170212175

Magnetic field sensor with multiple sense layer magnetization orientations

A magnetic field sensor comprises a sensor bridge having multiple sensor legs. Each sensor leg includes magnetoresistive sense elements, each comprising a pinned layer having a reference magnetization parallel to a plane of the sensor and a sense layer having a sense magnetization. A permanent magnet layer spaced apart from... Freescale Semiconductor Inc

07/27/17 / #20170212176

Magnetic field sensor with skewed sense magnetization of sense layer

A magnetic field sensor comprises a sensor bridge having multiple sensor legs. Each sensor leg includes magnetoresistive sense elements, each comprising a pinned layer having a reference magnetization parallel to a plane of the sensor and a sense layer having a sense magnetization that is skewed away from three orthogonal... Freescale Semiconductor Inc

07/27/17 / #20170212189

Magnetic field sensor with permanent magnet biasing

A magnetic field sensor comprises a sensor bridge having multiple sensor legs. Each sensor leg includes magnetoresistive sense elements located in a plane of the magnetic field sensor. Each sense element comprises a pinned layer and a sense layer. The pinned layer has a reference magnetization oriented parallel to the... Freescale Semiconductor Inc

07/27/17 / #20170212800

System and performing bus transactions

A system that performs a bus transaction includes a transaction controller and a protection code processing circuit. The transaction controller identifies a set of parameters corresponding to the bus transaction based on address and received control information, and modifies at least one parameter or splits the bus transaction into sub-transactions... Freescale Semiconductor Inc

07/27/17 / #20170213601

Full address coverage during memory array built-in self-test with minimum transitions

A method and apparatus for generating an address sequence in a memory device is provided. The method includes providing a memory array having a set of unique addresses, storing one of a first subset of the set of unique addresses in a first storage element, storing one of a second... Freescale Semiconductor Inc

07/06/17 / #20170192040

Current sensing circuit and method

The present application relates to a circuit arrangement for sensing a current. The circuit arrangement comprises a current sense circuit configured to cause the sense current through a sense transistor, wherein the sense current is representative of a load current through a load transistor. The current sense circuit comprises a... Freescale Semiconductor Inc

07/06/17 / #20170192790

Providing task-triggered determinisitic operational mode for simultaneous multi-threaded superscalar processor

A task identifier-based mechanism is configured to temporarily disable a dual-issue capability of one or more threads in a superscalar simultaneous multi-threaded core. The core executes a first thread and a second thread which are each provided with a dual-issue capability wherein up to two instructions may be issued in... Freescale Semiconductor Inc

07/06/17 / #20170194488

Semiconductor device with floating field plates

A semiconductor device with a current terminal region located in a device active area of a substrate of the device. A guard region is located in a termination area of the device. A plurality of floating field plates are located in the termination area and are ohmically coupled to the... Freescale Semiconductor Inc

07/06/17 / #20170195981

System and automatic delay compensation in a radio base station system

A method including performing a delay measurement of a first round trip delay value of an interface link, the first round trip delay value based on a transmission of a first REC synchronization signal to a RE and when a REC receives a first RE synchronization signal back, wherein frames... Freescale Semiconductor Inc

06/29/17 / #20170185519

Computing system with a cache invalidation unit, a cache invalidation unit and a operating a cache invalidation unit in a computing system

The present application relates to a cache invalidation unit for a computing system having a processor unit, CPU, with a cache memory, a main memory and at least one an alternate bus master unit. The CPU, the main memory and the at least one an alternate bus master unit are... Freescale Semiconductor Inc

06/29/17 / #20170187399

Transmitter output driver circuits for high data rate applications, and methods of their operation

Embodiments of single-ended and differential output driver circuits include one or more complementary data switch pairs, each coupled to a T-coil. Each complementary data switch pair is coupled between a voltage source and a ground reference node, and each complementary data switch pair includes complementary transistors, each with a control... Freescale Semiconductor Inc

06/22/17 / #20170179898

Amplifier devices with in-package bias modulation buffer

The embodiments described herein include amplifiers that are typically used in radio frequency (RF) applications. The amplifiers described herein use a buffer that is implemented inside the device package. Specifically, the amplifiers can be implemented with a gate bias modulation buffer inside the device package, where the gate bias modulation... Freescale Semiconductor Inc

06/22/17 / #20170180253

Hash-based packet classification with multiple algorithms at a network processor

A network processor has a “bi-level” architecture including a classification algorithm level and a single-record search level to search a hash database that stores packet classification information based on packet field values. The classification algorithm level implements multiple different classification algorithm engines, wherein the individual algorithm applied to a received... Freescale Semiconductor Inc

06/22/17 / #20170176535

Clock gating for x-bounding timing exceptions in ic testing

An integrated circuit includes a clock gate that is used to prevent timing exception paths from affecting data being captured by scan chain registers during at-speed scan testing. A single clock gate can be used to control multiple timing-exception paths, so the amount of X-bounding circuitry inserted into the IC... Freescale Semiconductor Inc

06/22/17 / #20170177428

Memory error detection system

An error detection system detects errors in data packets stored in a memory. A read signature generation circuit generates a read signature of a first data packet. A write signature generation circuit generates a write signature of a second data packet. When a trigger generation circuit generates a trigger signal,... Freescale Semiconductor Inc

06/22/17 / #20170177432

Memory controller and operating a memory controller

The present application relates to a memory controller and a method of operating thereof. The memory controller comprises a transaction interface arranged to be coupled to a transaction interconnect to receive a write transaction comprising write data; a mode controller arranged to obtain context information and to select a data... Freescale Semiconductor Inc

06/22/17 / #20170179049

Power grid balancing apparatus, system and method

A semiconductor apparatus for power distribution on a die, the semiconductor apparatus, comprising a first die, wherein the first die comprises a first integrated circuit, a dam coupled to the first die, wherein the dam is a metal ring, a second die, wherein the second die comprises a second integrated... Freescale Semiconductor Inc

06/22/17 / #20170179279

Partial, self-biased isolation in semiconductor devices

A device includes a semiconductor substrate, a buried doped isolation layer disposed in the semiconductor substrate to isolate the device, a drain region disposed in the semiconductor substrate and to which a voltage is applied during operation, and a depletion region disposed in the semiconductor substrate and having a conductivity... Freescale Semiconductor Inc

06/22/17 / #20170181192

Apparatus for reception and detection of random access channel (rach) data

An apparatus for reception and detection of RACH data in an LTE input signal includes a hardware accelerator that has a decimator that filters and down-samples the input signal, a first Fourier transform circuit that transforms the decimated signal from the time domain to the frequency domain, and a second... Freescale Semiconductor Inc








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