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Global Foundries Inc patents

Recent patent applications related to Global Foundries Inc. Global Foundries Inc is listed as an Agent/Assignee. Note: Global Foundries Inc may have other listings under different names/spellings. We're not affiliated with Global Foundries Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Global Foundries Inc-related inventors

Date Global Foundries Inc patents (updated weekly) - BOOKMARK this page
04/27/17Controlling right-of-way for priority vehicles
03/16/17Preventing leakage inside air-gap spacer during contact formation
03/02/17Patterning scheme to minimize dry/wets strip induced device degradation
02/23/17Finfet pcm access transistor having gate-wrapped source and drain regions
12/08/16Design of temperature-compliant integrated circuits
11/17/16Gate contact structure having gate contact layer
09/15/16Optical die packaging
09/01/16Metal-insulator-metal capacitor architecture
06/23/16Semiconductor device metal-insulator-semiconductor contacts with interface layers and methods for forming the same
05/26/16Methods, apparatus and system for voltage ramp testing
05/05/16Low threshold voltage cmos device
04/28/16Method and quantifying defects due to through silicon vias in integrated circuits
03/10/16Opposite polarity borderless replacement metal contact scheme
03/10/16Directed self-assembly material etch mask for forming vertical nanowires
02/18/16Gate stack and contact structure
01/28/16Methods for fabricating integrated circuits using directed self-assembly
01/14/16Integrated circuits with an insultating layer and methods for producing such integrated circuits
12/24/15Integrated circuits including modified liners and methods for fabricating the same
12/17/15Double self-aligned via patterning
12/03/15Reduced capacitance interlayer structures and fabrication methods
11/26/15Mask-aware routing and resulting device
11/05/15Semiconductor device configured for avoiding electrical shorting
10/29/15Methods of forming gate structures for transistor devices for cmos applications and the resulting products
08/20/15Integrated circuits with improved contact structures
08/13/15Replacement gate compatible edram transistor with recessed channel
07/30/15Gate structure cut after formation of epitaxial active regions
07/30/15E-fuse structure with methods of fusing the same and monitoring material leakage
07/09/15Threshold voltage tuning using self-aligned contact cap
07/09/15Integrated circuits including selectively deposited metal capping layers on copper lines and methods for fabricating the same
07/02/15Methods for fabricating multiple-gate integrated circuits
06/25/15Transistor device with strained layer
06/18/15Methods of forming replacement gate structures for semiconductor devices and the resulting semiconductor products
06/11/15Method of forming a dielectric film
06/11/15Semiconductor device including a transistor having a low doped drift region and the formation thereof
05/28/15Methods of forming spacers on finfets and other semiconductor devices
05/28/15Low threshold voltage cmos device
05/21/15Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
05/21/15Overlay metrology system and method
05/21/15Euv mask for use during euv photolithography processes
05/14/15Tuck strategy in transistor manufacturing flow
05/07/15Common fill of gate and source and drain contacts
05/07/15Methods for fabricating integrated circuits including generating e-beam patterns for directed self-assembly
04/16/15Preventing epi damage for cap nitride strip scheme in a fin-shaped field effect transistor (finfet) device
04/02/15Gate electrode with a shrink spacer
04/02/15Methods of forming finfet semiconductor devices using a replacement gate technique and the resulting devices
04/02/15Finfet fabrication method
04/02/15Integrated circuits with dual silicide contacts and methods for fabricating same
03/19/15Enlarged fin tip profile for fins of a field effect transistor (finfet) device
03/19/15Electronic fuse having a substantially uniform thermal profile
03/19/15Through-silicon via unit cell and methods of use
03/19/15Test macro for use with a multi-patterning lithography process
03/12/15Methods of forming finfet semiconductor devices with self-aligned contact elements using a replacement gate process and the resulting devices
02/26/15Replacement metal gate structure for cmos device
02/12/15Retargeting semiconductor device shapes for multiple patterning processes
02/05/15Reduced spacer thickness in semiconductor device fabrication
02/05/15Semiconductor fuse with enhanced post-programming resistance
02/05/15Wafer support system for 3d packaging
02/05/15Integrated circuits having finfet semiconductor devices and methods of fabricating the same to resist sub-fin current leakage
01/29/15Methods of forming an e-fuse for an integrated circuit product and the resulting e-fuse structure
01/22/15Fin transformation process and isolation structures facilitating different fin isolation schemes
01/22/15Methods for forming integrated circuits with reduced replacement metal gate height variability
01/01/15Forming tunneling field-effect transistor with stacking fault and resulting device
01/01/15Semiconductor structure with improved isolation and fabrication to enable fine pitch transistor arrays
11/20/14Methods of forming semiconductor devices with different insulation thicknesses on the same semiconductor substrate and the resulting devices
11/06/14Computer-implemented methods and systems for revision control of integrated circuit layout recipe files
Patent Packs
10/30/14Finfet with active region shaped structures and channel separation
10/23/14Method of forming a dielectric film
10/02/14Double patterning via triangular shaped sidewall spacers
09/18/14Semiconductor devices having dielectric caps on contacts and related fabrication methods
09/18/14Through-silicon via with sidewall air gap
09/18/14Technique for manufacturing semiconductor devices comprising transistors with different threshold voltages
06/19/14Partial poly amorphization for channeling prevention
03/20/14Encapsulation of closely spaced gate electrode structures
02/27/14Replacement gate fabrication methods
12/26/13Method and recording status of shippable goods
12/19/13Soi semiconductor device comprising a substrate diode and a film diode formed by using a common well implantation mask
10/24/13Silicidation and/or germanidation on sige or ge by cosputtering ni and ge and using an intralayer for thermal stability
03/14/13Semiconductor fuse with enhanced post-programming resistance
06/21/12Embedded sigma-shaped semiconductor alloys formed in transistors by applying a uniform oxide layer prior to cavity etching
01/26/12Self-aligned contact structure laterally enclosed by an isolation structure of a semiconductor device
Patent Packs
10/06/11Silicide contact formation
01/27/11Dielectric breakdown lifetime enhancement using alternating current (ac) capacitance
11/11/10Method of reducing stacking faults through annealing

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Global Foundries Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Global Foundries Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by