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Global Unichip Corporation
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Global Unichip Corp patents

Recent patent applications related to Global Unichip Corp. Global Unichip Corp is listed as an Agent/Assignee. Note: Global Unichip Corp may have other listings under different names/spellings. We're not affiliated with Global Unichip Corp, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Global Unichip Corp-related inventors




Date Global Unichip Corp patents (updated weekly) - BOOKMARK this page
04/20/17Probe card and testing method
02/23/17Testing unit and testing apparatus using the same
02/23/17Optical inspection device and optical inspection fixture thereof
02/16/17Circuit probing system and its circuit probing device
01/12/17Probe card
01/12/17Timing analysis digital circuit design and system thereof
01/12/17Common-mode filter
01/12/17Voltage mode transmitter
12/29/16Brightness calibration method and optical detection system
11/10/16Diode, diode string circuit, and electrostatic discharge protection device
10/06/16Phase interpolator and clock and data recovery circuit
06/23/16Scan flip-flop and associated method
04/21/16Clock and data recovery circuit and method
11/26/15Integrated circuit
11/05/15Voltage mode transmitter
10/22/15Aging detection circuit and method thereof
10/22/15Circuit and clock and data recovery
09/24/15Signal transmission circuit
08/13/15Electronic device, performance binning system and method, voltage automatic calibration system
04/23/15Analog to digital converter
04/23/15Scan flip-flop and associated method
04/09/15Method and associated processing module for interconnection system
02/12/15Circuit with flat electromagnetic band gap resonance structure
02/12/15Esd clamp circuit
09/25/14Current-mode d latch with reset function and associated circuit
06/05/14Phase offset cancellation circuit and associated clock generator
04/17/14Two-stage post driver circuit
04/17/14Method of controlling two-stage post driver circuit
10/24/13Method for input/output design of chip
10/17/13Eye diagram scan circuit and associated method
08/22/13Dc converter
08/22/13High speed level shifter for converting low input voltage into wide-range high output voltage
05/09/13Electronic test system and associated method
02/14/13Oscillation circuit and associated method
02/07/13Semiconductor device and associated method
09/06/12Two-stage post driver circuit
09/06/12Receiver circuit
07/26/12Power gating for in-rush current mitigation
07/19/12Esd protection circuit
06/14/12Semiconductor package device with cavity structure and the packaging method thereof
06/07/12Tunable delay cell apparatus
05/24/12Method of adaptive motion estimation in search windows for video coding
05/03/12Semiconductor package device with a heat dissipation structure and the packaging method thereof
05/03/12Method to synchronize and synthesize bus transaction traces for an un-timed virtual environment
05/03/12Hybrid electronic design system and reconfigurable connection matrix thereof
03/01/12Abutment structure of semiconductor cell
03/01/12Method for detecting the under-fill void in flip chip bga
03/01/12Communication apparatus having automatic gain control apparatus and automatic gain control method
02/09/12Package structure with underfilling material and packaging method thereof
02/09/12Esd protection scheme for integrated circuit having multi-power domains
02/02/12Burn-in socket and testing fixture using the same
02/02/12Device for storing pulse latch with logic circuit
01/26/12Semiconductor package structure and forming method thereof
01/26/12Clock and data recovery system
01/26/12Method and device for multi-channel data alignment in transmission system
01/26/12Slicing level and sampling phase adaptation circuitry for data recovery systems
01/26/12Method for packaging semiconductor device
01/19/12Through-silicon via testing structure
12/15/11Low leakage boundary scan device design and implementation
12/15/11Data transfer protection flash memory controller
12/15/11Hybrid system combining tlm simulators and hw accelerators
11/17/11Power control manager
04/14/11Programmable current mirror
12/09/10System and multi-protocol bus communications
07/28/16Substrate structure and the process manufacturing the same
Patent Packs
11/19/15Io and pvt calibration using bulk input technique
10/29/15Assembly structure for connecting multiple dies into a system-in-package chip and the method thereof
07/02/15Method and on-the-fly learning traffic control scheme
04/16/15Method and on-the-fly memory channel built-in-self-test
02/19/15Method of optimizing the width of transaction id for an interconnecting bus
02/12/15Method and an apparatus of determining performance of an integrated circuit
06/26/14Method of dynamic element matching and an apparatus thereof
11/28/13Duty cycle corrector
10/31/13Phase locked loop circuit
07/04/13Gated voltage-controlled oscillator and clock and data recovery circuit
06/06/13Clock and data recovery circuit
04/11/13Apparatus for reducing simultaneous switching noise
06/28/12Esd protection circuit for negative-powered integrated circuit
06/28/12Esd protection circuit for multi-powered integrated circuit
04/26/12System and optimizing logic timing
Patent Packs
01/05/12System for driver amplifier







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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