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Globalfoundries Inc patents

Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors




Date Globalfoundries Inc patents (updated weekly) - BOOKMARK this page
03/23/17 new patent  Dual liner silicide
03/23/17 new patent  Three-dimensional scatterometry for measuring dielectric thickness
03/23/17 new patent  Integrated circuit chip design methods and systems using process window-aware timing analysis
03/23/17 new patent  3d multipath inductor
03/23/17 new patent  Method including an adjustment of a plurality of wafer handling elements, system including a plurality of wafer handling elements and photolithography track
03/23/17 new patent  Semiconductor device with reduced poly spacing effect
03/23/17 new patent  Fin structures and multi-vt scheme based on tapered fin and method to form
03/23/17 new patent  Dual metal-insulator-semiconductor contact structure and formulation method
03/23/17 new patent  Stacked nanowire device width adjustment by gas cluster ion beam (gcib)
03/23/17 new patent  Poc process flow for conformal recess fill
03/23/17 new patent  Stacked nanowire device width adjustment by gas cluster ion beam (gcib)
03/16/17Method, apparatus and system for using hybrid library track design for soi technology
03/16/17Removal of semiconductor growth defects
03/16/17Hdp fill with reduced void formation and spacer damage
03/16/17Asymmetric semiconductor device and forming same
03/16/17Spacer chamfering gate stack scheme
03/16/17Devices and methods of creating elastic relaxation of epitaxially grown lattice mismatched films
03/16/17Methods of forming semiconductor device with self-aligned contact elements and the resulting device
03/16/17Preventing leakage inside air-gap spacer during contact formation
03/16/17Spacer chamfering gate stack scheme
03/16/17Semiconductor device with gate inside u-shaped channel and methods of making such a device
03/16/17Methods of making source/drain regions positioned inside u-shaped semiconductor material using source/drain placeholder structures
03/16/17Vertical slit transistor with optimized ac performance
03/16/17Wafer with soi structure having a buried insulating multilayer structure and semiconductor device structure
03/16/17Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins
03/09/17Detection of gate-to-source/drain shorts
03/09/17Electrostatic substrate holder with non-planar surface and etching
03/09/17Methods of forming cmos based integrated circuit products using disposable spacers
03/09/17Method of forming a semiconductor device
03/09/17Forming reliable contacts on tight semiconductor pitch
03/09/17Three-dimensional finfet transistor with portion(s) of the fin channel removed in gate-last flow
03/02/17Hard mask etch and dielectric etch aware overlap for via and metal layers
03/02/17Reliability of an electronic device
03/02/17Raised e-fuse
03/02/17Integrated circuit structure with metal crack stop and methods of forming same
03/02/17Integrated circuit structure with crack stop and forming same
03/02/17Method and structure for low-k face-to-face bonded wafer dicing
03/02/17Fin liner integration under aggressive pitch
03/02/17Electrical gate-to-source/drain connection
03/02/17Methods for fabricating programmable devices and related structures
03/02/17High voltage finfet structure with shaped drift region
03/02/17Photodetector methods and photodetector structures
03/02/17Method, apparatus and system for using tunable timing circuits for fdsoi technology
03/02/17Fin cut for taper device
03/02/17Self-aligned local interconnect technology
03/02/17Fin cut for taper device
02/23/17Method, apparatus, and system for passive die strain measurement
02/23/17Diffractive overlay mark
02/23/17Data aware write scheme for sram
02/23/17Disturb free bitcell and array
02/23/17Automatic control of spray bar and units for chemical mechanical polishing in-situ brush cleaning
02/23/17Dual liner cmos integration methods for finfet devices
02/23/17Methods for forming fin structures
02/23/17Finfet pcm access transistor having gate-wrapped source and drain regions
02/23/17Germanium photodetector with soi doping source
02/23/17Series resistance reduction in vertically stacked silicon nanowire transistors
02/23/17Forming a gate contact in the active area
02/23/17Forming a gate contact in the active area
02/16/17Process design kit for efficient and accurate mismatch simulation of analog circuits
02/16/17Methods of forming air gaps in metallization layers on integrated circuit products
02/16/17Self-aligned back end of line cut
02/16/17Filling cavities in an integrated circuit and resulting devices
02/16/17Gate tie-down enablement with inner spacer
02/16/17Methods of forming self-aligned device level contact structures
02/16/17Gate tie-down enablement with inner spacer
Patent Packs
02/16/17Field effect transistors having multiple effective work functions
02/16/17Reducing liner corrosion during metallization of semiconductor devices
02/16/17Methods and devices for metal filling processes
02/16/17Semiconductor structure including a nonvolatile memory cell and the formation thereof
02/16/17Structure and method to form a finfet device
02/16/17Semiconductor structure with multilayer iii-v heterostructures
02/16/17Early pts with buffer for channel doping control
02/16/17Forming a contact for a tall fin transistor
02/16/17Forming a contact for a tall fin transistor
02/16/17Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins
02/16/17Self-aligned gate tie-down contacts with selective etch stop liner
02/09/17Capacitor structures with embedded electrodes and fabrication methods thereof
02/09/17Damascene wires with top via structures
02/09/17Methods for forming transistor devices with different threshold voltages and the resulting devices
02/09/17Bond pad structure for low temperature flip chip bonding
Patent Packs
02/09/17Capacitor structure and forming a capacitor structure
02/09/17Bulex contacts in advanced fdsoi techniques
02/09/17Measurement measuring in thin films
02/09/17Method for forming field effect transistors
02/09/17Field effect transistor device spacers
02/09/17Forming field effect transistor device spacers
02/02/17Finfet electrical characterization with enhanced hall effect and probe
02/02/17Method and system for adjusting a circuit symbol
02/02/17Charge dynamics effect for detection of voltage contrast defect and determination of shorting location
02/02/17Mitigating transient tsv-induced ic substrate noise and resulting devices
02/02/17Three-dimensional semiconductor device with co-fabricated adjacent capacitor
02/02/17Methods of forming replacement fins comprised of multiple layers of different semiconductor materials
02/02/17Method for improved fin profile
02/02/17Trench formation for dielectric filled cut region
02/02/17Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions
02/02/17Integrated circuits and methods for their fabrication
02/02/17Trench formation for dielectric filled cut region
02/02/17High doped iii-v source/drain junctions for field effect transistors
02/02/17High doped iii-v source/drain junctions for field effect transistors
01/26/17Method including a formation of a transistor and semiconductor structure including a first transistor and a second transistor
01/26/17Method to fabricate a high performance capacitor in a back end of line (beol)
01/26/17Methods and structures for back end of line integration
01/26/17Die-die stacking
01/26/17High-k and p-type work function metal first fabrication process having improved annealing process flows
01/26/17High-k and p-type work function metal first fabrication process having improved annealing process flows
01/19/17Inline buried metal void detection by surface plasmon resonance (spr)
01/19/17Hybrid metrology technique
01/19/17Coupling inductors in an ic device using interconnecting elements with solder caps and resulting devices
01/19/17Stress relaxed buffer layer on textured silicon surface
01/19/17Gate cut with high selectivity to preserve interlevel dielectric layer
Social Network Patent Pack
01/19/17Soi-based semiconductor device with dynamic threshold voltage
01/19/17Gate cut with high selectivity to preserve interlevel dielectric layer
01/19/17Method, apparatus and system for providing multiple euv beams for semiconductor processing
01/19/17Semiconductor substrates and methods for processing semiconductor substrates
01/19/17Methods for fabricating integrated circuits using flowable chemical vapor deposition techniques with low-temperature thermal annealing
01/19/17Interconnect structure including middle of line (mol) metal layer local interconnect on etch stop layer
01/19/17Dipole-based contact structure to reduce metal-semiconductor contact resistance in mosfets
01/12/17High-pressure anneal
01/12/17Method and structure of forming controllable unmerged epitaxial material
01/12/17Process for integrated circuit fabrication including a uniform depth tungsten recess technique
Patent Packs
01/12/17Methods for producing integrated circuits using long and short regions and integrated circuits produced from such methods
01/12/17Large area contacts for small transistors
01/05/17Method of simultaneous lithography and etch correction flow
01/05/17Self-aligned via process flow
01/05/17Lateral bicmos replacement metal gate
01/05/17Integrated circuit structure with methods of electrically connecting same
01/05/17Embedded metal-insulator-metal capacitor
01/05/17Method to improve reliability of replacement gate device
01/05/17Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions
12/29/16Predicting and alerting user to navigation options and predicting user intentions
12/29/16Generative learning for realistic and ground rule clean hot spot synthesis
12/29/16Dynamic and adaptive timing sensitivity during static timing analysis using look-up table
12/29/16Methods of design rule checking of circuit designs
12/29/16Insulating a via in a semiconductor substrate
12/29/16Method to protect mol metallization from hardmask strip process
12/29/16Hdp fill with reduced void formation and spacer damage
12/29/16Integrated circuit (ic) chips with through silicon vias (tsv) and forming the ic
12/29/16Methods including a processing of wafers and spin coating tool
12/29/16Electrical fuse with high off resistance
12/29/16Electrostatic discharge and passive structures integrated in a veritcal gate fin-type field effect diode
12/29/16Tunable capacitor for fdsoi applications
12/29/16High performance heat shields with reduced capacitance
12/29/16Planar qubits having increased coherence times
12/29/16Semiconductor structures with field effect transistor(s) having low-resistance source/drain contact(s)
12/29/16Shaped terminals for a bipolar junction transistor
12/29/16Method to improve reliability of replacement gate device
12/29/16Hdp fill with reduced void formation and spacer damage
12/29/16Bipolar junction transistors with a buried dielectric region in the active device region
12/29/16Fdsoi voltage reference
12/29/16Integrated circuits with self aligned contacts and methods of manufacturing the same
Patent Packs
12/29/16Interconnect structure including middle of line (mol) metal layer local interconnect on etch stop layer
12/29/16Replacement gate multigate transistor for embedded dram
12/22/16Dual liner silicide
12/22/16Dual liner silicide
12/22/16Detecting a void between a via and a wiring line
12/22/16Siarc removal with plasma etch and fluorinated wet chemical solution combination
12/22/16Non-destructive dielectric layer thickness and dopant measuring method
12/22/16Test structures for dielectric reliability evaluations
12/22/16Chip packages with reduced temperature variation
12/22/16Unique bi-layer etch stop to protect conductive structures during a metal hard mask removal process and methods of using same
12/22/16Through silicon via device having low stress, thin film gaps and methods for forming the same
12/22/16Induction heating for underfill removal and chip rework
12/22/16Bipolar junction transistors with double-tapered emitter fingers
12/22/16Fin shape contacts and methods for forming fin shape contacts
12/22/16Recessing rmg metal gate stack for forming self-aligned contact
12/22/16Device structures for a silicon-on-insulator substrate with a high-resistance handle wafer
12/22/16Generating tensile strain in bulk finfet channel
12/22/16Dual channel finfet with relaxed pfet region
12/15/16Methods and structures for achieving target resistance post cmp using in-situ resistance measurements
12/15/16Sacrificial amorphous silicon hard mask for beol
Social Network Patent Pack
12/15/16Dummy gate used as interconnection and making the same
12/15/16Spacer chamfering gate stack scheme
12/15/16Spacer chamfering gate stack scheme
12/15/16Spacer chamfering gate stack scheme
12/15/16Freestanding spacer having sub-lithographic lateral dimension and forming same
12/15/16Spacer chamfering gate stack scheme
12/15/16Devices and methods of forming unmerged epitaxy for finfet device
12/15/16Series resistance reduction in vertically stacked silicon nanowire transistors
12/08/16Integration of hybrid germanium and group iii-v contact epilayer in cmos
12/08/16Electronic device including moat power metallization in trench
12/08/16Contacts to semiconductor substrate and methods of forming same
12/08/16Methods of forming v0 structures for semiconductor devices by forming a protection layer with a non-uniform thickness
12/08/16Ferroelectric finfet
12/08/16Method and structure to form tensile strained sige fins and compressive strained sige fins on a same substrate
12/08/16Methods of forming a gate contact above an active region of a semiconductor device
12/08/16Local thinning of semiconductor fins
12/08/16Diodes and fabrication methods thereof
12/08/16Via formation using sidewall image tranfer process to define lateral dimension
12/08/16Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same
12/01/16Defect detection process in a semiconductor manufacturing environment
Social Network Patent Pack
12/01/16Hybrid fin cutting processes for finfet semiconductor devices
12/01/16Method and structure for formation of replacement metal gate field effect transistors
12/01/16Method for forming source/drain contacts during cmos integration using confined epitaxial growth techniques and the resulting semiconductor devices
12/01/16Methods of forming replacement fins for a finfet device using a targeted thickness for the patterned fin etch mask
12/01/16Integrated circuits and methods for fabricating integrated circuits having replacement metal gate electrodes
11/24/16Method, apparatus, and system for offset metal power rail for cell design
11/24/16Device comprising a plurality of fdsoi static random-access memory bitcells and operation thereof
11/24/16Preserving the seed layer on sti edge and improving the epitaxial growth
11/24/16Implant-free punch through doping layer formation for bulk finfet structures
11/24/16Thin film based fan out and multi die package platform
11/24/16E-fuse in soi configuration
11/24/16Photodetector and forming the photodetector on stacked trench isolation regions
11/24/16Interface passivation layers and methods of fabricating
11/17/16Method, apparatus, and system for improved standard cell design and routing for improving standard cell routability
11/17/16Lithography stack and method
11/17/16Methods, apparatus and system for fabricating finfet devices using continuous active area design
11/17/16Alignment monitoring structure and alignment monitoring semiconductor devices
11/17/16Filling cavities in an integrated circuit and resulting devices
11/17/16Gate contact structure having gate contact layer
11/17/16Carbon nanotube device
11/17/16System and monitoring wafer handling and a wafer handling machine
11/17/16Via formation using sidewall image transfer process to define lateral dimension
11/10/16Detection of foreign material on a substrate chuck
11/10/16Method wherein test cells and dummy cells are included into a layout of an integrated circuit
11/10/16Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an ic device
11/10/162d self-aligned via first process flow
11/10/16Inducing device variation for security applications
11/10/16Silver alloying post-chip join
11/03/16Intelligent wardrobe program
11/03/16Block level patterning process
Social Network Patent Pack
11/03/16Method and detection of failures in under-fill layers in integrated circuit assemblies
11/03/16Cut first alternative for 2d self-aligned via
11/03/16Method to make gate-to-body contact to release plasma induced charging
11/03/16Memory bit cell for reduced layout area
11/03/16Semiconductor structure having logic region and analog region
11/03/16Novel integration process to form microelectronic or micromechanical structures
11/03/16Electrostatic discharge (esd) protection transistor devices and integrated circuits with electrostatic discharge protection transistor devices
10/27/16Method of manufacturing p-channel fet device with sige channel
10/27/16Different height of fins in semiconductor structure
10/27/16Contact geometry having a gate silicon length decoupled from a transistor length
10/27/16Semiconductor device structures with self-aligned fin structure(s) and fabrication methods thereof
10/27/16Methods for modifying an integrated circuit layout design
10/27/16Finfet devices having asymmetrical epitaxially-grown source and drain regions and methods of forming the same
10/20/16Systematic defects inspection method with combined ebeam inspection and net tracing classification
10/20/16Automatic analytical cloud scaling of hardware using resource sub-cloud
10/20/16Automatic analytical cloud scaling of hardware using resource sub-cloud
10/20/16Punch-through-stop after partial fin etch
10/20/16Layered contact structure
10/20/16Integrated circuit product with bulk and soi semiconductor devices
10/20/16Finfet conformal junction and high epi surface dopant concentration
10/20/16Fet device with tuned gate work function
10/20/16Replacement channel tfet
10/13/16Moisture and/or electrically conductive remains detection for wafers after rinse / dry process
10/13/16Electronic package that includes a plurality of integrated circuit devices bonded in a three-dimensional stack arrangement
10/13/16Semiconductor device with thin-film resistor
10/13/16Integrated circuits with spacer chamfering and methods of spacer chamfering
10/13/16Densely packed transistor devices
10/13/16Complex semiconductor devices of the soi type
10/13/16Iii-v lasers with integrated silicon photonic circuits







ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009



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