Real Time Touch



new TOP 200 Companies filing patents this week

new Companies with the Most Patent Filings (2010+)




Real Time Touch

Similar
Filing Names

Globalfoundries Inc
Globalfoundries Inc grand Cayman Cayman Islands
Globalfoundries Inc_20131212

Globalfoundries Inc patents


Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors


 new patent  Controlling of etch depth in deep via etching processes and resultant structures

The present disclosure relates to semiconductor structures and, more particularly, to a method to control depth of etch in deep via etching and related structures. The method includes: forming an interface within the substrate between an etch control dopant and material of the substrate; etching a via within substrate; and... Globalfoundries Inc

 new patent  Integrated circuit structure having deep trench capacitor and through-silicon via and forming same

One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include providing a substrate having a front side and a back side, the substrate including a deep trench (DT) capacitor within the substrate extending toward the back side of the substrate; etching... Globalfoundries Inc

 new patent  Method, apparatus, and system for using a cover mask for enabling metal line jumping over mol features in a standard cell

At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A... Globalfoundries Inc

 new patent  Ic structure including tsv having metal resistant to high temperatures and forming same

An integrated circuit (IC) structure including: a first layer including a first plurality of active devices in a first semiconductor layer over a substrate; a first wiring layer over the first layer; a second layer including a second plurality of active devices within a second semiconductor layer over the first... Globalfoundries Inc

 new patent  Interposer heater for high bandwidth memory applications

A method for integrating heaters in high bandwidth memory (HBM) applications and the related devices are provided. Embodiments include forming a silicon (Si) interposer over a substrate; forming HBM and an integrated circuit (IC) over the Si interposer; forming a heater on the Si interposer in a space between the... Globalfoundries Inc

 new patent  Deep trench metal-insulator-metal capacitors

Device structures for a metal-insulator-metal (MIM) capacitor, as well as methods of fabricating a device structure for a MIM capacitor. An active device level is formed on a substrate, a local interconnect level is formed on the active device level, and a metal-insulator-metal capacitor is formed in a via opening... Globalfoundries Inc

 new patent  Flash memory device

An integrated circuit product includes a silicon-on-insulator (SOI) substrate and a flash memory device positioned in a first area of the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulating layer positioned above the semiconductor bulk substrate, and a semiconductor layer positioned above the buried insulating... Globalfoundries Inc

 new patent  Spin-selective electron relay

Structures including a spin torque transfer magnetic tunnel junction (MTJ) stack and methods for fabricating same. A first contact is coupled with a first portion of a free layer of the MTJ stack, and a second contact is coupled with a second portion of the free layer of the MTJ... Globalfoundries Inc

 new patent  Notched fin structures and methods of manufacture

The present disclosure relates to semiconductor structures and, more particularly, to notched fin structures and methods of manufacture. The structure includes: a fin structure composed of a substrate material and a stack of multiple epitaxially grown materials on the substrate material; a notch formed in a first epitaxially grown material... Globalfoundries Inc

 new patent  Trench silicide contacts with high selectivity process

A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the... Globalfoundries Inc

 new patent  Vertical transistors stressed from various directions

A vertical transistor includes a semiconductor substrate, and fin(s) over the semiconductor substrate (n-type fin(s) and/or p-type fin(s)), the fin(s) acting as vertical transistor channels for vertical transistors. Each of the fin(s) is lattice mismatched at one or more interface(s), being stressed from below, from above, from fin sidewalls or... Globalfoundries Inc

 new patent  Finfet device with low resistance fins

A method of forming a FinFET device includes ion implanting a diffusion-inhibiting species such as carbon into source and drain regions of a semiconductor fin prior to a dopant activating anneal. The implanted carbon, which can be incorporated into the fin in conjunction with a replacement metal gate process after... Globalfoundries Inc

Tunable current ratio in a current mirror

Methods for designing and fabricating a current mirror. A first layout is received for a first back-end-of-line (BEOL) stack that is coupled with an emitter of a bipolar junction transistor in a current mirror that has a first current ratio. A second layout for a second back-end-of-line (BEOL) stack, which... Globalfoundries Inc

Method and system for constructing finfet devices having a super steep retrograde well

Generally, the present disclosure is directed to a method for forming a FinFET device that may be used in designs that include both tight and relaxed fin pitches. The method for forming the fins includes: forming a first layer of doped silicate glass above a semiconductor wafer and within a... Globalfoundries Inc

Surface area-dependent semiconductor device with increased surface area

The surface area of a surface area-dependent semiconductor device is increased by providing a dielectric layer, removing portion(s) of the dielectric layer, resulting in recession(s), and forming surface area-dependent semiconductor device(s), a portion of the device being formed along a sidewall of one, or more, of the recession(s). The resulting... Globalfoundries Inc

Compound resistor structure for semiconductor device

A compound resistor structure can use multiple electrically conductive pads connected by resistive elements to provide the equivalent resistance of a conventional resistor while spreading generated heat over a larger area. An array of pads and resistive elements can create larger resistances, metal connectors between rows of pads allowing current... Globalfoundries Inc

Method, apparatus, and system for two-dimensional power rail to enable scaling of a standard cell

At least one method, apparatus and system disclosed involves providing a functional cell for a circuit layout for an integrated circuit device. A determination as to a first location for a two-dimensional portion of a first power rail in a functional cell is made. A first portion of the first... Globalfoundries Inc

Integrated circuit products that include finfet devices and a protection layer formed on an isolation region

An integrated circuit product includes a FinFET device, a device isolation region that is positioned around a perimeter of the FinFET device, and an isolation protection layer that is positioned above the device isolation region. The FinFET device includes at least one fin, a gate structure, and a sidewall spacer,... Globalfoundries Inc

Transistor with an airgap for reduced base-emitter capacitance and forming the transistor

Disclosed are embodiments of a transistor, which incorporates an airgap for low base-emitter capacitance (Cbe). Each embodiment of the transistor has a monocrystalline base and, within the monocrystalline base, an intrinsic base region and an extrinsic base region positioned laterally adjacent to the intrinsic base region, wherein the intrinsic and... Globalfoundries Inc

Vertical vacuum channel transistor

A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a... Globalfoundries Inc

Vertical vacuum channel transistor

A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a... Globalfoundries Inc

Expansion of allowed design rule space by waiving benign geometries

Systems, methods, and computer program products for design rules checking in which the waiver of design rules is optimized while ensuring compliant designs that are manufacturable. A first design rule and a plurality of patterns of a layout that violate the first design rule are received by a design rule... Globalfoundries Inc

Shrink process aware assist features

Methods for fabricating integrated circuits are provided. In one example, a method includes providing a circuit structure layer over a substrate and at least one etch layer over the circuit structure layer, in the at least one etch layer patterning at least one primary pattern feature having at least one... Globalfoundries Inc

Method of forming a semiconductor device structure and semiconductor device structure

The present disclosure provides a method of forming a semiconductor device structure including forming a first gate stack comprising a first gate dielectric material and a first gate electrode material over a first active region in an upper portion of a substrate, forming a first spacer structure adjacent to the... Globalfoundries Inc

Preventing oxidation defects in strain-relaxed fins by reducing local gap fill voids

A semiconductor structure includes a strain-relaxed semiconductor substrate, fins on the strain-relaxed semiconductor substrate, the fins each having a bottom inactive region and an exposed top active region. The semiconductor structure further includes a liner layer along sidewalls of the bottom inactive region and adjacent surface areas of the strain-relaxed... Globalfoundries Inc

Method of manufacturing selective nanostructures into finfet process flow

A method for integrating nanostructures in finFET processing and a related device are provided. Embodiments include forming fins in a Si substrate in first and second device regions; forming STI regions in spaces between fins; forming a first hardmask over the fins and STI regions; removing a portion of the... Globalfoundries Inc

Methods of forming metallization lines on integrated circuit products and the resulting products

One illustrative method disclosed includes, among other things, forming a layer of insulating material comprising a first insulating material above a substrate and forming a metallization blocking structure in the layer of insulating material at a location that is in a path of a metallization trench to be formed in... Globalfoundries Inc

Method to reduce resistance for a copper (cu) interconnect landing on multilayered metal contacts, and semiconductor structures formed therefrom

A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench... Globalfoundries Inc

Composite isolation structures for a fin-type field effect transistor

Structures for the isolation of a fin-type field-effect transistor and methods of forming isolation for a fin-type field-effect transistor. A first dielectric layer is formed that encapsulates a plurality of fins. A second dielectric layer is formed that surrounds the first dielectric layer and the plurality of fins. A surface... Globalfoundries Inc

Devices and methods of forming unmerged epitaxy for finfet device

Devices and methods of growing unmerged epitaxy for fin field-effect transistor (FinFet) devices are provided. One method includes, for instance: obtaining a wafer having at least one source, at least one drain, and at least one fin; etching to expose at least a portion of the at least one fin;... Globalfoundries Inc

Local trap-rich isolation

A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity. In various embodiments, the trap-rich layer extends vertically through a portion of an isolation... Globalfoundries Inc

Directed surface functionalization on selected surface areas of topographical features with nanometer resolution

A method for making a single molecule receptor in a nanopore structure includes depositing a material by a physical vapor deposition (PVD) technique onto a selected interior surface of a nanochannel and functionalizing a surface of the material with a chemical compound having at least two functional groups. The material... Globalfoundries Inc

Slew window shift placement method to reduce hot spots and recover vt/area

Systems and methods for reducing hot spots and recovering Vt/area to improve chip performance in an integrated circuit design. According to the method, physical grid areas for an IC chip are defined and a switching window for library elements of an integrated circuit design in a region of the chip... Globalfoundries Inc

Method, system and program product for identifying anomalies in integrated circuit design layouts

Disclosed is a method and corresponding system and program product that includes providing integrated circuit design layout(s), deconstructing the integrated circuit design layout(s) into unit-level geometric constructs, identifying anomalies in the unit-level geometric constructs, and storing anomaly data in a database. The method further includes determining one or more feature... Globalfoundries Inc

Semiconductor structure including low-k spacer material

A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is... Globalfoundries Inc

03/29/18 / #20180090386

Process for forming semiconductor layers of different thickness in fdsoi technologies

In fully depleted SOI transistors, specifically designed semiconductor materials may be provided for different types of transistors, thereby, for instance, enabling a reduction of hot carrier injection in transistors that are required to be operated at a moderately high operating voltage. To this end, well-controllable epitaxial growth techniques may be... Globalfoundries Inc

03/29/18 / #20180090387

Method for forming nanowires including multiple integrated devices with alternate channel materials

Methods for forming a NW with multiple devices having alternate channel materials and resulting devices are disclosed. Embodiments include forming a first stack of semiconductor layers including a first doped Si layer, a first channel layer, and a second doped Si layer, respectively, on a Si substrate; forming a second... Globalfoundries Inc

03/29/18 / #20180090391

Methods, apparatus and system for self-aligned retrograde well doping for finfet devices

At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having doping region self-aligned with a fin reveal position. A plurality of fins of a transistor is formed. A nitride cap layer on the plurality of fins is formed. An N-type doped region... Globalfoundries Inc

03/29/18 / #20180090447

Contacts to semiconductor substrate and methods of forming same

An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a contact opening in a dielectric layer over the semiconductor substrate to expose an upper portion of the semiconductor substrate; depositing a first liner layer... Globalfoundries Inc

03/29/18 / #20180090516

Method to improve crystalline regrowth

The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the... Globalfoundries Inc

03/29/18 / #20180090558

Capacitive structure in a semiconductor device having reduced capacitance variability

A capacitor, such as an N-well capacitor, in a semiconductor device includes a floating semiconductor region, which allows a negative biasing of the channel region of the capacitor while suppressing leakage into the depth of the substrate. In this manner, N-well-based capacitors may be provided in the device level and... Globalfoundries Inc

03/29/18 / #20180090598

Controlling self-aligned gate length in vertical transistor replacement gate flow

A semiconductor structure includes a semiconductor substrate, a bottom source/drain layer for a first vertical transistor over the semiconductor substrate, a vertical channel over the source/drain layer, and a metal gate wrapped around the vertical channel, the vertical channel having a fixed height relative to the metal gate at an... Globalfoundries Inc

03/29/18 / #20180090624

Width adjustment of stacked nanowires

In one aspect, a method of forming a semiconductor device includes the steps of: forming an alternating series of sacrificial/active layers on a wafer and patterning it into at least one nano device stack; forming a dummy gate on the nano device stack; patterning at least one upper active layer... Globalfoundries Inc

03/29/18 / #20180090374

Two-dimensional self-aligned super via integration on self-aligned gate contact

Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts. First gate contacts and terminal contacts are recessed to form a metal layer on top. Second gate contacts are recessed... Globalfoundries Inc

03/22/18 / #20180082007

Performance matching in three-dimensional (3d) integrated circuit (ic) using back-bias compensation

Various embodiments include approaches for designing three-dimensional (3D) integrated circuits (ICs). In one embodiment, a system is configured to: read an electronic chip identification (ECID) for a plurality of dies formed from distinct wafer lots, the ECID indicating a process performance parameter for each distinct wafer lot; create a reference... Globalfoundries Inc

03/22/18 / #20180082852

Fin patterning for a fin-type field-effect transistor

Methods for fabricating fins for a fin-type field-effect transistor (FinFET) and fin structures for a FinFET. A conformal layer is formed that includes respective first portions on sidewalls of first hardmask sections previously formed on a substrate, a recess between the first portions on the sidewalls of each adjacent pair... Globalfoundries Inc

03/22/18 / #20180082871

Gas flow process control system and method using crystal microbalance(s)

Disclosed are process control systems and methods incorporating a crystal microbalance (CM) (e.g., a quartz crystal microbalance (QCM)) into gas flow line(s) entering and/or exiting a processing chamber. A CM measures the resonance of a quartz crystal sensor contained therein as gas flows over that crystal sensor and can, thereby... Globalfoundries Inc

03/22/18 / #20180082889

Fdsoi channel control by implanted high-k buried oxide

Methods of locally changing the BOX layer of a MOSFET device to a high-k layer to provide different Vts with one backside voltage and the resulting device are provided. Embodiments include providing a Si substrate having a BOX layer formed over the substrate and a SOI layer formed over the... Globalfoundries Inc

03/22/18 / #20180083089

Semiconductor device resistor structure

A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat... Globalfoundries Inc

03/22/18 / #20180083121

Methods of forming bottom and top source/drain regions on a vertical transistor device

One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure above a substrate, performing an epi deposition process to simultaneously form at least a portion of a bottom source/drain region and at least a portion of a top source/drain region during the epi deposition... Globalfoundries Inc

03/22/18 / #20180083136

Methods of forming a vertical transistor device

One illustrative method disclosed herein includes, among other things, defining a cavity in a plurality of layers of material positioned above a bottom source/drain (S/D) layer of semiconductor material, wherein a portion of the bottom source/drain (S/D) layer of semiconductor material is exposed at the bottom of the cavity, and... Globalfoundries Inc

03/22/18 / #20180083441

Method, apparatus, and system for a semiconductor device having novel electrostatic discharge (esd) protection scheme and circuit

Methods, apparatus, and systems relating to a semiconductor device having an ESD function for providing a first ESD current flow in a first path and a second ESD current flow in a second path. The semiconductor device includes a pad for at least one of receiving or transmitting an electrical... Globalfoundries Inc

03/22/18 / #20180083629

Integrated level translator and latch for fence architecture

The present disclosure relates to integrated level translator and latch circuits and, more particularly, to an integrated level translator and latch circuits for fence architectures in SRAM cells. The integrated level translator and latch for input signals includes a first clock (CLKS) and a second clock (CLKH). The first clock... Globalfoundries Inc

03/15/18 / #20180075921

Word line voltage generator for programmable memory array

The present disclosure relates to a method of generating a high differential read current through a non-volatile memory, including receiving a voltage read input from a word line voltage generator, outputting a first current to a bit line true (BLT), outputting a second current to a bit line complement (BLC),... Globalfoundries Inc

03/15/18 / #20180076082

Forming air gap

A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming an air gap mask layer over a dielectric interconnect layer, the dielectric interconnect layer including a dielectric layer having a conductive interconnect therein and a cap layer over... Globalfoundries Inc

03/15/18 / #20180076110

Backside spacer structures for improved thermal performance

Methods for reducing the junction temperature between an IC chip and its lid by including metal spacers in the TIM layer and the resulting devices are disclosed. Embodiments include providing a substrate, including integrated circuit devices, having front and back sides; forming vertical spacers on the backside of the substrate;... Globalfoundries Inc

03/15/18 / #20180076299

Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins

A method of making a semiconductor device includes forming a fin in a substrate; depositing a first spacer material to form a first spacer around the fin; depositing a second spacer material to form a second spacer over the first spacer; recessing the first spacer and the second spacer; removing... Globalfoundries Inc

03/08/18 / #20180067396

Forming edge etch protection using dual layer of positive-negative tone resists

Methods of forming edge etch protection using dual layers of positive-negative tone resists. According to a method, a wafer substrate is provided. A first type resist is deposited on a surface of the wafer substrate. The first type resist is patterned and a resist ring is created around a peripheral... Globalfoundries Inc

03/08/18 / #20180068993

Thermally enhanced package to reduce thermal interaction between dies

A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a substrate; forming a lid over the IC chips; and forming a slit through the lid at a boundary between adjacent IC chips.... Globalfoundries Inc

03/08/18 / #20180069005

Punchthrough stop layers for fin-type field-effect transistors

Device structures for a FinFET and fabrication methods for making a device structure for a FinFET. A first layer containing a first dopant is formed on a first region of a substrate. A second layer containing a second dopant is formed on a second region of the substrate. A first... Globalfoundries Inc

03/08/18 / #20180069009

Selective sac capping on fin field effect transistor structures and related methods

FinFET structures and methods of forming such structures. The FinFET structures including a substrate; at least two gates disposed on the substrate; a plurality of source/drain regions within the substrate adjacent to each of the gates; a dielectric disposed between each gate and the plurality of source/drain regions adjacent to... Globalfoundries Inc

03/08/18 / #20180069091

Method for late differential soi thinning for improved fdsoi performance and hci optimization

Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate... Globalfoundries Inc

03/08/18 / #20180069092

Source/drain parasitic capacitance reduction in finfet-based semiconductor structure having tucked fins

A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps,... Globalfoundries Inc

03/08/18 / #20180069106

Fabrication of integrated circuit structures for bipolor transistors

Methods according to the present disclosure include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming an epitaxial layer on at least the first semiconductor region of the substrate, wherein the epitaxial layer... Globalfoundries Inc

03/08/18 / #20180068858

Forming a contact for a tall fin transistor

A method of making a semiconductor device includes forming a recessed fin in a substrate, the recessed fin being substantially flush with a surface of the substrate; performing an epitaxial growth process over the recessed fin to form a source/drain over the recessed fin; and disposing a conductive metal around... Globalfoundries Inc

Patent Packs
03/01/18 / #20180061699

Multiple patterning process for forming pillar mask elements

A method includes forming a stack of hard mask layers above a process layer. The stack includes first, second and third hard mask layers. The third hard mask layer is patterned to define therein a first mask element and to expose portions of the second hard mask layer. The second... Globalfoundries Inc

03/01/18 / #20180061749

Post zero via layer keep out zone over through silicon via reducing beol pumping effects

An IC structure and related method are provided. The IC structure includes: a semiconductor substrate and a TSV disposed within the semiconductor substrate. A first interconnect layer includes a plurality of V0 vias disposed on the TSV, where the plurality of V0 vias are positioned laterally within an upper surface... Globalfoundries Inc

03/01/18 / #20180061777

Tiled-stress-alleviating pad structure

Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad structure.... Globalfoundries Inc

03/01/18 / #20180061832

Methods, apparatus and system for sti recess control for highly scaled finfet devices

At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess... Globalfoundries Inc

03/01/18 / #20180061839

Semiconductor device structure with self-aligned capacitor device

A semiconductor device structure is disclosed including a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer, a substrate material and a buried insulating material layer positioned between the semiconductor layer and the substrate material, a trench isolation structure positioned in at least a portion of the SOI substrate,... Globalfoundries Inc

03/01/18 / #20180061842

Devices with contact-to-gate shorting through conductive paths between fins and fabrication methods

Semiconductor devices and methods of fabricating the semiconductor devices for forming conductive paths between fins for contact-to-gate shorting. One method includes, for instance: obtaining wafer with a substrate, at least one fin, at least one hard mask, and an oxide layer; etching the oxide layer to reveal at least one... Globalfoundries Inc

03/01/18 / #20180061969

Integrated circuit fabrication with boron etch-stop layer

Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element;... Globalfoundries Inc

03/01/18 / #20180061976

Integrated circuit structure without gate contact and forming same

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a channel region within the fin; and... Globalfoundries Inc

03/01/18 / #20180061993

Formation of bottom junction in vertical fet devices

Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and... Globalfoundries Inc

02/22/18 / #20180052388

Adjusting of patterns in design layout for optical proximity correction

Embodiments of the present disclosure include methods, program products, and systems for adjusting an integrated circuit (IC) layout for optical proximity correction (OPC). Methods according to the disclosure can include: defining a target region of the IC design layout, the target region having a plurality of patterns including a first... Globalfoundries Inc

02/22/18 / #20180053662

Texturing of silicon surface with direct-self assembly patterning

A method of texturing a silicon (Si) wafer and the resulting device are provided. Embodiments include forming a mask over an upper surface of a Si wafer; patterning the mask by direct-self assembly (DSA); etching the Si wafer through the patterned mask to form holes in the Si wafer; removing... Globalfoundries Inc

02/22/18 / #20180053707

Integrated circuits with peltier cooling provided by back-end wiring

A semiconductor structure comprises one or more semiconductor devices, each of the semiconductor devices having two or more electrical connections; one or more first conductors connected to a first electrical connection on the semiconductor device, the first conductor comprising a first material having a positive Seebeck coefficient; and one or... Globalfoundries Inc

02/22/18 / #20180053743

Ic structure on two sides of substrate and forming

An integrated circuit (IC) structure uses a single semiconductor substrate having a first side and an opposing, second side. A first plurality of active devices are positioned on the first side of the single semiconductor substrate, and a second plurality of active devices are positioned on the opposing, second side... Globalfoundries Inc

02/22/18 / #20180053757

Assist cuts disposed in dummy lines to improve metal signal cuts in active lines of a semiconductor structure

A semiconductor structure includes a substrate having a plurality of semiconductor devices disposed therein. A dielectric layer is disposed over the substrate. A plurality of substantially parallel metal lines are disposed in the dielectric layer. The metal lines include active lines for routing signals to and from the devices, and... Globalfoundries Inc

02/22/18 / #20180053789

Compensation of temperature effects in semiconductor device structures

A method includes providing a semiconductor device structure including a substrate having a semiconductor-on-insulator (SOI) region and a hybrid region. A semiconductor device is provided in the SOI region. The semiconductor device includes a gate structure, a diode structure provided in the hybrid region and coupled to a substrate material... Globalfoundries Inc

Patent Packs
02/22/18 / #20180053829

Method of forming a semiconductor device and semiconductor device

A method of forming a semiconductor device is provided, wherein the method includes forming a shaped gate structure over an active region, the shaped gate structure comprising a gate dielectric layer and a gate electrode disposed on the gate dielectric layer, and forming raised source/drain regions adjacent to the gate... Globalfoundries Inc

02/22/18 / #20180053831

Etch stop for airgap protection

A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The... Globalfoundries Inc

02/22/18 / #20180053832

Nvm device in soi technology and fabricating an according device

The present disclosure provides in one aspect a semiconductor device including a substrate structure comprising an active semiconductor material formed over a base substrate and a buried insulating material formed between the active semiconductor material and the base substrate, a ferroelectric gate structure disposed over the active semiconductor material in... Globalfoundries Inc

02/15/18 / #20180046072

Automated full-chip design space sampling using unsupervised machine learning

An illustrative method includes reading in a layout as current layout to be analyzed, splitting the current layout into n sub-layouts, where n is a positive integer, such that each sub-layout fits into a predetermined memory, performing a clustering step for each of the sub-layouts, including scanning the respective sub-layout... Globalfoundries Inc

02/15/18 / #20180046073

Dual exposure patterning of a photomask to print a contact, a via or a curvilinear shape on an integrated circuit

A method and system for: forming a first rectangular shape with photomask writing equipment, using a first sub-threshold dosage on a photoresist layer of a photomask substrate; forming an overlapping second rectangular shape with the photomask writing equipment using a second sub-threshold dosage on the photoresist layer, the second rectangular... Globalfoundries Inc

02/15/18 / #20180047626

Thru-silicon-via structures

Stress generation free thru-silicon-via structures with improved performance and reliability and methods of manufacture are provided. The method includes forming a first conductive diffusion barrier liner on an insulator layer within a thru-silicon-via of a wafer material. The method further includes forming a stress absorption layer on the first conductive... Globalfoundries Inc

02/15/18 / #20180047641

Transistor device structures with retrograde wells in cmos applications

A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on... Globalfoundries Inc

02/15/18 / #20180047642

Air gap spacer implant for nzg reliability fix

A method of forming a semiconductor device includes providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, providing at least one N-type metal-oxide semiconductor gate structure being an NZG gate... Globalfoundries Inc

02/15/18 / #20180047648

Ic structure integrity sensor having interdigitated conductive elements

A sensor for an integrated circuit (IC) structure is disclosed. The sensor includes a sensor layer in a layer of the IC structure, the sensor layer including: a first conductive structure disposed proximate a perimeter of the IC structure; and a second conductive structure disposed parallel to the first conductive... Globalfoundries Inc

02/15/18 / #20180047727

Preventing shorting between source and/or drain contacts and gate

Electrical shorting between source and/or drain contacts and a conductive gate of a FinFET-based semiconductor structure are prevented by forming the source and drain contacts in two parts, a bottom contact part extending up to a height of the gate cap and an upper contact part situated on at least... Globalfoundries Inc

02/15/18 / #20180047734

Transistor structure having n-type and p-type elongated regions intersecting under common gate

A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated region of the other of n-type or p-type, the first and second elongated regions crossing such that the first elongated region and the second elongated region... Globalfoundries Inc

02/15/18 / #20180047738

Semiconductor device comprising a floating gate flash memory device

A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, forming a first transistor device on and in the SOI... Globalfoundries Inc

02/15/18 / #20180047807

Deep trench capacitors with a diffusion pad

Device structures for a deep trench capacitor and methods of fabricating device structures for a deep trench capacitor. A dielectric layer is formed on a substrate and an opening is formed that extends from a top surface of the dielectric layer through the dielectric layer. A deep trench is formed... Globalfoundries Inc

02/15/18 / #20180047824

Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts

An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of... Globalfoundries Inc

02/15/18 / #20180048169

Rechargeable wafer carrier systems

Rechargeable wafer carrier systems and methods are provided. A rechargeable wafer carrier system includes, for instance, a housing for holding at least one wafer and at least one electronics system therein, a rechargeable power source operably connected to the housing for powering the at least one electronics system, and a... Globalfoundries Inc

02/15/18 / #20180047564

Method to tune contact cd and reduce mask count by tilted ion beam

A novel method of processing and fabricating semiconductor devices is provided to reduce critical dimensions inherent in a given photolithography process. A patterned mask layer generated via transfer of the pattern to the masking layer (e.g., printing) has a given set of dimensions. The method or process forms multiple layers... Globalfoundries Inc

02/08/18 / #20180040477

Oxidizing filler material lines to increase width of hard mask lines

A starting semiconductor structure includes a layer of filler material, a hard mask layer over the layer of filler material, and filler material lines over the hard mask layer. The starting semiconductor structure is placed in an etching chamber, and oxygen gas and high plasma power are inserted into the... Globalfoundries Inc

02/08/18 / #20180040505

Method for forming a shallow trench isolation structure using a nitride liner and a diffusionless anneal

A method includes forming a trench in a stack comprising a substrate, a buried oxide layer formed above the substrate, a semiconductor layer formed above the buried oxide layer and a hard mask layer formed above the semiconductor layer. A first liner is formed in the trench. A first oxide... Globalfoundries Inc

02/08/18 / #20180040511

Methods of forming a through-substrate-via (tsv) and a metallization layer after formation of a semiconductor device

One illustrative method disclosed includes, among other things, forming a semiconductor device above a semiconducting substrate, forming a device level contact to the semiconductor device and, after forming the device level contact, performing at least one common process operation so as to form a through-substrate-via (TSV) in a trench in... Globalfoundries Inc

02/08/18 / #20180040516

Finfet device and manufacturing

A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a... Globalfoundries Inc

02/08/18 / #20180040555

Devices and methods of forming low resistivity noble metal interconnect

Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer... Globalfoundries Inc

02/08/18 / #20180040556

Integrated circuit including wire structure, related method and design structure

Various aspects include an integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire... Globalfoundries Inc

02/08/18 / #20180040611

Co-integration of self-aligned and non-self aligned heterojunction bipolar transistors

The present disclosure relates to semiconductor structures and, more particularly, to co-integration of self-aligned and non-self aligned heterojunction bipolar transistors and methods of manufacture. The structure includes at least two heterojunction bipolar transistor (HBT) devices integrated onto a same wafer with different epitaxial base profiles. An intrinsic base epitaxy for... Globalfoundries Inc

02/08/18 / #20180040631

Method, apparatus, and system for improved memory cell design having unidirectional layout using self-aligned double patterning

At least one method, apparatus and system disclosed involves an integrated circuit comprising a unidirectional metal layout. A first set of metal features are formed in a vertical configuration in a first metal layer of a memory cell. A second set of metal features are formed in a unidirectional horizontal... Globalfoundries Inc

02/08/18 / #20180040696

Multiple-step epitaxial growth s/d regions for nmos finfet

A method of forming NFET S/D structures with multiple layers, with consecutive epi-SiP layers being doped at increasing dosages of P and the resulting device are provided. Embodiments include forming multiple epi-Si layers in each S/D cavity of a NFET; and performing in-situ doping of P for each epi-Si layer,... Globalfoundries Inc

02/08/18 / #20180040731

Semiconductor-on-insulator wafer, semiconductor structure including a transistor, and methods for the formation and operation thereof

A semiconductor-on-insulator wafer includes a support substrate, an electrically insulating layer over the support substrate and a semiconductor layer over the electrically insulating layer. A semiconductor structure includes a transistor. The transistor includes an electrically insulating layer including a piezoelectric material over a support substrate, a semiconductor layer over the... Globalfoundries Inc








ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009



###

This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Globalfoundries Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Globalfoundries Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

###