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Globalfoundries, Inc. patents


      
Recent patent applications related to Globalfoundries, Inc.. Globalfoundries, Inc. is listed as an Agent/Assignee. Note: Globalfoundries, Inc. may have other listings under different names/spellings. We're not affiliated with Globalfoundries, Inc., we're just tracking patents.

ARCHIVE: New 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries, Inc.-related inventors



Globalfoundries

Barrier layer conformality in copper interconnects

Globalfoundries

Integrating optimal planar and three-dimensional semiconductor design layouts

Search recent Press Releases: Globalfoundries, Inc.-related press releases
Count Application # Date Globalfoundries, Inc. patents (updated weekly) - BOOKMARK this page
12014025242409/11/14 new patent  Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
22014025242509/11/14 new patent  Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
32014025242909/11/14 new patent  Contact geometry having a gate silicon length decoupled from a transistor length
42014025248009/11/14 new patent  Combination finfet and planar fet semiconductor device and methods of making such a device
52014025248109/11/14 new patent  Transistor including a gate electrode extending all around one or more channel regions
62014025255709/11/14 new patent  Method for forming a semiconductor device and semiconductor device structures
72014025261709/11/14 new patent  Barrier layer conformality in copper interconnects
82014025266009/11/14 new patent  Multilayer pattern transfer for chemical guides
92014025390209/11/14 new patent  Multiple patterning process for forming trenches or holes using stitched assist features
102014025401809/11/14 new patent  Scattering enhanced thin absorber for euv reflective reticle and a method of making
112014025606409/11/14 new patent  Methods of repairing damaged insulating materials by introducing carbon into the layer of insulating material
122014025609709/11/14 new patent  Methods for forming integrated circuit systems employing fluorine doping
132014025613509/11/14 new patent  Methods of removing gate cap layers in cmos applications
142014025613709/11/14 new patent  Method of forming a semiconductor structure including an implantation of ions into a layer of spacer material
152014025773809/11/14 new patent  Hierarchically divided signal path for characterizing integrated circuits
162014025896009/11/14 new patent  Integrating optimal planar and three-dimensional semiconductor design layouts
172014025614109/11/14 new patent  Methods for fabricating integrated circuits utilizing silicon nitride layers
182014024669609/04/14Transistor with embedded strain-inducing material formed in cavities formed in a silicon/germanium substrate
192014024669809/04/14Channel sige removal from pfet source/drain region for improved silicide formation in hkmg technologies without embedded sige
202014024673409/04/14Replacement metal gate with mulitiple titanium nitride laters
212014024673509/04/14Metal gate structure for semiconductor devices
222014024677509/04/14Methods of forming non-continuous conductive layers for conductive structures on an integrated circuit product
232014024679109/04/1414 lpm contact power rail
242014024743809/04/14Reticle defect correction by second exposure
252014024874909/04/14Stress memorization technique
262014024876409/04/14Methods of forming structures on an integrated circuit product
272014024877009/04/14Microwave-assisted heating of strong acid solution to remove nickel platinum/platinum residues
282014024877809/04/14Methods of forming asymmetric spacers on various structures on integrated circuit products
292014024660509/04/14Defect removal process
302014023804508/28/14Semiconductor device comprising a stacked die configuration including an integrated peltier element
312014024278808/28/14Method of forming a high quality interfacial layer for a semiconductor device by performing a low temperature ald process
322014024523808/28/14Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications
332014023950308/28/14Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
342014023124508/21/14Adjustable current shield for electroplating processes
352014023190708/21/14Methods of inducing a desired stress in the channel region of a transistor by performing ion implantation/anneal processes on the gate electrode
362014023196008/21/14Polysilicon resistor formation
372014023243308/21/14Circuit element including a layer of a stress-creating material providing a variable stress and method for the formation thereof
382014023301408/21/14Infrared-based metrology for detection of stress and defects around through silicon vias
392014023188508/21/14Integrated circuits and methods for fabricating integrated circuits having metal gate electrodes
402014023192208/21/14Semiconductor gate structure for threshold voltage modulation and method of making same
412014023201008/21/14Integrated circuits and methods of forming the same with multi-level electrical connection
422014023505508/21/14Method for fabricating a semiconductor integrated circuit with a litho-etch, litho-etch process for etching trenches
432014022476408/14/14Chemical and physical templates for forming patterns using directed self-assembly materials
442014022516808/14/14Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device
452014022520108/14/14Edge and strap cell design for sram array
462014022527008/14/14Method for off-grid routing structures utilizing self aligned double patterning (sadp) technology
472014022784508/14/14Methods of forming multiple n-type semiconductor devices with different threshold voltages on a semiconductor substrate
482014022784908/14/14Methods of trimming nanowire structures
492014022785808/14/14Shallow trench isolation integration methods and devices formed thereby
502014022786908/14/14Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions
512014022787208/14/14Methods of forming conductive structures using a sacrificial liner layer
522014022787908/14/14Methods for fabricating integrated circuits with improved semiconductor fin structures
532014021746708/07/14Methods of forming substrates comprised of different semiconductor materials and the resulting device
542014021748008/07/14Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer
552014021754408/07/14Methods of forming a transistor device on a bulk substrate and the resulting device
562014021758808/07/14Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device
572014021759108/07/14Multi-layer barrier layer for interconnect structure
582014022075608/07/14Methods of forming semiconductor devices by forming a semiconductor layer above source/drain regions prior to removing a gate cap layer
592014022075908/07/14Methods for fabricating integrated circuits having gate to active and gate to gate interconnects
602014022076708/07/14Double-pattern gate formation processing with critical dimension control
612014022339008/07/14Retargeting semiconductor device shapes for multiple patterning processes
622014022339208/07/14Optimized optical proximity correction handling for lithographic fills
632014021748208/07/14Integrated circuits having replacement gate structures and methods for fabricating the same
642014021751708/07/14Integrated circuits including finfet devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
652014022077508/07/14Methods for fabricating integrated circuits having embedded electrical interconnects
662014022078608/07/14Methods for optical proximity correction in the design and fabrication of integrated circuits
672014021008807/31/14Method for reducing wettability of interconnect material at corner interface and device incorporating same
682014021117507/31/14Enhancing resolution in lithographic processes using high refractive index fluids
692014021541507/31/14Automated design layout pattern correction based on context-aware patterns
702014020956307/31/14Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein
712014021303307/31/14Methods for fabricating electrically-isolated finfet semiconductor devices
722014021303707/31/14Methods for fabricating integrated circuits having confined epitaxial growth regions
732014020328007/24/14Electrical test structure for devices employing high-k dielectrics or metal gates
742014020329807/24/14Strained silicon carbide channel for electron mobility of nmos
752014020333907/24/14Semiconductor device comprising self-aligned contact elements and a replacement gate electrode structure
762014020337607/24/14Finfet integrated circuits with uniform fin height and methods for fabricating the same
772014020340507/24/14Method to dynamically tune precision resistance
782014020344607/24/14Through silicon via device having low stress, thin film gaps and methods for forming the same
792014020381407/24/14Method and apparatus for measuring alpha particle induced soft errors in semiconductor devices
802014020615707/24/14Method of forming a semiconductor structure including a vertical nanowire
812014020828507/24/14Self-aligned double patterning via enclosure design
822014020327907/24/14Test structure and method to faciltiate development/optimization of process parameters
832014020344907/24/14Integrated circuits and methods of forming the same with metal layer connection to through-semiconductor via
842014020382707/24/14Integrated circuits and methods of forming the same with embedded interconnect connection to through-semiconductor via
852014019746807/17/14Methods of forming semiconductor device with self-aligned contact elements and the resulting device
862014019754407/17/14Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials
872014019749807/17/14Integrated circuits and methods for fabricating integrated circuits with improved silicide contacts
882014019984507/17/14Selective removal of gate structure sidewall(s) to facilitate sidewall spacer protection
892014019132407/10/14Methods of forming bulk finfet devices by performing a recessing process on liner materials to define different fin heights and finfet devices with such recessed liner materials
902014019133207/10/14Pfet devices with different structures and performance characteristics
912014019395707/10/14Reducing gate height variance during semiconductor device formation
922014018355107/03/14Blanket epi super steep retrograde well formation without si recess
932014018363807/03/14Methods of using a trench salicide routing layer
942014018372007/03/14Methods of manufacturing integrated circuits having a compressive nitride layer
952014018503007/03/14Asymmetric reticle heating of multilayer reticles eliminated by dummy exposures and related methods
962014018703607/03/14Integration of ru wet etch and cmp for beol interconnects with ru layer
972014018374507/03/14Gate electrode(s) and contact structure(s), and methods of fabrication thereof
982014017553906/26/14Canyon gate transistor and methods for its fabrication
992014017816006/26/14Overhead substrate handling and storage system
1002014017882406/26/14Optimizing lithographic processes using laser annealing techniques
1012014017556206/26/14Spacer divot sealing method and semiconductor device incorporating same
1022014017909306/26/14Gate structure formation processes
1032014016711906/19/14Methods of forming a sidewall spacer having a generally triangular shape and a semiconductor device having such a spacer
1042014016712006/19/14Methods of forming a finfet semiconductor device by performing an epitaxial growth process
1052014016726406/19/14Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structures
1062014016726506/19/14Methods of forming a bi-layer cap layer on copper-based conductive structures and devices with such a cap layer
1072014017053306/19/14Extreme ultraviolet lithography (euvl) alternating phase shift mask
1082014017083906/19/14Methods of forming fins for a finfet device wherein the fins have a high germanium content
1092014017353306/19/14Locally optimized coloring for cleaning lithographic hotspots
1102014015905206/12/14Method and structure for transistor with reduced drain-induced barrier lowering and on resistance
1112014015912506/12/14Contact landing pads for a semiconductor device and methods of making same
1122014015912606/12/14Methods of forming a finfet semiconductor device with undoped fins
1132014015916406/12/14Double sidewall image transfer process
1142014015917106/12/14Methods of forming bulk finfet semiconductor devices by performing a liner recessing process to define fin heights and finfet devices with such a recessed liner
1152014015919906/12/14High density serial capacitor device and methods of making such a capacitor device
1162014016217606/12/14Semiconductor device resolution enhancement by etching multiple sides of a mask
1172014016244706/12/14Finfet hybrid full metal gate with borderless contacts
1182014015176006/05/14Doped flowable pre-metal dielectric
1192014015180706/05/14Combination finfet and planar fet semiconductor device and methods of making such a device
1202014015181606/05/14Novel contact structure for a semiconductor device and methods of making same
1212014015181806/05/14Semiconductor device with a silicon dioxide gate insulation layer implanted with a rare earth element and methods of making such a device
1222014014525705/29/14Semiconductor device having a metal recess
1232014014527405/29/14Methods of forming replacement gate structures for nfet semiconductor devices and devices having such gate structures
1242014014533205/29/14Methods of forming graphene liners and/or cap layers on copper-based conductive structures
1252014014801105/29/14Method of forming semiconductor fins
1262014014995205/29/14Trench silicide mask generation using designated trench transfer and trench block regions
1272014014160505/22/14Finfet formation using double patterning memorization
1282014013877905/22/14Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance
1292014014160505/22/14Finfet formation using double patterning memorization
1302014013877905/22/14Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance
1312014013173505/15/14Source and drain doping using doped raised source and drain regions
1322014013177105/15/14Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof
1332014013180505/15/14Transistor with embedded si/ge material having reduced offset and superior uniformity
1342014013188105/15/14Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection
1352014013183105/15/14Integrated ciruit including an fin-based diode and methods of its fabrication
1362014013481405/15/14Methods of manufacturing integrated circuits having finfet structures with epitaxially formed source/drain regions
1372014013482205/15/14Methods for fabricating integrated circuits including semiconductive resistor structures in a finfet architecture
1382014013173505/15/14Source and drain doping using doped raised source and drain regions
1392014013177105/15/14Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof
1402014013180505/15/14Transistor with embedded si/ge material having reduced offset and superior uniformity
1412014013188105/15/14Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection
1422014013183105/15/14Integrated ciruit including an fin-based diode and methods of its fabrication
1432014013481405/15/14Methods of manufacturing integrated circuits having finfet structures with epitaxially formed source/drain regions
1442014013482205/15/14Methods for fabricating integrated circuits including semiconductive resistor structures in a finfet architecture
1452014012479405/08/14Fabrication of reverse shallow trench isolation structures with super-steep retrograde wells
1462014012484105/08/14Methods of forming replacement gate structures on semiconductor devices and the resulting device
1472014012999905/08/14Method for selectively modeling narrow-width stacked device performance
1482014012479405/08/14Fabrication of reverse shallow trench isolation structures with super-steep retrograde wells
1492014012484105/08/14Methods of forming replacement gate structures on semiconductor devices and the resulting device
1502014012999905/08/14Method for selectively modeling narrow-width stacked device performance
1512014011741705/01/14Performance enhancement in transistors by providing a graded embedded strain-inducing semiconductor region with adapted angles with respect to the substrate surface
1522014011741805/01/14Three-dimensional silicon-based transistor comprising a high-mobility channel formed by non-masked epitaxy
1532014011741905/01/14Fin etch and fin replacement for finfet integration
1542014011750705/01/14Double trench well formation in sram cells
1552014012067705/01/14Methods of forming enhanced mobility channel regions on 3d semiconductor devices, and devices comprising same
1562014011741705/01/14Performance enhancement in transistors by providing a graded embedded strain-inducing semiconductor region with adapted angles with respect to the substrate surface
1572014011741805/01/14Three-dimensional silicon-based transistor comprising a high-mobility channel formed by non-masked epitaxy
1582014011741905/01/14Fin etch and fin replacement for finfet integration
1592014011750705/01/14Double trench well formation in sram cells
1602014012067705/01/14Methods of forming enhanced mobility channel regions on 3d semiconductor devices, and devices comprising same
1612014011079804/24/14Methods of forming a semiconductor device with low-k spacers and the resulting device
1622014011085404/24/14Semiconductor dies with reduced area consumption
1632014011341904/24/14Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material
1642014011342004/24/14Methods of avoiding shadowing when forming source/drain implant regions on 3d semiconductor devices
1652014011345504/24/14Method of forming a semiconductor structure including a wet etch process for removing silicon nitride
1662014011077204/24/14Integrated circuit decoupling capacitor arrangement
1672014011079404/24/14Facilitating gate height uniformity and inter-layer dielectric protection
1682014011079804/24/14Methods of forming a semiconductor device with low-k spacers and the resulting device
1692014011085404/24/14Semiconductor dies with reduced area consumption
1702014011341904/24/14Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material
1712014011342004/24/14Methods of avoiding shadowing when forming source/drain implant regions on 3d semiconductor devices
1722014011345504/24/14Method of forming a semiconductor structure including a wet etch process for removing silicon nitride
1732014011077204/24/14Integrated circuit decoupling capacitor arrangement
1742014011079404/24/14Facilitating gate height uniformity and inter-layer dielectric protection
1752014010342004/17/14Advanced faraday shield for a semiconductor device
1762014010657504/17/14Directed self-assembly of block copolymers using laser annealing
1772014010342004/17/14Advanced faraday shield for a semiconductor device
1782014010657504/17/14Directed self-assembly of block copolymers using laser annealing
1792014009753804/10/14Semiconductor device having a self-forming barrier layer at via bottom
1802014009789204/10/14Double patterning compatible colorless m1 route
1812014010080604/10/14Method and apparatus for matching tools based on time trace data
1822014009845904/10/14Capacitor and contact structures, and formation processes thereof
1832014009753804/10/14Semiconductor device having a self-forming barrier layer at via bottom
1842014009789204/10/14Double patterning compatible colorless m1 route
1852014010080604/10/14Method and apparatus for matching tools based on time trace data
1862014009845904/10/14Capacitor and contact structures, and formation processes thereof
1872014009753804/10/14Semiconductor device having a self-forming barrier layer at via bottom
1882014009789204/10/14Double patterning compatible colorless m1 route
1892014010080604/10/14Method and apparatus for matching tools based on time trace data
1902014009845904/10/14Capacitor and contact structures, and formation processes thereof
1912014008438303/27/14Methods of forming 3-d semiconductor devices using a replacement gate technique and a novel 3-d device
1922014008438303/27/14Methods of forming 3-d semiconductor devices using a replacement gate technique and a novel 3-d device
1932014007727403/20/14Integrated circuits with improved gate uniformity and methods for fabricating same
1942014007736803/20/14Repairing anomalous stiff pillar bumps
1952014007738003/20/14Bit cell with double patterned metal layer structures
1962014007881703/20/14Integrated circuits with sram cells having additional read stacks and methods for their fabrication
1972014007727403/20/14Integrated circuits with improved gate uniformity and methods for fabricating same
1982014007736803/20/14Repairing anomalous stiff pillar bumps
1992014007738003/20/14Bit cell with double patterned metal layer structures
2002014007881703/20/14Integrated circuits with sram cells having additional read stacks and methods for their fabrication
2012014007028303/13/14Field effect transistor and method of fabrication
2022014007028503/13/14Methods of forming semiconductor devices with self-aligned contacts and the resulting devices
2032014007032103/13/14Integrated circuits having boron-doped silicon germanium channels and methods for fabricating the same
2042014007032203/13/14Methods of forming different finfet devices with different threshold voltages and integrated circuit products containing such devices
2052014007035803/13/14Method of tailoring silicon trench profile for super steep retrograde well field effect transistor
2062014007040503/13/14Stacked semiconductor devices with a glass window wafer having an engineered coefficient of thermal expansion and methods of making same
2072014007028303/13/14Field effect transistor and method of fabrication
2082014007028503/13/14Methods of forming semiconductor devices with self-aligned contacts and the resulting devices
2092014007032103/13/14Integrated circuits having boron-doped silicon germanium channels and methods for fabricating the same
2102014007032203/13/14Methods of forming different finfet devices with different threshold voltages and integrated circuit products containing such devices
2112014007035803/13/14Method of tailoring silicon trench profile for super steep retrograde well field effect transistor
2122014007040503/13/14Stacked semiconductor devices with a glass window wafer having an engineered coefficient of thermal expansion and methods of making same
2132014006173203/06/14Method and device to achieve self-stop and precise gate height
2142014006181203/06/14Semiconductor device incorporating a multi-function layer into gate stacks
2152014006192503/06/14Low resistivity gate conductor
2162014006573403/06/14Method and system for determining overlap process windows in semiconductors by inspection techniques
2172014006580803/06/14Method of forming a material layer in a semiconductor structure
2182014006581103/06/14Replacement metal gate semiconductor device formation using low resistivity metals
2192014006581503/06/14Beol integration scheme for copper cmp to prevent dendrite formation
2202014006854303/06/14Method to enhance double patterning routing efficiency
2212014006582803/06/14Selective fin cut process
2222014006173203/06/14Method and device to achieve self-stop and precise gate height
2232014006181203/06/14Semiconductor device incorporating a multi-function layer into gate stacks
2242014006192503/06/14Low resistivity gate conductor
2252014006573403/06/14Method and system for determining overlap process windows in semiconductors by inspection techniques
2262014006580803/06/14Method of forming a material layer in a semiconductor structure
2272014006581103/06/14Replacement metal gate semiconductor device formation using low resistivity metals
2282014006581503/06/14Beol integration scheme for copper cmp to prevent dendrite formation
2292014006854303/06/14Method to enhance double patterning routing efficiency
2302014006582803/06/14Selective fin cut process
2312014005464902/27/14Semiconductor devices and methods of forming the semiconductor devices including a retrograde well
2322014005472302/27/14Isolation structures for finfet semiconductor devices
2332014005708902/27/14Hardmask layer with alternating nanolayers
2342014005709902/27/14Hardmask capping layer
2352014005741502/27/14Methods of forming a layer of silicon on a layer of silicon/germanium
2362014005743502/27/14Methods of forming a metal cap layer on copper-based conductive structures on an integrated circuit device
2372014005950602/27/14Method and apparatus for applying post graphic data system stream enhancements
2382014004891202/20/14Compressive stress transfer in an interlayer dielectric of a semiconductor device by providing a bi-layer of superior adhesion and internal stress
2392014005001702/20/14Device comprising a plurality of static random access memory cells and method of operation thereof
2402014005003302/20/14Memory cell assembly including an avoid disturb cell
2412014005122702/20/14Methods of forming isolation structures for semiconductor devices by performing a dry chemical removal process
2422014005123302/20/14Methods of thinning and/or dicing semiconducting substrates having integrated circuit products formed thereon
2432014005124002/20/14Methods of forming a replacement gate structure having a gate electrode comprised of a deposited intermetallic compound material
2442014004251002/13/14Capacitors positioned at the device level in an integrated circuit product and methods of making such capacitors
2452014004254902/13/14Methods of forming stress-inducing layers on semiconductor devices
2462014004255002/13/14Integrated circuits with improved spacers and methods for fabricating same
2472014004255102/13/14Sram integrated circuits with buried saddle-shaped finfet and methods for their fabrication
2482014004264102/13/14Middle-of-the-line constructs using diffusion contact structures
2492014004306102/13/14Computing multi-magnet based devices and methods for solution of optimization problems


ARCHIVE: New 2014 2013 2012 2011 2010 2009



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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Globalfoundries, Inc. in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Globalfoundries, Inc. with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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