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Globalfoundries Inc
Globalfoundries Inc grand Cayman Cayman Islands
Globalfoundries Inc_20131212


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Globalfoundries Inc patents

Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors

Search recent Press Releases: Globalfoundries Inc-related press releases
Count Application # Date Globalfoundries Inc patents (updated weekly) - BOOKMARK this page
12016003395802/04/16  new patent  Endpoint determination using individually measured target spectra
22016003563002/04/16  new patent  Methods of forming transistors with retrograde wells in cmos applications and the resulting device structures
32016003564102/04/16  new patent  Semiconductor device including passivation layer encapsulant
42016003572302/04/16  new patent  Macro design of device characterization for 14nm and beyond technologies
52016003572702/04/16  new patent  Cmos structure with beneficial nmos and pmos band offsets
62016003572802/04/16  new patent  Retrograde doped layer for device isolation
72016003574302/04/16  new patent  Field effect transistor (fet) with self-aligned contacts, integrated circuit (ic) chip and manufacture
82016003581802/04/16  new patent  Forming a vertical capacitor and resulting device
92016003582002/04/16  new patent  Uniaxially-strained fd-soi finfet
102016003585602/04/16  new patent  Semiconductor structure including a ferroelectric transistor and the formation thereof
112016003586302/04/16  new patent  Methods of forming stressed channel regions for a finfet semiconductor device and the resulting device
122016003590602/04/16  new patent  Planar semiconductor esd device and making same
132016003387902/04/16  new patent  Methods and controllers for controlling focus of ultraviolet light from a lithographic imaging system, and apparatuses for forming an integrated circuit employing the same
142016003556502/04/16  new patent  Methods for fabricating integrated circuits using directed self-assembly chemoepitaxy
152016003563102/04/16  new patent  Atomic layer deposition of hfalc as a metal gate workfunction material in mos devices
162016002580501/28/16 Wafer test structures and methods of providing wafer test structures
172016002674801/28/16 Multi-polygon constraint decomposition techniques for use in double patterning applications
182016002770001/28/16 Gate structure cut after formation of epitaxial active regions
192016002771301/28/16 Establishing a thermal profile across a semiconductor chip
202016002773401/28/16 E-fuse structure with methods of fusing the same and monitoring material leakage
212016002774401/28/16 Method of forming an integrated crackstop
222016002777501/28/16 Dual-width fin structure for finfets devices
232016002789501/28/16 Methods of forming fins for a finfet device by forming and replacing sacrificial fin structures with alternative materials
242016002790501/28/16 Bipolar junction transistors and methods of fabrication
252016002679301/28/16 Threat condition management
262016002014001/21/16 Anisotropic material damage process for etching low-k dielectric materials
272016002015401/21/16 Simplified multi-threshold voltage scheme for fully depleted soi mosfets
282016002020401/21/16 Three-dimensional electrostatic discharge semiconductor device
292016002027501/21/16 Shallow trench isolation structure with sigma cavity
302016002027701/21/16 Three-dimensional electrostatic discharge semiconductor device
312016002033501/21/16 Transistors comprising doped region-gap-doped region structures and methods of fabrication
322016001295201/14/16 Inductor structure having embedded airgap
332016001326201/14/16 Fabrication of multilayer circuit elements
342016001329101/14/16 Methods of forming isolated channel regions for a finfet semiconductor device and the resulting device
352016001329601/14/16 Methods of forming low defect replacement fins for a finfet semiconductor device and the resulting devices
362016000559801/07/16 Inhibiting diffusion of elements between material layers of a layered circuit structure
372016000565701/07/16 Semiconductor structure with increased space and volume between shaped epitaxial structures
382016000573301/07/16 Integrated circuit product with a gate height registration structure
392016000573401/07/16 Integrated circuit product comprised of multiple p-type semiconductor devices with different threshold voltages
402016000582801/07/16 Gate dielectric protection for transistors
412016000583401/07/16 Methods of forming a channel region for a semiconductor device by performing a triple cladding process
422016000586701/07/16 Silicide protection during contact metallization and resulting semiconductor structures
432016000586801/07/16 Finfet with confined epitaxy
442015037795612/31/15 Method and inline device characterization and temperature profiling
452015037809612/31/15 Integration of optical components in integrated circuits
462015038024612/31/15 Dimension-controlled via formation processing
472015038025012/31/15 Semiconductor contacts and methods of fabrication
482015038025212/31/15 Sidewall image templates for directed self-assembly materials
492015038025812/31/15 Method for controlling height of a fin structure
502015038026212/31/15 Sub-lithographic semiconductor structures with non-constant pitch
512015038030412/31/15 Titanium silicide formation in a narrow source-drain contact
522015038031612/31/15 Uniform exposed raised structures for non-planar semiconductor devices
532015038032012/31/15 Test pattern for feature cross-sectioning
542015038040412/31/15 Non-planar structure with extended exposed raised structures and same-level gate and spacers
552015038040512/31/15 Removal of semiconductor growth defects
562015038040912/31/15 Threshold voltage control for mixed-type non-planar semiconductor devices
572015038050212/31/15 Method to form wrap-around contact for finfet
582015038051012/31/15 Structure and forming silicide on fins
592015038051412/31/15 Junction overlap control in a semiconductor device using a sacrificial spacer layer
602015038051512/31/15 Multi-phase source/drain/gate spacer-epi formation
612015038026912/31/15 Methods of forming integrated circuits with a planarized permanet layer and methods for forming finfet devices with a planarized permanent layer
622015038030912/31/15 Metal-insulator-semiconductor (mis) contact with controlled defect density
632015037189212/24/15 Methods of forming a finfet semiconductor device with a unique gate configuration, and the resulting finfet device
642015037189612/24/15 Double self aligned via patterning
652015037189912/24/15 Minimizing void formation in semiconductor vias and trenches
662015037195612/24/15 Crackstops for bulk semiconductor wafers
672015037208012/24/15 Self-aligned dual-height isolation for bulk finfet
682015037208412/24/15 Raised fin structures and methods of fabrication
692015037210412/24/15 Multi-channel gate-all-around fet
702015037210712/24/15 Semiconductor devices having fins, and methods of forming semiconductor devices having fins
712015037210812/24/15 Method and structure for protecting gates during epitaxial growth
722015037211112/24/15 Methods of forming nanowire devices with spacers and the resulting devices
732015037211512/24/15 Methods of forming nanowire devices with doped extension regions and the resulting devices
742015037214012/24/15 Finfets having strained channels, and methods of fabricating finfets having strained channels
752015037191212/24/15 Methods and systems for chemical mechanical planarization endpoint detection using an alternating current reference signal
762015037205512/24/15 Non-volatile random access memory devices with shared transistor configuration and methods of forming the same
772015037210012/24/15 Integrated circuits having improved contacts and methods for fabricating same
782015036353212/17/15 Optimization of integrated circuits for a reticle transmission process window using multiple fill cells
792015036418312/17/15 Method and bit-line sensing gates on an sram cell
802015036432612/17/15 Methods of forming a protection layer on a semiconductor device and the resulting device
812015036433612/17/15 Uniform gate height for mixed-type non-planar semiconductor devices
822015036437812/17/15 Forming gate and source/drain contact openings by performing a common etch patterning process
832015036442612/17/15 Decoupling capacitor for semiconductors
842015036449112/17/15 Semiconductor device including soi butted junction to reduce short-channel penalty
852015036453512/17/15 Semiconductor structure including capacitors having different capacitor dielectrics and the formation thereof
862015036454012/17/15 Capacitor and contact structures, and formation processes thereof
872015036457012/17/15 Stress memorization techniques for transistor devices
882015036457812/17/15 Method of forming a reduced resistance fin structure
892015036459512/17/15 Replacement gate structure on finfet devices with reduced size fin in the channel region
902015035742512/10/15 Buried source-drain contact for integrated circuit transistor devices and making same
912015035525312/10/15 Visually detecting electrostatic discharge events
922015035712012/10/15 Vertical capacitors with spaced conductive lines
932015035719912/10/15 Chemical mechanical polishing method and apparatus
942015035724312/10/15 Method for making strained semiconductor device and related methods
952015035728512/10/15 Formation of carbon-rich contact liner material
962015035729212/10/15 Methods of fabricating defect-free semiconductor structures
972015035733212/10/15 Devices and methods of forming bulk finfets with lateral seg for source and drain on dielectrics
982015035740912/10/15 Gate contact with vertical isolation from source-drain
992015035743412/10/15 Replacement metal gate including dielectric gate material
1002015035743912/10/15 Method for making semiconductor device with isolation pillars between adjacent semiconductor fins
1012015035744112/10/15 Method for making a semiconductor device while avoiding nodules on a gate
1022015035743312/10/15 Integrated circuits with vertical junctions between nfets and pfets, and methods of manufacturing the same
1032015034429312/03/15 Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure
1042015034627112/03/15 Methods, apparatus and system for screening process splits for technology development
1052015034878712/03/15 Semiconductor devices and methods for forming a gate with reduced defects
1062015034883012/03/15 Shallow trench isolation
1072015034884912/03/15 Transistor with embedded stress-inducing layers
1082015034891312/03/15 Planar metrology pad adjacent a set of fins in a fin field effect transistor device
1092015034897012/03/15 Gate structures for cmos based integrated circuit products
1102015034897412/03/15 Low energy ion implantation of a junction butting region
1112015034905312/03/15 Semiconductor devices with a layer of material having a plurality of source/drain trenches
1122015034905412/03/15 Double/multiple fin structure for finfet devices
1132015034906912/03/15 Finfet semiconductor devices with improved source/drain resistance
1142015034908312/03/15 Methods of forming mis contact structures for semiconductor devices and the resulting devices
1152015034908512/03/15 Method for making a semiconductor device with sidewall spacers for confining epitaxial growth
1162015034912012/03/15 Semiconductor device structure
1172015034883312/03/15 Method to etch cu/ta/tan selectively using dilute aqueous hf/hcl solution
1182015034046111/26/15 Metal gate structure and formation
1192015034022911/26/15 Transistor(s) with different source/drain channel junction characteristics, and methods of fabrication
1202015034023811/26/15 Methods of removing fins for finfet semiconductor devices
1212015034028911/26/15 Methods of fabricating semiconductor fin structures
1222015034029611/26/15 Planar metrology pad adjacent a set of fins of a fin field effect transistor device
1232015034031911/26/15 E-fuse structure for an integrated circuit product
1242015034036211/26/15 Transistor devices with high-k insulation layers
1252015034038011/26/15 Integrated circuit including a semiconductor-on-insulator region and a bulk region
1262015034045211/26/15 Buried fin contact structures on finfet semiconductor devices
1272015034045711/26/15 Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices
1282015034046111/26/15 Metal gate structure and formation
1292015034046711/26/15 Merged gate and source/drain contacts in a semiconductor device
1302015034046811/26/15 Recessed channel fin device with raised source and drain regions
1312015034047011/26/15 Methods for forming semiconductor fin support structures
1322015034047111/26/15 Raised source/drain epi with suppressed lateral epi overgrowth
1332015034049111/26/15 Spacer chamfering for a replacement metal gate device
1342015034049711/26/15 Methods of increasing silicide to epi contact areas and the resulting devices
1352015034050011/26/15 Semiconductor structure with self-aligned wells and multiple channel materials
1362015034050111/26/15 Forming independent-gate finfet with tilted pre-amorphization implantation and resulting device
1372015033942911/26/15 Methods for fabricating integrated circuits including generating photomasks for directed self-assembly (dsa) using dsa target patterns
1382015034027411/26/15 Methods for producing integrated circuits with an insultating layer
1392015033315511/19/15 Method for making semiconductor device with filled gate line end recesses
1402015033198811/19/15 Wide pin for improved circuit routing
1412015033293411/19/15 Lithographic stack excluding siarc and using same
1422015033295911/19/15 Methods and structures for back end of line integration
1432015033296311/19/15 T-shaped contacts for semiconductor device
1442015033297211/19/15 Fabricating raised fins using ancillary fin structures
1452015033305711/19/15 Meander resistor
1462015033306211/19/15 Finfet fabrication method
1472015033306711/19/15 Devices and methods of forming finfets with self aligned fin formation
1482015033308611/19/15 Method for making semiconductor device with different fin sets
1492015033312111/19/15 Shallow trench isolation integration methods and devices formed thereby
1502015033313611/19/15 Semiconductor devices with replacement spacer structures
1512015033316211/19/15 Methods of forming nanowire devices with metal-insulator-semiconductor source/drain contacts and the resulting devices
1522015033303511/19/15 Articles including bonded metal structures and methods of preparing the same
1532015033308011/19/15 Integrated circuits and methods for operating integrated circuits with non-volatile memory
1542015032544511/12/15 Reduced silicon gouging during oxide spacer formation
1552015032547311/12/15 Integrated circuits with metal-titanium oxide contacts and fabrication methods
1562015032552511/12/15 Forming interconnect structure with polymeric layer and resulting device
1572015032563511/12/15 Metal-insulator-metal back end of line capacitor structures
1582015032568211/12/15 Planar semiconductor growth on iii-v material
1592015032569211/12/15 Fin field effect transistor (finfet) device including a set of merged fins formed adjacent a set of unmerged fins
1602015032543611/12/15 Semiconductor devices including an electrically-decoupled fin and methods of forming the same
1612015032546711/12/15 Methods for fabricating integrated circuits including barrier layers for interconnect structures
1622015032548211/12/15 Integrated circuits having improved gate structures and methods for fabricating same
1632015032562211/12/15 Integrated circuits having magnetic tunnel junctions (mtj) and methods for fabricating the same
1642015032568111/12/15 Methods of fabricating integrated circuits
1652015031816911/05/15 Methods of forming epitaxial semiconductor cladding material on fins of a finfet semiconductor device
1662015031817611/05/15 Forming alternative material fins with reduced defect density by performing an implantation/anneal defect generation process
1672015031817811/05/15 Methods of forming a semiconductor device with a spacer etch block cap and the resulting device
1682015031820411/05/15 Spacer to prevent source-drain contact encroachment
1692015031821511/05/15 Methods for removing selected fins that are formed for finfet semiconductor devices
1702015031821711/05/15 Mixed n/p type non-planar semiconductor structure with multiple epitaxial heads and making same
1712015031828011/05/15 Wide-bottom contact for non-planar semiconductor structure and making same
1722015031828811/05/15 Vertical transistor static random access memory cell
1732015031834511/05/15 Semiconductor device configured for avoiding electrical shorting
1742015031835111/05/15 Multiple epitaxial head raised semiconductor structure and making same
1752015031839811/05/15 Methods of forming epi semiconductor material in a trench formed above a semiconductor device and the resulting devices
1762015031818111/05/15 Methods for fabricating integrated circuits using self-aligned quadruple patterning
1772015030911310/29/15 Measuring setup and hold times using a virtual delay
1782015031015710/29/15 Mask error compensation by optical modeling calibration
1792015031108110/29/15 Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
1802015031108210/29/15 Self-aligned gate contact formation
1812015031108310/29/15 Replacement low-k spacer
1822015031108510/29/15 Field effect transistor (finfet) device with a planar block area to enable varialble fin pitch and width
1832015031112010/29/15 Fabricating field effect transistor(s) with stressed channel region(s) and low-resistance source/drain regions
1842015031112210/29/15 Forming gate tie between abutting cells and resulting device
1852015031119910/29/15 Multiple fin finfet with low-resistance gate structure
1862015031129310/29/15 Source/drain profile engineering for enhanced p-mosfet
1872015031130810/29/15 Alternative gate dielectric films for silicon germanium and germanium channel materials
1882015031133710/29/15 Finfet device comprising a thermal oxide region positioned between a portion of the fin and a layer of insulating material
1892015031127210/29/15 Integrated circuits with resistor structures formed from gate metal and methods for fabricating same
1902015030311510/22/15 Modification of a threshold voltage of a transistor by oxygen treatment
1912015030326110/22/15 Tensile nitride profile shaper etch to provide void free gapfill
1922015030327310/22/15 Patterning multiple, dense features in a semiconductor device using a memorization layer
1932015030329510/22/15 Self-aligned contact openings over fins of a semiconductor device
1942015030305510/22/15 Methods for fabricating integrated circuits including surface treating for directed self-assembly
1952015030305710/22/15 Methods for fabricating integrated circuits including fluorine incorporation
1962015030324910/22/15 Methods for the production of integrated circuits comprising epitaxially grown replacement structures
1972015029491210/15/15 Methods of forming substantially self-aligned isolation regions on finfet semiconductor devices and the resulting devices
1982015029504710/15/15 Defect-free relaxed covering layer on semiconductor substrate with lattice mismatch
1992015029491510/15/15 Integrated circuits having finfets with improved doped channel regions and methods for fabricating same
2002015028676310/08/15 Pattern matching for predicting defect limited yield
2012015028676410/08/15 Methods of generating circuit layouts using self-alligned double patterning (sadp) techniques
2022015028717610/08/15 Method and appratus for hybrid test pattern generation for opc model calibration
2032015028759510/08/15 Devices and methods of forming fins at tight fin pitches
2042015028760410/08/15 Methods of cross-coupling line segments on a wafer
2052015028763610/08/15 Transistor contacts self-aligned in two dimensions
2062015028765110/08/15 Overlay mark dependent dummy fill to mitigate gate height variation
2072015028772510/08/15 Multiple threshold voltage semiconductor device
2082015028772710/08/15 Silicon-on-insulator finfet with bulk source and drain
2092015028764610/08/15 Methods for fabricating integrated circuits with improved implantation processes
2102015028764810/08/15 Finfet including tunable fin height and tunable fin width ratio
2112015028778210/08/15 Integrated circuits and methods of fabrication thereof
2122015028779510/08/15 Processes for preparing integrated circuits with improved source/drain contact structures and integrated circuits prepared according to such processes
2132015028782410/08/15 Integrated circuits with stressed semiconductor substrates and processes for preparing integrated circuits including the stressed semiconductor substrates
2142015027842610/01/15 Metrology pattern layout and use thereof
2152015027968010/01/15 Deposition of titanium-aluminum layers
2162015027968410/01/15 Method of forming semiconductor fins
2172015027973810/01/15 Self-aligned contacts and methods of fabrication
2182015027974210/01/15 Methods of forming replacement gate structures using a gate height register process to improve gate height uniformity and the resulting integrated circuit products
2192015027993510/01/15 Semiconductor devices with contact structures and a gate structure positioned in trenches formed in a layer of material
2202015027995910/01/15 Methods of removing portions of fins by preforming a selectively etchable material in the substrate
2212015027996310/01/15 Methods of forming a finfet semiconductor device so as to reduce punch-through leakage currents and the resulting device
2222015027997110/01/15 Methods of forming fins for finfet semiconductor devices and the selective removal of such fins
2232015027997210/01/15 Methods of forming semiconductor devices using a layer of material having a plurality of trenches formed therein
2242015027997310/01/15 Methods of forming substantially defect-free, fully-strained silicon-germanium fins for a finfet semiconductor device
2252015027999910/01/15 Finfet devices with different fin heights in the channel and source/drain regions
2262015027014209/24/15 De-oxidation of metal gate for improved gate performance
2272015027015909/24/15 Fabrication of semiconductor structures using oxidized polycrystalline silicon as conformal stop layers
2282015027017509/24/15 Partially crystallized fin hard mask for fin field-effect-transistor (finfet) device
2292015027017609/24/15 Methods of forming reduced resistance local interconnect structures and the resulting devices
2302015027026209/24/15 Gate structures with protected end surfaces to eliminate or reduce unwanted epi material growth
2312015027034609/24/15 Semiconductor devices with a replacement gate structure having a recessed channel
2322015027036409/24/15 Gate height uniformity in semiconductor devices
2332015027039809/24/15 Methods of forming isolated channel regions for a finfet semiconductor device and the resulting device
2342015027040009/24/15 Split well zero threshold voltage field effect transistor for integrated circuits
2352015026108409/17/15 Methods of modifying masking reticles to remove forbidden pitch regions thereof
2362015026308909/17/15 Non-planar semiconductor device with p-n junction located in substrate
2372015026312009/17/15 Replacement gate structure with low-k sidewall spacer for semiconductor devices
2382015026316009/17/15 Semiconductor device with self-aligned contact elements
2392015026316909/17/15 Semiconductor structures with bridging films and methods of fabrication
2402015025527709/10/15 Conformal nitridation of one or more fin-type transistor layers
2412015025529509/10/15 Methods of forming alternative channel materials on a non-planar semiconductor device and the resulting device
2422015025533909/10/15 Methods of forming a metal cap layer on copper-based conductive structures on an integrated circuit device
2432015025535309/10/15 Forming source/drain regions with single reticle and resulting device
2442015025545609/10/15 Replacement fin insolation in a semiconductor device
2452015025554209/10/15 Methods of forming stressed channel regions for a finfet semiconductor device and the resulting device
2462015025555509/10/15 Methods of forming a non-planar ultra-thin body device
2472015025556109/10/15 Semiconductor device with low-k spacers
2482015025560809/10/15 Methods of forming stressed channel regions for a finfet semiconductor device and the resulting device
2492015025529909/10/15 Methods for fabricating integrated circuits including selectively forming and removing fin structures

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Globalfoundries Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Globalfoundries Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by