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Globalfoundries Inc
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Globalfoundries Inc patents

Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors




Date Globalfoundries Inc patents (updated weekly) - BOOKMARK this page
11/16/17 new patent  Generating manufacturable sub-resolution assist feature shapes from a usefulness map
11/16/17 new patent  Method for in-die overlay control using feol dummy fill layer
11/16/17 new patent  Air gap over transistor gate and related method
11/16/17 new patent  Air gap over transistor gate and related method
11/16/17 new patent  Contact line having insulating spacer therein and forming same
11/16/17 new patent  Stable and reliable finfet sram with improved beta ratio
11/16/17 new patent  Semiconductor structure including a plurality of pairs of nonvolatile memory cells and an edge cell and the formation thereof
11/16/17 new patent  Air gaps formed by porous silicon removal
11/16/17 new patent  Devices and methods of forming self-aligned, uniform nano sheet spacers
11/16/17 new patent  Differential sg/eg spacer integration with equivalent nfet/pfet spacer widths & dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage eg device on fdsoi
11/16/17 new patent  Semiconductor structure including a transistor having stress creating regions and the formation thereof
11/16/17 new patent  Novel method to fabricate vertical nws
11/09/17Model-based generation of dummy features
11/09/17Laser scribe structures for a wafer
11/09/17Method, apparatus, and system for improved cell design having unidirectional metal layout architecture
11/09/17High density capacitor structure and method
11/09/17Thermoelectric cooling using through-silicon vias
11/09/17Method, apparatus and system for back gate biasing for fd-soi devices
11/09/17Method, apparatus and system for security application for integrated circuit devices
11/02/17Chip joining by induction heating
11/02/17Extreme ultraviolet lithography photomasks
11/02/17Double bandwidth algorithmic memory array
11/02/17Netlist editing of graphical data
11/02/17Method, apparatus and system for forming recolorable standard cells with triple patterned metal layer structures
11/02/17Short-channel nfet device
11/02/17Dual liner cmos integration methods for finfet devices
11/02/17Commonly-bodied field-effect transistors
11/02/17Fin diode with increased junction area
11/02/17Method of forming a semiconductor device structure and semiconductor device structure
11/02/17Fdsoi - capacitor
11/02/17Method of forming a capacitor structure and capacitor structure
11/02/17Isolation structures for circuits sharing a substrate
11/02/17Methods, apparatus, and system for improved nanowire/nanosheet spacers
11/02/17Semiconductor device and method
10/26/17Failure analysis and repair register sharing for memory bist
10/26/17Methods for forming fin structures
10/26/17Devices and methods for forming cross coupled contacts
10/26/17Metal-insulator-metal capacitor and methods of fabrication
10/26/17Interconnect structure having tungsten contact copper wiring
10/26/17Method, apparatus, and system for metal-oxide-semiconductor field-effect transistor (mosfet) with electrostatic discharge (esd) protection
10/26/17Method, apparatus, and system for increasing drive current of finfet device
10/26/17Finfet device with enlarged channel regions
10/26/17Tunable capacitor for fdsoi applications
10/26/17Method of forming a semiconductor device with a gate contact positioned above the active region
10/19/17Method, system and program product for sadp-friendly interconnect structure track generation
10/19/17Method and reducing threshold voltage mismatch in an integrated circuit
10/19/17Fabrication of multi threshold-voltage devices
10/19/17Methods of forming nmos and pmos finfet devices and the resulting product
10/19/17Silicon germanium fins on insulator formed by lateral recrystallization
10/19/17Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts
10/19/17Methods of forming a gate structure on a vertical transistor device
10/19/17Unifying realtime and static data for presenting over a web service
10/12/17Methods, apparatus and system for screening process splits for technology development
10/12/17Three-dimensional pattern risk scoring
10/12/17Integrated circuit performance modeling that includes substrate-generated signal distortions
10/12/17Oxidizing filler material lines to increase width of hard mask lines
10/12/17Protecting, oxidizing, and etching of material lines for use in increasing or decreasing critical dimensions of hard mask lines
10/12/17Oxidizing and etching of material lines for use in increasing or decreasing critical dimensions of hard mask lines
10/12/17Devices and methods for dynamically tunable biasing to backplates and wells
10/12/17Methods, apparatus and system for local isolation formation for finfet devices
10/12/17Integration of nominal gate width finfets and devices having larger gate width
10/12/17Method to fabricate a high performance capacitor in a back end of line (beol)
10/12/17Semiconductor structures with field effect transistor(s) having low-resistance source/drain contact(s)
10/12/17Recess liner for silicon germanium fin formation
10/12/17Integrated circuit structure having thin gate dielectric device and thick gate dielectric device
Patent Packs
10/12/17Methods of forming source/drain regions on finfet devices
10/12/17Methods, apparatus and system for screening process splits for technology development
10/12/17Two-dimensional self-aligned super via integration on self-aligned gate contact
10/12/17Two-dimensional self-aligned super via integration on self-aligned gate contact
10/05/17Repairable rigid test probe card assembly
10/05/17Overlay sampling reduction
10/05/17Timing/power risk optimized selective voltage binning using non-linear voltage slope
10/05/17Hdp fill with reduced void formation and spacer damage
10/05/17Methods of forming mis contact structures on transistor devices
10/05/17Methods of forming self-aligned contact structures by work function material layer recessing and the resulting devices
10/05/17Hdp fill with reduced void formation and spacer damage
10/05/17Transistor structures gated using a conductor-filled via or trench
10/05/17Method and ic structure for increasing pitch between gates
10/05/17Semiconductor structure including a transistor including a gate electrode region provided in a substrate and the formation thereof
10/05/17Multi-finger devices in mutliple-gate-contacted-pitch, integrated structures
Patent Packs
10/05/17Method to improve crystalline regrowth
10/05/17Semiconductor structure including a trench capping layer
10/05/17Finfet with isolated source and drain
10/05/17Fabrication of vertical field effect transistor structure with controlled gate length
10/05/17Shaped terminals for a bipolar junction transistor
10/05/17Method for forming a doped region in a fin using a variable thickness spacer and the resulting device
10/05/17Dual metal-insulator-semiconductor contact structure and formulation method
09/28/17System and method to adjust vehicle temperature based on driver location
09/28/17Pre-test power-optimized bin reassignment following selective voltage binning
09/28/17Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit
09/28/17Gate tie-down enablement with inner spacer
09/28/17Methods, apparatus and system for sti recess control for highly scaled finfet devices
09/28/17Introducing material with a lower etch rate to form a t-shaped sdb sti structure
09/28/17High density memory cell structures
09/28/17Stress memorization and defect suppression techniques for nmos transistor devices
09/28/17Compact device structures for a bipolar junction transistor
09/28/17Methods for fin thinning providing improved sce and s/d epi growth
09/21/17Tactile sensing intrumented wafer
09/21/17Static random access memory (sram) write assist circuit with improved boost
09/21/17Methods, apparatus, and system for global healing of write-limited die through bias temperature instability
09/21/17Semiconductor structure having insulator pillars and semiconductor material on substrate
09/21/17Block patterning method enabling merged space in sram with heterogeneous mandrel
09/21/17Methods of predicting unity gain frequency with direct current and/or low frequency parameters
09/21/17Inline monitoring of transistor-to-transistor critical dimension
09/21/17Integrated circuit package using polymer-solder ball structures and forming methods
09/21/17Three-dimensional hybrid packaging with through-silicon-vias and tape-automated-bonding
09/21/17Transistor structure with varied gate cross-sectional area
09/21/17Finfet based flash memory cell
09/21/17Dynamic bleed dynamic loading of a dimmer using event driven architecture
09/21/17A active power factor correction and current regulation in led circuit
Social Network Patent Pack
09/14/17Photonics chip
09/14/17Vertical nanowires formed on upper fin surface
09/14/17Methods, apparatus and system for a passthrough-based architecture
09/14/17Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor
09/14/17Method, apparatus and system for a high density middle of line flow
09/14/17Finfet semiconductor structures and methods of fabricating same
09/07/17In-situ euv collector cleaning utilizing a cryogenic process
09/07/17Processor with content addressable memory (cam) and monitor component
09/07/17Methods of forming conductive structures with different material compositions in a metallization layer
09/07/17Methods to form multi threshold-voltage dual channel without channel doping
Patent Packs
09/07/17Method and structure for srb elastic relaxation
09/07/17Test method and structure for integrated circuits before complete metalization
09/07/17Method of forming super steep retrograde wells on finfet
09/07/17Field-effect transistors with a non-relaxed strained channel
09/07/17Common metal contact regions having different schottky barrier heights and methods of manufacturing same
08/31/17Sense amplifier and latching scheme
08/31/17Compensating for lithographic limitations in fabricating semiconductor interconnect structures
08/31/17Fin cutting process for manufacturing finfet semiconductor devices
08/31/17Electronic device including moat power metallization in trench
08/31/17Semiconductor devices with varying threshold voltage and fabrication methods thereof
08/31/17Finfet device with enlarged channel regions
08/31/17Method, apparatus, and system having super steep retrograde well with silicon and silicon germanium fins
08/31/17Method of forming a semiconductor device structure and semiconductor device structure
08/31/17Serial capacitor device with middle electrode contact
08/31/17Method, apparatus and system for improved nanowire/nanosheet spacers
08/31/17Etch stop for airgap protection
08/31/17Formation of work-function layers for gate electrode using a gas cluster ion beam
08/31/17Increased contact area for finfets
08/31/17Photodetector and methods of manufacture
08/24/17Interconnect reliability structures
08/24/17Method, apparatus, and system for targeted healing of write fails through bias temperature instability
08/24/17Integrated circuit (ic) design analysis and feature extraction
08/24/17Methods for gate formation in circuit structures
08/24/17Methods of forming field effect transistor (fet) and non-fet circuit elements on a semiconductor-on-insulator substrate
08/24/17Devices and methods of reducing damage during beol m1 integration
08/24/17Methods of performing concurrent fin and gate cut etch processes for finfet semiconductor devices and the resulting devices
08/24/17Methods of forming graphene contacts on source/drain regions of finfet devices
08/24/17Method, apparatus, and system for mol interconnects without titanium liner
08/24/17Interconnect structure and forming
08/24/17Reducing antenna effects in soi devices
Patent Packs
08/24/17Metal layer tip to tip short
08/24/17Fin cut for taper device
08/17/17A photomask structure with an etch stop layer that enables repairs of drtected defects therein and extreme ultraviolet(euv) photolithograpy methods using the photomask structure
08/17/17Placing and routing implementing back bias in fdsoi
08/17/17Method wherein test cells and dummy cells are included into a layout of an integrated circuit
08/17/17Metal line layout based on line shifting
08/17/17Rapid heating process in the production of semiconductor components
08/17/17Integrated circuit having improved electromigration performance and forming same
08/17/17Finfet having notched fins and forming same
08/10/17Apparatus and vector s-parameter measurements
08/10/17Rule and process assumption co-optimization using feature-specific layout-based statistical analyses
08/10/17Memory built-in self-test (mbist) test time reduction
08/10/17Test strucutre for monitoring interface delamination
08/10/17Corrosion resistant chip sidewall connection with crackstop and hermetic seal
08/10/17Electrostatic discharge and passive structures integrated in a vertical gate fin-type field effect diode
08/10/17Field effect transistors
08/10/17Device with diffusion blocking layer in source/drain region
08/10/17Modified tunneling field effect transistors and fabrication methods
08/03/17System managing mobile sensors for continuous monitoring of pipe networks
08/03/17Gimbal assembly test system and method
Social Network Patent Pack
08/03/17Multiple contact probe head disassembly method and system
08/03/17Application specific integrated circuit (asic) test screens and selection of such screens
08/03/17Gate cut with high selectivity to preserve interlevel dielectric layer
08/03/17Methods to form multi threshold-voltage dual channel without channel doping
08/03/17Method, apparatus, and system for e-fuse in advanced cmos technologies
08/03/17Interconnect structure having tungsten contact copper wiring
08/03/17Dicing channels for glass interposers
08/03/17Switch improvement using layout optimization
08/03/17Transistor contacts self-aligned in two dimensions
08/03/17Bipolar junction transistors with extrinsic device regions free of trench isolation
08/03/17Method of forming super steep retrograde wells on finfet
08/03/17Gate stack for integrated circuit structure and forming same
08/03/17Epi facet height uniformity improvement for fdsoi technologies
08/03/17Semiconductor structure(s) with extended source/drain channel interfaces and methods of fabrication
08/03/17Methods to utilize piezoelectric materials as gate dielectric in high frequency rbts in an ic device
08/03/17Method, apparatus and system for voltage compensation in a semiconductor wafer
08/03/17Self-aligned local interconnect technology
07/27/17Electrodeposition systems and methods that minimize anode and/or plating solution degradation
07/27/17Resistance measurement-dependent integrated circuit chip reliability estimation
07/27/17Area and/or power optimization through post-layout modification of integrated circuit (ic) design blocks
Social Network Patent Pack
07/27/17Post-layout thermal-aware integrated circuit performance modeling
07/27/17Vertically stacked inductors and transformers
07/27/17Hybrid fin cut etching processes for products comprising tapered and non-tapered finfet semiconductor devices
07/27/17Fabrication of ic structure with metal plug
07/27/17Transistor structures and fabrication methods thereof
07/27/17High performance multiplexed latches
07/27/17Fin cut for taper device
07/20/17Sampling for opc model building
07/20/17Dual-bit 3-t high density mtprom array
07/20/17Stress memorization and defect suppression techniques for nmos transistor devices
07/20/17Self-aligned source/drain contact in replacement metal gate process
07/20/17Structure for beol metal levels with multiple dielectric layers for improved dielectric to metal adhesion
07/20/17Self-aligned device level contact structures
07/20/17Structures with thinned dielectric material
07/20/17Method, apparatus, and system for offset metal power rail for cell design
07/20/17Contact using multilayer liner
07/20/17Multiple threshold voltages using fin pitch and profile
07/20/17Environmentally aware mobile computing devices
07/13/17Signal detection metholodogy for fabrication control
07/13/17Content-addressable memory having multiple reference matchlines to reduce latency
07/13/17Using tensile mask to minimize buckling in substrate
07/13/17Metholodogy for profile control and capacitance reduction
07/13/17Semiconductor structure including a first transistor and a second transistor
07/13/17Fabrication of transistor-based semiconductor device using closed-loop fins
07/13/17Siloxane and organic-based mol contact patterning
07/13/17Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression
07/13/17Self aligned gate shape preventing void formation
07/13/17Method for characterization of a layered structure
07/13/17Method for making semiconductor device with filled gate line end recesses
07/06/17Methodology for early detection of ts to pc short issue
Social Network Patent Pack
07/06/17Test patterns for determining sizing and spacing of sub-resolution assist features (srafs)
07/06/17Replacement low-k spacer
07/06/17On-chip variable capacitor with geometric cross-section
07/06/17Electrical connection around a crackstop structure
07/06/17Replacement low-k spacer
06/29/17Device layer transfer with a preserved handle wafer section
06/29/17Process flow for a combined ca and tsv oxide deposition
06/29/17Self-aligned via forming to conductive line and related wiring structure
06/29/17Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an ic device
06/29/17Methods and devices for metal filling processes
06/29/17Soi wafers with buried dielectric layers to prevent cu diffusion
06/29/17Transistor using selective undercut at gate conductor and gate insulator corner
06/22/17Electrostatic discharge protection structures for efuses
06/22/17Post-polish wafer cleaning
06/22/17Methods and devices for back end of line via formation
06/22/17Self aligned gate shape preventing void formation
06/22/17Semiconductor structure having silicon germanium fins and fabricating same
06/22/17Structure and fully depleted silicon on insulator structure for threshold voltage modification
06/22/17Methods of forming a protection layer on a semiconductor device and the resulting device
06/22/17Horizontal gate all around nanowire transistor bottom isolation
06/22/17Junction butting structure using nonuniform trench shape
06/15/17Waveguide structures
06/15/17Patterned magnetic shields for inductors and transformers
06/15/17Multiple patterning substrate
06/15/17Wafer handler for infrared laser release
06/15/17Gate tie-down enablement with inner spacer
06/15/17Gate contact with vertical isolation from source-drain
06/15/17Epi facet height uniformity improvement for fdsoi technologies
06/15/17Integrated circuits with spacer chamfering and methods of spacer chamfering







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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