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Globalfoundries Inc
Globalfoundries Inc grand Cayman Cayman Islands
Globalfoundries Inc_20131212


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Globalfoundries Inc patents

Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors

Search recent Press Releases: Globalfoundries Inc-related press releases
Count Application # Date Globalfoundries Inc patents (updated weekly) - BOOKMARK this page
12016011643504/28/16  new patent  Nanochannel electrode devices
22016011724004/28/16  new patent  Performing secure address relocation within a multi-processor system sharing a same physical memory channel to external memory
32016011743204/28/16  new patent  Method and assisted metal routing
42016011743304/28/16  new patent  Integrated circuit timing variability reduction
52016011813804/28/16  new patent  Programming an electrical fuse with a silicon-controlled rectifier
62016011825104/28/16  new patent  Methods of forming doped epitaxial sige material on semiconductor devices
72016011825504/28/16  new patent  Methods of forming strained epitaxial semiconductor material(s) above a strain-relaxed buffer layer
82016011829804/28/16  new patent  Oxide mediated epitaxial nickel disilicide alloy contact formation
92016011830404/28/16  new patent  Fabrication of nanowire structures
102016011834104/28/16  new patent  Precut metal lines
112016011835804/28/16  new patent  Direct injection molded solder process for forming solder bumps on wafers
122016011838504/28/16  new patent  Replacement gate structures for transistor devices
132016011838604/28/16  new patent  Semiconductor structure having finfet ultra thin body and methods of fabrication thereof
142016011841404/28/16  new patent  Dual three-dimensional and rf semiconductor devices using local soi
152016011845804/28/16  new patent  Metal-insulator-metal back end of line capacitor structures
162016011846804/28/16  new patent  Multiple layer interface formation for semiconductor structure
172016011847204/28/16  new patent  Methods of forming 3d devices with dielectric isolation and a strained channel region
182016011847304/28/16  new patent  Non-planar schottky diode and fabrication
192016011848004/28/16  new patent  Methods of forming a tri-gate finfet device and the resulting device
202016011848304/28/16  new patent  Multi-gate fets having corrugated semiconductor stacks and forming the same
212016011849904/28/16  new patent  Fd devices in advanced semiconductor techniques
222016011829204/28/16  new patent  Integrated circuits with an air gap and methods of producing the same
232016011850004/28/16  new patent  Fin structures and multi-vt scheme based on tapered fin and method to form
242016011048904/21/16 Methods, apparatus, and system for using filler cells in design of integrated circuit devices
252016011132004/21/16 T-shaped fin isolation region and methods of fabrication
262016011132204/21/16 Finfet semiconductor device having local buried oxide
272016011133504/21/16 Semiconductor structure with self-aligned wells and multiple channel materials
282016011133904/21/16 Contact liners for integrated circuits and fabrication methods thereof
292016011134104/21/16 Method of utilizing trench silicide in a gate cross-couple construct
302016011135204/21/16 Dielectric cover for a through silicon via
312016011136004/21/16 Dummy metal structure and forming dummy metal structure
322016011137404/21/16 Low energy etch process for nitrogen-containing dielectric layer
332016011138104/21/16 Semiconductor structure including a die seal leakage detection material, the formation thereof and method including a test of a semiconductor structure
342016011138204/21/16 Vertical breakdown protection layer
352016011138604/21/16 Bond pad structure for low temperature flip chip bonding
362016011140604/21/16 Top-side interconnection substrate for die-to-die interconnection
372016011141404/21/16 Scr with fin body regions for esd protection
382016011142204/21/16 Method for making high voltage integrated circuit devices in a fin-type process and resulting devices
392016011149104/21/16 Fin device with blocking layer in channel region
402016011151304/21/16 Multi-channel gate-all-around fet
412016011151404/21/16 Ultra-low resistance gate structure for non-planar device via minimized work function material
422016011153904/21/16 High mobility pmos and nmos devices having si-ge quantum wells
432016011154904/21/16 Methods of forming a semiconductor circuit element and semiconductor circuit element
442016011186704/21/16 Methods of post-process dispensation of plasma induced damage protection component
452016010464404/14/16 Process for integrated circuit fabrication including a uniform depth tungsten recess technique
462016010454104/14/16 Novel otprom for post-process programming using selective breakdown
472016010462104/14/16 Semiconductor device having common contact and gate properties
482016010463804/14/16 Semiconductor structure including a layer of a first metal between a diffusion barrier layer and a second metal and the formation thereof
492016010467004/14/16 Interlayer ballistic conductor signal lines
502016010467204/14/16 Low capacitance ballistic conductor signal lines
512016010467704/14/16 Self aligned via fuse
522016010470704/14/16 Method and structure for transistors using gate stack dopants with minimal nitrogen penetration
532016010476204/14/16 Method of fabricating a mim capacitor with minimal voltage coefficient and a decoupling mim capacitor and analog/rf mim capacitor on the same chip with high-k dielectrics
542016010477004/14/16 Profile control over a collector of a bipolar junction transistor
552016010477404/14/16 Non-planar vertical dual source drift metal-oxide semiconductor (vdsmos)
562016010479904/14/16 Dual-strained nanowire and finfet devices with dielectric isolation
572016010517904/14/16 Level shifting an i/o signal into multiple voltage domains
582016009833204/07/16 Dynamic multi-purpose external access points connected to core interfaces within a system on chip (soc)
592016009916804/07/16 Method for defining an isolation region(s) of a semiconductor structure
602016009917104/07/16 Dimension-controlled via formation processing
612016009923904/07/16 Methods, apparatus and system for reduction of power consumption in a semiconductor device
622016009929704/07/16 Flexible active matrix display
632016009930204/07/16 Embedded metal-insulator-metal capacitor
642016009932104/07/16 Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layers
652016009932904/07/16 Suspended body field effect transistor
662016009933304/07/16 Field effect transistor and fabrication
672016009933604/07/16 Opc enlarged dummy electrode to eliminate ski slope at esige
682016009934304/07/16 Tunneling field effect transistor and methods of making such a transistor
692016009934404/07/16 Facilitating fabricating gate-all-around nanowire field-effect transistors
702016009356503/31/16 Printing minimum width features at non-minimum pitch and resulting device
712016009369203/31/16 Finfet semiconductor devices with replacement gate structures
722016009370403/31/16 Method for creating self-aligned transistor contacts
732016009371303/31/16 Semiconductor devices with replacement gate structures
742016009373903/31/16 Finfet semiconductor device with isolated channel regions
752016009371103/31/16 Tantalum carbide metal gate stack for mid-gap work function applications
762016008707303/24/16 Bipolar junction transistors with an air gap in the shallow trench isolation
772016008256603/24/16 Wafer slip detection during cmp processing
782016008684903/24/16 Constrained nanosecond laser anneal of metal interconnect structures
792016008686003/24/16 Methods for making robust replacement metal gates and multi-threshold devices in a soft mask integration scheme
802016008688603/24/16 Nanowire compatible e-fuse
812016008695203/24/16 Preventing epi damage for cap nitride strip scheme in a fin-shaped field effect transistor (finfet) device
822016007793903/17/16 Recovering from uncorrected memory errors
832016007908603/17/16 Method of forming a semiconductor device and according semiconductor device
842016007911603/17/16 Wafer with improved plating current distribution
852016007916803/17/16 Integrated circuits with metal-titanium oxide contacts and fabrication methods
862016007918003/17/16 Overlay mark dependent dummy fill to mitigate gate height variation
872016007924203/17/16 Patterning multiple, dense features in a semiconductor device using a memorization layer
882016007934203/17/16 Method and device for an integrated trench capacitor
892016007939703/17/16 Partial fin on oxide for improved electrical isolation of raised active regions
902016007173103/10/16 Finfet doping method with curvilinear trajectory implantation beam path
912016007174203/10/16 Photoresist collapse forming a physical unclonable function
922016007179103/10/16 Multimetal interlayer interconnects
932016007183503/10/16 Metal gate for robust esd protection
942016007184503/10/16 Directed self-assembly material growth mask for forming vertical nanowires
952016007192803/10/16 Methods of forming gate structures for finfet devices and the resulting semiconductor products
962016007193003/10/16 Multiple directed self-assembly material mask patterning for forming vertical nanowires
972016007193203/10/16 Finfet structures having uniform channel size and methods of fabrication
982016007194703/10/16 Method including a replacement of a dummy gate structure with a gate structure including a ferroelectric material
992016007195403/10/16 Robust post-gate spacer processing and device
1002016007196203/10/16 Symmetrical lateral bipolar junction transistor and use of same in characterizing and protecting transistors
1012016007197803/10/16 Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer
1022016007197903/10/16 Fin device with blocking layer in channel region
1032016006188003/03/16 Methods, apparatus and system for tddb testing
1042016006316703/03/16 Method and system for via retargeting
1052016006412303/03/16 Temperature independent resistor
1062016006422803/03/16 Method of forming a semiconductor structure including a ferroelectric material and semiconductor structure including a ferroelectric transistor
1072016006423603/03/16 Methods of patterning features having differing widths
1082016006425003/03/16 Methods of forming metastable replacement fins for a finfet semiconductor device by performing a replacement growth process
1092016006435403/03/16 Method for electronic circuit assembly on a paper substrate
1102016006437103/03/16 Non-planar esd device for non-planar output transistor and common fabrication thereof
1112016006437203/03/16 Esd snapback based clamp for finfet
1122016006438203/03/16 Selective fusi gate formation in gate first cmos technologies
1132016006447103/03/16 Embedded capacitor
1142016006448403/03/16 Lateral bipolar junction transistors on a silicon-on-insulator substrate with a thin device layer thickness
1152016006451003/03/16 Device including a floating gate electrode and a layer of ferroelectric material and the formation thereof
1162016006451403/03/16 Borderless contact formation through metal-recess dual cap integration
1172016006452303/03/16 Semiconductor structure having a source and a drain with reverse facets
1182016006452603/03/16 Methods of forming alternative channel materials on finfet semiconductor devices
1192016006454403/03/16 Finfet semiconductor device with isolated fins made of alternative channel materials
1202016006428603/03/16 Integrated circuits and methods for fabricating integrated circuits
1212016006447203/03/16 Integrated circuits including a mimcap device and methods of forming the same for long and controllable reliability lifetime
1222016006451303/03/16 Integrated circuits with a bowed substrate, and methods for producing the same
1232016006451503/03/16 Methods of making integrated circuits and components thereof
1242016005438302/25/16 Semiconductor structure having test device
1252016005528102/25/16 Model-based generation of dummy features
1262016005607502/25/16 Precut metal lines
1272016005610402/25/16 Self-aligned back end of line cut
1282016005610602/25/16 Structure with self aligned resist layer on an interconnect surface and making same
1292016005623102/25/16 Semiconductor devices and fabrication methods thereof
1302016005623802/25/16 Raised source/drain epi with suppressed lateral epi overgrowth
1312016005626102/25/16 Embedded sigma-shaped semiconductor alloys formed in transistors
1322016005626302/25/16 Methods of forming a gate cap layer above a replacement gate structure
1332016005626502/25/16 Methods of making a self-aligned channel drift device
1342016005628802/25/16 Circuit element including a layer of a stress-creating material providing a variable stress
1352016005629402/25/16 Epitaxial growth of silicon for finfets with non-rectangular cross-sections
1362016005603302/25/16 Low temperature atomic layer deposition of oxides on compound semiconductors
1372016005607202/25/16 Multilayered contact structure having nickel, copper, and nickel-iron layers
1382016005625302/25/16 Integrated circuits with diffusion barrier layers and processes for preparing integrated circuits including diffusion barrier layers
1392016004705802/18/16 Metal plating system including gas bubble removal unit
1402016004930202/18/16 Method of forming a semiconductor circuit element and semiconductor circuit element
1412016004932702/18/16 Methods of fabricating beol interlayer structures
1422016004933202/18/16 Methods of forming contact structures for semiconductor devices and the resulting devices
1432016004937002/18/16 Methods of forming mis contact structures for semiconductor devices by selective deposition of insulating material and the resulting devices
1442016004939902/18/16 Gate structures for semiconductor devices with a conductive etch stop layer
1452016004940002/18/16 Threshold voltage control for mixed-type non-planar semiconductor devices
1462016004940102/18/16 Hybrid contacts for commonly fabricated semiconductor devices using same metal
1472016004940202/18/16 Semiconductor device having fins with in-situ doped, punch-through stopper layer and related methods
1482016004942702/18/16 Integrated circuits with self aligned contact structures for improved windows and fabrication methods
1492016004946802/18/16 Product comprised of finfet devices with single diffusion break isolation structures
1502016004948102/18/16 Transistor contacts self-aligned two dimensions
1512016004948802/18/16 Semiconductor gate with wide top or bottom
1522016004949402/18/16 Forming transistors without spacers and resulting devices
1532016004949502/18/16 Semiconductor structures with coplanar recessed gate layers and fabrication methods
1542016004950302/18/16 Bipolar junction transistors with reduced epitaxial base facets effect for low parasitic collector-base capacitance
1552016004936602/18/16 Integrated circuits with electronic fuse structures
1562016004948902/18/16 Integrated circuits with nanowires and methods of manufacturing the same
1572016004949002/18/16 Integrated circuits with dual silicide contacts and methods for fabricating same
1582016004295402/11/16 Replacement metal gate and fabrication process with reduced lithography steps
1592016004304602/11/16 Etching of under bump metallization layer and resulting device
1602016004304802/11/16 Preventing misshaped solder balls
1612016004308102/11/16 Method of forming semiconductor fins
1622016004319002/11/16 Semiconductor structure(s) with extended source/drain channel interfaces and methods of fabrication
1632016004320202/11/16 Self-aligned bipolar junction transistor having self-planarizing isolation raised base structures
1642016004322302/11/16 Finfet semiconductor devices with stressed layers
1652016004402302/11/16 Authentication policy enforcement
1662016003395802/04/16 Endpoint determination using individually measured target spectra
1672016003563002/04/16 Methods of forming transistors with retrograde wells in cmos applications and the resulting device structures
1682016003564102/04/16 Semiconductor device including passivation layer encapsulant
1692016003572302/04/16 Macro design of device characterization for 14nm and beyond technologies
1702016003572702/04/16 Cmos structure with beneficial nmos and pmos band offsets
1712016003572802/04/16 Retrograde doped layer for device isolation
1722016003574302/04/16 Field effect transistor (fet) with self-aligned contacts, integrated circuit (ic) chip and manufacture
1732016003581802/04/16 Forming a vertical capacitor and resulting device
1742016003582002/04/16 Uniaxially-strained fd-soi finfet
1752016003585602/04/16 Semiconductor structure including a ferroelectric transistor and the formation thereof
1762016003586302/04/16 Methods of forming stressed channel regions for a finfet semiconductor device and the resulting device
1772016003590602/04/16 Planar semiconductor esd device and making same
1782016003387902/04/16 Methods and controllers for controlling focus of ultraviolet light from a lithographic imaging system, and apparatuses for forming an integrated circuit employing the same
1792016003556502/04/16 Methods for fabricating integrated circuits using directed self-assembly chemoepitaxy
1802016003563102/04/16 Atomic layer deposition of hfalc as a metal gate workfunction material in mos devices
1812016002580501/28/16 Wafer test structures and methods of providing wafer test structures
1822016002674801/28/16 Multi-polygon constraint decomposition techniques for use in double patterning applications
1832016002770001/28/16 Gate structure cut after formation of epitaxial active regions
1842016002771301/28/16 Establishing a thermal profile across a semiconductor chip
1852016002773401/28/16 E-fuse structure with methods of fusing the same and monitoring material leakage
1862016002774401/28/16 Method of forming an integrated crackstop
1872016002777501/28/16 Dual-width fin structure for finfets devices
1882016002789501/28/16 Methods of forming fins for a finfet device by forming and replacing sacrificial fin structures with alternative materials
1892016002790501/28/16 Bipolar junction transistors and methods of fabrication
1902016002679301/28/16 Threat condition management
1912016002014001/21/16 Anisotropic material damage process for etching low-k dielectric materials
1922016002015401/21/16 Simplified multi-threshold voltage scheme for fully depleted soi mosfets
1932016002020401/21/16 Three-dimensional electrostatic discharge semiconductor device
1942016002027501/21/16 Shallow trench isolation structure with sigma cavity
1952016002027701/21/16 Three-dimensional electrostatic discharge semiconductor device
1962016002033501/21/16 Transistors comprising doped region-gap-doped region structures and methods of fabrication
1972016001295201/14/16 Inductor structure having embedded airgap
1982016001326201/14/16 Fabrication of multilayer circuit elements
1992016001329101/14/16 Methods of forming isolated channel regions for a finfet semiconductor device and the resulting device
2002016001329601/14/16 Methods of forming low defect replacement fins for a finfet semiconductor device and the resulting devices
2012016000559801/07/16 Inhibiting diffusion of elements between material layers of a layered circuit structure
2022016000565701/07/16 Semiconductor structure with increased space and volume between shaped epitaxial structures
2032016000573301/07/16 Integrated circuit product with a gate height registration structure
2042016000573401/07/16 Integrated circuit product comprised of multiple p-type semiconductor devices with different threshold voltages
2052016000582801/07/16 Gate dielectric protection for transistors
2062016000583401/07/16 Methods of forming a channel region for a semiconductor device by performing a triple cladding process
2072016000586701/07/16 Silicide protection during contact metallization and resulting semiconductor structures
2082016000586801/07/16 Finfet with confined epitaxy
2092015037795612/31/15 Method and inline device characterization and temperature profiling
2102015037809612/31/15 Integration of optical components in integrated circuits
2112015038024612/31/15 Dimension-controlled via formation processing
2122015038025012/31/15 Semiconductor contacts and methods of fabrication
2132015038025212/31/15 Sidewall image templates for directed self-assembly materials
2142015038025812/31/15 Method for controlling height of a fin structure
2152015038026212/31/15 Sub-lithographic semiconductor structures with non-constant pitch
2162015038030412/31/15 Titanium silicide formation in a narrow source-drain contact
2172015038031612/31/15 Uniform exposed raised structures for non-planar semiconductor devices
2182015038032012/31/15 Test pattern for feature cross-sectioning
2192015038040412/31/15 Non-planar structure with extended exposed raised structures and same-level gate and spacers
2202015038040512/31/15 Removal of semiconductor growth defects
2212015038040912/31/15 Threshold voltage control for mixed-type non-planar semiconductor devices
2222015038050212/31/15 Method to form wrap-around contact for finfet
2232015038051012/31/15 Structure and forming silicide on fins
2242015038051412/31/15 Junction overlap control in a semiconductor device using a sacrificial spacer layer
2252015038051512/31/15 Multi-phase source/drain/gate spacer-epi formation
2262015038026912/31/15 Methods of forming integrated circuits with a planarized permanet layer and methods for forming finfet devices with a planarized permanent layer
2272015038030912/31/15 Metal-insulator-semiconductor (mis) contact with controlled defect density
2282015037189212/24/15 Methods of forming a finfet semiconductor device with a unique gate configuration, and the resulting finfet device
2292015037189612/24/15 Double self aligned via patterning
2302015037189912/24/15 Minimizing void formation in semiconductor vias and trenches
2312015037195612/24/15 Crackstops for bulk semiconductor wafers
2322015037208012/24/15 Self-aligned dual-height isolation for bulk finfet
2332015037208412/24/15 Raised fin structures and methods of fabrication
2342015037210412/24/15 Multi-channel gate-all-around fet
2352015037210712/24/15 Semiconductor devices having fins, and methods of forming semiconductor devices having fins
2362015037210812/24/15 Method and structure for protecting gates during epitaxial growth
2372015037211112/24/15 Methods of forming nanowire devices with spacers and the resulting devices
2382015037211512/24/15 Methods of forming nanowire devices with doped extension regions and the resulting devices
2392015037214012/24/15 Finfets having strained channels, and methods of fabricating finfets having strained channels
2402015037191212/24/15 Methods and systems for chemical mechanical planarization endpoint detection using an alternating current reference signal
2412015037205512/24/15 Non-volatile random access memory devices with shared transistor configuration and methods of forming the same
2422015037210012/24/15 Integrated circuits having improved contacts and methods for fabricating same
2432015036353212/17/15 Optimization of integrated circuits for a reticle transmission process window using multiple fill cells
2442015036418312/17/15 Method and bit-line sensing gates on an sram cell
2452015036432612/17/15 Methods of forming a protection layer on a semiconductor device and the resulting device
2462015036433612/17/15 Uniform gate height for mixed-type non-planar semiconductor devices
2472015036437812/17/15 Forming gate and source/drain contact openings by performing a common etch patterning process
2482015036442612/17/15 Decoupling capacitor for semiconductors
2492015036449112/17/15 Semiconductor device including soi butted junction to reduce short-channel penalty

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Globalfoundries Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Globalfoundries Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by