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Globalfoundries Inc
Globalfoundries Inc grand Cayman Cayman Islands
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Globalfoundries Inc patents


      
Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors


Salicide protection during contact metallization and resulting semiconductor structures

Globalfoundries

Salicide protection during contact metallization and resulting semiconductor structures

Finfet with active region shaped structures and channel separation

Globalfoundries

Finfet with active region shaped structures and channel separation

Search recent Press Releases: Globalfoundries Inc-related press releases
Count Application # Date Globalfoundries Inc patents (updated weekly) - BOOKMARK this page
12015018766007/02/15 new patent  Balancing asymmetric spacers
22015018770207/02/15 new patent  Middle-of-the-line constructs using diffusion contact structures
32015018776207/02/15 new patent  Semiconductor device with a multiple nanowire channel structure and methods of variably connecting such nanowires for current density modulation
42015018789607/02/15 new patent  Silicide protection during contact metallization and resulting semiconductor structures
52015018790507/02/15 new patent  Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
62015018794507/02/15 new patent  Salicide protection during contact metallization and resulting semiconductor structures
72015018794707/02/15 new patent  Finfet with active region shaped structures and channel separation
82015017963206/25/15Semiconductor device comprising an e-fuse and a fet
92015017964006/25/15Common fabrication of different semiconductor devices with different threshold voltages
102015017975306/25/15Novel e-fuse design for high-k metal-gate technology
112015017976606/25/15Buried local interconnect in finfet structure
122015017964406/25/15Finfet integrated circuits and methods for their fabrication
132015016882406/18/15Euv pellicle frame with holes and forming
142015016981806/18/15Pattern-based via redundancy insertion
152015017073506/18/15Dual port sram bitcell structures with improved transistor arrangement
162015017100106/18/15Methods of protecting a dielectric mask layer and related semiconductor devices
172015017108606/18/15Selective growth of a work-function metal in a replacement metal gate of a semiconductor device
182015017097306/18/15Methods for fabricating integrated circuits using self-aligned quadruple patterning
192015017108206/18/15Integrated circuit and fabricating the same having a replacement gate structure
202015016218006/11/15Method, storage medium and system for controlling the processing of lots of workpieces
212015016218806/11/15Method of forming a dielectric film
222015016241406/11/15Sandwich silicidation for fully silicided gate formation
232015016243506/11/15Asymmetric channel growth of a cladding layer over fins of a field effect transistor (finfet) device
242015015523806/04/15Making an efuse
252015014505905/28/15Methods of forming an e-fuse for an integrated circuit product and the resulting integrated circuit product
262015014506105/28/15Novel contact structure for a semiconductor device and methods of making same
272015014507105/28/15Methods of forming spacers on finfets and other semiconductor devices
282015014500005/28/15Integrated circuits with shallow trench isolations, and methods for producing the same
292015014634105/28/15Ald dielectric films with leakage-reducing impurity layers
302015014696605/28/15Methods and media for averaging contours of wafer feature edges
312015013723505/21/15Finfet semiconductor device having local buried oxide
322015013719405/21/15Inverted contact and methods of fabrication
332015013720305/21/15Forming finfet cell with fin tip and resulting device
342015013723505/21/15Finfet semiconductor device having local buried oxide
352015013723705/21/15Undoped epitaxial layer for junction isolation in a fin field effect transistor (finfet) device
362015013725805/21/15Forming a low votage antifuse device and resulting device
372015013727005/21/15Superior integrity of a high-k gate stack by forming a controlled undercut on the basis of a wet chemistry
382015013727305/21/15Method and device for self-aligned contact on a non-recessed metal gate
392015013730805/21/15Self-aligned dual-height isolation for bulk finfet
402015013731605/21/15Semiconductor device including a resistor and the formation thereof
412015013737205/21/15Self forming barrier layer and forming
422015013855505/21/15Overlay metrology system and method
432015014069505/21/15Method and system for determining overlap process windows in semiconductors by inspection techniques
442015014075105/21/15Modified, etch-resistant gate structure(s) facilitating circuit fabrication
452015014075605/21/15Fabrication methods facilitating integration of different device architectures
462015014076105/21/15Device isolation in finfet cmos
472015013737305/21/15Integrated circuits and methods for fabricating integrated circuits with improved contact structures
482015013738505/21/15Integrated circuits with close electrical contacts and methods for fabricating the same
492015014069705/21/15Test macro for use with a multi-patterning lithography process
502015014069805/21/15Test macro for use with a multi-patterning lithography process
512015012993405/14/15Methods of forming substantially self-aligned isolation regions on finfet semiconductor devices and the resulting devices
522015012996205/14/15Methods of forming replacement gate structures and fins on finfet devices and the resulting devices
532015012996405/14/15Nanowire transistor device
542015012996605/14/15Transistor including a gate electrode extending all around one or more channel regions
552015012997005/14/15Methods and structures for eliminating or reducing line end epi material growth on gate structures
562015012998305/14/15Fin-type transistor structures with extended embedded stress elements and fabrication methods
572015013002605/14/15Printing minimum width features at non-minimum pitch and resulting device
582015013006305/14/15Method to use self-repair cu barrier to solve barrier degradation due to ru cmp
592015013296205/14/15Facilitating mask pattern formation
602015012997205/14/15Methods of scaling thickness of a gate dielectric structure, methods of forming an integrated circuit, and integrated circuits
612015013006505/14/15Method to etch cu/ta/tan selectively using dilute aqueous hf/h2so4 solution
622015013291405/14/15Methods for fabricating integrated circuits with robust gate electrode structure protection
632015012314605/07/15Increased space between epitaxy on adjacent fins of finfet
642015012316605/07/15Methods of forming finfet devices with alternative channel materials
652015012318105/07/15Capacitors positioned at the device level in an integrated circuit product and methods of making such capacitors
662015012321105/07/15Narrow diffusion break for a fin field effect (finfet) transistor device
672015012321205/07/15Planar metrology pad adjacent a set of fins of a fin field effect transistor device
682015012321405/07/15Methods of forming a finfet semiconductor device with undoped fins
692015012325005/07/15Methods of fabricating defect-free semiconductor structures
702015012600805/07/15Methods of forming stressed multilayer finfet devices with alternative channel materials
712015012601005/07/15Band engineered semiconductor device and manufacturing thereof
722015012602305/07/15Methods of forming gate structures with multiple work functions and the resulting products
732015012602805/07/15Methods for fabricating integrated circuits using surface modification to selectively inhibit etching
742015012603405/07/15Methods for fabricating integrated circuits including topographical features for directed self-assembly
752015011515304/30/15Detection of particle contamination on wafers
762015011526704/30/15Planar metrology pad adjacent a set of fins of a fin field effect transistor device
772015011537004/30/15Semiconductor device providing enhanced fin isolation and related methods
782015011537104/30/15Finfet semiconductor structures and methods of fabricating same
792015011541804/30/15Devices and methods of forming fins at tight fin pitches
802015010857304/23/15Semiconductor device including vertically spaced semiconductor channel structures and related methods
812015010857704/23/15Selective growth of a work-function metal in a replacement metal gate of a semiconductor device
822015010858004/23/15Methods of forming bipolar devices and an integrated circuit product containing such bipolar devices
832015010858304/23/15Densely packed standard cells for integrated circuit products, and methods of making same
842015010858604/23/15Transistor device with improved source/drain junction architecture and methods of making such a device
852015010864604/23/15Electro-migration enhancing self-forming barrier process in copper mettalization
862015011131604/23/15Method for detecting defects in a diffusion barrier layer
872015011134904/23/15Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and the formation thereof
882015011348404/23/15Methods of generating circuit layouts that are to be manufactured using sadp routing techniques
892015010864704/23/15Hybrid manganese and manganese nitride barriers for back-end-of-line metallization and methods for fabricating the same
902015011137304/23/15Reducing gate height variation in rmg process
912015010241004/16/15Semiconductor device including stress layer adjacent channel and related methods
922015010241704/16/15Double trench well formation in sram cells
932015010242604/16/15Three-dimensional transistor with improved channel mobility
942015010282604/16/15Design structures and methods for extraction of device channel width
952015010491804/16/15Facilitating fabricating gate-all-around nanowire field-effect transistors
962015010494804/16/15Facilitating etch processing of a thin film via partial implantation thereof
972015010242204/16/15Integrated circuits including finfet devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
982015010530804/16/15Aqua regia and hydrogen peroxide hcl combination to remove ni and nipt residues
992015009719704/09/15Finfet with sigma cavity with multiple epitaxial material regions
1002015009724604/09/15Integrated circuit and fabricating the same having a replacement gate structure
1012015009724904/09/15Cross coupling gate using mulitple patterning
1022015009725204/09/15Simplified gate-first hkmg manufacturing flow
1032015009726304/09/15Method and high yield contact integration scheme
1042015009934004/09/15Methods for preventing oxidation damage during finfet fabrication
1052015009729104/09/15Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
1062015009933604/09/15Methods of manufacturing integrated circuits having finfet structures with epitaxially formed source/drain regions
1072015009109404/02/15Devices and methods of forming finfets with self aligned fin formation
1082015009109704/02/15Hardmask for a halo/extension implant of a static random access memory (sram) layout
1092015009387704/02/15Method for manufacturing a semiconductor device by stopping planarization of insulating material on fins
1102015009388704/02/15Methods for removing a native oxide layer from germanium susbtrates in the fabrication of integrated circuitsi
1112015009388904/02/15Methods for removing a native oxide layer from germanium susbtrates in the fabrication of integrated circuits
1122015009391404/02/15Methods for depositing an aluminum oxide layer over germanium susbtrates in the fabrication of integrated circuits
1132015008413103/26/15Gate height uniformity in semiconductor devices
1142015008713403/26/15Semiconductor isolation region uniformity
1152015008418303/26/15Integrated circuits with protected resistors and methods for fabricating the same
1162015008714903/26/15Methods for fabricating integrated circuits using improved masks
1172015007708603/19/15Fin width measurement using quantum well structure
1182015007611103/19/15Feature etching using varying supply of power pulses
1192015007660903/19/15Methods of forming stressed layers on finfet semiconductor devices and the resulting devices
1202015007662203/19/15Reducing gate expansion after source and drain implant in gate last process
1212015007665303/19/15Overlay performance for a fin field effect transistor device
1222015007670503/19/15Reduced capacitance interlayer structures and fabrication methods
1232015007806803/19/15Integrated circuits with sram cells having additional read stacks
1242015007977303/19/15Conformal doping for finfet devices
1252015007655903/19/15Integrated circuits with strained silicon and methods for fabricating such circuits
1262015007656003/19/15Integrated circuits including epitaxially grown strain-inducing fills doped with boron for improved robustness from delimination and methods for fabricating the same
1272015007661803/19/15Integrated circuits with a corrugated gate, and methods for producing the same
1282015007662403/19/15Integrated circuits having smooth metal gates and methods for fabricating same
1292015006951503/12/15Integrated circuits having laterally confined epitaxial material overlying fin structures and methods for fabricating same
1302015006096003/05/15Methods of forming contact structures on finfet semiconductor devices and the resulting devices
1312015006098303/05/15Semiconductor structure including a split gate nonvolatile memory cell and a high voltage transistor, and the formation thereof
1322015006101403/05/15Fin pitch scaling and active layer isolation
1332015006102703/05/15Methods of forming gate structures for transistor devices for cmos applications and the resulting products
1342015006103203/05/15Fabrication of nickel free silicide for semiconductor contact metallization
1352015006113503/05/15Copper interconnect with cvd liner and metallic cap
1362015006299603/05/15Embedded selector-less one-time programmable non-volatile memory
1372015006481203/05/15Method of forming a semiconductor device employing an optical planarization layer
1382015006487203/05/15Top corner rounding by implant-enhanced wet etching
1392015006763303/05/15Color-insensitive rules for routing structures
1402015006104003/05/15Self-aligned dielectric isolation for finfet devices
1412015006490303/05/15Methods for fabricating integrated circuits using chemical mechanical planarization to recess metal
1422015006491203/05/15Methods of forming integrated circuits and multiple critical dimension self-aligned double patterning processes
1432015005398102/26/15Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device
1442015005407802/26/15Methods of forming gate structures for finfet devices and the resulting smeiconductor products
1452015005408302/26/15Strain engineering in semiconductor devices by using a piezoelectric material
1462015005413902/26/15Through-silicon via with sidewall air gap
1472015005679602/26/15Method for forming a semiconductor device having a metal gate recess
1482015005678102/26/15Gate length independent silicon-on-nothing (son) scheme for bulk finfets
1492015005682002/26/15Systems and methods of solvent temperature control for wafer coating processes
1502015004844602/19/15Reduction of oxide recesses for gate height control
1512015005078702/19/15Fully silicided gate formed according to the gate-first hkmg approach
1522015005079202/19/15Extra narrow diffusion break for 3d finfet technologies
1532015005081102/19/15Critical dimension and pattern recognition structures for devices manufactured using double patterning techniques
1542015005081202/19/15Wafer-less auto clean of processing chamber
1552015005210802/19/15Method, computer readable storage medium and computer system for obtaining snapshots of data
1562015005249402/19/15Power rail layout for dense standard cell library
1572015004186902/12/15Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
1582015004189802/12/15Bulk finfet semiconductor-on-nothing integration
1592015004190502/12/15Methods of forming replacement gate structures for transistors and the resulting devices
1602015004190602/12/15Methods of forming stressed fin channel structures for finfet semiconductor devices
1612015004190902/12/15Completing middle of line integration allowing for self-aligned contacts
1622015004485502/12/15Methods of forming spacers on finfets and other semiconductor devices
1632015004486102/12/15Gate silicidation
1642015004185802/12/153d transistor channel mobility enhancement
1652015004191002/12/15Integrated circuits with a partially-depleted region formed over a bulk silicon substrate and methods for fabricating the same
1662015004191102/12/153d transistor channel mobility enhancement
1672015003501602/05/15Nitride spacer for protecting a fin-shaped field effect transistor (finfet) device
1682015003501802/05/15Devices and methods of forming bulk finfets with lateral seg for source and drain on dielectrics
1692015003505202/05/15Contact power rail
1702015003505302/05/15Device and a ldmos design for a finfet integrated circuit
1712015003507302/05/15Enabling enhanced reliability and mobility for replacement gate planar and finfet structures
1722015003508602/05/15Methods of forming cap layers for semiconductor devices with self-aligned contact elements and the resulting devices
1732015003697802/05/15Blazed grating spectral purity filter and methods of making such a filter
1742015003794502/05/15Epitaxially forming a set of fins in a semiconductor device
1752015003494102/05/15Integrated circuits having finfet semiconductor devices and methods of fabricating the same to resist sub-fin current leakage
1762015003506202/05/15Integrated circuits having finfets with improved doped channel regions and methods for fabricating same
1772015003760302/05/15Articles including metal structures having maximized bond adhesion and bond reliability, and methods of forming the same
1782015004007802/05/15Methods and systems for designing and manufacturing optical lithography masks
1792015004008002/05/15Methods for modifying an integrated circuit layout design
1802015004009102/05/15Methods for modifying an integrated circuit layout design
1812015002834801/29/15Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (finfet) device
1822015002843101/29/15Mol insitu pt rework sequence
1832015002848201/29/15Device layout for reducing through-silicon-via stress
1842015002848901/29/15Method for off-grid routing structures utilizing self aligned double patterning (sadp) technology
1852015002850001/29/15Forming alignment mark and resulting mark
1862015003117901/29/15Method of forming a semiconductor structure including silicided and non-silicided circuit elements
1872015003320101/29/15Systems and methods for fabricating semiconductor device structures
1882015002166301/22/15Finfet with insulator under channel
1892015002168301/22/15Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
1902015002169101/22/15Finfet with electrically isolated active region on bulk semiconductor substrate and fabricating same
1912015002169301/22/15Enhancing transistor performance and reliability by incorporating deuterium into a strained capping layer
1922015002169501/22/15Epitaxial block layer for a fin field effect transistor device
1932015002170201/22/15Shallow trench isolation
1942015002170301/22/15Gate oxide quality for complex mosfet devices
1952015002170401/22/15Finfet work function metal formation
1962015002170901/22/15Structures and methods integrating different fin device architectures
1972015002171201/22/15Highly conformal extension doping in advanced multi-gate devices
1982015002455701/22/15Semiconductor device having local buried oxide
1992015002456001/22/15Gate encapsulation achieved by single-step deposition
2002015002457201/22/15Process for faciltiating fin isolation schemes
2012015002457301/22/15Methods of forming replacement fins for a finfet semiconductor device by performing a replacement growth process
2022015002458501/22/15Systems and methods for fabricating gate structures for semiconductor devices
2032015002169401/22/15Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating the same
2042015002171401/22/15Integrated circuits having a metal gate structure and methods for fabricating the same
2052015002358301/22/15Methods and systems for determining a dose-to-clear of a photoresist
2062015002457801/22/15Methods for etching dielectric materials in the fabrication of integrated circuits
2072015001477701/15/15Channel semiconductor alloy layer growth adjusted by impurity ion implantation
2082015001481301/15/15Complex circuit element and capacitor utilizing cmos compatible antiferroelectric high-k materials
2092015001484301/15/15Semiconductor device with improved metal pillar configuration
2102015001777401/15/15Method of forming fins with recess shapes
2112015001780301/15/15Customized alleviation of stresses generated by through-substrate via(s)
2122015001477601/15/15Finfet integrated circuits and methods for their fabrication
2132015001617401/15/15Integrated circuits with programmable electrical connections and methods for fabricating the same
2142015000853601/08/15Semiconductor device structure and forming a semiconductor device structure
2152015000975001/08/15Device including a dual port static random access memory cell and the formation thereof
2162015001085101/08/15Methods involving color-aware retargeting of individual decomposed patterns when designing masks to be used in multiple patterning processes
2172015001289601/08/15Methods for fabricating integrated circuits including generating photomasks for directed self-assembly
2182015000162701/01/15Spacer chamfering for a replacement metal gate device
2192015000163401/01/15Methods of forming bipolar devices and an integrated circuit product containing such bipolar devices
2202015000163501/01/15Methods of forming an e-fuse for an integrated circuit product and the resulting integrated circuit product
2212015000164001/01/15Transistor device with improved source/drain junction architecture and methods of making such a device
2222015000164201/01/15Field effect transistor and fabrication
2232015000613801/01/15Optical proximity correction for connecting via between layers of a device
2242015000159101/01/15Bulk finfet with partial dielectric isolation featuring a punch-through stopping layer under the oxide
2252015000163001/01/15Structure and methods of fabricating y-shaped dmos finfet
2262015000164301/01/15Integrated circuits having improved high-k dielectric layers and methods for fabrication of same
2272014037480712/25/14Method of device isolation in cladding si through in situ doping
2282014037491512/25/14Integration of optical components in integrated circuits
2292014037796512/25/14Directed self-assembly (dsa) formulations used to form dsa-based lithography films
2302014036775112/18/14Finfet spacer etch for esige improvement
2312014036778712/18/14Methods of forming transistors with retrograde wells in cmos applications and the resulting device structures
2322014036778812/18/14Methods of forming gate structures for cmos based integrated circuit products and the resulting devices
2332014036779012/18/14Methods of forming gate structures for cmos based integrated circuit products and the resulting devices
2342014036779412/18/14Device including an array of memory cells and well contact areas, and the formation thereof
2352014036779512/18/14Methods of forming different finfet devices having different fin heights and an integrated circuit product containing such devices
2362014037043912/18/14Methods and systems for reducing bubbles in layers of photoresist material
2372014037069712/18/14Removal of nitride bump in opening replacement gate structure
2382014036780312/18/14Finfet gate with insulated vias and making same
2392014036782612/18/14Making an efuse
2402014037044712/18/14Semiconductor device resolution enhancement by etching multiple sides of a mask
2412014037070512/18/14Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein
2422014035372812/04/14Method and a reduced capacitance middle-of-the-line (mol) nitride stack
2432014035373412/04/14Semiconductor devices and methods of fabrication with reduced gate and contact resistances
2442014035380212/04/14Methods for integration of pore stuffing material
2452014035380512/04/14Methods of semiconductor contaminant removal using supercritical fluid
2462014035707912/04/14Methods of forming conductive structures using a sacrificial material during a metal hard mask removal process
2472014035955112/04/14Systems and methods for semiconductor voltage drop analysis
2482014034664811/27/14Low-k nitride film and making
2492014034666211/27/14Forming modified cell architecture for finfet technology and resulting device



ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009



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