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Globalfoundries Inc patents

Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors




Date Globalfoundries Inc patents (updated weekly) - BOOKMARK this page
07/20/17 new patent  Sampling for opc model building
07/20/17 new patent  Dual-bit 3-t high density mtprom array
07/20/17 new patent  Stress memorization and defect suppression techniques for nmos transistor devices
07/20/17 new patent  Self-aligned source/drain contact in replacement metal gate process
07/20/17 new patent  Structure for beol metal levels with multiple dielectric layers for improved dielectric to metal adhesion
07/20/17 new patent  Self-aligned device level contact structures
07/20/17 new patent  Structures with thinned dielectric material
07/20/17 new patent  Method, apparatus, and system for offset metal power rail for cell design
07/20/17 new patent  Contact using multilayer liner
07/20/17 new patent  Multiple threshold voltages using fin pitch and profile
07/20/17 new patent  Environmentally aware mobile computing devices
07/13/17Signal detection metholodogy for fabrication control
07/13/17Content-addressable memory having multiple reference matchlines to reduce latency
07/13/17Using tensile mask to minimize buckling in substrate
07/13/17Metholodogy for profile control and capacitance reduction
07/13/17Semiconductor structure including a first transistor and a second transistor
07/13/17Fabrication of transistor-based semiconductor device using closed-loop fins
07/13/17Siloxane and organic-based mol contact patterning
07/13/17Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression
07/13/17Self aligned gate shape preventing void formation
07/13/17Method for characterization of a layered structure
07/13/17Method for making semiconductor device with filled gate line end recesses
07/06/17Methodology for early detection of ts to pc short issue
07/06/17Test patterns for determining sizing and spacing of sub-resolution assist features (srafs)
07/06/17Replacement low-k spacer
07/06/17On-chip variable capacitor with geometric cross-section
07/06/17Electrical connection around a crackstop structure
07/06/17Replacement low-k spacer
06/29/17Device layer transfer with a preserved handle wafer section
06/29/17Process flow for a combined ca and tsv oxide deposition
06/29/17Self-aligned via forming to conductive line and related wiring structure
06/29/17Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an ic device
06/29/17Methods and devices for metal filling processes
06/29/17Soi wafers with buried dielectric layers to prevent cu diffusion
06/29/17Transistor using selective undercut at gate conductor and gate insulator corner
06/22/17Electrostatic discharge protection structures for efuses
06/22/17Post-polish wafer cleaning
06/22/17Methods and devices for back end of line via formation
06/22/17Self aligned gate shape preventing void formation
06/22/17Semiconductor structure having silicon germanium fins and fabricating same
06/22/17Structure and fully depleted silicon on insulator structure for threshold voltage modification
06/22/17Methods of forming a protection layer on a semiconductor device and the resulting device
06/22/17Horizontal gate all around nanowire transistor bottom isolation
06/22/17Junction butting structure using nonuniform trench shape
06/15/17Waveguide structures
06/15/17Patterned magnetic shields for inductors and transformers
06/15/17Multiple patterning substrate
06/15/17Wafer handler for infrared laser release
06/15/17Gate tie-down enablement with inner spacer
06/15/17Gate contact with vertical isolation from source-drain
06/15/17Epi facet height uniformity improvement for fdsoi technologies
06/15/17Integrated circuits with spacer chamfering and methods of spacer chamfering
06/15/17Method of forming a semiconductor device structure and semiconductor device structure
06/15/17Method to adjust alley gap between large blocks for floorplan optimization
06/15/17Local interconnect structure including non-eroded contact via trenches
06/08/17Dual-bit 3-t high density mtprom array
06/08/17Gate tie-down enablement with inner spacer
06/08/17Strain engineering devices using partial depth films in through-substrate vias
06/08/17Trench based charge pump device
06/08/17Substrate resistor with overlying gate structure
06/08/17Integrated cmos wafers
06/08/17Metal gate structure and formation
06/08/17Germanium photodetector with soi doping source
06/08/17Methods for producing integrated circuits with air gaps and integrated circuits produced from such methods
06/01/17Sram-like ebi structure design and implementation to capture mosfet source-drain leakage eariler
Patent Packs
06/01/17Coupling inductors in an ic device using interconnecting elements with solder caps and resulting devices
06/01/17Mass spectrometry contaminant identification in semiconductor fabrication
06/01/17Wafer handler and methods of manufacture
06/01/17Amorphous metal interconnections by subtractive etch
06/01/17Raised e-fuse
06/01/17Tri-gate finfet device
06/01/17Methods of forming a contact structure for a vertical channel semiconductor device and the resulting device
06/01/17Replacement body finfet for improved junction profile with gate self-aligned junctions
06/01/17Semiconductor device including finfet and fin varactor
06/01/17Semiconductor device including finfet and fin varactor
05/25/17On-chip sensor for monitoring active circuits on integrated circuit (ic) chips
05/25/17Modeling localized temperature changes on an integrated circuit chip using thermal potential theory
05/25/17Temperature-aware integrated circuit design methods and systems
05/25/17Zig-zag trench structure to prevent aspect ratio trapping defect escape
05/25/17Hdp fill with reduced void formation and spacer damage
Patent Packs
05/25/17Method, apparatus, and system for mol interconnects without titanium liner
05/25/17Method and structure for establishing interconnects in packages using thin interposers
05/25/17Extrusion-resistant solder interconnect structures and methods of forming
05/25/17Memory device structure
05/25/17Replacement low-k spacer
05/25/17Semiconductor circuit element
05/25/17Poc process flow for conformal recess fill
05/18/17Additions of organic species to facilitate crosslinker removal during pspi cure
05/18/17Methods, apparatus, and systems for minimizing defectivity in top-coat-free lithography and improving reticle cd uniformity
05/18/17Multi-frequency inductors with low-k dielectric area
05/18/17Self-aligned conductive polymer pattern placement error compensation layer
05/18/17Gate structure cut after formation of epitaxial active regions
05/18/17Conductively doped polymer pattern placement error compensation layer
05/18/17Semiconductor fuses with nanowire fuse links and fabrication methods thereof
05/18/17Pattern placement error compensation layer
05/18/17Pattern placement error compensation layer in via opening
05/18/17Special construct for continuous non-uniform active region finfet standard cells
05/18/17Dummy gate used as interconnection and making the same
05/18/17Single and double diffusion breaks on integrated circuit products comprised of finfet devices
05/18/17Method, apparatus and system for improved performance using tall fins in finfet devices
05/18/17Methods of forming pmos and nmos finfet devices on cmos based integrated circuit products
05/18/17Methods of forming pmos finfet devices and multiple nmos finfet devices with different performance characteristics
05/18/17Interconnect structure including middle of line (mol) metal layer local interconnect on etch stop layer
05/18/17Mosfet with asymmetric self-aligned contact
05/18/17Mosfet with asymmetric self-aligned contact
05/11/17Barrier structures for underfill blockout regions
05/11/17Chamferless via structures
05/11/17Alternative threshold voltage scheme via direct metal gate patterning for high performance cmos finfets
05/11/17Test structures and forming an according test structure
05/11/17Method, apparatus, and system for e-fuse in advanced cmos technologies
Social Network Patent Pack
05/11/17Methods of self-forming barrier formation in metal interconnection applications
05/11/17Method, apparatus, and system for stacked cmos logic circuits on fins
05/11/17Reducing thermal runaway in inverter devices
05/11/17Advanced mosfet contact structure to reduce metal-semiconductor interface resistance
05/04/17In-situ contactless monitoring of photomask pellicle degradation
05/04/17Etch stop for airgap protection
05/04/17Anisotropic material damage process for etching low-k dielectric materials
05/04/17Trench silicide contacts with high selectivity process
05/04/17Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices
05/04/17Semiconductor structure with anti-efuse device
Patent Packs
05/04/17Antenna diode circuit for manufacturing of semiconductor devices
05/04/17Trench silicide contacts with high selectivity process
05/04/17Semiconductor device with a memory device and a high-k metal gate transistor
05/04/17Metal resistor forming method using ion implantation
05/04/17Method of forming a gate contact structure for a semiconductor device
05/04/17Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts
05/04/17Etch stop for airgap protection
05/04/17Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices
05/04/17Trench silicide contacts with high selectivity process
05/04/17Fin field effect transistor complementary metal oxide semiconductor with dual strained channels with solid phase doping
05/04/17Fin field effect transistor complementary metal oxide semiconductor with dual strained channels with solid phase doping
05/04/17Stress memorization techniques for transistor devices
05/04/17Semiconductor structure including a varactor
04/27/17Wafer level electrical test for optical proximity correction and/or etch bias
04/27/17Use of multivariate models to control manufacturing operations
04/27/17Method including a formation of a diffusion barrier and semiconductor structure including a diffusion barrier
04/27/17Unmerged epitaxial process for finfet devices with aggressive fin pitch scaling
04/27/17Unmerged epitaxial process for finfet devices with aggressive fin pitch scaling
04/27/17Method of forming a memory device structure and memory device structure
04/27/17Buffer layer for modulating vt across devices
04/27/17Finfet devices having fins with a tapered configuration and methods of fabricating the same
04/20/17Auto test grouping/clock sequencing for at-speed test
04/20/17Built-in self-test (bist) circuit and associated bist embedded memories
04/20/17Structures with thinned dielectric material
04/20/17Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor
04/20/17Semiconductor device with a gate contact positioned above the active region
04/20/17High doped iii-v source/drain junctions for field effect transistors
04/13/17Forming replacement low-k spacer in tight pitch fin field effect transistors
04/13/17Contacting soi substrates
04/13/17Co-fabricated bulk devices and semiconductor-on-insulator devices
Patent Packs
04/13/17Forming replacement low-k spacer in tight pitch fin field effect transistors
04/13/17Forming stressed epitaxial layer using dummy gates
04/06/17Methods of error detection in fabrication processes
04/06/17Methods of error detection in fabrication processes
04/06/17Amophization induced metal-silicon contact formation
04/06/17Source/drain epitaxial electrical monitor
04/06/17Ic structure with angled interconnect elements
04/06/17Implementing stress in a bipolar junction transistor
03/30/17Programmable devices with current-facilitated migration and fabrication methods
03/30/17Programmable via devices with metal/semiconductor via links and fabrication methods thereof
03/30/17Self-aligned gate tie-down contacts with selective etch stop liner
03/30/17Three-dimensional semiconductor transistor with gate contact in active region
03/30/17Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme
03/30/17Field effect transistor device spacers
03/30/17Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme
03/23/17Dual liner silicide
03/23/17Three-dimensional scatterometry for measuring dielectric thickness
03/23/17Integrated circuit chip design methods and systems using process window-aware timing analysis
03/23/173d multipath inductor
03/23/17Method including an adjustment of a plurality of wafer handling elements, system including a plurality of wafer handling elements and photolithography track
Social Network Patent Pack
03/23/17Semiconductor device with reduced poly spacing effect
03/23/17Fin structures and multi-vt scheme based on tapered fin and method to form
03/23/17Dual metal-insulator-semiconductor contact structure and formulation method
03/23/17Stacked nanowire device width adjustment by gas cluster ion beam (gcib)
03/23/17Poc process flow for conformal recess fill
03/23/17Stacked nanowire device width adjustment by gas cluster ion beam (gcib)
03/16/17Method, apparatus and system for using hybrid library track design for soi technology
03/16/17Removal of semiconductor growth defects
03/16/17Hdp fill with reduced void formation and spacer damage
03/16/17Asymmetric semiconductor device and forming same
03/16/17Spacer chamfering gate stack scheme
03/16/17Devices and methods of creating elastic relaxation of epitaxially grown lattice mismatched films
03/16/17Methods of forming semiconductor device with self-aligned contact elements and the resulting device
03/16/17Preventing leakage inside air-gap spacer during contact formation
03/16/17Spacer chamfering gate stack scheme
03/16/17Semiconductor device with gate inside u-shaped channel and methods of making such a device
03/16/17Methods of making source/drain regions positioned inside u-shaped semiconductor material using source/drain placeholder structures
03/16/17Vertical slit transistor with optimized ac performance
03/16/17Wafer with soi structure having a buried insulating multilayer structure and semiconductor device structure
03/16/17Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins
Social Network Patent Pack
03/09/17Detection of gate-to-source/drain shorts
03/09/17Electrostatic substrate holder with non-planar surface and etching
03/09/17Methods of forming cmos based integrated circuit products using disposable spacers
03/09/17Method of forming a semiconductor device
03/09/17Forming reliable contacts on tight semiconductor pitch
03/09/17Three-dimensional finfet transistor with portion(s) of the fin channel removed in gate-last flow
03/02/17Hard mask etch and dielectric etch aware overlap for via and metal layers
03/02/17Reliability of an electronic device
03/02/17Raised e-fuse
03/02/17Integrated circuit structure with metal crack stop and methods of forming same
03/02/17Integrated circuit structure with crack stop and forming same
03/02/17Method and structure for low-k face-to-face bonded wafer dicing
03/02/17Fin liner integration under aggressive pitch
03/02/17Electrical gate-to-source/drain connection
03/02/17Methods for fabricating programmable devices and related structures
03/02/17High voltage finfet structure with shaped drift region
03/02/17Photodetector methods and photodetector structures
03/02/17Method, apparatus and system for using tunable timing circuits for fdsoi technology
03/02/17Fin cut for taper device
03/02/17Self-aligned local interconnect technology
03/02/17Fin cut for taper device
02/23/17Method, apparatus, and system for passive die strain measurement
02/23/17Diffractive overlay mark
02/23/17Data aware write scheme for sram
02/23/17Disturb free bitcell and array
02/23/17Automatic control of spray bar and units for chemical mechanical polishing in-situ brush cleaning
02/23/17Dual liner cmos integration methods for finfet devices
02/23/17Methods for forming fin structures
02/23/17Finfet pcm access transistor having gate-wrapped source and drain regions
02/23/17Germanium photodetector with soi doping source
Social Network Patent Pack
02/23/17Series resistance reduction in vertically stacked silicon nanowire transistors
02/23/17Forming a gate contact in the active area
02/23/17Forming a gate contact in the active area
02/16/17Process design kit for efficient and accurate mismatch simulation of analog circuits
02/16/17Methods of forming air gaps in metallization layers on integrated circuit products
02/16/17Self-aligned back end of line cut
02/16/17Filling cavities in an integrated circuit and resulting devices
02/16/17Gate tie-down enablement with inner spacer
02/16/17Methods of forming self-aligned device level contact structures
02/16/17Gate tie-down enablement with inner spacer
02/16/17Field effect transistors having multiple effective work functions
02/16/17Reducing liner corrosion during metallization of semiconductor devices
02/16/17Methods and devices for metal filling processes
02/16/17Semiconductor structure including a nonvolatile memory cell and the formation thereof
02/16/17Structure and method to form a finfet device
02/16/17Semiconductor structure with multilayer iii-v heterostructures
02/16/17Early pts with buffer for channel doping control
02/16/17Forming a contact for a tall fin transistor
02/16/17Forming a contact for a tall fin transistor
02/16/17Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins
02/16/17Self-aligned gate tie-down contacts with selective etch stop liner
02/09/17Capacitor structures with embedded electrodes and fabrication methods thereof
02/09/17Damascene wires with top via structures
02/09/17Methods for forming transistor devices with different threshold voltages and the resulting devices
02/09/17Bond pad structure for low temperature flip chip bonding
02/09/17Capacitor structure and forming a capacitor structure
02/09/17Bulex contacts in advanced fdsoi techniques
02/09/17Measurement measuring in thin films
02/09/17Method for forming field effect transistors







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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