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Globalfoundries, Inc. patents


      
Recent patent applications related to Globalfoundries, Inc.. Globalfoundries, Inc. is listed as an Agent/Assignee. Note: Globalfoundries, Inc. may have other listings under different names/spellings. We're not affiliated with Globalfoundries, Inc., we're just tracking patents.

ARCHIVE: New 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries, Inc.-related inventors



Globalfoundries

Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein

Globalfoundries

Methods for fabricating integrated circuits having confined epitaxial growth regions

Search recent Press Releases: Globalfoundries, Inc.-related press releases
Count Application # Date Globalfoundries, Inc. patents (updated weekly) - BOOKMARK this page
12014021008807/31/14 new patent  Method for reducing wettability of interconnect material at corner interface and device incorporating same
22014021117507/31/14 new patent  Enhancing resolution in lithographic processes using high refractive index fluids
32014021541507/31/14 new patent  Automated design layout pattern correction based on context-aware patterns
42014020956307/31/14 new patent  Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein
52014021303307/31/14 new patent  Methods for fabricating electrically-isolated finfet semiconductor devices
62014021303707/31/14 new patent  Methods for fabricating integrated circuits having confined epitaxial growth regions
72014020328007/24/14Electrical test structure for devices employing high-k dielectrics or metal gates
82014020329807/24/14Strained silicon carbide channel for electron mobility of nmos
92014020333907/24/14Semiconductor device comprising self-aligned contact elements and a replacement gate electrode structure
102014020337607/24/14Finfet integrated circuits with uniform fin height and methods for fabricating the same
112014020340507/24/14Method to dynamically tune precision resistance
122014020344607/24/14Through silicon via device having low stress, thin film gaps and methods for forming the same
132014020381407/24/14Method and apparatus for measuring alpha particle induced soft errors in semiconductor devices
142014020615707/24/14Method of forming a semiconductor structure including a vertical nanowire
152014020828507/24/14Self-aligned double patterning via enclosure design
162014020327907/24/14Test structure and method to faciltiate development/optimization of process parameters
172014020344907/24/14Integrated circuits and methods of forming the same with metal layer connection to through-semiconductor via
182014020382707/24/14Integrated circuits and methods of forming the same with embedded interconnect connection to through-semiconductor via
192014019746807/17/14Methods of forming semiconductor device with self-aligned contact elements and the resulting device
202014019754407/17/14Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials
212014019749807/17/14Integrated circuits and methods for fabricating integrated circuits with improved silicide contacts
222014019984507/17/14Selective removal of gate structure sidewall(s) to facilitate sidewall spacer protection
232014019132407/10/14Methods of forming bulk finfet devices by performing a recessing process on liner materials to define different fin heights and finfet devices with such recessed liner materials
242014019133207/10/14Pfet devices with different structures and performance characteristics
252014019395707/10/14Reducing gate height variance during semiconductor device formation
262014018355107/03/14Blanket epi super steep retrograde well formation without si recess
272014018363807/03/14Methods of using a trench salicide routing layer
282014018372007/03/14Methods of manufacturing integrated circuits having a compressive nitride layer
292014018503007/03/14Asymmetric reticle heating of multilayer reticles eliminated by dummy exposures and related methods
302014018703607/03/14Integration of ru wet etch and cmp for beol interconnects with ru layer
312014018374507/03/14Gate electrode(s) and contact structure(s), and methods of fabrication thereof
322014017553906/26/14Canyon gate transistor and methods for its fabrication
332014017816006/26/14Overhead substrate handling and storage system
342014017882406/26/14Optimizing lithographic processes using laser annealing techniques
352014017556206/26/14Spacer divot sealing method and semiconductor device incorporating same
362014017909306/26/14Gate structure formation processes
372014016711906/19/14Methods of forming a sidewall spacer having a generally triangular shape and a semiconductor device having such a spacer
382014016712006/19/14Methods of forming a finfet semiconductor device by performing an epitaxial growth process
392014016726406/19/14Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structures
402014016726506/19/14Methods of forming a bi-layer cap layer on copper-based conductive structures and devices with such a cap layer
412014017053306/19/14Extreme ultraviolet lithography (euvl) alternating phase shift mask
422014017083906/19/14Methods of forming fins for a finfet device wherein the fins have a high germanium content
432014017353306/19/14Locally optimized coloring for cleaning lithographic hotspots
442014015905206/12/14Method and structure for transistor with reduced drain-induced barrier lowering and on resistance
452014015912506/12/14Contact landing pads for a semiconductor device and methods of making same
462014015912606/12/14Methods of forming a finfet semiconductor device with undoped fins
472014015916406/12/14Double sidewall image transfer process
482014015917106/12/14Methods of forming bulk finfet semiconductor devices by performing a liner recessing process to define fin heights and finfet devices with such a recessed liner
492014015919906/12/14High density serial capacitor device and methods of making such a capacitor device
502014016217606/12/14Semiconductor device resolution enhancement by etching multiple sides of a mask
512014016244706/12/14Finfet hybrid full metal gate with borderless contacts
522014015176006/05/14Doped flowable pre-metal dielectric
532014015180706/05/14Combination finfet and planar fet semiconductor device and methods of making such a device
542014015181606/05/14Novel contact structure for a semiconductor device and methods of making same
552014015181806/05/14Semiconductor device with a silicon dioxide gate insulation layer implanted with a rare earth element and methods of making such a device
562014014525705/29/14Semiconductor device having a metal recess
572014014527405/29/14Methods of forming replacement gate structures for nfet semiconductor devices and devices having such gate structures
582014014533205/29/14Methods of forming graphene liners and/or cap layers on copper-based conductive structures
592014014801105/29/14Method of forming semiconductor fins
602014014995205/29/14Trench silicide mask generation using designated trench transfer and trench block regions
612014014160505/22/14Finfet formation using double patterning memorization
622014013877905/22/14Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance
632014014160505/22/14Finfet formation using double patterning memorization
642014013877905/22/14Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance
652014013173505/15/14Source and drain doping using doped raised source and drain regions
662014013177105/15/14Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof
672014013180505/15/14Transistor with embedded si/ge material having reduced offset and superior uniformity
682014013188105/15/14Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection
692014013183105/15/14Integrated ciruit including an fin-based diode and methods of its fabrication
702014013481405/15/14Methods of manufacturing integrated circuits having finfet structures with epitaxially formed source/drain regions
712014013482205/15/14Methods for fabricating integrated circuits including semiconductive resistor structures in a finfet architecture
722014013173505/15/14Source and drain doping using doped raised source and drain regions
732014013177105/15/14Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof
742014013180505/15/14Transistor with embedded si/ge material having reduced offset and superior uniformity
752014013188105/15/14Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection
762014013183105/15/14Integrated ciruit including an fin-based diode and methods of its fabrication
772014013481405/15/14Methods of manufacturing integrated circuits having finfet structures with epitaxially formed source/drain regions
782014013482205/15/14Methods for fabricating integrated circuits including semiconductive resistor structures in a finfet architecture
792014012479405/08/14Fabrication of reverse shallow trench isolation structures with super-steep retrograde wells
802014012484105/08/14Methods of forming replacement gate structures on semiconductor devices and the resulting device
812014012999905/08/14Method for selectively modeling narrow-width stacked device performance
822014012479405/08/14Fabrication of reverse shallow trench isolation structures with super-steep retrograde wells
832014012484105/08/14Methods of forming replacement gate structures on semiconductor devices and the resulting device
842014012999905/08/14Method for selectively modeling narrow-width stacked device performance
852014011741705/01/14Performance enhancement in transistors by providing a graded embedded strain-inducing semiconductor region with adapted angles with respect to the substrate surface
862014011741805/01/14Three-dimensional silicon-based transistor comprising a high-mobility channel formed by non-masked epitaxy
872014011741905/01/14Fin etch and fin replacement for finfet integration
882014011750705/01/14Double trench well formation in sram cells
892014012067705/01/14Methods of forming enhanced mobility channel regions on 3d semiconductor devices, and devices comprising same
902014011741705/01/14Performance enhancement in transistors by providing a graded embedded strain-inducing semiconductor region with adapted angles with respect to the substrate surface
912014011741805/01/14Three-dimensional silicon-based transistor comprising a high-mobility channel formed by non-masked epitaxy
922014011741905/01/14Fin etch and fin replacement for finfet integration
932014011750705/01/14Double trench well formation in sram cells
942014012067705/01/14Methods of forming enhanced mobility channel regions on 3d semiconductor devices, and devices comprising same
952014011079804/24/14Methods of forming a semiconductor device with low-k spacers and the resulting device
962014011085404/24/14Semiconductor dies with reduced area consumption
972014011341904/24/14Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material
982014011342004/24/14Methods of avoiding shadowing when forming source/drain implant regions on 3d semiconductor devices
992014011345504/24/14Method of forming a semiconductor structure including a wet etch process for removing silicon nitride
1002014011077204/24/14Integrated circuit decoupling capacitor arrangement
1012014011079404/24/14Facilitating gate height uniformity and inter-layer dielectric protection
1022014011079804/24/14Methods of forming a semiconductor device with low-k spacers and the resulting device
1032014011085404/24/14Semiconductor dies with reduced area consumption
1042014011341904/24/14Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material
1052014011342004/24/14Methods of avoiding shadowing when forming source/drain implant regions on 3d semiconductor devices
1062014011345504/24/14Method of forming a semiconductor structure including a wet etch process for removing silicon nitride
1072014011077204/24/14Integrated circuit decoupling capacitor arrangement
1082014011079404/24/14Facilitating gate height uniformity and inter-layer dielectric protection
1092014010342004/17/14Advanced faraday shield for a semiconductor device
1102014010657504/17/14Directed self-assembly of block copolymers using laser annealing
1112014010342004/17/14Advanced faraday shield for a semiconductor device
1122014010657504/17/14Directed self-assembly of block copolymers using laser annealing
1132014009753804/10/14Semiconductor device having a self-forming barrier layer at via bottom
1142014009789204/10/14Double patterning compatible colorless m1 route
1152014010080604/10/14Method and apparatus for matching tools based on time trace data
1162014009845904/10/14Capacitor and contact structures, and formation processes thereof
1172014009753804/10/14Semiconductor device having a self-forming barrier layer at via bottom
1182014009789204/10/14Double patterning compatible colorless m1 route
1192014010080604/10/14Method and apparatus for matching tools based on time trace data
1202014009845904/10/14Capacitor and contact structures, and formation processes thereof
1212014009753804/10/14Semiconductor device having a self-forming barrier layer at via bottom
1222014009789204/10/14Double patterning compatible colorless m1 route
1232014010080604/10/14Method and apparatus for matching tools based on time trace data
1242014009845904/10/14Capacitor and contact structures, and formation processes thereof
1252014008438303/27/14Methods of forming 3-d semiconductor devices using a replacement gate technique and a novel 3-d device
1262014008438303/27/14Methods of forming 3-d semiconductor devices using a replacement gate technique and a novel 3-d device
1272014007727403/20/14Integrated circuits with improved gate uniformity and methods for fabricating same
1282014007736803/20/14Repairing anomalous stiff pillar bumps
1292014007738003/20/14Bit cell with double patterned metal layer structures
1302014007881703/20/14Integrated circuits with sram cells having additional read stacks and methods for their fabrication
1312014007727403/20/14Integrated circuits with improved gate uniformity and methods for fabricating same
1322014007736803/20/14Repairing anomalous stiff pillar bumps
1332014007738003/20/14Bit cell with double patterned metal layer structures
1342014007881703/20/14Integrated circuits with sram cells having additional read stacks and methods for their fabrication
1352014007028303/13/14Field effect transistor and method of fabrication
1362014007028503/13/14Methods of forming semiconductor devices with self-aligned contacts and the resulting devices
1372014007032103/13/14Integrated circuits having boron-doped silicon germanium channels and methods for fabricating the same
1382014007032203/13/14Methods of forming different finfet devices with different threshold voltages and integrated circuit products containing such devices
1392014007035803/13/14Method of tailoring silicon trench profile for super steep retrograde well field effect transistor
1402014007040503/13/14Stacked semiconductor devices with a glass window wafer having an engineered coefficient of thermal expansion and methods of making same
1412014007028303/13/14Field effect transistor and method of fabrication
1422014007028503/13/14Methods of forming semiconductor devices with self-aligned contacts and the resulting devices
1432014007032103/13/14Integrated circuits having boron-doped silicon germanium channels and methods for fabricating the same
1442014007032203/13/14Methods of forming different finfet devices with different threshold voltages and integrated circuit products containing such devices
1452014007035803/13/14Method of tailoring silicon trench profile for super steep retrograde well field effect transistor
1462014007040503/13/14Stacked semiconductor devices with a glass window wafer having an engineered coefficient of thermal expansion and methods of making same
1472014006173203/06/14Method and device to achieve self-stop and precise gate height
1482014006181203/06/14Semiconductor device incorporating a multi-function layer into gate stacks
1492014006192503/06/14Low resistivity gate conductor
1502014006573403/06/14Method and system for determining overlap process windows in semiconductors by inspection techniques
1512014006580803/06/14Method of forming a material layer in a semiconductor structure
1522014006581103/06/14Replacement metal gate semiconductor device formation using low resistivity metals
1532014006581503/06/14Beol integration scheme for copper cmp to prevent dendrite formation
1542014006854303/06/14Method to enhance double patterning routing efficiency
1552014006582803/06/14Selective fin cut process
1562014006173203/06/14Method and device to achieve self-stop and precise gate height
1572014006181203/06/14Semiconductor device incorporating a multi-function layer into gate stacks
1582014006192503/06/14Low resistivity gate conductor
1592014006573403/06/14Method and system for determining overlap process windows in semiconductors by inspection techniques
1602014006580803/06/14Method of forming a material layer in a semiconductor structure
1612014006581103/06/14Replacement metal gate semiconductor device formation using low resistivity metals
1622014006581503/06/14Beol integration scheme for copper cmp to prevent dendrite formation
1632014006854303/06/14Method to enhance double patterning routing efficiency
1642014006582803/06/14Selective fin cut process
1652014005464902/27/14Semiconductor devices and methods of forming the semiconductor devices including a retrograde well
1662014005472302/27/14Isolation structures for finfet semiconductor devices
1672014005708902/27/14Hardmask layer with alternating nanolayers
1682014005709902/27/14Hardmask capping layer
1692014005741502/27/14Methods of forming a layer of silicon on a layer of silicon/germanium
1702014005743502/27/14Methods of forming a metal cap layer on copper-based conductive structures on an integrated circuit device
1712014005950602/27/14Method and apparatus for applying post graphic data system stream enhancements
1722014004891202/20/14Compressive stress transfer in an interlayer dielectric of a semiconductor device by providing a bi-layer of superior adhesion and internal stress
1732014005001702/20/14Device comprising a plurality of static random access memory cells and method of operation thereof
1742014005003302/20/14Memory cell assembly including an avoid disturb cell
1752014005122702/20/14Methods of forming isolation structures for semiconductor devices by performing a dry chemical removal process
1762014005123302/20/14Methods of thinning and/or dicing semiconducting substrates having integrated circuit products formed thereon
1772014005124002/20/14Methods of forming a replacement gate structure having a gate electrode comprised of a deposited intermetallic compound material
1782014004251002/13/14Capacitors positioned at the device level in an integrated circuit product and methods of making such capacitors
1792014004254902/13/14Methods of forming stress-inducing layers on semiconductor devices
1802014004255002/13/14Integrated circuits with improved spacers and methods for fabricating same
1812014004255102/13/14Sram integrated circuits with buried saddle-shaped finfet and methods for their fabrication
1822014004264102/13/14Middle-of-the-line constructs using diffusion contact structures
1832014004306102/13/14Computing multi-magnet based devices and methods for solution of optimization problems
1842014004488902/13/14Methods of making stressed material layers and a system for forming such layers
1852014004533002/13/14Methods of in-situ vapor phase deposition of self-assembled monolayers as copper adhesion promoters and diffusion barriers
1862014004647402/13/14Waferstart processes and systems for integrated circuit fabrication
1872014003501002/06/14Integrated circuit having a replacement gate structure and method for fabricating the same
1882014003509902/06/14Integrated circuits with metal-insulator-metal (mim) capacitors and methods for fabricating same
1892014003515102/06/14Integrated circuits and methods for fabricating integrated circuits using double patterning processes
1902014003808902/06/14Self-polarized mask and self-polarized mask application
1912014003840202/06/14Dual work function finfet structures and methods for fabricating the same
1922014003841202/06/14Interconnect formation using a sidewall mask layer
1932014002667501/30/14Detecting anomalous stiff pillar bumps formed above a metallization system
1942014002667601/30/14Detecting anomalous weak beol sites in a metallization system
1952014002782501/30/14Threshold voltage adjustment in a fin transistor by corner implantation
1962014002785901/30/14Methods of forming transistor devices with high-k insulation layers and the resulting devices
1972014002790201/30/14Repairing anomalous stiff pillar bumps
1982014002791001/30/14Method for reducing wettability of interconnect material at corner interface and device incorporating same
1992014002791801/30/14Cross-coupling based design using diffusion contact structures
2002014003063701/30/14Reticles for use in forming implant masking layers and methods of forming implant masking layers
2012014003087601/30/14Methods for fabricating high carrier mobility finfet structures
2022014002160401/23/14Integrated circuit devices with bump structures that include a protection layer
2032014002161301/23/14Multi-layer barrier layer for interconnect structure
2042014002421201/23/14Multi-layer barrier layer for interconnect structure
2052014002421301/23/14Processes for forming integrated circuits with post-patterning treament
2062014002157901/23/14Integrated circuit with a fin-based fuse, and related fabrication method
2072014001501501/16/14Finfet device with a graphene gate electrode and methods of forming same
2082014001505501/16/14Finfet structures and methods for fabricating the same
2092014001506001/16/14Stress enhanced cmos circuits and methods for their manufacture
2102014001790301/16/14Methods for fabricating integrated circuits with stressed semiconductor material
2112014000872001/09/14Integrated circuit and method for fabricating the same having a replacement gate structure
2122014001130201/09/14Spacer for a gate electrode having tensile stress and a method of forming the same
2132014001134101/09/14Methods of forming finfet devices with alternative channel materials
2142014000156301/02/14Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making same
2152014000469201/02/14Finfet structure with multiple workfunctions and method for fabricating the same
2162014000469301/02/14Methods for fabricating integrated circuits having improved metal gate structures
2172014000657001/02/14Method and system for customer specific test system allocation in a production environment
2182013034172212/26/13Ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating same
2192013034172312/26/13Memory cell with asymmetric read port transistors
2202013034384412/26/13Overhead substrate handling and storage system
2212013034466912/26/13Methods for fabricating integrated circuits with drift regions and replacement gates
2222013034467312/26/13Semiconductor device fabrication methods
2232013034469212/26/13Methods for fabricating integrated circuits with fluorine passivation
2242013033453212/19/13Stress gauge comprised of a piezoelectric material for use with integrated circuit products
2252013032811212/12/13Semiconductor devices having improved gate height uniformity and methods for fabricating same
2262013033090012/12/13Methods of tailoring work function of semiconductor devices with high-k/metal layer gate structures by performing a fluorine implant process
2272013033090712/12/13Methods of forming semiconductor devices by forming semiconductor channel region materials prior to forming isolation structures
2282013033091612/12/13Methods of forming high mobility fin channels on three dimensional semiconductor devices
2292013033213612/12/13Modeling memory cell skew sensitivity
2302013032811212/12/13Semiconductor devices having improved gate height uniformity and methods for fabricating same
2312013033090012/12/13Methods of tailoring work function of semiconductor devices with high-k/metal layer gate structures by performing a fluorine implant process
2322013033090712/12/13Methods of forming semiconductor devices by forming semiconductor channel region materials prior to forming isolation structures
2332013033091612/12/13Methods of forming high mobility fin channels on three dimensional semiconductor devices
2342013033213612/12/13Modeling memory cell skew sensitivity
2352013032040912/05/13Source and drain architecture in an active region of a p-channel transistor by tilted implantation
2362013032041512/05/13Full silicidation prevention via dual nickel deposition approach
2372013032389212/05/13Methods of performing highly tilted halo implantation processes on semiconductor devices
2382013032392312/05/13Methods for fabricating integrated circuits having improved spacers
2392013031355311/28/13Semiconductor fuse with enhanced post-programming resistance
2402013031357211/28/13Semiconductor device with strain-inducing regions and method thereof
2412013031651111/28/13Superior stability of characteristics of transistors having an early formed high-k metal gate
2422013030696711/21/13Adjusting configuration of a multiple gate transistor by controlling individual fins
2432013030703211/21/13Methods of forming conductive contacts for a semiconductor device
2442013030709011/21/13Adjusting of strain caused in a transistor channel by semiconductor material provided for the threshold adjustment
2452013030711211/21/13Substrate diode formed by angled ion implantation processes
2462013030711411/21/13Semiconductor device comprising metal-based efuses of enhanced programming efficiency by enhancing metal agglomeration and/or voiding
2472013030984611/21/13Methods of forming a silicon seed layer and layers of silicon and silicon-containing material therefrom
2482013030984711/21/13Methods of forming finfet devices with alternative channel materials
2492013030986811/21/13Methods for forming an integrated circuit with straightened recess profile


ARCHIVE: New 2014 2013 2012 2011 2010 2009



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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Globalfoundries, Inc. in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Globalfoundries, Inc. with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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