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Recent patent applications related to Globalfoundries, Inc.. Globalfoundries, Inc. is listed as an Agent/Assignee. Note: Globalfoundries, Inc. may have other listings under different names/spellings. We're not affiliated with Globalfoundries, Inc., we're just tracking patents.

ARCHIVE: New 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries, Inc.-related inventors



Methods of forming isolation regions for bulk finfet semiconductor devices

Globalfoundries

Methods of forming isolation regions for bulk finfet semiconductor devices

Search recent Press Releases: Globalfoundries, Inc.-related press releases
Count Application # Date Globalfoundries, Inc. patents (updated weekly) - BOOKMARK this page
12014031243410/23/14 new patent  Finfet device with a graphene gate electrode and methods of forming same
22014031537110/23/14 new patent  Methods of forming isolation regions for bulk finfet semiconductor devices
32014030631710/16/14Finfet fin height control
42014030810810/16/14System for separately handling different size foups
52014029994110/09/14Sram cell with reduced voltage droop
62014030266010/09/14Local interconnect to a protection diode
72014029184710/02/14Methods of forming a barrier system containing an alloy of metals introduced into the barrier system, and an integrated circuit product containing such a barrier system
82014029566410/02/14Methods of forming masking layers for use in forming integrated circuit products
92014028969509/25/14Evaluation of pin geometry accessibility in a layer of circuit
102014026438609/18/14Performance enhancement in pmos and nmos transistors on the basis of silicon/carbon material
112014026434209/18/14Semiconductor device including a resistor and method for the formation thereof
122014026434709/18/14Transistor with embedded strain-inducing material formed in cavities based on an amorphization process and a heat treatment
132014026434909/18/14Low thermal budget schemes in semiconductor device fabrication
142014026446109/18/14Metal layer enabling directed self-assembly semiconductor layout designs
152014026447909/18/14Methods of increasing space for contact elements by using a sacrificial liner and the resulting device
162014026448609/18/14Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
172014026448709/18/14Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
182014026448909/18/14Wrap around stressor formation
192014026461709/18/14Hk/mg process flows for p-type semiconductor devices
202014026462609/18/14Method for forming a gate electrode of a semiconductor device, gate electrode structure for a semiconductor device and according semiconductor device structure
212014026463109/18/14Methods of forming alignment marks and overlay marks on integrated circuit products employing finfet devices and the resulting alignment/overlay mark
222014026463209/18/14Semiconductor structure including a transistor having a layer of a stress-creating material and method for the formation thereof
232014026464109/18/14Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layers
242014026473109/18/14Programmable e-fuse for an integrated circuit product
252014026475809/18/14Methods of forming a protection layer to protect a metal hard mask layer during lithography reworking processes
262014026487609/18/14Multi-layer barrier layer stacks for interconnect structures
272014026487709/18/14Metallization systems of semiconductor devices comprising a copper/silicon compound as a barrier material
282014026489009/18/14Novel pillar structure for use in packaging integrated circuit products and methods of making such a pillar structure
292014027336509/18/14Methods of forming contacts to source/drain regions of finfet devices by forming a region that includes a schottky barrier lowering material
302014027336909/18/14Methods of forming contacts to source/drain regions of finfet devices
312014027338909/18/14Semiconductor device having controlled final metal critical dimension
322014027339609/18/14Method of forming a semiconductor structure including a metal-insulator-metal capacitor
332014027342309/18/14Methods of forming a semiconductor device with a nanowire channel structure by performing an anneal process
342014027342909/18/14Methods of forming finfet devices with a shared gate structure
352014027343609/18/14Methods of forming barrier layers for conductive copper structures
362014027345509/18/14Hard mask removal during finfet formation
372014027347309/18/14Methods of forming a masking layer for patterning underlying structures
382014027347409/18/14Interconnection designs using sidewall image transfer (sit)
392014028229609/18/14Hybrid method for performing full field optical proximity correction for finfet mandrel layer
402014028230109/18/14Stitch insertion for reducing color density differences in double patterning technology (dpt)
412014028230309/18/14Pattern-independent and hybrid matching/tuning including light manipulation by projection optics
422014028230709/18/14Method and apparatus for providing metric relating two or more process parameters to yield
432014028232309/18/14Parameterized cell for planar and finfet technology design
442014028233009/18/14Priority based layout versus schematic (lvs)
452014028234509/18/14Via insertion in integrated circuit (ic) designs
462014026461309/18/14Integrated circuits and methods for fabricating integrated circuits with active area protection
472014026463309/18/14Finfet devices having a body contact and methods of forming the same
482014026898309/18/14Otprom array with leakage current cancelation for enhanced efuse sensing
492014026906009/18/14Integrated circuits and methods for operating integrated circuits with non-volatile memory
502014027267709/18/14Methods for fabricating euv masks and methods for fabricating integrated circuits using such euv masks
512014027329909/18/14Systems and methods for fabricating semiconductor device structures using different metrology tools
522014027330609/18/14Methods for fabricating integrated circuits including multi-patterning of masks for extreme ultraviolet lithography
532014027336709/18/14Integrated circuits and methods for fabricating integrated circuits with gate electrode structure protection
542014027337509/18/14Methods for fabricating integrated circuits with semiconductor substrate protection
552014027346309/18/14Methods for fabricating integrated circuits that include a sealed sidewall in a porous low-k dielectric layer
562014027347509/18/14Methods for fabricating guide patterns and methods for fabricating integrated circuits using such guide patterns
572014027351109/18/14Methods for fabricating integrated circuits including formation of chemical guide patterns for directed self-assembly lithography
582014027766809/18/14Methods and systems for fabricating integrated circuits utilizing universal and local processing management
592014025242409/11/14Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
602014025242509/11/14Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
612014025242909/11/14Contact geometry having a gate silicon length decoupled from a transistor length
622014025248009/11/14Combination finfet and planar fet semiconductor device and methods of making such a device
632014025248109/11/14Transistor including a gate electrode extending all around one or more channel regions
642014025255709/11/14Method for forming a semiconductor device and semiconductor device structures
652014025261709/11/14Barrier layer conformality in copper interconnects
662014025266009/11/14Multilayer pattern transfer for chemical guides
672014025390209/11/14Multiple patterning process for forming trenches or holes using stitched assist features
682014025401809/11/14Scattering enhanced thin absorber for euv reflective reticle and a method of making
692014025606409/11/14Methods of repairing damaged insulating materials by introducing carbon into the layer of insulating material
702014025609709/11/14Methods for forming integrated circuit systems employing fluorine doping
712014025613509/11/14Methods of removing gate cap layers in cmos applications
722014025613709/11/14Method of forming a semiconductor structure including an implantation of ions into a layer of spacer material
732014025773809/11/14Hierarchically divided signal path for characterizing integrated circuits
742014025896009/11/14Integrating optimal planar and three-dimensional semiconductor design layouts
752014025614109/11/14Methods for fabricating integrated circuits utilizing silicon nitride layers
762014024669609/04/14Transistor with embedded strain-inducing material formed in cavities formed in a silicon/germanium substrate
772014024669809/04/14Channel sige removal from pfet source/drain region for improved silicide formation in hkmg technologies without embedded sige
782014024673409/04/14Replacement metal gate with mulitiple titanium nitride laters
792014024673509/04/14Metal gate structure for semiconductor devices
802014024677509/04/14Methods of forming non-continuous conductive layers for conductive structures on an integrated circuit product
812014024679109/04/1414 lpm contact power rail
822014024743809/04/14Reticle defect correction by second exposure
832014024874909/04/14Stress memorization technique
842014024876409/04/14Methods of forming structures on an integrated circuit product
852014024877009/04/14Microwave-assisted heating of strong acid solution to remove nickel platinum/platinum residues
862014024877809/04/14Methods of forming asymmetric spacers on various structures on integrated circuit products
872014024660509/04/14Defect removal process
882014023804508/28/14Semiconductor device comprising a stacked die configuration including an integrated peltier element
892014024278808/28/14Method of forming a high quality interfacial layer for a semiconductor device by performing a low temperature ald process
902014024523808/28/14Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications
912014023950308/28/14Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
922014023124508/21/14Adjustable current shield for electroplating processes
932014023190708/21/14Methods of inducing a desired stress in the channel region of a transistor by performing ion implantation/anneal processes on the gate electrode
942014023196008/21/14Polysilicon resistor formation
952014023243308/21/14Circuit element including a layer of a stress-creating material providing a variable stress and method for the formation thereof
962014023301408/21/14Infrared-based metrology for detection of stress and defects around through silicon vias
972014023188508/21/14Integrated circuits and methods for fabricating integrated circuits having metal gate electrodes
982014023192208/21/14Semiconductor gate structure for threshold voltage modulation and method of making same
992014023201008/21/14Integrated circuits and methods of forming the same with multi-level electrical connection
1002014023505508/21/14Method for fabricating a semiconductor integrated circuit with a litho-etch, litho-etch process for etching trenches
1012014022476408/14/14Chemical and physical templates for forming patterns using directed self-assembly materials
1022014022516808/14/14Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device
1032014022520108/14/14Edge and strap cell design for sram array
1042014022527008/14/14Method for off-grid routing structures utilizing self aligned double patterning (sadp) technology
1052014022784508/14/14Methods of forming multiple n-type semiconductor devices with different threshold voltages on a semiconductor substrate
1062014022784908/14/14Methods of trimming nanowire structures
1072014022785808/14/14Shallow trench isolation integration methods and devices formed thereby
1082014022786908/14/14Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions
1092014022787208/14/14Methods of forming conductive structures using a sacrificial liner layer
1102014022787908/14/14Methods for fabricating integrated circuits with improved semiconductor fin structures
1112014021746708/07/14Methods of forming substrates comprised of different semiconductor materials and the resulting device
1122014021748008/07/14Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer
1132014021754408/07/14Methods of forming a transistor device on a bulk substrate and the resulting device
1142014021758808/07/14Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device
1152014021759108/07/14Multi-layer barrier layer for interconnect structure
1162014022075608/07/14Methods of forming semiconductor devices by forming a semiconductor layer above source/drain regions prior to removing a gate cap layer
1172014022075908/07/14Methods for fabricating integrated circuits having gate to active and gate to gate interconnects
1182014022076708/07/14Double-pattern gate formation processing with critical dimension control
1192014022339008/07/14Retargeting semiconductor device shapes for multiple patterning processes
1202014022339208/07/14Optimized optical proximity correction handling for lithographic fills
1212014021748208/07/14Integrated circuits having replacement gate structures and methods for fabricating the same
1222014021751708/07/14Integrated circuits including finfet devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
1232014022077508/07/14Methods for fabricating integrated circuits having embedded electrical interconnects
1242014022078608/07/14Methods for optical proximity correction in the design and fabrication of integrated circuits
1252014021008807/31/14Method for reducing wettability of interconnect material at corner interface and device incorporating same
1262014021117507/31/14Enhancing resolution in lithographic processes using high refractive index fluids
1272014021541507/31/14Automated design layout pattern correction based on context-aware patterns
1282014020956307/31/14Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein
1292014021303307/31/14Methods for fabricating electrically-isolated finfet semiconductor devices
1302014021303707/31/14Methods for fabricating integrated circuits having confined epitaxial growth regions
1312014020328007/24/14Electrical test structure for devices employing high-k dielectrics or metal gates
1322014020329807/24/14Strained silicon carbide channel for electron mobility of nmos
1332014020333907/24/14Semiconductor device comprising self-aligned contact elements and a replacement gate electrode structure
1342014020337607/24/14Finfet integrated circuits with uniform fin height and methods for fabricating the same
1352014020340507/24/14Method to dynamically tune precision resistance
1362014020344607/24/14Through silicon via device having low stress, thin film gaps and methods for forming the same
1372014020381407/24/14Method and apparatus for measuring alpha particle induced soft errors in semiconductor devices
1382014020615707/24/14Method of forming a semiconductor structure including a vertical nanowire
1392014020828507/24/14Self-aligned double patterning via enclosure design
1402014020327907/24/14Test structure and method to faciltiate development/optimization of process parameters
1412014020344907/24/14Integrated circuits and methods of forming the same with metal layer connection to through-semiconductor via
1422014020382707/24/14Integrated circuits and methods of forming the same with embedded interconnect connection to through-semiconductor via
1432014019746807/17/14Methods of forming semiconductor device with self-aligned contact elements and the resulting device
1442014019754407/17/14Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials
1452014019749807/17/14Integrated circuits and methods for fabricating integrated circuits with improved silicide contacts
1462014019984507/17/14Selective removal of gate structure sidewall(s) to facilitate sidewall spacer protection
1472014019132407/10/14Methods of forming bulk finfet devices by performing a recessing process on liner materials to define different fin heights and finfet devices with such recessed liner materials
1482014019133207/10/14Pfet devices with different structures and performance characteristics
1492014019395707/10/14Reducing gate height variance during semiconductor device formation
1502014018355107/03/14Blanket epi super steep retrograde well formation without si recess
1512014018363807/03/14Methods of using a trench salicide routing layer
1522014018372007/03/14Methods of manufacturing integrated circuits having a compressive nitride layer
1532014018503007/03/14Asymmetric reticle heating of multilayer reticles eliminated by dummy exposures and related methods
1542014018703607/03/14Integration of ru wet etch and cmp for beol interconnects with ru layer
1552014018374507/03/14Gate electrode(s) and contact structure(s), and methods of fabrication thereof
1562014017553906/26/14Canyon gate transistor and methods for its fabrication
1572014017816006/26/14Overhead substrate handling and storage system
1582014017882406/26/14Optimizing lithographic processes using laser annealing techniques
1592014017556206/26/14Spacer divot sealing method and semiconductor device incorporating same
1602014017909306/26/14Gate structure formation processes
1612014016711906/19/14Methods of forming a sidewall spacer having a generally triangular shape and a semiconductor device having such a spacer
1622014016712006/19/14Methods of forming a finfet semiconductor device by performing an epitaxial growth process
1632014016726406/19/14Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structures
1642014016726506/19/14Methods of forming a bi-layer cap layer on copper-based conductive structures and devices with such a cap layer
1652014017053306/19/14Extreme ultraviolet lithography (euvl) alternating phase shift mask
1662014017083906/19/14Methods of forming fins for a finfet device wherein the fins have a high germanium content
1672014017353306/19/14Locally optimized coloring for cleaning lithographic hotspots
1682014015905206/12/14Method and structure for transistor with reduced drain-induced barrier lowering and on resistance
1692014015912506/12/14Contact landing pads for a semiconductor device and methods of making same
1702014015912606/12/14Methods of forming a finfet semiconductor device with undoped fins
1712014015916406/12/14Double sidewall image transfer process
1722014015917106/12/14Methods of forming bulk finfet semiconductor devices by performing a liner recessing process to define fin heights and finfet devices with such a recessed liner
1732014015919906/12/14High density serial capacitor device and methods of making such a capacitor device
1742014016217606/12/14Semiconductor device resolution enhancement by etching multiple sides of a mask
1752014016244706/12/14Finfet hybrid full metal gate with borderless contacts
1762014015176006/05/14Doped flowable pre-metal dielectric
1772014015180706/05/14Combination finfet and planar fet semiconductor device and methods of making such a device
1782014015181606/05/14Novel contact structure for a semiconductor device and methods of making same
1792014015181806/05/14Semiconductor device with a silicon dioxide gate insulation layer implanted with a rare earth element and methods of making such a device
1802014014525705/29/14Semiconductor device having a metal recess
1812014014527405/29/14Methods of forming replacement gate structures for nfet semiconductor devices and devices having such gate structures
1822014014533205/29/14Methods of forming graphene liners and/or cap layers on copper-based conductive structures
1832014014801105/29/14Method of forming semiconductor fins
1842014014995205/29/14Trench silicide mask generation using designated trench transfer and trench block regions
1852014014160505/22/14Finfet formation using double patterning memorization
1862014013877905/22/14Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance
1872014014160505/22/14Finfet formation using double patterning memorization
1882014013877905/22/14Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance
1892014013173505/15/14Source and drain doping using doped raised source and drain regions
1902014013177105/15/14Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof
1912014013180505/15/14Transistor with embedded si/ge material having reduced offset and superior uniformity
1922014013188105/15/14Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection
1932014013183105/15/14Integrated ciruit including an fin-based diode and methods of its fabrication
1942014013481405/15/14Methods of manufacturing integrated circuits having finfet structures with epitaxially formed source/drain regions
1952014013482205/15/14Methods for fabricating integrated circuits including semiconductive resistor structures in a finfet architecture
1962014013173505/15/14Source and drain doping using doped raised source and drain regions
1972014013177105/15/14Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof
1982014013180505/15/14Transistor with embedded si/ge material having reduced offset and superior uniformity
1992014013188105/15/14Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection
2002014013183105/15/14Integrated ciruit including an fin-based diode and methods of its fabrication
2012014013481405/15/14Methods of manufacturing integrated circuits having finfet structures with epitaxially formed source/drain regions
2022014013482205/15/14Methods for fabricating integrated circuits including semiconductive resistor structures in a finfet architecture
2032014012479405/08/14Fabrication of reverse shallow trench isolation structures with super-steep retrograde wells
2042014012484105/08/14Methods of forming replacement gate structures on semiconductor devices and the resulting device
2052014012999905/08/14Method for selectively modeling narrow-width stacked device performance
2062014012479405/08/14Fabrication of reverse shallow trench isolation structures with super-steep retrograde wells
2072014012484105/08/14Methods of forming replacement gate structures on semiconductor devices and the resulting device
2082014012999905/08/14Method for selectively modeling narrow-width stacked device performance
2092014011741705/01/14Performance enhancement in transistors by providing a graded embedded strain-inducing semiconductor region with adapted angles with respect to the substrate surface
2102014011741805/01/14Three-dimensional silicon-based transistor comprising a high-mobility channel formed by non-masked epitaxy
2112014011741905/01/14Fin etch and fin replacement for finfet integration
2122014011750705/01/14Double trench well formation in sram cells
2132014012067705/01/14Methods of forming enhanced mobility channel regions on 3d semiconductor devices, and devices comprising same
2142014011741705/01/14Performance enhancement in transistors by providing a graded embedded strain-inducing semiconductor region with adapted angles with respect to the substrate surface
2152014011741805/01/14Three-dimensional silicon-based transistor comprising a high-mobility channel formed by non-masked epitaxy
2162014011741905/01/14Fin etch and fin replacement for finfet integration
2172014011750705/01/14Double trench well formation in sram cells
2182014012067705/01/14Methods of forming enhanced mobility channel regions on 3d semiconductor devices, and devices comprising same
2192014011079804/24/14Methods of forming a semiconductor device with low-k spacers and the resulting device
2202014011085404/24/14Semiconductor dies with reduced area consumption
2212014011341904/24/14Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material
2222014011342004/24/14Methods of avoiding shadowing when forming source/drain implant regions on 3d semiconductor devices
2232014011345504/24/14Method of forming a semiconductor structure including a wet etch process for removing silicon nitride
2242014011077204/24/14Integrated circuit decoupling capacitor arrangement
2252014011079404/24/14Facilitating gate height uniformity and inter-layer dielectric protection
2262014011079804/24/14Methods of forming a semiconductor device with low-k spacers and the resulting device
2272014011085404/24/14Semiconductor dies with reduced area consumption
2282014011341904/24/14Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material
2292014011342004/24/14Methods of avoiding shadowing when forming source/drain implant regions on 3d semiconductor devices
2302014011345504/24/14Method of forming a semiconductor structure including a wet etch process for removing silicon nitride
2312014011077204/24/14Integrated circuit decoupling capacitor arrangement
2322014011079404/24/14Facilitating gate height uniformity and inter-layer dielectric protection
2332014010342004/17/14Advanced faraday shield for a semiconductor device
2342014010657504/17/14Directed self-assembly of block copolymers using laser annealing
2352014010342004/17/14Advanced faraday shield for a semiconductor device
2362014010657504/17/14Directed self-assembly of block copolymers using laser annealing
2372014009753804/10/14Semiconductor device having a self-forming barrier layer at via bottom
2382014009789204/10/14Double patterning compatible colorless m1 route
2392014010080604/10/14Method and apparatus for matching tools based on time trace data
2402014009845904/10/14Capacitor and contact structures, and formation processes thereof
2412014009753804/10/14Semiconductor device having a self-forming barrier layer at via bottom
2422014009789204/10/14Double patterning compatible colorless m1 route
2432014010080604/10/14Method and apparatus for matching tools based on time trace data
2442014009845904/10/14Capacitor and contact structures, and formation processes thereof
2452014009753804/10/14Semiconductor device having a self-forming barrier layer at via bottom
2462014009789204/10/14Double patterning compatible colorless m1 route
2472014010080604/10/14Method and apparatus for matching tools based on time trace data
2482014009845904/10/14Capacitor and contact structures, and formation processes thereof
2492014008438303/27/14Methods of forming 3-d semiconductor devices using a replacement gate technique and a novel 3-d device


ARCHIVE: New 2014 2013 2012 2011 2010 2009



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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Globalfoundries, Inc. in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Globalfoundries, Inc. with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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