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Globalfoundries Inc patents

Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors




Date Globalfoundries Inc patents (updated weekly) - BOOKMARK this page
05/25/17 new patent  On-chip sensor for monitoring active circuits on integrated circuit (ic) chips
05/25/17 new patent  Modeling localized temperature changes on an integrated circuit chip using thermal potential theory
05/25/17 new patent  Temperature-aware integrated circuit design methods and systems
05/25/17 new patent  Zig-zag trench structure to prevent aspect ratio trapping defect escape
05/25/17 new patent  Hdp fill with reduced void formation and spacer damage
05/25/17 new patent  Method, apparatus, and system for mol interconnects without titanium liner
05/25/17 new patent  Method and structure for establishing interconnects in packages using thin interposers
05/25/17 new patent  Extrusion-resistant solder interconnect structures and methods of forming
05/25/17 new patent  Memory device structure
05/25/17 new patent  Replacement low-k spacer
05/25/17 new patent  Semiconductor circuit element
05/25/17 new patent  Poc process flow for conformal recess fill
05/18/17Additions of organic species to facilitate crosslinker removal during pspi cure
05/18/17Methods, apparatus, and systems for minimizing defectivity in top-coat-free lithography and improving reticle cd uniformity
05/18/17Multi-frequency inductors with low-k dielectric area
05/18/17Self-aligned conductive polymer pattern placement error compensation layer
05/18/17Gate structure cut after formation of epitaxial active regions
05/18/17Conductively doped polymer pattern placement error compensation layer
05/18/17Semiconductor fuses with nanowire fuse links and fabrication methods thereof
05/18/17Pattern placement error compensation layer
05/18/17Pattern placement error compensation layer in via opening
05/18/17Special construct for continuous non-uniform active region finfet standard cells
05/18/17Dummy gate used as interconnection and making the same
05/18/17Single and double diffusion breaks on integrated circuit products comprised of finfet devices
05/18/17Method, apparatus and system for improved performance using tall fins in finfet devices
05/18/17Methods of forming pmos and nmos finfet devices on cmos based integrated circuit products
05/18/17Methods of forming pmos finfet devices and multiple nmos finfet devices with different performance characteristics
05/18/17Interconnect structure including middle of line (mol) metal layer local interconnect on etch stop layer
05/18/17Mosfet with asymmetric self-aligned contact
05/18/17Mosfet with asymmetric self-aligned contact
05/11/17Barrier structures for underfill blockout regions
05/11/17Chamferless via structures
05/11/17Alternative threshold voltage scheme via direct metal gate patterning for high performance cmos finfets
05/11/17Test structures and forming an according test structure
05/11/17Method, apparatus, and system for e-fuse in advanced cmos technologies
05/11/17Methods of self-forming barrier formation in metal interconnection applications
05/11/17Method, apparatus, and system for stacked cmos logic circuits on fins
05/11/17Reducing thermal runaway in inverter devices
05/11/17Advanced mosfet contact structure to reduce metal-semiconductor interface resistance
05/04/17In-situ contactless monitoring of photomask pellicle degradation
05/04/17Etch stop for airgap protection
05/04/17Anisotropic material damage process for etching low-k dielectric materials
05/04/17Trench silicide contacts with high selectivity process
05/04/17Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices
05/04/17Semiconductor structure with anti-efuse device
05/04/17Antenna diode circuit for manufacturing of semiconductor devices
05/04/17Trench silicide contacts with high selectivity process
05/04/17Semiconductor device with a memory device and a high-k metal gate transistor
05/04/17Metal resistor forming method using ion implantation
05/04/17Method of forming a gate contact structure for a semiconductor device
05/04/17Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts
05/04/17Etch stop for airgap protection
05/04/17Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices
05/04/17Trench silicide contacts with high selectivity process
05/04/17Fin field effect transistor complementary metal oxide semiconductor with dual strained channels with solid phase doping
05/04/17Fin field effect transistor complementary metal oxide semiconductor with dual strained channels with solid phase doping
05/04/17Stress memorization techniques for transistor devices
05/04/17Semiconductor structure including a varactor
04/27/17Wafer level electrical test for optical proximity correction and/or etch bias
04/27/17Use of multivariate models to control manufacturing operations
04/27/17Method including a formation of a diffusion barrier and semiconductor structure including a diffusion barrier
04/27/17Unmerged epitaxial process for finfet devices with aggressive fin pitch scaling
04/27/17Unmerged epitaxial process for finfet devices with aggressive fin pitch scaling
04/27/17Method of forming a memory device structure and memory device structure
04/27/17Buffer layer for modulating vt across devices
Patent Packs
04/27/17Finfet devices having fins with a tapered configuration and methods of fabricating the same
04/20/17Auto test grouping/clock sequencing for at-speed test
04/20/17Built-in self-test (bist) circuit and associated bist embedded memories
04/20/17Structures with thinned dielectric material
04/20/17Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor
04/20/17Semiconductor device with a gate contact positioned above the active region
04/20/17High doped iii-v source/drain junctions for field effect transistors
04/13/17Forming replacement low-k spacer in tight pitch fin field effect transistors
04/13/17Contacting soi substrates
04/13/17Co-fabricated bulk devices and semiconductor-on-insulator devices
04/13/17Forming replacement low-k spacer in tight pitch fin field effect transistors
04/13/17Forming stressed epitaxial layer using dummy gates
04/06/17Methods of error detection in fabrication processes
04/06/17Methods of error detection in fabrication processes
04/06/17Amophization induced metal-silicon contact formation
Patent Packs
04/06/17Source/drain epitaxial electrical monitor
04/06/17Ic structure with angled interconnect elements
04/06/17Implementing stress in a bipolar junction transistor
03/30/17Programmable devices with current-facilitated migration and fabrication methods
03/30/17Programmable via devices with metal/semiconductor via links and fabrication methods thereof
03/30/17Self-aligned gate tie-down contacts with selective etch stop liner
03/30/17Three-dimensional semiconductor transistor with gate contact in active region
03/30/17Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme
03/30/17Field effect transistor device spacers
03/30/17Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme
03/23/17Dual liner silicide
03/23/17Three-dimensional scatterometry for measuring dielectric thickness
03/23/17Integrated circuit chip design methods and systems using process window-aware timing analysis
03/23/173d multipath inductor
03/23/17Method including an adjustment of a plurality of wafer handling elements, system including a plurality of wafer handling elements and photolithography track
03/23/17Semiconductor device with reduced poly spacing effect
03/23/17Fin structures and multi-vt scheme based on tapered fin and method to form
03/23/17Dual metal-insulator-semiconductor contact structure and formulation method
03/23/17Stacked nanowire device width adjustment by gas cluster ion beam (gcib)
03/23/17Poc process flow for conformal recess fill
03/23/17Stacked nanowire device width adjustment by gas cluster ion beam (gcib)
03/16/17Method, apparatus and system for using hybrid library track design for soi technology
03/16/17Removal of semiconductor growth defects
03/16/17Hdp fill with reduced void formation and spacer damage
03/16/17Asymmetric semiconductor device and forming same
03/16/17Spacer chamfering gate stack scheme
03/16/17Devices and methods of creating elastic relaxation of epitaxially grown lattice mismatched films
03/16/17Methods of forming semiconductor device with self-aligned contact elements and the resulting device
03/16/17Preventing leakage inside air-gap spacer during contact formation
03/16/17Spacer chamfering gate stack scheme
Social Network Patent Pack
03/16/17Semiconductor device with gate inside u-shaped channel and methods of making such a device
03/16/17Methods of making source/drain regions positioned inside u-shaped semiconductor material using source/drain placeholder structures
03/16/17Vertical slit transistor with optimized ac performance
03/16/17Wafer with soi structure having a buried insulating multilayer structure and semiconductor device structure
03/16/17Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins
03/09/17Detection of gate-to-source/drain shorts
03/09/17Electrostatic substrate holder with non-planar surface and etching
03/09/17Methods of forming cmos based integrated circuit products using disposable spacers
03/09/17Method of forming a semiconductor device
03/09/17Forming reliable contacts on tight semiconductor pitch
Patent Packs
03/09/17Three-dimensional finfet transistor with portion(s) of the fin channel removed in gate-last flow
03/02/17Hard mask etch and dielectric etch aware overlap for via and metal layers
03/02/17Reliability of an electronic device
03/02/17Raised e-fuse
03/02/17Integrated circuit structure with metal crack stop and methods of forming same
03/02/17Integrated circuit structure with crack stop and forming same
03/02/17Method and structure for low-k face-to-face bonded wafer dicing
03/02/17Fin liner integration under aggressive pitch
03/02/17Electrical gate-to-source/drain connection
03/02/17Methods for fabricating programmable devices and related structures
03/02/17High voltage finfet structure with shaped drift region
03/02/17Photodetector methods and photodetector structures
03/02/17Method, apparatus and system for using tunable timing circuits for fdsoi technology
03/02/17Fin cut for taper device
03/02/17Self-aligned local interconnect technology
03/02/17Fin cut for taper device
02/23/17Method, apparatus, and system for passive die strain measurement
02/23/17Diffractive overlay mark
02/23/17Data aware write scheme for sram
02/23/17Disturb free bitcell and array
02/23/17Automatic control of spray bar and units for chemical mechanical polishing in-situ brush cleaning
02/23/17Dual liner cmos integration methods for finfet devices
02/23/17Methods for forming fin structures
02/23/17Finfet pcm access transistor having gate-wrapped source and drain regions
02/23/17Germanium photodetector with soi doping source
02/23/17Series resistance reduction in vertically stacked silicon nanowire transistors
02/23/17Forming a gate contact in the active area
02/23/17Forming a gate contact in the active area
02/16/17Process design kit for efficient and accurate mismatch simulation of analog circuits
02/16/17Methods of forming air gaps in metallization layers on integrated circuit products
Patent Packs
02/16/17Self-aligned back end of line cut
02/16/17Filling cavities in an integrated circuit and resulting devices
02/16/17Gate tie-down enablement with inner spacer
02/16/17Methods of forming self-aligned device level contact structures
02/16/17Gate tie-down enablement with inner spacer
02/16/17Field effect transistors having multiple effective work functions
02/16/17Reducing liner corrosion during metallization of semiconductor devices
02/16/17Methods and devices for metal filling processes
02/16/17Semiconductor structure including a nonvolatile memory cell and the formation thereof
02/16/17Structure and method to form a finfet device
02/16/17Semiconductor structure with multilayer iii-v heterostructures
02/16/17Early pts with buffer for channel doping control
02/16/17Forming a contact for a tall fin transistor
02/16/17Forming a contact for a tall fin transistor
02/16/17Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins
02/16/17Self-aligned gate tie-down contacts with selective etch stop liner
02/09/17Capacitor structures with embedded electrodes and fabrication methods thereof
02/09/17Damascene wires with top via structures
02/09/17Methods for forming transistor devices with different threshold voltages and the resulting devices
02/09/17Bond pad structure for low temperature flip chip bonding
Social Network Patent Pack
02/09/17Capacitor structure and forming a capacitor structure
02/09/17Bulex contacts in advanced fdsoi techniques
02/09/17Measurement measuring in thin films
02/09/17Method for forming field effect transistors
02/09/17Field effect transistor device spacers
02/09/17Forming field effect transistor device spacers
02/02/17Finfet electrical characterization with enhanced hall effect and probe
02/02/17Method and system for adjusting a circuit symbol
02/02/17Charge dynamics effect for detection of voltage contrast defect and determination of shorting location
02/02/17Mitigating transient tsv-induced ic substrate noise and resulting devices
02/02/17Three-dimensional semiconductor device with co-fabricated adjacent capacitor
02/02/17Methods of forming replacement fins comprised of multiple layers of different semiconductor materials
02/02/17Method for improved fin profile
02/02/17Trench formation for dielectric filled cut region
02/02/17Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions
02/02/17Integrated circuits and methods for their fabrication
02/02/17Trench formation for dielectric filled cut region
02/02/17High doped iii-v source/drain junctions for field effect transistors
02/02/17High doped iii-v source/drain junctions for field effect transistors
01/26/17Method including a formation of a transistor and semiconductor structure including a first transistor and a second transistor
Social Network Patent Pack
01/26/17Method to fabricate a high performance capacitor in a back end of line (beol)
01/26/17Methods and structures for back end of line integration
01/26/17Die-die stacking
01/26/17High-k and p-type work function metal first fabrication process having improved annealing process flows
01/26/17High-k and p-type work function metal first fabrication process having improved annealing process flows
01/19/17Inline buried metal void detection by surface plasmon resonance (spr)
01/19/17Hybrid metrology technique
01/19/17Coupling inductors in an ic device using interconnecting elements with solder caps and resulting devices
01/19/17Stress relaxed buffer layer on textured silicon surface
01/19/17Gate cut with high selectivity to preserve interlevel dielectric layer
01/19/17Soi-based semiconductor device with dynamic threshold voltage
01/19/17Gate cut with high selectivity to preserve interlevel dielectric layer
01/19/17Method, apparatus and system for providing multiple euv beams for semiconductor processing
01/19/17Semiconductor substrates and methods for processing semiconductor substrates
01/19/17Methods for fabricating integrated circuits using flowable chemical vapor deposition techniques with low-temperature thermal annealing
01/19/17Interconnect structure including middle of line (mol) metal layer local interconnect on etch stop layer
01/19/17Dipole-based contact structure to reduce metal-semiconductor contact resistance in mosfets
01/12/17High-pressure anneal
01/12/17Method and structure of forming controllable unmerged epitaxial material
01/12/17Process for integrated circuit fabrication including a uniform depth tungsten recess technique
01/12/17Methods for producing integrated circuits using long and short regions and integrated circuits produced from such methods
01/12/17Large area contacts for small transistors
01/05/17Method of simultaneous lithography and etch correction flow
01/05/17Self-aligned via process flow
01/05/17Lateral bicmos replacement metal gate
01/05/17Integrated circuit structure with methods of electrically connecting same
01/05/17Embedded metal-insulator-metal capacitor
01/05/17Method to improve reliability of replacement gate device
01/05/17Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions
12/29/16Predicting and alerting user to navigation options and predicting user intentions
Social Network Patent Pack
12/29/16Generative learning for realistic and ground rule clean hot spot synthesis
12/29/16Dynamic and adaptive timing sensitivity during static timing analysis using look-up table
12/29/16Methods of design rule checking of circuit designs
12/29/16Insulating a via in a semiconductor substrate
12/29/16Method to protect mol metallization from hardmask strip process
12/29/16Hdp fill with reduced void formation and spacer damage
12/29/16Integrated circuit (ic) chips with through silicon vias (tsv) and forming the ic
12/29/16Methods including a processing of wafers and spin coating tool
12/29/16Electrical fuse with high off resistance
12/29/16Electrostatic discharge and passive structures integrated in a veritcal gate fin-type field effect diode
12/29/16Tunable capacitor for fdsoi applications
12/29/16High performance heat shields with reduced capacitance
12/29/16Planar qubits having increased coherence times
12/29/16Semiconductor structures with field effect transistor(s) having low-resistance source/drain contact(s)
12/29/16Shaped terminals for a bipolar junction transistor
12/29/16Method to improve reliability of replacement gate device
12/29/16Hdp fill with reduced void formation and spacer damage
12/29/16Bipolar junction transistors with a buried dielectric region in the active device region
12/29/16Fdsoi voltage reference
12/29/16Integrated circuits with self aligned contacts and methods of manufacturing the same
12/29/16Interconnect structure including middle of line (mol) metal layer local interconnect on etch stop layer
12/29/16Replacement gate multigate transistor for embedded dram
12/22/16Dual liner silicide
12/22/16Dual liner silicide
12/22/16Detecting a void between a via and a wiring line
12/22/16Siarc removal with plasma etch and fluorinated wet chemical solution combination
12/22/16Non-destructive dielectric layer thickness and dopant measuring method
12/22/16Test structures for dielectric reliability evaluations
12/22/16Chip packages with reduced temperature variation







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