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Globalfoundries Inc
Globalfoundries Inc grand Cayman Cayman Islands
Globalfoundries Inc_20131212


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Globalfoundries Inc patents

Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors

Search recent Press Releases: Globalfoundries Inc-related press releases
Count Application # Date Globalfoundries Inc patents (updated weekly) - BOOKMARK this page
12016014120605/19/16 Self-aligned via process flow
22016014124205/19/16 Method and a high yield contact integration scheme
32016014125205/19/16 Methods of forming alignment marks and overlay marks on integrated circuit products employing finfet devices and the resulting alignment/overlay mark
42016014129105/19/16 Metal segments as landing pads and local interconnects in an ic device
52016014136805/19/16 Tall strained high percentage silicon-germanium fins
62016014137905/19/16 Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and fabrication methods
72016014139305/19/16 Meander resistor
82016014148905/19/16 Topological method to build self-aligned mtj without a mask
92016013357205/12/16 Methods of forming a protective layer on an insulating layer for protection during formation of conductive structures
102016013357805/12/16 Design rule clean layer marker
112016013362305/12/16 Methods of forming a combined gate and source/drain contact structure and the resulting device
122016013369205/12/16 Uniaxially-strained fd-soi finfet
132016013371605/12/16 Alternative gate dielectric films for silicon germanium and germanium channel materials
142016013371905/12/16 Methods of forming replacement gate structures on finfet devices and the resulting devices
152016013372005/12/16 Methods of forming replacement gate structures on finfet devices and the resulting devices
162016013372105/12/16 Selectively forming a protective conductive cap on a metal gate electrode
172016013372605/12/16 Methods of forming products with finfet semiconductor devices without removing fins in certain areas of the product
182016013372705/12/16 Semiconductor junction formation
192016013374005/12/16 Semiconductor device comprising a multi-layer channel region
202016012430805/05/16 Alternating space decomposition in circuit structure fabrication
212016012512105/05/16 Achieving a critical dimension target based on resist characteristics
222016012613505/05/16 Methods of forming an improved via to contact interface by selective formation of a metal silicide capping layer
232016012614105/05/16 Methods for forming finfets having a capping layer for reducing punch through leakage
242016012614605/05/16 Efficient main spacer pull back process for advanced vlsi cmos technologies
252016012619005/05/16 Methods of forming an improved via to contact interface by selective formation of a conductive capping layer
262016012624505/05/16 Embedded dram in replacement metal gate technology
272016012631605/05/16 Transistor structures and fabrication methods thereof
282016012633605/05/16 Method of improved ca/cb contact and device thereof
292016012635205/05/16 Hybrid orientation fin field effect transistor and planar field effect transistor
302016012635305/05/16 Finfet device including a uniform silicon alloy fin
312016012430805/05/16 Alternating space decomposition in circuit structure fabrication
322016012612005/05/16 Work-in-progress substrate processing methods and systems for use in the fabrication of integrated circuits
332016012613205/05/16 Methods for fabricating integrated circuits with isolation regions having uniform step heights
342016012623905/05/16 Integrated circuits with resistor structures formed from mim capacitor material and methods for fabricating same
352016011643504/28/16 Nanochannel electrode devices
362016011724004/28/16 Performing secure address relocation within a multi-processor system sharing a same physical memory channel to external memory
372016011743204/28/16 Method and assisted metal routing
382016011743304/28/16 Integrated circuit timing variability reduction
392016011813804/28/16 Programming an electrical fuse with a silicon-controlled rectifier
402016011825104/28/16 Methods of forming doped epitaxial sige material on semiconductor devices
412016011825504/28/16 Methods of forming strained epitaxial semiconductor material(s) above a strain-relaxed buffer layer
422016011829804/28/16 Oxide mediated epitaxial nickel disilicide alloy contact formation
432016011830404/28/16 Fabrication of nanowire structures
442016011834104/28/16 Precut metal lines
452016011835804/28/16 Direct injection molded solder process for forming solder bumps on wafers
462016011838504/28/16 Replacement gate structures for transistor devices
472016011838604/28/16 Semiconductor structure having finfet ultra thin body and methods of fabrication thereof
482016011841404/28/16 Dual three-dimensional and rf semiconductor devices using local soi
492016011845804/28/16 Metal-insulator-metal back end of line capacitor structures
502016011846804/28/16 Multiple layer interface formation for semiconductor structure
512016011847204/28/16 Methods of forming 3d devices with dielectric isolation and a strained channel region
522016011847304/28/16 Non-planar schottky diode and fabrication
532016011848004/28/16 Methods of forming a tri-gate finfet device and the resulting device
542016011848304/28/16 Multi-gate fets having corrugated semiconductor stacks and forming the same
552016011849904/28/16 Fd devices in advanced semiconductor techniques
562016011829204/28/16 Integrated circuits with an air gap and methods of producing the same
572016011850004/28/16 Fin structures and multi-vt scheme based on tapered fin and method to form
582016011048904/21/16 Methods, apparatus, and system for using filler cells in design of integrated circuit devices
592016011132004/21/16 T-shaped fin isolation region and methods of fabrication
602016011132204/21/16 Finfet semiconductor device having local buried oxide
612016011133504/21/16 Semiconductor structure with self-aligned wells and multiple channel materials
622016011133904/21/16 Contact liners for integrated circuits and fabrication methods thereof
632016011134104/21/16 Method of utilizing trench silicide in a gate cross-couple construct
642016011135204/21/16 Dielectric cover for a through silicon via
652016011136004/21/16 Dummy metal structure and forming dummy metal structure
662016011137404/21/16 Low energy etch process for nitrogen-containing dielectric layer
672016011138104/21/16 Semiconductor structure including a die seal leakage detection material, the formation thereof and method including a test of a semiconductor structure
682016011138204/21/16 Vertical breakdown protection layer
692016011138604/21/16 Bond pad structure for low temperature flip chip bonding
702016011140604/21/16 Top-side interconnection substrate for die-to-die interconnection
712016011141404/21/16 Scr with fin body regions for esd protection
722016011142204/21/16 Method for making high voltage integrated circuit devices in a fin-type process and resulting devices
732016011149104/21/16 Fin device with blocking layer in channel region
742016011151304/21/16 Multi-channel gate-all-around fet
752016011151404/21/16 Ultra-low resistance gate structure for non-planar device via minimized work function material
762016011153904/21/16 High mobility pmos and nmos devices having si-ge quantum wells
772016011154904/21/16 Methods of forming a semiconductor circuit element and semiconductor circuit element
782016011186704/21/16 Methods of post-process dispensation of plasma induced damage protection component
792016010464404/14/16 Process for integrated circuit fabrication including a uniform depth tungsten recess technique
802016010454104/14/16 Novel otprom for post-process programming using selective breakdown
812016010462104/14/16 Semiconductor device having common contact and gate properties
822016010463804/14/16 Semiconductor structure including a layer of a first metal between a diffusion barrier layer and a second metal and the formation thereof
832016010467004/14/16 Interlayer ballistic conductor signal lines
842016010467204/14/16 Low capacitance ballistic conductor signal lines
852016010467704/14/16 Self aligned via fuse
862016010470704/14/16 Method and structure for transistors using gate stack dopants with minimal nitrogen penetration
872016010476204/14/16 Method of fabricating a mim capacitor with minimal voltage coefficient and a decoupling mim capacitor and analog/rf mim capacitor on the same chip with high-k dielectrics
882016010477004/14/16 Profile control over a collector of a bipolar junction transistor
892016010477404/14/16 Non-planar vertical dual source drift metal-oxide semiconductor (vdsmos)
902016010479904/14/16 Dual-strained nanowire and finfet devices with dielectric isolation
912016010517904/14/16 Level shifting an i/o signal into multiple voltage domains
922016009833204/07/16 Dynamic multi-purpose external access points connected to core interfaces within a system on chip (soc)
932016009916804/07/16 Method for defining an isolation region(s) of a semiconductor structure
942016009917104/07/16 Dimension-controlled via formation processing
952016009923904/07/16 Methods, apparatus and system for reduction of power consumption in a semiconductor device
962016009929704/07/16 Flexible active matrix display
972016009930204/07/16 Embedded metal-insulator-metal capacitor
982016009932104/07/16 Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layers
992016009932904/07/16 Suspended body field effect transistor
1002016009933304/07/16 Field effect transistor and fabrication
1012016009933604/07/16 Opc enlarged dummy electrode to eliminate ski slope at esige
1022016009934304/07/16 Tunneling field effect transistor and methods of making such a transistor
1032016009934404/07/16 Facilitating fabricating gate-all-around nanowire field-effect transistors
1042016009356503/31/16 Printing minimum width features at non-minimum pitch and resulting device
1052016009369203/31/16 Finfet semiconductor devices with replacement gate structures
1062016009370403/31/16 Method for creating self-aligned transistor contacts
1072016009371303/31/16 Semiconductor devices with replacement gate structures
1082016009373903/31/16 Finfet semiconductor device with isolated channel regions
1092016009371103/31/16 Tantalum carbide metal gate stack for mid-gap work function applications
1102016008707303/24/16 Bipolar junction transistors with an air gap in the shallow trench isolation
1112016008256603/24/16 Wafer slip detection during cmp processing
1122016008684903/24/16 Constrained nanosecond laser anneal of metal interconnect structures
1132016008686003/24/16 Methods for making robust replacement metal gates and multi-threshold devices in a soft mask integration scheme
1142016008688603/24/16 Nanowire compatible e-fuse
1152016008695203/24/16 Preventing epi damage for cap nitride strip scheme in a fin-shaped field effect transistor (finfet) device
1162016007793903/17/16 Recovering from uncorrected memory errors
1172016007908603/17/16 Method of forming a semiconductor device and according semiconductor device
1182016007911603/17/16 Wafer with improved plating current distribution
1192016007916803/17/16 Integrated circuits with metal-titanium oxide contacts and fabrication methods
1202016007918003/17/16 Overlay mark dependent dummy fill to mitigate gate height variation
1212016007924203/17/16 Patterning multiple, dense features in a semiconductor device using a memorization layer
1222016007934203/17/16 Method and device for an integrated trench capacitor
1232016007939703/17/16 Partial fin on oxide for improved electrical isolation of raised active regions
1242016007173103/10/16 Finfet doping method with curvilinear trajectory implantation beam path
1252016007174203/10/16 Photoresist collapse forming a physical unclonable function
1262016007179103/10/16 Multimetal interlayer interconnects
1272016007183503/10/16 Metal gate for robust esd protection
1282016007184503/10/16 Directed self-assembly material growth mask for forming vertical nanowires
1292016007192803/10/16 Methods of forming gate structures for finfet devices and the resulting semiconductor products
1302016007193003/10/16 Multiple directed self-assembly material mask patterning for forming vertical nanowires
1312016007193203/10/16 Finfet structures having uniform channel size and methods of fabrication
1322016007194703/10/16 Method including a replacement of a dummy gate structure with a gate structure including a ferroelectric material
1332016007195403/10/16 Robust post-gate spacer processing and device
1342016007196203/10/16 Symmetrical lateral bipolar junction transistor and use of same in characterizing and protecting transistors
1352016007197803/10/16 Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer
1362016007197903/10/16 Fin device with blocking layer in channel region
1372016006188003/03/16 Methods, apparatus and system for tddb testing
1382016006316703/03/16 Method and system for via retargeting
1392016006412303/03/16 Temperature independent resistor
1402016006422803/03/16 Method of forming a semiconductor structure including a ferroelectric material and semiconductor structure including a ferroelectric transistor
1412016006423603/03/16 Methods of patterning features having differing widths
1422016006425003/03/16 Methods of forming metastable replacement fins for a finfet semiconductor device by performing a replacement growth process
1432016006435403/03/16 Method for electronic circuit assembly on a paper substrate
1442016006437103/03/16 Non-planar esd device for non-planar output transistor and common fabrication thereof
1452016006437203/03/16 Esd snapback based clamp for finfet
1462016006438203/03/16 Selective fusi gate formation in gate first cmos technologies
1472016006447103/03/16 Embedded capacitor
1482016006448403/03/16 Lateral bipolar junction transistors on a silicon-on-insulator substrate with a thin device layer thickness
1492016006451003/03/16 Device including a floating gate electrode and a layer of ferroelectric material and the formation thereof
1502016006451403/03/16 Borderless contact formation through metal-recess dual cap integration
1512016006452303/03/16 Semiconductor structure having a source and a drain with reverse facets
1522016006452603/03/16 Methods of forming alternative channel materials on finfet semiconductor devices
1532016006454403/03/16 Finfet semiconductor device with isolated fins made of alternative channel materials
1542016006428603/03/16 Integrated circuits and methods for fabricating integrated circuits
1552016006447203/03/16 Integrated circuits including a mimcap device and methods of forming the same for long and controllable reliability lifetime
1562016006451303/03/16 Integrated circuits with a bowed substrate, and methods for producing the same
1572016006451503/03/16 Methods of making integrated circuits and components thereof
1582016005438302/25/16 Semiconductor structure having test device
1592016005528102/25/16 Model-based generation of dummy features
1602016005607502/25/16 Precut metal lines
1612016005610402/25/16 Self-aligned back end of line cut
1622016005610602/25/16 Structure with self aligned resist layer on an interconnect surface and making same
1632016005623102/25/16 Semiconductor devices and fabrication methods thereof
1642016005623802/25/16 Raised source/drain epi with suppressed lateral epi overgrowth
1652016005626102/25/16 Embedded sigma-shaped semiconductor alloys formed in transistors
1662016005626302/25/16 Methods of forming a gate cap layer above a replacement gate structure
1672016005626502/25/16 Methods of making a self-aligned channel drift device
1682016005628802/25/16 Circuit element including a layer of a stress-creating material providing a variable stress
1692016005629402/25/16 Epitaxial growth of silicon for finfets with non-rectangular cross-sections
1702016005603302/25/16 Low temperature atomic layer deposition of oxides on compound semiconductors
1712016005607202/25/16 Multilayered contact structure having nickel, copper, and nickel-iron layers
1722016005625302/25/16 Integrated circuits with diffusion barrier layers and processes for preparing integrated circuits including diffusion barrier layers
1732016004705802/18/16 Metal plating system including gas bubble removal unit
1742016004930202/18/16 Method of forming a semiconductor circuit element and semiconductor circuit element
1752016004932702/18/16 Methods of fabricating beol interlayer structures
1762016004933202/18/16 Methods of forming contact structures for semiconductor devices and the resulting devices
1772016004937002/18/16 Methods of forming mis contact structures for semiconductor devices by selective deposition of insulating material and the resulting devices
1782016004939902/18/16 Gate structures for semiconductor devices with a conductive etch stop layer
1792016004940002/18/16 Threshold voltage control for mixed-type non-planar semiconductor devices
1802016004940102/18/16 Hybrid contacts for commonly fabricated semiconductor devices using same metal
1812016004940202/18/16 Semiconductor device having fins with in-situ doped, punch-through stopper layer and related methods
1822016004942702/18/16 Integrated circuits with self aligned contact structures for improved windows and fabrication methods
1832016004946802/18/16 Product comprised of finfet devices with single diffusion break isolation structures
1842016004948102/18/16 Transistor contacts self-aligned two dimensions
1852016004948802/18/16 Semiconductor gate with wide top or bottom
1862016004949402/18/16 Forming transistors without spacers and resulting devices
1872016004949502/18/16 Semiconductor structures with coplanar recessed gate layers and fabrication methods
1882016004950302/18/16 Bipolar junction transistors with reduced epitaxial base facets effect for low parasitic collector-base capacitance
1892016004936602/18/16 Integrated circuits with electronic fuse structures
1902016004948902/18/16 Integrated circuits with nanowires and methods of manufacturing the same
1912016004949002/18/16 Integrated circuits with dual silicide contacts and methods for fabricating same
1922016004295402/11/16 Replacement metal gate and fabrication process with reduced lithography steps
1932016004304602/11/16 Etching of under bump metallization layer and resulting device
1942016004304802/11/16 Preventing misshaped solder balls
1952016004308102/11/16 Method of forming semiconductor fins
1962016004319002/11/16 Semiconductor structure(s) with extended source/drain channel interfaces and methods of fabrication
1972016004320202/11/16 Self-aligned bipolar junction transistor having self-planarizing isolation raised base structures
1982016004322302/11/16 Finfet semiconductor devices with stressed layers
1992016004402302/11/16 Authentication policy enforcement
2002016003395802/04/16 Endpoint determination using individually measured target spectra
2012016003563002/04/16 Methods of forming transistors with retrograde wells in cmos applications and the resulting device structures
2022016003564102/04/16 Semiconductor device including passivation layer encapsulant
2032016003572302/04/16 Macro design of device characterization for 14nm and beyond technologies
2042016003572702/04/16 Cmos structure with beneficial nmos and pmos band offsets
2052016003572802/04/16 Retrograde doped layer for device isolation
2062016003574302/04/16 Field effect transistor (fet) with self-aligned contacts, integrated circuit (ic) chip and manufacture
2072016003581802/04/16 Forming a vertical capacitor and resulting device
2082016003582002/04/16 Uniaxially-strained fd-soi finfet
2092016003585602/04/16 Semiconductor structure including a ferroelectric transistor and the formation thereof
2102016003586302/04/16 Methods of forming stressed channel regions for a finfet semiconductor device and the resulting device
2112016003590602/04/16 Planar semiconductor esd device and making same
2122016003387902/04/16 Methods and controllers for controlling focus of ultraviolet light from a lithographic imaging system, and apparatuses for forming an integrated circuit employing the same
2132016003556502/04/16 Methods for fabricating integrated circuits using directed self-assembly chemoepitaxy
2142016003563102/04/16 Atomic layer deposition of hfalc as a metal gate workfunction material in mos devices
2152016002580501/28/16 Wafer test structures and methods of providing wafer test structures
2162016002674801/28/16 Multi-polygon constraint decomposition techniques for use in double patterning applications
2172016002770001/28/16 Gate structure cut after formation of epitaxial active regions
2182016002771301/28/16 Establishing a thermal profile across a semiconductor chip
2192016002773401/28/16 E-fuse structure with methods of fusing the same and monitoring material leakage
2202016002774401/28/16 Method of forming an integrated crackstop
2212016002777501/28/16 Dual-width fin structure for finfets devices
2222016002789501/28/16 Methods of forming fins for a finfet device by forming and replacing sacrificial fin structures with alternative materials
2232016002790501/28/16 Bipolar junction transistors and methods of fabrication
2242016002679301/28/16 Threat condition management
2252016002014001/21/16 Anisotropic material damage process for etching low-k dielectric materials
2262016002015401/21/16 Simplified multi-threshold voltage scheme for fully depleted soi mosfets
2272016002020401/21/16 Three-dimensional electrostatic discharge semiconductor device
2282016002027501/21/16 Shallow trench isolation structure with sigma cavity
2292016002027701/21/16 Three-dimensional electrostatic discharge semiconductor device
2302016002033501/21/16 Transistors comprising doped region-gap-doped region structures and methods of fabrication
2312016001295201/14/16 Inductor structure having embedded airgap
2322016001326201/14/16 Fabrication of multilayer circuit elements
2332016001329101/14/16 Methods of forming isolated channel regions for a finfet semiconductor device and the resulting device
2342016001329601/14/16 Methods of forming low defect replacement fins for a finfet semiconductor device and the resulting devices
2352016000559801/07/16 Inhibiting diffusion of elements between material layers of a layered circuit structure
2362016000565701/07/16 Semiconductor structure with increased space and volume between shaped epitaxial structures
2372016000573301/07/16 Integrated circuit product with a gate height registration structure
2382016000573401/07/16 Integrated circuit product comprised of multiple p-type semiconductor devices with different threshold voltages
2392016000582801/07/16 Gate dielectric protection for transistors
2402016000583401/07/16 Methods of forming a channel region for a semiconductor device by performing a triple cladding process
2412016000586701/07/16 Silicide protection during contact metallization and resulting semiconductor structures
2422016000586801/07/16 Finfet with confined epitaxy
2432015037795612/31/15 Method and inline device characterization and temperature profiling
2442015037809612/31/15 Integration of optical components in integrated circuits
2452015038024612/31/15 Dimension-controlled via formation processing
2462015038025012/31/15 Semiconductor contacts and methods of fabrication
2472015038025212/31/15 Sidewall image templates for directed self-assembly materials
2482015038025812/31/15 Method for controlling height of a fin structure
2492015038026212/31/15 Sub-lithographic semiconductor structures with non-constant pitch

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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Globalfoundries Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Globalfoundries Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by