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Globalfoundries, Inc. patents


      
Recent patent applications related to Globalfoundries, Inc.. Globalfoundries, Inc. is listed as an Agent/Assignee. Note: Globalfoundries, Inc. may have other listings under different names/spellings. We're not affiliated with Globalfoundries, Inc., we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries, Inc.-related inventors



Method of forming a semiconductor structure including silicided and non-silicided circuit elements

Globalfoundries

Method of forming a semiconductor structure including silicided and non-silicided circuit elements

Mol insitu pt rework sequence

Globalfoundries

Mol insitu pt rework sequence

Mol insitu pt rework sequence

Globalfoundries

Systems and methods for fabricating semiconductor device structures

Search recent Press Releases: Globalfoundries, Inc.-related press releases
Count Application # Date Globalfoundries, Inc. patents (updated weekly) - BOOKMARK this page
12015002834801/29/15 new patent  Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (finfet) device
22015002843101/29/15 new patent  Mol insitu pt rework sequence
32015002848201/29/15 new patent  Device layout for reducing through-silicon-via stress
42015002848901/29/15 new patent  Method for off-grid routing structures utilizing self aligned double patterning (sadp) technology
52015002850001/29/15 new patent  Forming alignment mark and resulting mark
62015003117901/29/15 new patent  Method of forming a semiconductor structure including silicided and non-silicided circuit elements
72015003320101/29/15 new patent  Systems and methods for fabricating semiconductor device structures
82015002166301/22/15Finfet with insulator under channel
92015002168301/22/15Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
102015002169101/22/15Finfet with electrically isolated active region on bulk semiconductor substrate and fabricating same
112015002169301/22/15Enhancing transistor performance and reliability by incorporating deuterium into a strained capping layer
122015002169501/22/15Epitaxial block layer for a fin field effect transistor device
132015002170201/22/15Shallow trench isolation
142015002170301/22/15Gate oxide quality for complex mosfet devices
152015002170401/22/15Finfet work function metal formation
162015002170901/22/15Structures and methods integrating different fin device architectures
172015002171201/22/15Highly conformal extension doping in advanced multi-gate devices
182015002455701/22/15Semiconductor device having local buried oxide
192015002456001/22/15Gate encapsulation achieved by single-step deposition
202015002457201/22/15Process for faciltiating fin isolation schemes
212015002457301/22/15Methods of forming replacement fins for a finfet semiconductor device by performing a replacement growth process
222015002458501/22/15Systems and methods for fabricating gate structures for semiconductor devices
232015002169401/22/15Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating the same
242015002171401/22/15Integrated circuits having a metal gate structure and methods for fabricating the same
252015002358301/22/15Methods and systems for determining a dose-to-clear of a photoresist
262015002457801/22/15Methods for etching dielectric materials in the fabrication of integrated circuits
272015001477701/15/15Channel semiconductor alloy layer growth adjusted by impurity ion implantation
282015001481301/15/15Complex circuit element and capacitor utilizing cmos compatible antiferroelectric high-k materials
292015001484301/15/15Semiconductor device with improved metal pillar configuration
302015001777401/15/15Method of forming fins with recess shapes
312015001780301/15/15Customized alleviation of stresses generated by through-substrate via(s)
322015001477601/15/15Finfet integrated circuits and methods for their fabrication
332015001617401/15/15Integrated circuits with programmable electrical connections and methods for fabricating the same
342015000853601/08/15Semiconductor device structure and forming a semiconductor device structure
352015000975001/08/15Device including a dual port static random access memory cell and the formation thereof
362015001085101/08/15Methods involving color-aware retargeting of individual decomposed patterns when designing masks to be used in multiple patterning processes
372015001289601/08/15Methods for fabricating integrated circuits including generating photomasks for directed self-assembly
382015000162701/01/15Spacer chamfering for a replacement metal gate device
392015000163401/01/15Methods of forming bipolar devices and an integrated circuit product containing such bipolar devices
402015000163501/01/15Methods of forming an e-fuse for an integrated circuit product and the resulting integrated circuit product
412015000164001/01/15Transistor device with improved source/drain junction architecture and methods of making such a device
422015000164201/01/15Field effect transistor and fabrication
432015000613801/01/15Optical proximity correction for connecting via between layers of a device
442015000159101/01/15Bulk finfet with partial dielectric isolation featuring a punch-through stopping layer under the oxide
452015000163001/01/15Structure and methods of fabricating y-shaped dmos finfet
462015000164301/01/15Integrated circuits having improved high-k dielectric layers and methods for fabrication of same
472014037480712/25/14Method of device isolation in cladding si through in situ doping
482014037491512/25/14Integration of optical components in integrated circuits
492014037796512/25/14Directed self-assembly (dsa) formulations used to form dsa-based lithography films
502014036775112/18/14Finfet spacer etch for esige improvement
512014036778712/18/14Methods of forming transistors with retrograde wells in cmos applications and the resulting device structures
522014036778812/18/14Methods of forming gate structures for cmos based integrated circuit products and the resulting devices
532014036779012/18/14Methods of forming gate structures for cmos based integrated circuit products and the resulting devices
542014036779412/18/14Device including an array of memory cells and well contact areas, and the formation thereof
552014036779512/18/14Methods of forming different finfet devices having different fin heights and an integrated circuit product containing such devices
562014037043912/18/14Methods and systems for reducing bubbles in layers of photoresist material
572014037069712/18/14Removal of nitride bump in opening replacement gate structure
582014036780312/18/14Finfet gate with insulated vias and making same
592014036782612/18/14Making an efuse
602014037044712/18/14Semiconductor device resolution enhancement by etching multiple sides of a mask
612014037070512/18/14Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein
622014035372812/04/14Method and a reduced capacitance middle-of-the-line (mol) nitride stack
632014035373412/04/14Semiconductor devices and methods of fabrication with reduced gate and contact resistances
642014035380212/04/14Methods for integration of pore stuffing material
652014035380512/04/14Methods of semiconductor contaminant removal using supercritical fluid
662014035707912/04/14Methods of forming conductive structures using a sacrificial material during a metal hard mask removal process
672014035955112/04/14Systems and methods for semiconductor voltage drop analysis
682014034664811/27/14Low-k nitride film and making
692014034666211/27/14Forming modified cell architecture for finfet technology and resulting device
702014034947811/27/14Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean process
712014034659911/27/14Finfet semiconductor devices with local isolation features and methods for fabricating the same
722014033961011/20/14Finfet device and fabrication
732014033961211/20/14Using sacrificial oxide layer for gate length tuning and resulting device
742014033962911/20/14Contact formation for ultra-scaled devices
752014033964711/20/14Densely packed standard cells for integrated circuit products, and methods of making same
762014034255611/20/14Reusing active area mask for trench transfer exposure
772014033566811/13/14Contact landing pads for a semiconductor device and methods of making same
782014032714611/06/14Methods for improving double patterning route efficiency
792014032713911/06/14Contact liner and methods of fabrication thereof
802014032715311/06/14Standard cell connection for circuit routing
812014032938811/06/14Methods of patterning features having differing widths
822014032714011/06/14Integrated circuits and methods for fabricating integrated circuits with improved contact structures
832014032746511/06/14Structures and methods for testing integrated circuits and via chains therein
842014031961710/30/14Methods of forming metal silicide regions on a semiconductor device
852014032476910/30/14Document driven methods of managing the content of databases that contain information relating to semiconductor manufacturing operations
862014031961410/30/14Finfet channel stress using tungsten contacts in raised epitaxial source and drain
872014031962010/30/14Methods for fabricating integrated circuits with polycrystalline silicon resistor structures using a replacment gate process flow, and the integrated circuits fabricated thereby
882014032420810/30/14System and monitoring wafer handling and a wafer handling machine
892014031243410/23/14Finfet device with a graphene gate electrode and methods of forming same
902014031537110/23/14Methods of forming isolation regions for bulk finfet semiconductor devices
912014030631710/16/14Finfet fin height control
922014030810810/16/14System for separately handling different size foups
932014029994110/09/14Sram cell with reduced voltage droop
942014030266010/09/14Local interconnect to a protection diode
952014029184710/02/14Methods of forming a barrier system containing an alloy of metals introduced into the barrier system, and an integrated circuit product containing such a barrier system
962014029566410/02/14Methods of forming masking layers for use in forming integrated circuit products
972014028969509/25/14Evaluation of pin geometry accessibility in a layer of circuit
982014026438609/18/14Performance enhancement in pmos and nmos transistors on the basis of silicon/carbon material
992014026434209/18/14Semiconductor device including a resistor and the formation thereof
1002014026434709/18/14Transistor with embedded strain-inducing material formed in cavities based on an amorphization process and a heat treatment
1012014026434909/18/14Low thermal budget schemes in semiconductor device fabrication
1022014026446109/18/14Metal layer enabling directed self-assembly semiconductor layout designs
1032014026447909/18/14Methods of increasing space for contact elements by using a sacrificial liner and the resulting device
1042014026448609/18/14Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
1052014026448709/18/14Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
1062014026448909/18/14Wrap around stressor formation
1072014026461709/18/14Hk/mg process flows for p-type semiconductor devices
1082014026462609/18/14Method for forming a gate electrode of a semiconductor device, gate electrode structure for a semiconductor device and according semiconductor device structure
1092014026463109/18/14Methods of forming alignment marks and overlay marks on integrated circuit products employing finfet devices and the resulting alignment/overlay mark
1102014026463209/18/14Semiconductor structure including a transistor having a layer of a stress-creating material and the formation thereof
1112014026464109/18/14Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layers
1122014026473109/18/14Programmable e-fuse for an integrated circuit product
1132014026475809/18/14Methods of forming a protection layer to protect a metal hard mask layer during lithography reworking processes
1142014026487609/18/14Multi-layer barrier layer stacks for interconnect structures
1152014026487709/18/14Metallization systems of semiconductor devices comprising a copper/silicon compound as a barrier material
1162014026489009/18/14Novel pillar structure for use in packaging integrated circuit products and methods of making such a pillar structure
1172014027336509/18/14Methods of forming contacts to source/drain regions of finfet devices by forming a region that includes a schottky barrier lowering material
1182014027336909/18/14Methods of forming contacts to source/drain regions of finfet devices
1192014027338909/18/14Semiconductor device having controlled final metal critical dimension
1202014027339609/18/14Method of forming a semiconductor structure including a metal-insulator-metal capacitor
1212014027342309/18/14Methods of forming a semiconductor device with a nanowire channel structure by performing an anneal process
1222014027342909/18/14Methods of forming finfet devices with a shared gate structure
1232014027343609/18/14Methods of forming barrier layers for conductive copper structures
1242014027345509/18/14Hard mask removal during finfet formation
1252014027347309/18/14Methods of forming a masking layer for patterning underlying structures
1262014027347409/18/14Interconnection designs using sidewall image transfer (sit)
1272014028229609/18/14Hybrid performing full field optical proximity correction for finfet mandrel layer
1282014028230109/18/14Stitch insertion for reducing color density differences in double patterning technology (dpt)
1292014028230309/18/14Pattern-independent and hybrid matching/tuning including light manipulation by projection optics
1302014028230709/18/14Method and providing metric relating two or more process parameters to yield
1312014028232309/18/14Parameterized cell for planar and finfet technology design
1322014028233009/18/14Priority based layout versus schematic (lvs)
1332014028234509/18/14Via insertion in integrated circuit (ic) designs
1342014026461309/18/14Integrated circuits and methods for fabricating integrated circuits with active area protection
1352014026463309/18/14Finfet devices having a body contact and methods of forming the same
1362014026898309/18/14Otprom array with leakage current cancelation for enhanced efuse sensing
1372014026906009/18/14Integrated circuits and methods for operating integrated circuits with non-volatile memory
1382014027267709/18/14Methods for fabricating euv masks and methods for fabricating integrated circuits using such euv masks
1392014027329909/18/14Systems and methods for fabricating semiconductor device structures using different metrology tools
1402014027330609/18/14Methods for fabricating integrated circuits including multi-patterning of masks for extreme ultraviolet lithography
1412014027336709/18/14Integrated circuits and methods for fabricating integrated circuits with gate electrode structure protection
1422014027337509/18/14Methods for fabricating integrated circuits with semiconductor substrate protection
1432014027346309/18/14Methods for fabricating integrated circuits that include a sealed sidewall in a porous low-k dielectric layer
1442014027347509/18/14Methods for fabricating guide patterns and methods for fabricating integrated circuits using such guide patterns
1452014027351109/18/14Methods for fabricating integrated circuits including formation of chemical guide patterns for directed self-assembly lithography
1462014027766809/18/14Methods and systems for fabricating integrated circuits utilizing universal and local processing management
1472014025242409/11/14Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
1482014025242509/11/14Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
1492014025242909/11/14Contact geometry having a gate silicon length decoupled from a transistor length
1502014025248009/11/14Combination finfet and planar fet semiconductor device and methods of making such a device
1512014025248109/11/14Transistor including a gate electrode extending all around one or more channel regions
1522014025255709/11/14Method for forming a semiconductor device and semiconductor device structures
1532014025261709/11/14Barrier layer conformality in copper interconnects
1542014025266009/11/14Multilayer pattern transfer for chemical guides
1552014025390209/11/14Multiple patterning process for forming trenches or holes using stitched assist features
1562014025401809/11/14Scattering enhanced thin absorber for euv reflective reticle and a making
1572014025606409/11/14Methods of repairing damaged insulating materials by introducing carbon into the layer of insulating material
1582014025609709/11/14Methods for forming integrated circuit systems employing fluorine doping
1592014025613509/11/14Methods of removing gate cap layers in cmos applications
1602014025613709/11/14Method of forming a semiconductor structure including an implantation of ions into a layer of spacer material
1612014025773809/11/14Hierarchically divided signal path for characterizing integrated circuits
1622014025896009/11/14Integrating optimal planar and three-dimensional semiconductor design layouts
1632014025614109/11/14Methods for fabricating integrated circuits utilizing silicon nitride layers
1642014024669609/04/14Transistor with embedded strain-inducing material formed in cavities formed in a silicon/germanium substrate
1652014024669809/04/14Channel sige removal from pfet source/drain region for improved silicide formation in hkmg technologies without embedded sige
1662014024673409/04/14Replacement metal gate with mulitiple titanium nitride laters
1672014024673509/04/14Metal gate structure for semiconductor devices
1682014024677509/04/14Methods of forming non-continuous conductive layers for conductive structures on an integrated circuit product
1692014024679109/04/1414 lpm contact power rail
1702014024743809/04/14Reticle defect correction by second exposure
1712014024874909/04/14Stress memorization technique
1722014024876409/04/14Methods of forming structures on an integrated circuit product
1732014024877009/04/14Microwave-assisted heating of strong acid solution to remove nickel platinum/platinum residues
1742014024877809/04/14Methods of forming asymmetric spacers on various structures on integrated circuit products
1752014024660509/04/14Defect removal process
1762014023804508/28/14Semiconductor device comprising a stacked die configuration including an integrated peltier element
1772014024278808/28/14Method of forming a high quality interfacial layer for a semiconductor device by performing a low temperature ald process
1782014024523808/28/14Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications
1792014023950308/28/14Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
1802014023124508/21/14Adjustable current shield for electroplating processes
1812014023190708/21/14Methods of inducing a desired stress in the channel region of a transistor by performing ion implantation/anneal processes on the gate electrode
1822014023196008/21/14Polysilicon resistor formation
1832014023243308/21/14Circuit element including a layer of a stress-creating material providing a variable stress and the formation thereof
1842014023301408/21/14Infrared-based metrology for detection of stress and defects around through silicon vias
1852014023188508/21/14Integrated circuits and methods for fabricating integrated circuits having metal gate electrodes
1862014023192208/21/14Semiconductor gate structure for threshold voltage modulation and making same
1872014023201008/21/14Integrated circuits and methods of forming the same with multi-level electrical connection
1882014023505508/21/14Method for fabricating a semiconductor integrated circuit with a litho-etch, litho-etch process for etching trenches
1892014022476408/14/14Chemical and physical templates for forming patterns using directed self-assembly materials
1902014022516808/14/14Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device
1912014022520108/14/14Edge and strap cell design for sram array
1922014022527008/14/14Method for off-grid routing structures utilizing self aligned double patterning (sadp) technology
1932014022784508/14/14Methods of forming multiple n-type semiconductor devices with different threshold voltages on a semiconductor substrate
1942014022784908/14/14Methods of trimming nanowire structures
1952014022785808/14/14Shallow trench isolation integration methods and devices formed thereby
1962014022786908/14/14Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions
1972014022787208/14/14Methods of forming conductive structures using a sacrificial liner layer
1982014022787908/14/14Methods for fabricating integrated circuits with improved semiconductor fin structures
1992014021746708/07/14Methods of forming substrates comprised of different semiconductor materials and the resulting device
2002014021748008/07/14Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer
2012014021754408/07/14Methods of forming a transistor device on a bulk substrate and the resulting device
2022014021758808/07/14Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device
2032014021759108/07/14Multi-layer barrier layer for interconnect structure
2042014022075608/07/14Methods of forming semiconductor devices by forming a semiconductor layer above source/drain regions prior to removing a gate cap layer
2052014022075908/07/14Methods for fabricating integrated circuits having gate to active and gate to gate interconnects
2062014022076708/07/14Double-pattern gate formation processing with critical dimension control
2072014022339008/07/14Retargeting semiconductor device shapes for multiple patterning processes
2082014022339208/07/14Optimized optical proximity correction handling for lithographic fills
2092014021748208/07/14Integrated circuits having replacement gate structures and methods for fabricating the same
2102014021751708/07/14Integrated circuits including finfet devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
2112014022077508/07/14Methods for fabricating integrated circuits having embedded electrical interconnects
2122014022078608/07/14Methods for optical proximity correction in the design and fabrication of integrated circuits
2132014021008807/31/14Method for reducing wettability of interconnect material at corner interface and device incorporating same
2142014021117507/31/14Enhancing resolution in lithographic processes using high refractive index fluids
2152014021541507/31/14Automated design layout pattern correction based on context-aware patterns
2162014020956307/31/14Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein
2172014021303307/31/14Methods for fabricating electrically-isolated finfet semiconductor devices
2182014021303707/31/14Methods for fabricating integrated circuits having confined epitaxial growth regions
2192014020328007/24/14Electrical test structure for devices employing high-k dielectrics or metal gates
2202014020329807/24/14Strained silicon carbide channel for electron mobility of nmos
2212014020333907/24/14Semiconductor device comprising self-aligned contact elements and a replacement gate electrode structure
2222014020337607/24/14Finfet integrated circuits with uniform fin height and methods for fabricating the same
2232014020340507/24/14Method to dynamically tune precision resistance
2242014020344607/24/14Through silicon via device having low stress, thin film gaps and methods for forming the same
2252014020381407/24/14Method and measuring alpha particle induced soft errors in semiconductor devices
2262014020615707/24/14Method of forming a semiconductor structure including a vertical nanowire
2272014020828507/24/14Self-aligned double patterning via enclosure design
2282014020327907/24/14Test structure and method to faciltiate development/optimization of process parameters
2292014020344907/24/14Integrated circuits and methods of forming the same with metal layer connection to through-semiconductor via
2302014020382707/24/14Integrated circuits and methods of forming the same with embedded interconnect connection to through-semiconductor via
2312014019746807/17/14Methods of forming semiconductor device with self-aligned contact elements and the resulting device
2322014019754407/17/14Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials
2332014019749807/17/14Integrated circuits and methods for fabricating integrated circuits with improved silicide contacts
2342014019984507/17/14Selective removal of gate structure sidewall(s) to facilitate sidewall spacer protection
2352014019132407/10/14Methods of forming bulk finfet devices by performing a recessing process on liner materials to define different fin heights and finfet devices with such recessed liner materials
2362014019133207/10/14Pfet devices with different structures and performance characteristics
2372014019395707/10/14Reducing gate height variance during semiconductor device formation
2382014018355107/03/14Blanket epi super steep retrograde well formation without si recess
2392014018363807/03/14Methods of using a trench salicide routing layer
2402014018372007/03/14Methods of manufacturing integrated circuits having a compressive nitride layer
2412014018503007/03/14Asymmetric reticle heating of multilayer reticles eliminated by dummy exposures and related methods
2422014018703607/03/14Integration of ru wet etch and cmp for beol interconnects with ru layer
2432014018374507/03/14Gate electrode(s) and contact structure(s), and methods of fabrication thereof
2442014017553906/26/14Canyon gate transistor and methods for its fabrication
2452014017816006/26/14Overhead substrate handling and storage system
2462014017882406/26/14Optimizing lithographic processes using laser annealing techniques
2472014017556206/26/14Spacer divot sealing method and semiconductor device incorporating same
2482014017909306/26/14Gate structure formation processes
2492014016711906/19/14Methods of forming a sidewall spacer having a generally triangular shape and a semiconductor device having such a spacer


ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009



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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Globalfoundries, Inc. in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Globalfoundries, Inc. with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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