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Globalfoundries, Inc. patents


      
Recent patent applications related to Globalfoundries, Inc.. Globalfoundries, Inc. is listed as an Agent/Assignee. Note: Globalfoundries, Inc. may have other listings under different names/spellings. We're not affiliated with Globalfoundries, Inc., we're just tracking patents.

ARCHIVE: New 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries, Inc.-related inventors



Methods of forming different finfet devices having different fin heights and an integrated circuit product containing…

Globalfoundries

Methods of forming different finfet devices having different fin heights and an integrated circuit product containing…

Methods of forming transistors with retrograde wells in cmos applications and the resulting device structures

Globalfoundries

Methods of forming transistors with retrograde wells in cmos applications and the resulting device structures

Methods of forming transistors with retrograde wells in cmos applications and the resulting device structures

Globalfoundries

Finfet gate with insulated vias and method of making same

Search recent Press Releases: Globalfoundries, Inc.-related press releases
Count Application # Date Globalfoundries, Inc. patents (updated weekly) - BOOKMARK this page
12014036775112/18/14 new patent  Finfet spacer etch for esige improvement
22014036778712/18/14 new patent  Methods of forming transistors with retrograde wells in cmos applications and the resulting device structures
32014036778812/18/14 new patent  Methods of forming gate structures for cmos based integrated circuit products and the resulting devices
42014036779012/18/14 new patent  Methods of forming gate structures for cmos based integrated circuit products and the resulting devices
52014036779412/18/14 new patent  Device including an array of memory cells and well contact areas, and method for the formation thereof
62014036779512/18/14 new patent  Methods of forming different finfet devices having different fin heights and an integrated circuit product containing such devices
72014037043912/18/14 new patent  Reducing bubbles in layers of photoresist material
82014037069712/18/14 new patent  Removal of nitride bump in opening replacement gate structure
92014036780312/18/14 new patent  Finfet gate with insulated vias and method of making same
102014036782612/18/14 new patent  Making an efuse
112014037044712/18/14 new patent  Semiconductor device resolution enhancement by etching multiple sides of a mask
122014037070512/18/14 new patent  Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein
132014035372812/04/14A reduced capacitance middle-of-the-line (mol) nitride stack
142014035373412/04/14Semiconductor devices and methods of fabrication with reduced gate and contact resistances
152014035380212/04/14Methods for integration of pore stuffing material
162014035380512/04/14Methods of semiconductor contaminant removal using supercritical fluid
172014035707912/04/14Methods of forming conductive structures using a sacrificial material during a metal hard mask removal process
182014035955112/04/14Semiconductor voltage drop analysis
192014034664811/27/14Low-k nitride film and method of making
202014034666211/27/14Forming modified cell architecture for finfet technology and resulting device
212014034947811/27/14Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean process
222014034659911/27/14Finfet semiconductor devices with local isolation features and methods for fabricating the same
232014033961011/20/14Finfet device and method of fabrication
242014033961211/20/14Using sacrificial oxide layer for gate length tuning and resulting device
252014033962911/20/14Contact formation for ultra-scaled devices
262014033964711/20/14Densely packed standard cells for integrated circuit products, and methods of making same
272014034255611/20/14Reusing active area mask for trench transfer exposure
282014033566811/13/14Contact landing pads for a semiconductor device and methods of making same
292014032714611/06/14Methods for improving double patterning route efficiency
302014032713911/06/14Contact liner and methods of fabrication thereof
312014032715311/06/14Standard cell connection for circuit routing
322014032938811/06/14Methods of patterning features having differing widths
332014032714011/06/14Integrated circuits and methods for fabricating integrated circuits with improved contact structures
342014032746511/06/14Structures and methods for testing integrated circuits and via chains therein
352014031961710/30/14Methods of forming metal silicide regions on a semiconductor device
362014032476910/30/14Document driven methods of managing the content of databases that contain information relating to semiconductor manufacturing operations
372014031961410/30/14Finfet channel stress using tungsten contacts in raised epitaxial source and drain
382014031962010/30/14Methods for fabricating integrated circuits with polycrystalline silicon resistor structures using a replacment gate process flow, and the integrated circuits fabricated thereby
392014032420810/30/14Monitoring wafer handling and a wafer handling machine
402014031243410/23/14Finfet device with a graphene gate electrode and methods of forming same
412014031537110/23/14Methods of forming isolation regions for bulk finfet semiconductor devices
422014030631710/16/14Finfet fin height control
432014030810810/16/14System for separately handling different size foups
442014029994110/09/14Sram cell with reduced voltage droop
452014030266010/09/14Local interconnect to a protection diode
462014029184710/02/14Methods of forming a barrier system containing an alloy of metals introduced into the barrier system, and an integrated circuit product containing such a barrier system
472014029566410/02/14Methods of forming masking layers for use in forming integrated circuit products
482014028969509/25/14Evaluation of pin geometry accessibility in a layer of circuit
492014026438609/18/14Performance enhancement in pmos and nmos transistors on the basis of silicon/carbon material
502014026434209/18/14Semiconductor device including a resistor and method for the formation thereof
512014026434709/18/14Transistor with embedded strain-inducing material formed in cavities based on an amorphization process and a heat treatment
522014026434909/18/14Low thermal budget schemes in semiconductor device fabrication
532014026446109/18/14Metal layer enabling directed self-assembly semiconductor layout designs
542014026447909/18/14Methods of increasing space for contact elements by using a sacrificial liner and the resulting device
552014026448609/18/14Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
562014026448709/18/14Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
572014026448909/18/14Wrap around stressor formation
582014026461709/18/14Hk/mg process flows for p-type semiconductor devices
592014026462609/18/14Method for forming a gate electrode of a semiconductor device, gate electrode structure for a semiconductor device and according semiconductor device structure
602014026463109/18/14Methods of forming alignment marks and overlay marks on integrated circuit products employing finfet devices and the resulting alignment/overlay mark
612014026463209/18/14Semiconductor structure including a transistor having a layer of a stress-creating material and method for the formation thereof
622014026464109/18/14Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layers
632014026473109/18/14Programmable e-fuse for an integrated circuit product
642014026475809/18/14Methods of forming a protection layer to protect a metal hard mask layer during lithography reworking processes
652014026487609/18/14Multi-layer barrier layer stacks for interconnect structures
662014026487709/18/14Metallization systems of semiconductor devices comprising a copper/silicon compound as a barrier material
672014026489009/18/14Novel pillar structure for use in packaging integrated circuit products and methods of making such a pillar structure
682014027336509/18/14Methods of forming contacts to source/drain regions of finfet devices by forming a region that includes a schottky barrier lowering material
692014027336909/18/14Methods of forming contacts to source/drain regions of finfet devices
702014027338909/18/14Semiconductor device having controlled final metal critical dimension
712014027339609/18/14Method of forming a semiconductor structure including a metal-insulator-metal capacitor
722014027342309/18/14Methods of forming a semiconductor device with a nanowire channel structure by performing an anneal process
732014027342909/18/14Methods of forming finfet devices with a shared gate structure
742014027343609/18/14Methods of forming barrier layers for conductive copper structures
752014027345509/18/14Hard mask removal during finfet formation
762014027347309/18/14Methods of forming a masking layer for patterning underlying structures
772014027347409/18/14Interconnection designs using sidewall image transfer (sit)
782014028229609/18/14Hybrid method for performing full field optical proximity correction for finfet mandrel layer
792014028230109/18/14Stitch insertion for reducing color density differences in double patterning technology (dpt)
802014028230309/18/14Pattern-independent and hybrid matching/tuning including light manipulation by projection optics
812014028230709/18/14Providing metric relating two or more process parameters to yield
822014028232309/18/14Parameterized cell for planar and finfet technology design
832014028233009/18/14Priority based layout versus schematic (lvs)
842014028234509/18/14Via insertion in integrated circuit (ic) designs
852014026461309/18/14Integrated circuits and methods for fabricating integrated circuits with active area protection
862014026463309/18/14Finfet devices having a body contact and methods of forming the same
872014026898309/18/14Otprom array with leakage current cancelation for enhanced efuse sensing
882014026906009/18/14Integrated circuits and methods for operating integrated circuits with non-volatile memory
892014027267709/18/14Methods for fabricating euv masks and methods for fabricating integrated circuits using such euv masks
902014027329909/18/14Fabricating semiconductor device structures using different metrology tools
912014027330609/18/14Methods for fabricating integrated circuits including multi-patterning of masks for extreme ultraviolet lithography
922014027336709/18/14Integrated circuits and methods for fabricating integrated circuits with gate electrode structure protection
932014027337509/18/14Methods for fabricating integrated circuits with semiconductor substrate protection
942014027346309/18/14Methods for fabricating integrated circuits that include a sealed sidewall in a porous low-k dielectric layer
952014027347509/18/14Methods for fabricating guide patterns and methods for fabricating integrated circuits using such guide patterns
962014027351109/18/14Methods for fabricating integrated circuits including formation of chemical guide patterns for directed self-assembly lithography
972014027766809/18/14Fabricating integrated circuits utilizing universal and local processing management
982014025242409/11/14Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
992014025242509/11/14Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
1002014025242909/11/14Contact geometry having a gate silicon length decoupled from a transistor length
1012014025248009/11/14Combination finfet and planar fet semiconductor device and methods of making such a device
1022014025248109/11/14Transistor including a gate electrode extending all around one or more channel regions
1032014025255709/11/14Method for forming a semiconductor device and semiconductor device structures
1042014025261709/11/14Barrier layer conformality in copper interconnects
1052014025266009/11/14Multilayer pattern transfer for chemical guides
1062014025390209/11/14Multiple patterning process for forming trenches or holes using stitched assist features
1072014025401809/11/14Scattering enhanced thin absorber for euv reflective reticle and a method of making
1082014025606409/11/14Methods of repairing damaged insulating materials by introducing carbon into the layer of insulating material
1092014025609709/11/14Methods for forming integrated circuit systems employing fluorine doping
1102014025613509/11/14Methods of removing gate cap layers in cmos applications
1112014025613709/11/14Method of forming a semiconductor structure including an implantation of ions into a layer of spacer material
1122014025773809/11/14Hierarchically divided signal path for characterizing integrated circuits
1132014025896009/11/14Integrating optimal planar and three-dimensional semiconductor design layouts
1142014025614109/11/14Methods for fabricating integrated circuits utilizing silicon nitride layers
1152014024669609/04/14Transistor with embedded strain-inducing material formed in cavities formed in a silicon/germanium substrate
1162014024669809/04/14Channel sige removal from pfet source/drain region for improved silicide formation in hkmg technologies without embedded sige
1172014024673409/04/14Replacement metal gate with mulitiple titanium nitride laters
1182014024673509/04/14Metal gate structure for semiconductor devices
1192014024677509/04/14Methods of forming non-continuous conductive layers for conductive structures on an integrated circuit product
1202014024679109/04/1414 lpm contact power rail
1212014024743809/04/14Reticle defect correction by second exposure
1222014024874909/04/14Stress memorization technique
1232014024876409/04/14Methods of forming structures on an integrated circuit product
1242014024877009/04/14Microwave-assisted heating of strong acid solution to remove nickel platinum/platinum residues
1252014024877809/04/14Methods of forming asymmetric spacers on various structures on integrated circuit products
1262014024660509/04/14Defect removal process
1272014023804508/28/14Semiconductor device comprising a stacked die configuration including an integrated peltier element
1282014024278808/28/14Method of forming a high quality interfacial layer for a semiconductor device by performing a low temperature ald process
1292014024523808/28/14Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications
1302014023950308/28/14Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
1312014023124508/21/14Adjustable current shield for electroplating processes
1322014023190708/21/14Methods of inducing a desired stress in the channel region of a transistor by performing ion implantation/anneal processes on the gate electrode
1332014023196008/21/14Polysilicon resistor formation
1342014023243308/21/14Circuit element including a layer of a stress-creating material providing a variable stress and method for the formation thereof
1352014023301408/21/14Infrared-based metrology for detection of stress and defects around through silicon vias
1362014023188508/21/14Integrated circuits and methods for fabricating integrated circuits having metal gate electrodes
1372014023192208/21/14Semiconductor gate structure for threshold voltage modulation and method of making same
1382014023201008/21/14Integrated circuits and methods of forming the same with multi-level electrical connection
1392014023505508/21/14Method for fabricating a semiconductor integrated circuit with a litho-etch, litho-etch process for etching trenches
1402014022476408/14/14Chemical and physical templates for forming patterns using directed self-assembly materials
1412014022516808/14/14Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device
1422014022520108/14/14Edge and strap cell design for sram array
1432014022527008/14/14Method for off-grid routing structures utilizing self aligned double patterning (sadp) technology
1442014022784508/14/14Methods of forming multiple n-type semiconductor devices with different threshold voltages on a semiconductor substrate
1452014022784908/14/14Methods of trimming nanowire structures
1462014022785808/14/14Shallow trench isolation integration methods and devices formed thereby
1472014022786908/14/14Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions
1482014022787208/14/14Methods of forming conductive structures using a sacrificial liner layer
1492014022787908/14/14Methods for fabricating integrated circuits with improved semiconductor fin structures
1502014021746708/07/14Methods of forming substrates comprised of different semiconductor materials and the resulting device
1512014021748008/07/14Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer
1522014021754408/07/14Methods of forming a transistor device on a bulk substrate and the resulting device
1532014021758808/07/14Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device
1542014021759108/07/14Multi-layer barrier layer for interconnect structure
1552014022075608/07/14Methods of forming semiconductor devices by forming a semiconductor layer above source/drain regions prior to removing a gate cap layer
1562014022075908/07/14Methods for fabricating integrated circuits having gate to active and gate to gate interconnects
1572014022076708/07/14Double-pattern gate formation processing with critical dimension control
1582014022339008/07/14Retargeting semiconductor device shapes for multiple patterning processes
1592014022339208/07/14Optimized optical proximity correction handling for lithographic fills
1602014021748208/07/14Integrated circuits having replacement gate structures and methods for fabricating the same
1612014021751708/07/14Integrated circuits including finfet devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
1622014022077508/07/14Methods for fabricating integrated circuits having embedded electrical interconnects
1632014022078608/07/14Methods for optical proximity correction in the design and fabrication of integrated circuits
1642014021008807/31/14Method for reducing wettability of interconnect material at corner interface and device incorporating same
1652014021117507/31/14Enhancing resolution in lithographic processes using high refractive index fluids
1662014021541507/31/14Automated design layout pattern correction based on context-aware patterns
1672014020956307/31/14Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein
1682014021303307/31/14Methods for fabricating electrically-isolated finfet semiconductor devices
1692014021303707/31/14Methods for fabricating integrated circuits having confined epitaxial growth regions
1702014020328007/24/14Electrical test structure for devices employing high-k dielectrics or metal gates
1712014020329807/24/14Strained silicon carbide channel for electron mobility of nmos
1722014020333907/24/14Semiconductor device comprising self-aligned contact elements and a replacement gate electrode structure
1732014020337607/24/14Finfet integrated circuits with uniform fin height and methods for fabricating the same
1742014020340507/24/14Method to dynamically tune precision resistance
1752014020344607/24/14Through silicon via device having low stress, thin film gaps and methods for forming the same
1762014020381407/24/14Measuring alpha particle induced soft errors in semiconductor devices
1772014020615707/24/14Method of forming a semiconductor structure including a vertical nanowire
1782014020828507/24/14Self-aligned double patterning via enclosure design
1792014020327907/24/14Test structure and method to faciltiate development/optimization of process parameters
1802014020344907/24/14Integrated circuits and methods of forming the same with metal layer connection to through-semiconductor via
1812014020382707/24/14Integrated circuits and methods of forming the same with embedded interconnect connection to through-semiconductor via
1822014019746807/17/14Methods of forming semiconductor device with self-aligned contact elements and the resulting device
1832014019754407/17/14Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials
1842014019749807/17/14Integrated circuits and methods for fabricating integrated circuits with improved silicide contacts
1852014019984507/17/14Selective removal of gate structure sidewall(s) to facilitate sidewall spacer protection
1862014019132407/10/14Methods of forming bulk finfet devices by performing a recessing process on liner materials to define different fin heights and finfet devices with such recessed liner materials
1872014019133207/10/14Pfet devices with different structures and performance characteristics
1882014019395707/10/14Reducing gate height variance during semiconductor device formation
1892014018355107/03/14Blanket epi super steep retrograde well formation without si recess
1902014018363807/03/14Methods of using a trench salicide routing layer
1912014018372007/03/14Methods of manufacturing integrated circuits having a compressive nitride layer
1922014018503007/03/14Asymmetric reticle heating of multilayer reticles eliminated by dummy exposures and related methods
1932014018703607/03/14Integration of ru wet etch and cmp for beol interconnects with ru layer
1942014018374507/03/14Gate electrode(s) and contact structure(s), and methods of fabrication thereof
1952014017553906/26/14Canyon gate transistor and methods for its fabrication
1962014017816006/26/14Overhead substrate handling and storage system
1972014017882406/26/14Optimizing lithographic processes using laser annealing techniques
1982014017556206/26/14Spacer divot sealing method and semiconductor device incorporating same
1992014017909306/26/14Gate structure formation processes
2002014016711906/19/14Methods of forming a sidewall spacer having a generally triangular shape and a semiconductor device having such a spacer
2012014016712006/19/14Methods of forming a finfet semiconductor device by performing an epitaxial growth process
2022014016726406/19/14Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structures
2032014016726506/19/14Methods of forming a bi-layer cap layer on copper-based conductive structures and devices with such a cap layer
2042014017053306/19/14Extreme ultraviolet lithography (euvl) alternating phase shift mask
2052014017083906/19/14Methods of forming fins for a finfet device wherein the fins have a high germanium content
2062014017353306/19/14Locally optimized coloring for cleaning lithographic hotspots
2072014015905206/12/14Method and structure for transistor with reduced drain-induced barrier lowering and on resistance
2082014015912506/12/14Contact landing pads for a semiconductor device and methods of making same
2092014015912606/12/14Methods of forming a finfet semiconductor device with undoped fins
2102014015916406/12/14Double sidewall image transfer process
2112014015917106/12/14Methods of forming bulk finfet semiconductor devices by performing a liner recessing process to define fin heights and finfet devices with such a recessed liner
2122014015919906/12/14High density serial capacitor device and methods of making such a capacitor device
2132014016217606/12/14Semiconductor device resolution enhancement by etching multiple sides of a mask
2142014016244706/12/14Finfet hybrid full metal gate with borderless contacts
2152014015176006/05/14Doped flowable pre-metal dielectric
2162014015180706/05/14Combination finfet and planar fet semiconductor device and methods of making such a device
2172014015181606/05/14Novel contact structure for a semiconductor device and methods of making same
2182014015181806/05/14Semiconductor device with a silicon dioxide gate insulation layer implanted with a rare earth element and methods of making such a device
2192014014525705/29/14Semiconductor device having a metal recess
2202014014527405/29/14Methods of forming replacement gate structures for nfet semiconductor devices and devices having such gate structures
2212014014533205/29/14Methods of forming graphene liners and/or cap layers on copper-based conductive structures
2222014014801105/29/14Method of forming semiconductor fins
2232014014995205/29/14Trench silicide mask generation using designated trench transfer and trench block regions
2242014014160505/22/14Finfet formation using double patterning memorization
2252014013877905/22/14Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance
2262014013173505/15/14Source and drain doping using doped raised source and drain regions
2272014013177105/15/14Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof
2282014013180505/15/14Transistor with embedded si/ge material having reduced offset and superior uniformity
2292014013188105/15/14Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection
2302014013183105/15/14Integrated ciruit including an fin-based diode and methods of its fabrication
2312014013481405/15/14Methods of manufacturing integrated circuits having finfet structures with epitaxially formed source/drain regions
2322014013482205/15/14Methods for fabricating integrated circuits including semiconductive resistor structures in a finfet architecture
2332014012479405/08/14Fabrication of reverse shallow trench isolation structures with super-steep retrograde wells
2342014012484105/08/14Methods of forming replacement gate structures on semiconductor devices and the resulting device
2352014012999905/08/14Method for selectively modeling narrow-width stacked device performance
2362014011741705/01/14Performance enhancement in transistors by providing a graded embedded strain-inducing semiconductor region with adapted angles with respect to the substrate surface
2372014011741805/01/14Three-dimensional silicon-based transistor comprising a high-mobility channel formed by non-masked epitaxy
2382014011741905/01/14Fin etch and fin replacement for finfet integration
2392014011750705/01/14Double trench well formation in sram cells
2402014012067705/01/14Methods of forming enhanced mobility channel regions on 3d semiconductor devices, and devices comprising same
2412014011079804/24/14Methods of forming a semiconductor device with low-k spacers and the resulting device
2422014011085404/24/14Semiconductor dies with reduced area consumption
2432014011341904/24/14Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material
2442014011342004/24/14Methods of avoiding shadowing when forming source/drain implant regions on 3d semiconductor devices
2452014011345504/24/14Method of forming a semiconductor structure including a wet etch process for removing silicon nitride
2462014011077204/24/14Integrated circuit decoupling capacitor arrangement
2472014011079404/24/14Facilitating gate height uniformity and inter-layer dielectric protection
2482014010342004/17/14Advanced faraday shield for a semiconductor device
2492014010657504/17/14Directed self-assembly of block copolymers using laser annealing


ARCHIVE: New 2014 2013 2012 2011 2010 2009



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