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Globalfoundries Inc patents


      
Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors


Superior integrity of a high-k gate stack by forming a controlled undercut on the basis of a wet chemistry

Globalfoundries

Superior integrity of a high-k gate stack by forming a controlled undercut on the basis of a wet chemistry

Self-aligned dual-height isolation for bulk finfet

Globalfoundries

Self-aligned dual-height isolation for bulk finfet

Fabrication methods facilitating integration of different device architectures

Globalfoundries

Fabrication methods facilitating integration of different device architectures

Search recent Press Releases: Globalfoundries Inc-related press releases
Count Application # Date Globalfoundries Inc patents (updated weekly) - BOOKMARK this page
12015013723505/21/15 new patent  Finfet semiconductor device having local buried oxide
22015013719405/21/15 new patent  Inverted contact and methods of fabrication
32015013720305/21/15 new patent  Forming finfet cell with fin tip and resulting device
42015013723505/21/15 new patent  Finfet semiconductor device having local buried oxide
52015013723705/21/15 new patent  Undoped epitaxial layer for junction isolation in a fin field effect transistor (finfet) device
62015013725805/21/15 new patent  Forming a low votage antifuse device and resulting device
72015013727005/21/15 new patent  Superior integrity of a high-k gate stack by forming a controlled undercut on the basis of a wet chemistry
82015013727305/21/15 new patent  Method and device for self-aligned contact on a non-recessed metal gate
92015013730805/21/15 new patent  Self-aligned dual-height isolation for bulk finfet
102015013731605/21/15 new patent  Semiconductor device including a resistor and the formation thereof
112015013737205/21/15 new patent  Self forming barrier layer and forming
122015013855505/21/15 new patent  Overlay metrology system and method
132015014069505/21/15 new patent  Method and system for determining overlap process windows in semiconductors by inspection techniques
142015014075105/21/15 new patent  Modified, etch-resistant gate structure(s) facilitating circuit fabrication
152015014075605/21/15 new patent  Fabrication methods facilitating integration of different device architectures
162015014076105/21/15 new patent  Device isolation in finfet cmos
172015013737305/21/15 new patent  Integrated circuits and methods for fabricating integrated circuits with improved contact structures
182015013738505/21/15 new patent  Integrated circuits with close electrical contacts and methods for fabricating the same
192015014069705/21/15 new patent  Test macro for use with a multi-patterning lithography process
202015014069805/21/15 new patent  Test macro for use with a multi-patterning lithography process
212015012993405/14/15Methods of forming substantially self-aligned isolation regions on finfet semiconductor devices and the resulting devices
222015012996205/14/15Methods of forming replacement gate structures and fins on finfet devices and the resulting devices
232015012996405/14/15Nanowire transistor device
242015012996605/14/15Transistor including a gate electrode extending all around one or more channel regions
252015012997005/14/15Methods and structures for eliminating or reducing line end epi material growth on gate structures
262015012998305/14/15Fin-type transistor structures with extended embedded stress elements and fabrication methods
272015013002605/14/15Printing minimum width features at non-minimum pitch and resulting device
282015013006305/14/15Method to use self-repair cu barrier to solve barrier degradation due to ru cmp
292015013296205/14/15Facilitating mask pattern formation
302015012997205/14/15Methods of scaling thickness of a gate dielectric structure, methods of forming an integrated circuit, and integrated circuits
312015013006505/14/15Method to etch cu/ta/tan selectively using dilute aqueous hf/h2so4 solution
322015013291405/14/15Methods for fabricating integrated circuits with robust gate electrode structure protection
332015012314605/07/15Increased space between epitaxy on adjacent fins of finfet
342015012316605/07/15Methods of forming finfet devices with alternative channel materials
352015012318105/07/15Capacitors positioned at the device level in an integrated circuit product and methods of making such capacitors
362015012321105/07/15Narrow diffusion break for a fin field effect (finfet) transistor device
372015012321205/07/15Planar metrology pad adjacent a set of fins of a fin field effect transistor device
382015012321405/07/15Methods of forming a finfet semiconductor device with undoped fins
392015012325005/07/15Methods of fabricating defect-free semiconductor structures
402015012600805/07/15Methods of forming stressed multilayer finfet devices with alternative channel materials
412015012601005/07/15Band engineered semiconductor device and manufacturing thereof
422015012602305/07/15Methods of forming gate structures with multiple work functions and the resulting products
432015012602805/07/15Methods for fabricating integrated circuits using surface modification to selectively inhibit etching
442015012603405/07/15Methods for fabricating integrated circuits including topographical features for directed self-assembly
452015011515304/30/15Detection of particle contamination on wafers
462015011526704/30/15Planar metrology pad adjacent a set of fins of a fin field effect transistor device
472015011537004/30/15Semiconductor device providing enhanced fin isolation and related methods
482015011537104/30/15Finfet semiconductor structures and methods of fabricating same
492015011541804/30/15Devices and methods of forming fins at tight fin pitches
502015010857304/23/15Semiconductor device including vertically spaced semiconductor channel structures and related methods
512015010857704/23/15Selective growth of a work-function metal in a replacement metal gate of a semiconductor device
522015010858004/23/15Methods of forming bipolar devices and an integrated circuit product containing such bipolar devices
532015010858304/23/15Densely packed standard cells for integrated circuit products, and methods of making same
542015010858604/23/15Transistor device with improved source/drain junction architecture and methods of making such a device
552015010864604/23/15Electro-migration enhancing self-forming barrier process in copper mettalization
562015011131604/23/15Method for detecting defects in a diffusion barrier layer
572015011134904/23/15Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and the formation thereof
582015011348404/23/15Methods of generating circuit layouts that are to be manufactured using sadp routing techniques
592015010864704/23/15Hybrid manganese and manganese nitride barriers for back-end-of-line metallization and methods for fabricating the same
602015011137304/23/15Reducing gate height variation in rmg process
612015010241004/16/15Semiconductor device including stress layer adjacent channel and related methods
622015010241704/16/15Double trench well formation in sram cells
632015010242604/16/15Three-dimensional transistor with improved channel mobility
642015010282604/16/15Design structures and methods for extraction of device channel width
652015010491804/16/15Facilitating fabricating gate-all-around nanowire field-effect transistors
662015010494804/16/15Facilitating etch processing of a thin film via partial implantation thereof
672015010242204/16/15Integrated circuits including finfet devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
682015010530804/16/15Aqua regia and hydrogen peroxide hcl combination to remove ni and nipt residues
692015009719704/09/15Finfet with sigma cavity with multiple epitaxial material regions
702015009724604/09/15Integrated circuit and fabricating the same having a replacement gate structure
712015009724904/09/15Cross coupling gate using mulitple patterning
722015009725204/09/15Simplified gate-first hkmg manufacturing flow
732015009726304/09/15Method and high yield contact integration scheme
742015009934004/09/15Methods for preventing oxidation damage during finfet fabrication
752015009729104/09/15Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
762015009933604/09/15Methods of manufacturing integrated circuits having finfet structures with epitaxially formed source/drain regions
772015009109404/02/15Devices and methods of forming finfets with self aligned fin formation
782015009109704/02/15Hardmask for a halo/extension implant of a static random access memory (sram) layout
792015009387704/02/15Method for manufacturing a semiconductor device by stopping planarization of insulating material on fins
802015009388704/02/15Methods for removing a native oxide layer from germanium susbtrates in the fabrication of integrated circuitsi
812015009388904/02/15Methods for removing a native oxide layer from germanium susbtrates in the fabrication of integrated circuits
822015009391404/02/15Methods for depositing an aluminum oxide layer over germanium susbtrates in the fabrication of integrated circuits
832015008413103/26/15Gate height uniformity in semiconductor devices
842015008713403/26/15Semiconductor isolation region uniformity
852015008418303/26/15Integrated circuits with protected resistors and methods for fabricating the same
862015008714903/26/15Methods for fabricating integrated circuits using improved masks
872015007708603/19/15Fin width measurement using quantum well structure
882015007611103/19/15Feature etching using varying supply of power pulses
892015007660903/19/15Methods of forming stressed layers on finfet semiconductor devices and the resulting devices
902015007662203/19/15Reducing gate expansion after source and drain implant in gate last process
912015007665303/19/15Overlay performance for a fin field effect transistor device
922015007670503/19/15Reduced capacitance interlayer structures and fabrication methods
932015007806803/19/15Integrated circuits with sram cells having additional read stacks
942015007977303/19/15Conformal doping for finfet devices
952015007655903/19/15Integrated circuits with strained silicon and methods for fabricating such circuits
962015007656003/19/15Integrated circuits including epitaxially grown strain-inducing fills doped with boron for improved robustness from delimination and methods for fabricating the same
972015007661803/19/15Integrated circuits with a corrugated gate, and methods for producing the same
982015007662403/19/15Integrated circuits having smooth metal gates and methods for fabricating same
992015006951503/12/15Integrated circuits having laterally confined epitaxial material overlying fin structures and methods for fabricating same
1002015006096003/05/15Methods of forming contact structures on finfet semiconductor devices and the resulting devices
1012015006098303/05/15Semiconductor structure including a split gate nonvolatile memory cell and a high voltage transistor, and the formation thereof
1022015006101403/05/15Fin pitch scaling and active layer isolation
1032015006102703/05/15Methods of forming gate structures for transistor devices for cmos applications and the resulting products
1042015006103203/05/15Fabrication of nickel free silicide for semiconductor contact metallization
1052015006113503/05/15Copper interconnect with cvd liner and metallic cap
1062015006299603/05/15Embedded selector-less one-time programmable non-volatile memory
1072015006481203/05/15Method of forming a semiconductor device employing an optical planarization layer
1082015006487203/05/15Top corner rounding by implant-enhanced wet etching
1092015006763303/05/15Color-insensitive rules for routing structures
1102015006104003/05/15Self-aligned dielectric isolation for finfet devices
1112015006490303/05/15Methods for fabricating integrated circuits using chemical mechanical planarization to recess metal
1122015006491203/05/15Methods of forming integrated circuits and multiple critical dimension self-aligned double patterning processes
1132015005398102/26/15Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device
1142015005407802/26/15Methods of forming gate structures for finfet devices and the resulting smeiconductor products
1152015005408302/26/15Strain engineering in semiconductor devices by using a piezoelectric material
1162015005413902/26/15Through-silicon via with sidewall air gap
1172015005679602/26/15Method for forming a semiconductor device having a metal gate recess
1182015005678102/26/15Gate length independent silicon-on-nothing (son) scheme for bulk finfets
1192015005682002/26/15Systems and methods of solvent temperature control for wafer coating processes
1202015004844602/19/15Reduction of oxide recesses for gate height control
1212015005078702/19/15Fully silicided gate formed according to the gate-first hkmg approach
1222015005079202/19/15Extra narrow diffusion break for 3d finfet technologies
1232015005081102/19/15Critical dimension and pattern recognition structures for devices manufactured using double patterning techniques
1242015005081202/19/15Wafer-less auto clean of processing chamber
1252015005210802/19/15Method, computer readable storage medium and computer system for obtaining snapshots of data
1262015005249402/19/15Power rail layout for dense standard cell library
1272015004186902/12/15Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
1282015004189802/12/15Bulk finfet semiconductor-on-nothing integration
1292015004190502/12/15Methods of forming replacement gate structures for transistors and the resulting devices
1302015004190602/12/15Methods of forming stressed fin channel structures for finfet semiconductor devices
1312015004190902/12/15Completing middle of line integration allowing for self-aligned contacts
1322015004485502/12/15Methods of forming spacers on finfets and other semiconductor devices
1332015004486102/12/15Gate silicidation
1342015004185802/12/153d transistor channel mobility enhancement
1352015004191002/12/15Integrated circuits with a partially-depleted region formed over a bulk silicon substrate and methods for fabricating the same
1362015004191102/12/153d transistor channel mobility enhancement
1372015003501602/05/15Nitride spacer for protecting a fin-shaped field effect transistor (finfet) device
1382015003501802/05/15Devices and methods of forming bulk finfets with lateral seg for source and drain on dielectrics
1392015003505202/05/15Contact power rail
1402015003505302/05/15Device and a ldmos design for a finfet integrated circuit
1412015003507302/05/15Enabling enhanced reliability and mobility for replacement gate planar and finfet structures
1422015003508602/05/15Methods of forming cap layers for semiconductor devices with self-aligned contact elements and the resulting devices
1432015003697802/05/15Blazed grating spectral purity filter and methods of making such a filter
1442015003794502/05/15Epitaxially forming a set of fins in a semiconductor device
1452015003494102/05/15Integrated circuits having finfet semiconductor devices and methods of fabricating the same to resist sub-fin current leakage
1462015003506202/05/15Integrated circuits having finfets with improved doped channel regions and methods for fabricating same
1472015003760302/05/15Articles including metal structures having maximized bond adhesion and bond reliability, and methods of forming the same
1482015004007802/05/15Methods and systems for designing and manufacturing optical lithography masks
1492015004008002/05/15Methods for modifying an integrated circuit layout design
1502015004009102/05/15Methods for modifying an integrated circuit layout design
1512015002834801/29/15Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (finfet) device
1522015002843101/29/15Mol insitu pt rework sequence
1532015002848201/29/15Device layout for reducing through-silicon-via stress
1542015002848901/29/15Method for off-grid routing structures utilizing self aligned double patterning (sadp) technology
1552015002850001/29/15Forming alignment mark and resulting mark
1562015003117901/29/15Method of forming a semiconductor structure including silicided and non-silicided circuit elements
1572015003320101/29/15Systems and methods for fabricating semiconductor device structures
1582015002166301/22/15Finfet with insulator under channel
1592015002168301/22/15Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
1602015002169101/22/15Finfet with electrically isolated active region on bulk semiconductor substrate and fabricating same
1612015002169301/22/15Enhancing transistor performance and reliability by incorporating deuterium into a strained capping layer
1622015002169501/22/15Epitaxial block layer for a fin field effect transistor device
1632015002170201/22/15Shallow trench isolation
1642015002170301/22/15Gate oxide quality for complex mosfet devices
1652015002170401/22/15Finfet work function metal formation
1662015002170901/22/15Structures and methods integrating different fin device architectures
1672015002171201/22/15Highly conformal extension doping in advanced multi-gate devices
1682015002455701/22/15Semiconductor device having local buried oxide
1692015002456001/22/15Gate encapsulation achieved by single-step deposition
1702015002457201/22/15Process for faciltiating fin isolation schemes
1712015002457301/22/15Methods of forming replacement fins for a finfet semiconductor device by performing a replacement growth process
1722015002458501/22/15Systems and methods for fabricating gate structures for semiconductor devices
1732015002169401/22/15Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating the same
1742015002171401/22/15Integrated circuits having a metal gate structure and methods for fabricating the same
1752015002358301/22/15Methods and systems for determining a dose-to-clear of a photoresist
1762015002457801/22/15Methods for etching dielectric materials in the fabrication of integrated circuits
1772015001477701/15/15Channel semiconductor alloy layer growth adjusted by impurity ion implantation
1782015001481301/15/15Complex circuit element and capacitor utilizing cmos compatible antiferroelectric high-k materials
1792015001484301/15/15Semiconductor device with improved metal pillar configuration
1802015001777401/15/15Method of forming fins with recess shapes
1812015001780301/15/15Customized alleviation of stresses generated by through-substrate via(s)
1822015001477601/15/15Finfet integrated circuits and methods for their fabrication
1832015001617401/15/15Integrated circuits with programmable electrical connections and methods for fabricating the same
1842015000853601/08/15Semiconductor device structure and forming a semiconductor device structure
1852015000975001/08/15Device including a dual port static random access memory cell and the formation thereof
1862015001085101/08/15Methods involving color-aware retargeting of individual decomposed patterns when designing masks to be used in multiple patterning processes
1872015001289601/08/15Methods for fabricating integrated circuits including generating photomasks for directed self-assembly
1882015000162701/01/15Spacer chamfering for a replacement metal gate device
1892015000163401/01/15Methods of forming bipolar devices and an integrated circuit product containing such bipolar devices
1902015000163501/01/15Methods of forming an e-fuse for an integrated circuit product and the resulting integrated circuit product
1912015000164001/01/15Transistor device with improved source/drain junction architecture and methods of making such a device
1922015000164201/01/15Field effect transistor and fabrication
1932015000613801/01/15Optical proximity correction for connecting via between layers of a device
1942015000159101/01/15Bulk finfet with partial dielectric isolation featuring a punch-through stopping layer under the oxide
1952015000163001/01/15Structure and methods of fabricating y-shaped dmos finfet
1962015000164301/01/15Integrated circuits having improved high-k dielectric layers and methods for fabrication of same
1972014037480712/25/14Method of device isolation in cladding si through in situ doping
1982014037491512/25/14Integration of optical components in integrated circuits
1992014037796512/25/14Directed self-assembly (dsa) formulations used to form dsa-based lithography films
2002014036775112/18/14Finfet spacer etch for esige improvement
2012014036778712/18/14Methods of forming transistors with retrograde wells in cmos applications and the resulting device structures
2022014036778812/18/14Methods of forming gate structures for cmos based integrated circuit products and the resulting devices
2032014036779012/18/14Methods of forming gate structures for cmos based integrated circuit products and the resulting devices
2042014036779412/18/14Device including an array of memory cells and well contact areas, and the formation thereof
2052014036779512/18/14Methods of forming different finfet devices having different fin heights and an integrated circuit product containing such devices
2062014037043912/18/14Methods and systems for reducing bubbles in layers of photoresist material
2072014037069712/18/14Removal of nitride bump in opening replacement gate structure
2082014036780312/18/14Finfet gate with insulated vias and making same
2092014036782612/18/14Making an efuse
2102014037044712/18/14Semiconductor device resolution enhancement by etching multiple sides of a mask
2112014037070512/18/14Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein
2122014035372812/04/14Method and a reduced capacitance middle-of-the-line (mol) nitride stack
2132014035373412/04/14Semiconductor devices and methods of fabrication with reduced gate and contact resistances
2142014035380212/04/14Methods for integration of pore stuffing material
2152014035380512/04/14Methods of semiconductor contaminant removal using supercritical fluid
2162014035707912/04/14Methods of forming conductive structures using a sacrificial material during a metal hard mask removal process
2172014035955112/04/14Systems and methods for semiconductor voltage drop analysis
2182014034664811/27/14Low-k nitride film and making
2192014034666211/27/14Forming modified cell architecture for finfet technology and resulting device
2202014034947811/27/14Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean process
2212014034659911/27/14Finfet semiconductor devices with local isolation features and methods for fabricating the same
2222014033961011/20/14Finfet device and fabrication
2232014033961211/20/14Using sacrificial oxide layer for gate length tuning and resulting device
2242014033962911/20/14Contact formation for ultra-scaled devices
2252014033964711/20/14Densely packed standard cells for integrated circuit products, and methods of making same
2262014034255611/20/14Reusing active area mask for trench transfer exposure
2272014033566811/13/14Contact landing pads for a semiconductor device and methods of making same
2282014032714611/06/14Methods for improving double patterning route efficiency
2292014032713911/06/14Contact liner and methods of fabrication thereof
2302014032715311/06/14Standard cell connection for circuit routing
2312014032938811/06/14Methods of patterning features having differing widths
2322014032714011/06/14Integrated circuits and methods for fabricating integrated circuits with improved contact structures
2332014032746511/06/14Structures and methods for testing integrated circuits and via chains therein
2342014031961710/30/14Methods of forming metal silicide regions on a semiconductor device
2352014032476910/30/14Document driven methods of managing the content of databases that contain information relating to semiconductor manufacturing operations
2362014031961410/30/14Finfet channel stress using tungsten contacts in raised epitaxial source and drain
2372014031962010/30/14Methods for fabricating integrated circuits with polycrystalline silicon resistor structures using a replacment gate process flow, and the integrated circuits fabricated thereby
2382014032420810/30/14System and monitoring wafer handling and a wafer handling machine
2392014031243410/23/14Finfet device with a graphene gate electrode and methods of forming same
2402014031537110/23/14Methods of forming isolation regions for bulk finfet semiconductor devices
2412014030631710/16/14Finfet fin height control
2422014030810810/16/14System for separately handling different size foups
2432014029994110/09/14Sram cell with reduced voltage droop
2442014030266010/09/14Local interconnect to a protection diode
2452014029184710/02/14Methods of forming a barrier system containing an alloy of metals introduced into the barrier system, and an integrated circuit product containing such a barrier system
2462014029566410/02/14Methods of forming masking layers for use in forming integrated circuit products
2472014028969509/25/14Evaluation of pin geometry accessibility in a layer of circuit
2482014026438609/18/14Performance enhancement in pmos and nmos transistors on the basis of silicon/carbon material
2492014026434209/18/14Semiconductor device including a resistor and the formation thereof



ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009



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