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Globalfoundries Inc patents


      
Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors


Integrated circuits including finfet devices with lower contact resistance and reduced parasitic capacitance and methods…

Globalfoundries

Integrated circuits including finfet devices with lower contact resistance and reduced parasitic capacitance and methods…

Facilitating etch processing of a thin film via partial implantation thereof

Globalfoundries

Facilitating etch processing of a thin film via partial implantation thereof

Double trench well formation in sram cells

Globalfoundries

Double trench well formation in sram cells

Search recent Press Releases: Globalfoundries Inc-related press releases
Count Application # Date Globalfoundries Inc patents (updated weekly) - BOOKMARK this page
12015010241004/16/15 new patent  Semiconductor device including stress layer adjacent channel and related methods
22015010241704/16/15 new patent  Double trench well formation in sram cells
32015010242604/16/15 new patent  Three-dimensional transistor with improved channel mobility
42015010282604/16/15 new patent  Design structures and methods for extraction of device channel width
52015010491804/16/15 new patent  Facilitating fabricating gate-all-around nanowire field-effect transistors
62015010494804/16/15 new patent  Facilitating etch processing of a thin film via partial implantation thereof
72015010242204/16/15 new patent  Integrated circuits including finfet devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
82015010530804/16/15 new patent  Aqua regia and hydrogen peroxide hcl combination to remove ni and nipt residues
92015009719704/09/15Finfet with sigma cavity with multiple epitaxial material regions
102015009724604/09/15Integrated circuit and fabricating the same having a replacement gate structure
112015009724904/09/15Cross coupling gate using mulitple patterning
122015009725204/09/15Simplified gate-first hkmg manufacturing flow
132015009726304/09/15Method and high yield contact integration scheme
142015009934004/09/15Methods for preventing oxidation damage during finfet fabrication
152015009729104/09/15Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
162015009933604/09/15Methods of manufacturing integrated circuits having finfet structures with epitaxially formed source/drain regions
172015009109404/02/15Devices and methods of forming finfets with self aligned fin formation
182015009109704/02/15Hardmask for a halo/extension implant of a static random access memory (sram) layout
192015009387704/02/15Method for manufacturing a semiconductor device by stopping planarization of insulating material on fins
202015009388704/02/15Methods for removing a native oxide layer from germanium susbtrates in the fabrication of integrated circuitsi
212015009388904/02/15Methods for removing a native oxide layer from germanium susbtrates in the fabrication of integrated circuits
222015009391404/02/15Methods for depositing an aluminum oxide layer over germanium susbtrates in the fabrication of integrated circuits
232015008413103/26/15Gate height uniformity in semiconductor devices
242015008713403/26/15Semiconductor isolation region uniformity
252015008418303/26/15Integrated circuits with protected resistors and methods for fabricating the same
262015008714903/26/15Methods for fabricating integrated circuits using improved masks
272015007708603/19/15Fin width measurement using quantum well structure
282015007611103/19/15Feature etching using varying supply of power pulses
292015007660903/19/15Methods of forming stressed layers on finfet semiconductor devices and the resulting devices
302015007662203/19/15Reducing gate expansion after source and drain implant in gate last process
312015007665303/19/15Overlay performance for a fin field effect transistor device
322015007670503/19/15Reduced capacitance interlayer structures and fabrication methods
332015007806803/19/15Integrated circuits with sram cells having additional read stacks
342015007977303/19/15Conformal doping for finfet devices
352015007655903/19/15Integrated circuits with strained silicon and methods for fabricating such circuits
362015007656003/19/15Integrated circuits including epitaxially grown strain-inducing fills doped with boron for improved robustness from delimination and methods for fabricating the same
372015007661803/19/15Integrated circuits with a corrugated gate, and methods for producing the same
382015007662403/19/15Integrated circuits having smooth metal gates and methods for fabricating same
392015006951503/12/15Integrated circuits having laterally confined epitaxial material overlying fin structures and methods for fabricating same
402015006096003/05/15Methods of forming contact structures on finfet semiconductor devices and the resulting devices
412015006098303/05/15Semiconductor structure including a split gate nonvolatile memory cell and a high voltage transistor, and the formation thereof
422015006101403/05/15Fin pitch scaling and active layer isolation
432015006102703/05/15Methods of forming gate structures for transistor devices for cmos applications and the resulting products
442015006103203/05/15Fabrication of nickel free silicide for semiconductor contact metallization
452015006113503/05/15Copper interconnect with cvd liner and metallic cap
462015006299603/05/15Embedded selector-less one-time programmable non-volatile memory
472015006481203/05/15Method of forming a semiconductor device employing an optical planarization layer
482015006487203/05/15Top corner rounding by implant-enhanced wet etching
492015006763303/05/15Color-insensitive rules for routing structures
502015006104003/05/15Self-aligned dielectric isolation for finfet devices
512015006490303/05/15Methods for fabricating integrated circuits using chemical mechanical planarization to recess metal
522015006491203/05/15Methods of forming integrated circuits and multiple critical dimension self-aligned double patterning processes
532015005398102/26/15Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device
542015005407802/26/15Methods of forming gate structures for finfet devices and the resulting smeiconductor products
552015005408302/26/15Strain engineering in semiconductor devices by using a piezoelectric material
562015005413902/26/15Through-silicon via with sidewall air gap
572015005679602/26/15Method for forming a semiconductor device having a metal gate recess
582015005678102/26/15Gate length independent silicon-on-nothing (son) scheme for bulk finfets
592015005682002/26/15Systems and methods of solvent temperature control for wafer coating processes
602015004844602/19/15Reduction of oxide recesses for gate height control
612015005078702/19/15Fully silicided gate formed according to the gate-first hkmg approach
622015005079202/19/15Extra narrow diffusion break for 3d finfet technologies
632015005081102/19/15Critical dimension and pattern recognition structures for devices manufactured using double patterning techniques
642015005081202/19/15Wafer-less auto clean of processing chamber
652015005210802/19/15Method, computer readable storage medium and computer system for obtaining snapshots of data
662015005249402/19/15Power rail layout for dense standard cell library
672015004186902/12/15Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
682015004189802/12/15Bulk finfet semiconductor-on-nothing integration
692015004190502/12/15Methods of forming replacement gate structures for transistors and the resulting devices
702015004190602/12/15Methods of forming stressed fin channel structures for finfet semiconductor devices
712015004190902/12/15Completing middle of line integration allowing for self-aligned contacts
722015004485502/12/15Methods of forming spacers on finfets and other semiconductor devices
732015004486102/12/15Gate silicidation
742015004185802/12/153d transistor channel mobility enhancement
752015004191002/12/15Integrated circuits with a partially-depleted region formed over a bulk silicon substrate and methods for fabricating the same
762015004191102/12/153d transistor channel mobility enhancement
772015003501602/05/15Nitride spacer for protecting a fin-shaped field effect transistor (finfet) device
782015003501802/05/15Devices and methods of forming bulk finfets with lateral seg for source and drain on dielectrics
792015003505202/05/15Contact power rail
802015003505302/05/15Device and a ldmos design for a finfet integrated circuit
812015003507302/05/15Enabling enhanced reliability and mobility for replacement gate planar and finfet structures
822015003508602/05/15Methods of forming cap layers for semiconductor devices with self-aligned contact elements and the resulting devices
832015003697802/05/15Blazed grating spectral purity filter and methods of making such a filter
842015003794502/05/15Epitaxially forming a set of fins in a semiconductor device
852015003494102/05/15Integrated circuits having finfet semiconductor devices and methods of fabricating the same to resist sub-fin current leakage
862015003506202/05/15Integrated circuits having finfets with improved doped channel regions and methods for fabricating same
872015003760302/05/15Articles including metal structures having maximized bond adhesion and bond reliability, and methods of forming the same
882015004007802/05/15Methods and systems for designing and manufacturing optical lithography masks
892015004008002/05/15Methods for modifying an integrated circuit layout design
902015004009102/05/15Methods for modifying an integrated circuit layout design
912015002834801/29/15Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (finfet) device
922015002843101/29/15Mol insitu pt rework sequence
932015002848201/29/15Device layout for reducing through-silicon-via stress
942015002848901/29/15Method for off-grid routing structures utilizing self aligned double patterning (sadp) technology
952015002850001/29/15Forming alignment mark and resulting mark
962015003117901/29/15Method of forming a semiconductor structure including silicided and non-silicided circuit elements
972015003320101/29/15Systems and methods for fabricating semiconductor device structures
982015002166301/22/15Finfet with insulator under channel
992015002168301/22/15Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
1002015002169101/22/15Finfet with electrically isolated active region on bulk semiconductor substrate and fabricating same
1012015002169301/22/15Enhancing transistor performance and reliability by incorporating deuterium into a strained capping layer
1022015002169501/22/15Epitaxial block layer for a fin field effect transistor device
1032015002170201/22/15Shallow trench isolation
1042015002170301/22/15Gate oxide quality for complex mosfet devices
1052015002170401/22/15Finfet work function metal formation
1062015002170901/22/15Structures and methods integrating different fin device architectures
1072015002171201/22/15Highly conformal extension doping in advanced multi-gate devices
1082015002455701/22/15Semiconductor device having local buried oxide
1092015002456001/22/15Gate encapsulation achieved by single-step deposition
1102015002457201/22/15Process for faciltiating fin isolation schemes
1112015002457301/22/15Methods of forming replacement fins for a finfet semiconductor device by performing a replacement growth process
1122015002458501/22/15Systems and methods for fabricating gate structures for semiconductor devices
1132015002169401/22/15Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating the same
1142015002171401/22/15Integrated circuits having a metal gate structure and methods for fabricating the same
1152015002358301/22/15Methods and systems for determining a dose-to-clear of a photoresist
1162015002457801/22/15Methods for etching dielectric materials in the fabrication of integrated circuits
1172015001477701/15/15Channel semiconductor alloy layer growth adjusted by impurity ion implantation
1182015001481301/15/15Complex circuit element and capacitor utilizing cmos compatible antiferroelectric high-k materials
1192015001484301/15/15Semiconductor device with improved metal pillar configuration
1202015001777401/15/15Method of forming fins with recess shapes
1212015001780301/15/15Customized alleviation of stresses generated by through-substrate via(s)
1222015001477601/15/15Finfet integrated circuits and methods for their fabrication
1232015001617401/15/15Integrated circuits with programmable electrical connections and methods for fabricating the same
1242015000853601/08/15Semiconductor device structure and forming a semiconductor device structure
1252015000975001/08/15Device including a dual port static random access memory cell and the formation thereof
1262015001085101/08/15Methods involving color-aware retargeting of individual decomposed patterns when designing masks to be used in multiple patterning processes
1272015001289601/08/15Methods for fabricating integrated circuits including generating photomasks for directed self-assembly
1282015000162701/01/15Spacer chamfering for a replacement metal gate device
1292015000163401/01/15Methods of forming bipolar devices and an integrated circuit product containing such bipolar devices
1302015000163501/01/15Methods of forming an e-fuse for an integrated circuit product and the resulting integrated circuit product
1312015000164001/01/15Transistor device with improved source/drain junction architecture and methods of making such a device
1322015000164201/01/15Field effect transistor and fabrication
1332015000613801/01/15Optical proximity correction for connecting via between layers of a device
1342015000159101/01/15Bulk finfet with partial dielectric isolation featuring a punch-through stopping layer under the oxide
1352015000163001/01/15Structure and methods of fabricating y-shaped dmos finfet
1362015000164301/01/15Integrated circuits having improved high-k dielectric layers and methods for fabrication of same
1372014037480712/25/14Method of device isolation in cladding si through in situ doping
1382014037491512/25/14Integration of optical components in integrated circuits
1392014037796512/25/14Directed self-assembly (dsa) formulations used to form dsa-based lithography films
1402014036775112/18/14Finfet spacer etch for esige improvement
1412014036778712/18/14Methods of forming transistors with retrograde wells in cmos applications and the resulting device structures
1422014036778812/18/14Methods of forming gate structures for cmos based integrated circuit products and the resulting devices
1432014036779012/18/14Methods of forming gate structures for cmos based integrated circuit products and the resulting devices
1442014036779412/18/14Device including an array of memory cells and well contact areas, and the formation thereof
1452014036779512/18/14Methods of forming different finfet devices having different fin heights and an integrated circuit product containing such devices
1462014037043912/18/14Methods and systems for reducing bubbles in layers of photoresist material
1472014037069712/18/14Removal of nitride bump in opening replacement gate structure
1482014036780312/18/14Finfet gate with insulated vias and making same
1492014036782612/18/14Making an efuse
1502014037044712/18/14Semiconductor device resolution enhancement by etching multiple sides of a mask
1512014037070512/18/14Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein
1522014035372812/04/14Method and a reduced capacitance middle-of-the-line (mol) nitride stack
1532014035373412/04/14Semiconductor devices and methods of fabrication with reduced gate and contact resistances
1542014035380212/04/14Methods for integration of pore stuffing material
1552014035380512/04/14Methods of semiconductor contaminant removal using supercritical fluid
1562014035707912/04/14Methods of forming conductive structures using a sacrificial material during a metal hard mask removal process
1572014035955112/04/14Systems and methods for semiconductor voltage drop analysis
1582014034664811/27/14Low-k nitride film and making
1592014034666211/27/14Forming modified cell architecture for finfet technology and resulting device
1602014034947811/27/14Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean process
1612014034659911/27/14Finfet semiconductor devices with local isolation features and methods for fabricating the same
1622014033961011/20/14Finfet device and fabrication
1632014033961211/20/14Using sacrificial oxide layer for gate length tuning and resulting device
1642014033962911/20/14Contact formation for ultra-scaled devices
1652014033964711/20/14Densely packed standard cells for integrated circuit products, and methods of making same
1662014034255611/20/14Reusing active area mask for trench transfer exposure
1672014033566811/13/14Contact landing pads for a semiconductor device and methods of making same
1682014032714611/06/14Methods for improving double patterning route efficiency
1692014032713911/06/14Contact liner and methods of fabrication thereof
1702014032715311/06/14Standard cell connection for circuit routing
1712014032938811/06/14Methods of patterning features having differing widths
1722014032714011/06/14Integrated circuits and methods for fabricating integrated circuits with improved contact structures
1732014032746511/06/14Structures and methods for testing integrated circuits and via chains therein
1742014031961710/30/14Methods of forming metal silicide regions on a semiconductor device
1752014032476910/30/14Document driven methods of managing the content of databases that contain information relating to semiconductor manufacturing operations
1762014031961410/30/14Finfet channel stress using tungsten contacts in raised epitaxial source and drain
1772014031962010/30/14Methods for fabricating integrated circuits with polycrystalline silicon resistor structures using a replacment gate process flow, and the integrated circuits fabricated thereby
1782014032420810/30/14System and monitoring wafer handling and a wafer handling machine
1792014031243410/23/14Finfet device with a graphene gate electrode and methods of forming same
1802014031537110/23/14Methods of forming isolation regions for bulk finfet semiconductor devices
1812014030631710/16/14Finfet fin height control
1822014030810810/16/14System for separately handling different size foups
1832014029994110/09/14Sram cell with reduced voltage droop
1842014030266010/09/14Local interconnect to a protection diode
1852014029184710/02/14Methods of forming a barrier system containing an alloy of metals introduced into the barrier system, and an integrated circuit product containing such a barrier system
1862014029566410/02/14Methods of forming masking layers for use in forming integrated circuit products
1872014028969509/25/14Evaluation of pin geometry accessibility in a layer of circuit
1882014026438609/18/14Performance enhancement in pmos and nmos transistors on the basis of silicon/carbon material
1892014026434209/18/14Semiconductor device including a resistor and the formation thereof
1902014026434709/18/14Transistor with embedded strain-inducing material formed in cavities based on an amorphization process and a heat treatment
1912014026434909/18/14Low thermal budget schemes in semiconductor device fabrication
1922014026446109/18/14Metal layer enabling directed self-assembly semiconductor layout designs
1932014026447909/18/14Methods of increasing space for contact elements by using a sacrificial liner and the resulting device
1942014026448609/18/14Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
1952014026448709/18/14Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
1962014026448909/18/14Wrap around stressor formation
1972014026461709/18/14Hk/mg process flows for p-type semiconductor devices
1982014026462609/18/14Method for forming a gate electrode of a semiconductor device, gate electrode structure for a semiconductor device and according semiconductor device structure
1992014026463109/18/14Methods of forming alignment marks and overlay marks on integrated circuit products employing finfet devices and the resulting alignment/overlay mark
2002014026463209/18/14Semiconductor structure including a transistor having a layer of a stress-creating material and the formation thereof
2012014026464109/18/14Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layers
2022014026473109/18/14Programmable e-fuse for an integrated circuit product
2032014026475809/18/14Methods of forming a protection layer to protect a metal hard mask layer during lithography reworking processes
2042014026487609/18/14Multi-layer barrier layer stacks for interconnect structures
2052014026487709/18/14Metallization systems of semiconductor devices comprising a copper/silicon compound as a barrier material
2062014026489009/18/14Novel pillar structure for use in packaging integrated circuit products and methods of making such a pillar structure
2072014027336509/18/14Methods of forming contacts to source/drain regions of finfet devices by forming a region that includes a schottky barrier lowering material
2082014027336909/18/14Methods of forming contacts to source/drain regions of finfet devices
2092014027338909/18/14Semiconductor device having controlled final metal critical dimension
2102014027339609/18/14Method of forming a semiconductor structure including a metal-insulator-metal capacitor
2112014027342309/18/14Methods of forming a semiconductor device with a nanowire channel structure by performing an anneal process
2122014027342909/18/14Methods of forming finfet devices with a shared gate structure
2132014027343609/18/14Methods of forming barrier layers for conductive copper structures
2142014027345509/18/14Hard mask removal during finfet formation
2152014027347309/18/14Methods of forming a masking layer for patterning underlying structures
2162014027347409/18/14Interconnection designs using sidewall image transfer (sit)
2172014028229609/18/14Hybrid performing full field optical proximity correction for finfet mandrel layer
2182014028230109/18/14Stitch insertion for reducing color density differences in double patterning technology (dpt)
2192014028230309/18/14Pattern-independent and hybrid matching/tuning including light manipulation by projection optics
2202014028230709/18/14Method and providing metric relating two or more process parameters to yield
2212014028232309/18/14Parameterized cell for planar and finfet technology design
2222014028233009/18/14Priority based layout versus schematic (lvs)
2232014028234509/18/14Via insertion in integrated circuit (ic) designs
2242014026461309/18/14Integrated circuits and methods for fabricating integrated circuits with active area protection
2252014026463309/18/14Finfet devices having a body contact and methods of forming the same
2262014026898309/18/14Otprom array with leakage current cancelation for enhanced efuse sensing
2272014026906009/18/14Integrated circuits and methods for operating integrated circuits with non-volatile memory
2282014027267709/18/14Methods for fabricating euv masks and methods for fabricating integrated circuits using such euv masks
2292014027329909/18/14Systems and methods for fabricating semiconductor device structures using different metrology tools
2302014027330609/18/14Methods for fabricating integrated circuits including multi-patterning of masks for extreme ultraviolet lithography
2312014027336709/18/14Integrated circuits and methods for fabricating integrated circuits with gate electrode structure protection
2322014027337509/18/14Methods for fabricating integrated circuits with semiconductor substrate protection
2332014027346309/18/14Methods for fabricating integrated circuits that include a sealed sidewall in a porous low-k dielectric layer
2342014027347509/18/14Methods for fabricating guide patterns and methods for fabricating integrated circuits using such guide patterns
2352014027351109/18/14Methods for fabricating integrated circuits including formation of chemical guide patterns for directed self-assembly lithography
2362014027766809/18/14Methods and systems for fabricating integrated circuits utilizing universal and local processing management
2372014025242409/11/14Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
2382014025242509/11/14Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
2392014025242909/11/14Contact geometry having a gate silicon length decoupled from a transistor length
2402014025248009/11/14Combination finfet and planar fet semiconductor device and methods of making such a device
2412014025248109/11/14Transistor including a gate electrode extending all around one or more channel regions
2422014025255709/11/14Method for forming a semiconductor device and semiconductor device structures
2432014025261709/11/14Barrier layer conformality in copper interconnects
2442014025266009/11/14Multilayer pattern transfer for chemical guides
2452014025390209/11/14Multiple patterning process for forming trenches or holes using stitched assist features
2462014025401809/11/14Scattering enhanced thin absorber for euv reflective reticle and a making
2472014025606409/11/14Methods of repairing damaged insulating materials by introducing carbon into the layer of insulating material
2482014025609709/11/14Methods for forming integrated circuit systems employing fluorine doping
2492014025613509/11/14Methods of removing gate cap layers in cmos applications



ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009



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