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Filing Names

Globalfoundries Inc
Globalfoundries Inc grand Cayman Cayman Islands
Globalfoundries Inc_20131212

Globalfoundries Inc patents

Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors

Date Globalfoundries Inc patents (updated weekly) - BOOKMARK this page
02/16/17 new patent  Process design kit for efficient and accurate mismatch simulation of analog circuits
02/16/17 new patent  Methods of forming air gaps in metallization layers on integrated circuit products
02/16/17 new patent  Self-aligned back end of line cut
02/16/17 new patent  Filling cavities in an integrated circuit and resulting devices
02/16/17 new patent  Gate tie-down enablement with inner spacer
02/16/17 new patent  Methods of forming self-aligned device level contact structures
02/16/17 new patent  Gate tie-down enablement with inner spacer
02/16/17 new patent  Field effect transistors having multiple effective work functions
02/16/17 new patent  Reducing liner corrosion during metallization of semiconductor devices
02/16/17 new patent  Methods and devices for metal filling processes
02/16/17 new patent  Semiconductor structure including a nonvolatile memory cell and the formation thereof
02/16/17 new patent  Structure and method to form a finfet device
02/16/17 new patent  Semiconductor structure with multilayer iii-v heterostructures
02/16/17 new patent  Early pts with buffer for channel doping control
02/16/17 new patent  Forming a contact for a tall fin transistor
02/16/17 new patent  Forming a contact for a tall fin transistor
02/16/17 new patent  Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins
02/16/17 new patent  Self-aligned gate tie-down contacts with selective etch stop liner
02/09/17Capacitor structures with embedded electrodes and fabrication methods thereof
02/09/17Damascene wires with top via structures
02/09/17Methods for forming transistor devices with different threshold voltages and the resulting devices
02/09/17Bond pad structure for low temperature flip chip bonding
02/09/17Capacitor structure and forming a capacitor structure
02/09/17Bulex contacts in advanced fdsoi techniques
02/09/17Measurement measuring in thin films
02/09/17Method for forming field effect transistors
02/09/17Field effect transistor device spacers
02/09/17Forming field effect transistor device spacers
02/02/17Finfet electrical characterization with enhanced hall effect and probe
02/02/17Method and system for adjusting a circuit symbol
02/02/17Charge dynamics effect for detection of voltage contrast defect and determination of shorting location
02/02/17Mitigating transient tsv-induced ic substrate noise and resulting devices
02/02/17Three-dimensional semiconductor device with co-fabricated adjacent capacitor
02/02/17Methods of forming replacement fins comprised of multiple layers of different semiconductor materials
02/02/17Method for improved fin profile
02/02/17Trench formation for dielectric filled cut region
02/02/17Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions
02/02/17Integrated circuits and methods for their fabrication
02/02/17Trench formation for dielectric filled cut region
02/02/17High doped iii-v source/drain junctions for field effect transistors
02/02/17High doped iii-v source/drain junctions for field effect transistors
01/26/17Method including a formation of a transistor and semiconductor structure including a first transistor and a second transistor
01/26/17Method to fabricate a high performance capacitor in a back end of line (beol)
01/26/17Methods and structures for back end of line integration
01/26/17Die-die stacking
01/26/17High-k and p-type work function metal first fabrication process having improved annealing process flows
01/26/17High-k and p-type work function metal first fabrication process having improved annealing process flows
01/19/17Inline buried metal void detection by surface plasmon resonance (spr)
01/19/17Hybrid metrology technique
01/19/17Coupling inductors in an ic device using interconnecting elements with solder caps and resulting devices
01/19/17Stress relaxed buffer layer on textured silicon surface
01/19/17Gate cut with high selectivity to preserve interlevel dielectric layer
01/19/17Soi-based semiconductor device with dynamic threshold voltage
01/19/17Gate cut with high selectivity to preserve interlevel dielectric layer
01/19/17Method, apparatus and system for providing multiple euv beams for semiconductor processing
01/19/17Semiconductor substrates and methods for processing semiconductor substrates
01/19/17Methods for fabricating integrated circuits using flowable chemical vapor deposition techniques with low-temperature thermal annealing
01/19/17Interconnect structure including middle of line (mol) metal layer local interconnect on etch stop layer
01/19/17Dipole-based contact structure to reduce metal-semiconductor contact resistance in mosfets
01/12/17High-pressure anneal
01/12/17Method and structure of forming controllable unmerged epitaxial material
01/12/17Process for integrated circuit fabrication including a uniform depth tungsten recess technique
01/12/17Methods for producing integrated circuits using long and short regions and integrated circuits produced from such methods
01/12/17Large area contacts for small transistors
01/05/17Method of simultaneous lithography and etch correction flow
Patent Packs
01/05/17Self-aligned via process flow
01/05/17Lateral bicmos replacement metal gate
01/05/17Integrated circuit structure with methods of electrically connecting same
01/05/17Embedded metal-insulator-metal capacitor
01/05/17Method to improve reliability of replacement gate device
01/05/17Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions
12/29/16Predicting and alerting user to navigation options and predicting user intentions
12/29/16Generative learning for realistic and ground rule clean hot spot synthesis
12/29/16Dynamic and adaptive timing sensitivity during static timing analysis using look-up table
12/29/16Methods of design rule checking of circuit designs
12/29/16Insulating a via in a semiconductor substrate
12/29/16Method to protect mol metallization from hardmask strip process
12/29/16Hdp fill with reduced void formation and spacer damage
12/29/16Integrated circuit (ic) chips with through silicon vias (tsv) and forming the ic
12/29/16Methods including a processing of wafers and spin coating tool
Patent Packs
12/29/16Electrical fuse with high off resistance
12/29/16Electrostatic discharge and passive structures integrated in a veritcal gate fin-type field effect diode
12/29/16Tunable capacitor for fdsoi applications
12/29/16High performance heat shields with reduced capacitance
12/29/16Planar qubits having increased coherence times
12/29/16Semiconductor structures with field effect transistor(s) having low-resistance source/drain contact(s)
12/29/16Shaped terminals for a bipolar junction transistor
12/29/16Method to improve reliability of replacement gate device
12/29/16Hdp fill with reduced void formation and spacer damage
12/29/16Bipolar junction transistors with a buried dielectric region in the active device region
12/29/16Fdsoi voltage reference
12/29/16Integrated circuits with self aligned contacts and methods of manufacturing the same
12/29/16Interconnect structure including middle of line (mol) metal layer local interconnect on etch stop layer
12/29/16Replacement gate multigate transistor for embedded dram
12/22/16Dual liner silicide
12/22/16Dual liner silicide
12/22/16Detecting a void between a via and a wiring line
12/22/16Siarc removal with plasma etch and fluorinated wet chemical solution combination
12/22/16Non-destructive dielectric layer thickness and dopant measuring method
12/22/16Test structures for dielectric reliability evaluations
12/22/16Chip packages with reduced temperature variation
12/22/16Unique bi-layer etch stop to protect conductive structures during a metal hard mask removal process and methods of using same
12/22/16Through silicon via device having low stress, thin film gaps and methods for forming the same
12/22/16Induction heating for underfill removal and chip rework
12/22/16Bipolar junction transistors with double-tapered emitter fingers
12/22/16Fin shape contacts and methods for forming fin shape contacts
12/22/16Recessing rmg metal gate stack for forming self-aligned contact
12/22/16Device structures for a silicon-on-insulator substrate with a high-resistance handle wafer
12/22/16Generating tensile strain in bulk finfet channel
12/22/16Dual channel finfet with relaxed pfet region
Social Network Patent Pack
12/15/16Methods and structures for achieving target resistance post cmp using in-situ resistance measurements
12/15/16Sacrificial amorphous silicon hard mask for beol
12/15/16Dummy gate used as interconnection and making the same
12/15/16Spacer chamfering gate stack scheme
12/15/16Spacer chamfering gate stack scheme
12/15/16Spacer chamfering gate stack scheme
12/15/16Freestanding spacer having sub-lithographic lateral dimension and forming same
12/15/16Spacer chamfering gate stack scheme
12/15/16Devices and methods of forming unmerged epitaxy for finfet device
12/15/16Series resistance reduction in vertically stacked silicon nanowire transistors
Patent Packs
12/08/16Integration of hybrid germanium and group iii-v contact epilayer in cmos
12/08/16Electronic device including moat power metallization in trench
12/08/16Contacts to semiconductor substrate and methods of forming same
12/08/16Methods of forming v0 structures for semiconductor devices by forming a protection layer with a non-uniform thickness
12/08/16Ferroelectric finfet
12/08/16Method and structure to form tensile strained sige fins and compressive strained sige fins on a same substrate
12/08/16Methods of forming a gate contact above an active region of a semiconductor device
12/08/16Local thinning of semiconductor fins
12/08/16Diodes and fabrication methods thereof
12/08/16Via formation using sidewall image tranfer process to define lateral dimension
12/08/16Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same
12/01/16Defect detection process in a semiconductor manufacturing environment
12/01/16Hybrid fin cutting processes for finfet semiconductor devices
12/01/16Method and structure for formation of replacement metal gate field effect transistors
12/01/16Method for forming source/drain contacts during cmos integration using confined epitaxial growth techniques and the resulting semiconductor devices
12/01/16Methods of forming replacement fins for a finfet device using a targeted thickness for the patterned fin etch mask
12/01/16Integrated circuits and methods for fabricating integrated circuits having replacement metal gate electrodes
11/24/16Method, apparatus, and system for offset metal power rail for cell design
11/24/16Device comprising a plurality of fdsoi static random-access memory bitcells and operation thereof
11/24/16Preserving the seed layer on sti edge and improving the epitaxial growth
11/24/16Implant-free punch through doping layer formation for bulk finfet structures
11/24/16Thin film based fan out and multi die package platform
11/24/16E-fuse in soi configuration
11/24/16Photodetector and forming the photodetector on stacked trench isolation regions
11/24/16Interface passivation layers and methods of fabricating
11/17/16Method, apparatus, and system for improved standard cell design and routing for improving standard cell routability
11/17/16Lithography stack and method
11/17/16Methods, apparatus and system for fabricating finfet devices using continuous active area design
11/17/16Alignment monitoring structure and alignment monitoring semiconductor devices
11/17/16Filling cavities in an integrated circuit and resulting devices
Patent Packs
11/17/16Gate contact structure having gate contact layer
11/17/16Carbon nanotube device
11/17/16System and monitoring wafer handling and a wafer handling machine
11/17/16Via formation using sidewall image transfer process to define lateral dimension
11/10/16Detection of foreign material on a substrate chuck
11/10/16Method wherein test cells and dummy cells are included into a layout of an integrated circuit
11/10/16Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an ic device
11/10/162d self-aligned via first process flow
11/10/16Inducing device variation for security applications
11/10/16Silver alloying post-chip join
11/03/16Intelligent wardrobe program
11/03/16Block level patterning process
11/03/16Method and detection of failures in under-fill layers in integrated circuit assemblies
11/03/16Cut first alternative for 2d self-aligned via
11/03/16Method to make gate-to-body contact to release plasma induced charging
11/03/16Memory bit cell for reduced layout area
11/03/16Semiconductor structure having logic region and analog region
11/03/16Novel integration process to form microelectronic or micromechanical structures
11/03/16Electrostatic discharge (esd) protection transistor devices and integrated circuits with electrostatic discharge protection transistor devices
10/27/16Method of manufacturing p-channel fet device with sige channel
Social Network Patent Pack
10/27/16Different height of fins in semiconductor structure
10/27/16Contact geometry having a gate silicon length decoupled from a transistor length
10/27/16Semiconductor device structures with self-aligned fin structure(s) and fabrication methods thereof
10/27/16Methods for modifying an integrated circuit layout design
10/27/16Finfet devices having asymmetrical epitaxially-grown source and drain regions and methods of forming the same
10/20/16Systematic defects inspection method with combined ebeam inspection and net tracing classification
10/20/16Automatic analytical cloud scaling of hardware using resource sub-cloud
10/20/16Automatic analytical cloud scaling of hardware using resource sub-cloud
10/20/16Punch-through-stop after partial fin etch
10/20/16Layered contact structure
10/20/16Integrated circuit product with bulk and soi semiconductor devices
10/20/16Finfet conformal junction and high epi surface dopant concentration
10/20/16Fet device with tuned gate work function
10/20/16Replacement channel tfet
10/13/16Moisture and/or electrically conductive remains detection for wafers after rinse / dry process
10/13/16Electronic package that includes a plurality of integrated circuit devices bonded in a three-dimensional stack arrangement
10/13/16Semiconductor device with thin-film resistor
10/13/16Integrated circuits with spacer chamfering and methods of spacer chamfering
10/13/16Densely packed transistor devices
10/13/16Complex semiconductor devices of the soi type
Social Network Patent Pack
10/13/16Iii-v lasers with integrated silicon photonic circuits
10/13/16Method, apparatus and system for security application for integrated circuit devices
10/13/16Methods for fabricating integrated circuits using multi-patterning processes
10/13/16Interposer and methods of forming and testing an interposer
10/06/16Via leakage and breakdown testing
10/06/16Reticle, system comprising a plurality of reticles and the formation thereof
10/06/16Self-aligned double patterning process for metal routing
10/06/16Method for making strained semiconductor device and related methods
10/06/16Method of utilizing trench silicide in a gate cross-couple construct
10/06/16Method of utilizing trench silicide in a gate cross-couple construct
10/06/16Integration structures for high current applications
10/06/16Finfet semiconductor devices with stressed channel regions
10/06/16Semiconductor structure having source/drain gouging immunity
10/06/16Finfet conformal junction and abrupt junction with reduced damage
10/06/16Integrated circuit product comprising lateral and vertical finfet devices
10/06/16Finfets having strained channels, and methods of fabricating finfets having strained channels
10/06/16Anonymous communication of devices in wireless networks
09/29/16Memory cell, memory device including a plurality of memory cells and method including read and write operations at a memory cell
09/29/16Method to identify extrinsic sram bits for failure analysis based on fail count voltage response
09/29/16Devices comprising high-k dielectric layer and methods of forming same
09/29/16Short-channel nfet device
09/29/16Method and structure to suppress finfet heating
09/29/16Buried source-drain contact for integrated circuit transistor devices and making same
09/29/16Dynamic integrated circuit fabrication methods
09/29/16Semiconductor fuses with nanowire fuse links and fabrication methods thereof
09/29/16Bulk finfet with partial dielectric isolation featuring a punch-through stopping layer under the oxide
09/29/16Method for making a semiconductor device with sidewal spacers for confinig epitaxial growth
09/29/16Forming tunneling field-effect transistor with stacking fault and resulting device
09/29/16Macro to monitor n-p bump
09/29/16Dual channel finfet with relaxed pfet region
Social Network Patent Pack
09/22/16Mis (metal-insulator-semiconductor) contact structures for semiconductor devices
09/22/16Transistors patterned with electrostatic discharge protection and methods of fabrication
09/22/16Eliminating field oxide loss prior to finfet source/drain epitaxial growth
09/22/16Merged n/p type transistor
09/22/16High-voltage transistor device
09/22/16Vertical fin field-effect semiconductor device
09/22/16Silicided nanowires for nanobridge weak links
09/22/16Finfet including tunable fin height and tunable fin width ratio
09/15/16Leakage testing of integrated circuits
09/15/16Low defect iii-v semiconductor template on porous silicon
09/15/16Overhead substrate handling and storage system
09/15/16Cap layer for spacer-constrained epitaxially grown material on fins of a finfet device
09/15/16Semiconductor device having non-magnetic single core inductor and producing the same
09/15/16Semiconductor device with transistor local interconnects
09/15/16Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression
09/15/16Reducing risk of punch-through in finfet semiconductor structure
09/15/16Method of forming a device including a floating gate electrode and a layer of ferroelectric material
09/15/16Integrated strained fin and relaxed fin
09/15/16Methods of forming embedded source/drain regions on finfet devices
09/15/16Common fabrication of multiple finfets with different channel heights
09/15/16Diamond shaped source drain epitaxy with underlying buffer layer
09/15/16Gate and source/drain contact structures for a semiconductor device
09/15/16Semiconductor structure including backgate regions and the formation thereof
09/15/16Three-dimensional transistor with improved channel mobility
09/15/16Fully depleted device with buried insulating layer in channel region
09/15/16Methods, apparatus and system for fabricating high performance finfet device
09/15/16Method, apparatus and system for using free-electron laser compatible euv beam for semiconductor wafer metrology
09/08/16Semiconductor devices having fins, and methods of forming semiconductor devices having fins
09/08/16Electromigration testing of interconnect analogues having bottom-connected sensory pins

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Globalfoundries Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Globalfoundries Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by