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Globalfoundries Inc patents


      
Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors




Search recent Press Releases: Globalfoundries Inc-related press releases
Date Globalfoundries Inc patents (updated weekly) - BOOKMARK this page
07/28/16 new patent  Data-dependent self-biased differential sense amplifier
07/28/16 new patent  Fin field effect transistor including asymmetric raised active regions
07/28/16 new patent  Anchored stress-generating active semiconductor regions for semiconductor-on-insulator finfet
07/28/16 new patent  Finfet crosspoint flash memory
07/28/16 new patent  Methods for fabricating integrated circuits including back-end-of-the-line interconnect structures
07/21/16Constrained die adhesion cure process
07/21/16Bipolar junction transistor with multiple emitter fingers
07/21/16Methods for preventing oxidation damage during finfet fabrication
07/21/16Finfet with multilayer fins for multi-value logic (mvl) applications and forming
07/14/16Antiferromagnetic storage device
07/14/16Method of forming a semiconductor structure including a plurality of fins and an alignment/overlay mark
07/14/16Temperature-controlled implanting of a diffusion-suppressing dopant in a semiconductor structure
07/14/16Gate dielectric protection for transistors
07/14/16Cointegration of bulk and soi semiconductor devices
07/14/16Fdsoi - capacitor
07/14/16Devices with fully and partially silicided gate structures in gate first cmos technologies
07/14/16Semiconductor structure comprising an aluminum gate electrode portion and the formation thereof
07/14/16Semiconductor device comprising ferroelectric elements and fast high-k metal gate transistors
07/14/16Stress modulation in field effect transistors in reducing contact resistance and increasing charge carrier mobility
07/14/16Channel cladding last process flow for forming a channel region on a finfet device having a reduced size fin in the channel region
07/14/16Finfet structures having uniform channel size and methods of fabrication
07/14/16Methods for fabricating integrated circuits with improved implantation processes
07/14/16Integrated circuits with electronic fuse structures
07/07/16Metrology pattern layout and use thereof
07/07/16Electrically insulated fin structure(s) with alternative channel materials and fabrication methods
07/07/16Semiconductor device with different fin sets
07/07/16High voltage lateral double-diffused metal oxide semiconductor field effect transistor (ldmosfet) having a deep fully depleted drain drift region
07/07/16Passive solar panel cooling
06/30/16Managing metadata for caching devices during shutdown and restart procedures
06/30/16Reducing defects and improving reliability of beol metal fill
06/30/16Fabrication methods for multi-layer semiconductor structures
06/30/16Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method
06/30/16Methods of forming 3-d integrated semiconductor devices having intermediate heat spreading capabilities
06/30/16Fin resistor with overlying gate structure
06/30/16Method for forming single diffusion breaks between finfet devices and the resulting devices
06/30/16Capacitor strap connection structure and fabrication method
06/30/16Substrate resistor with overlying gate structure
06/30/16Finfet conformal junction and high epi surface dopant concentration
06/30/16Finfet conformal junction and abrupt junction with reduced damage
06/30/16Methods for forming finfets having a capping layer for reducing punch through leakage
06/30/16Confined early epitaxy with local interconnect capability
06/30/16Devices formed by performing a common etch patterning process to form gate and source/drain contact openings
06/30/16Methods of forming contact structures for semiconductor devices and the resulting devices
06/30/16Methods of forming transistor structures
06/30/16Bipolar transistor with extrinsic base region and methods of fabrication
06/30/16Soi based finfet with strained source-drain regions
06/30/16Defect-free strain relaxed buffer layer
06/30/16Finfet device with a substantially self-aligned isolation region positioned under the channel region
06/30/16Vertical slit transistor with optimized ac performance
06/30/16Hetero-channel finfet
06/30/16Finfet device including a uniform silicon alloy fin
06/30/16Conformal nitridation of one or more fin-type transistor layers
06/30/16High-reliability, low-resistance contacts for nanoscale transistors
06/30/16Semiconductor devices with conductive contact structures having a larger metal silicide contact area
06/30/16Semiconductor devices with graphene nanoribbons
06/30/16Methods for retargeting circuit design layouts and for fabricating semiconductor devices using retargeted layouts
06/30/16Integrated circuits including magnetic tunnel junctions for magnetoresistive random-access memory and methods for fabricating the same
06/30/16Large area contacts for small transistors
06/23/16Trench epitaxial growth for a finfet device having reduced capacitance
06/23/16Nitride spacer for protecting a fin-shaped field effect transistor (finfet) device
06/23/16Silicon-germanium fin of height above critical thickness
06/23/16Silicon-germanium (sige) fin formation
06/23/16Discontinuous air gap crack stop
06/23/16Deep trench polysilicon fin first
06/23/16Uniform junction formation in finfets
06/23/16Zig-zag trench structure to prevent aspect ratio trapping defect escape
06/23/16Reduced trench profile for a gate
06/23/16Semiconductor devices having low contact resistance and low current leakage
06/23/16Bipolar junction transistors and methods of fabrication
06/23/16Methods of forming epi semiconductor material in a trench formed above a semiconductor device and the resulting devices
06/23/16Resonant radio frequency switch
06/16/16Optoelectronic structures having multi-level optical waveguides and methods of forming the structures
06/16/16Converting an xy tcam to a value tcam
06/16/16Structure to prevent deep trench moat charging and moat isolation fails
06/16/16Cmos gate contact resistance reduction
06/16/16Replacement metal gate including dielectric gate material
06/16/16Integrated circuits and methods of forming the same with effective dummy gate cap removal
06/16/16Wafer processing apparatuses and methods of operating the same
06/16/16Integrated circuits with capacitors and methods of producing the same
06/16/16Integrated circuits with dual silicide contacts and methods for fabricating same
06/09/16Ldmos finfet device and manufacture using a trench confined epitaxial growth process
06/09/16Chemical mechanical polishing method and apparatus
06/09/16Multiple threshold convergent opc model
06/09/16Sampling for opc model building
06/09/16Pellicle with aerogel support frame
06/09/16Method, computer readable storage medium and computer system for creating a layout of a photomask
06/09/16Lithography process window prediction based on design data
06/09/16Method for creating an otprom array possessing multi-bit capacity with tddb stress reliability mechanism
06/09/16Methods of forming metal silicide regions on semiconductor devices using an organic chelating material during a metal etch process
06/09/16Methods of forming features having differing pitch spacing and critical dimensions
06/09/16Method for recessing a carbon-doped layer of a semiconductor structure
06/09/16Self-aligned double patterning process for two dimensional patterns
06/09/16Methods of forming self-aligned contact structures on semiconductor devices and the resulting devices
06/09/16Methods of forming replacement gate structures for semiconductor devices and the resulting devices
06/09/16Methods of forming diffusion breaks on integrated circuit products comprised of finfet devices and the resulting products
06/09/16Merged source/drain and gate contacts in sram bitcell
06/09/16Semiconductor structure with bottom-free liner for top contact
06/09/16Tunable scaling of current gain in bipolar junction transistors
06/09/16Forming self-aligned nisi placement with improved performance and yield
06/09/16Finfet work function metal formation
06/09/16Epitaxially grown silicon germanium channel finfet with silicon underlayer
06/09/16Multi-gate field effect transistor (fet) including isolated fin body
06/09/16Replacement gate pfet materials having improved nbti performance
06/09/16Method of forming a semiconductor device structure and such a semiconductor device structure
06/09/16Method for forming air gap structure using carbon-containing spacer
06/09/16Semiconductor structure including a ferroelectric transistor and the formation thereof
06/09/16Finfet with wide unmerged source drain epi
06/09/16Finfet device including a dielectrically isolated silicon alloy fin
06/09/16Nitride layer protection between pfet source/drain regions and dummy gate during source/drain etch
06/09/16Epitaxial block layer for a fin field effect transistor device
06/09/16Channel cladding last process flow for forming a channel region on a finfet device
06/09/16Semiconductor device including embedded crystalline back-gate bias planes, related design structure and fabrication
06/09/16Method, apparatus and system for using free-electron laser compatible euv beam for semiconductor wafer processing
06/09/16Electronic circuit assembly substrate and device thereof
06/09/16Methods for retargeting vias and for fabricating semiconductor devices with retargeted vias
06/09/16Methods for optical proximity correction in the design and fabrication of integrated circuits using extreme ultraviolet lithography
06/09/16Integrated circuits including replacement gate structures and methods for fabricating the same
06/09/16Method for reducing gate height variation due to overlapping masks
06/02/16Optical proximity correction taking into account wafer topography
06/02/16Increased surface area of epitaxial structures in a mixed n/p type fin semiconductor structure with multiple epitaxial heads
06/02/16Fabricating stacked nanowire, field-effect transistors
06/02/16Pressure transfer process for thin film solar cell fabrication
06/02/163d multipath inductor
06/02/16Wafer carrier purge apparatuses, automated mechanical handling systems including the same, and methods of handling a wafer carrier during integrated circuit fabrication
05/26/16Recessing rmg metal gate stack for forming self-aligned contact
05/26/16Forward error correction synchronization
05/19/16Self-aligned via process flow
05/19/16Method and a high yield contact integration scheme
05/19/16Methods of forming alignment marks and overlay marks on integrated circuit products employing finfet devices and the resulting alignment/overlay mark
05/19/16Metal segments as landing pads and local interconnects in an ic device
05/19/16Tall strained high percentage silicon-germanium fins
05/19/16Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and fabrication methods
05/19/16Meander resistor
05/19/16Topological method to build self-aligned mtj without a mask
05/12/16Methods of forming a protective layer on an insulating layer for protection during formation of conductive structures
05/12/16Design rule clean layer marker
05/12/16Methods of forming a combined gate and source/drain contact structure and the resulting device
05/12/16Uniaxially-strained fd-soi finfet
05/12/16Alternative gate dielectric films for silicon germanium and germanium channel materials
05/12/16Methods of forming replacement gate structures on finfet devices and the resulting devices
05/12/16Methods of forming replacement gate structures on finfet devices and the resulting devices
05/12/16Selectively forming a protective conductive cap on a metal gate electrode
05/12/16Methods of forming products with finfet semiconductor devices without removing fins in certain areas of the product
05/12/16Semiconductor junction formation
05/12/16Semiconductor device comprising a multi-layer channel region
05/05/16Alternating space decomposition in circuit structure fabrication
05/05/16Achieving a critical dimension target based on resist characteristics
05/05/16Methods of forming an improved via to contact interface by selective formation of a metal silicide capping layer
05/05/16Methods for forming finfets having a capping layer for reducing punch through leakage
05/05/16Efficient main spacer pull back process for advanced vlsi cmos technologies
05/05/16Methods of forming an improved via to contact interface by selective formation of a conductive capping layer
05/05/16Embedded dram in replacement metal gate technology
05/05/16Transistor structures and fabrication methods thereof
05/05/16Method of improved ca/cb contact and device thereof
05/05/16Hybrid orientation fin field effect transistor and planar field effect transistor
05/05/16Finfet device including a uniform silicon alloy fin
05/05/16Alternating space decomposition in circuit structure fabrication
05/05/16Work-in-progress substrate processing methods and systems for use in the fabrication of integrated circuits
05/05/16Methods for fabricating integrated circuits with isolation regions having uniform step heights
05/05/16Integrated circuits with resistor structures formed from mim capacitor material and methods for fabricating same
04/28/16Nanochannel electrode devices
04/28/16Performing secure address relocation within a multi-processor system sharing a same physical memory channel to external memory
04/28/16Method and assisted metal routing
04/28/16Integrated circuit timing variability reduction
04/28/16Programming an electrical fuse with a silicon-controlled rectifier
04/28/16Methods of forming doped epitaxial sige material on semiconductor devices
04/28/16Methods of forming strained epitaxial semiconductor material(s) above a strain-relaxed buffer layer
04/28/16Oxide mediated epitaxial nickel disilicide alloy contact formation
04/28/16Fabrication of nanowire structures
04/28/16Precut metal lines
04/28/16Direct injection molded solder process for forming solder bumps on wafers
04/28/16Replacement gate structures for transistor devices
04/28/16Semiconductor structure having finfet ultra thin body and methods of fabrication thereof
04/28/16Dual three-dimensional and rf semiconductor devices using local soi
04/28/16Metal-insulator-metal back end of line capacitor structures
04/28/16Multiple layer interface formation for semiconductor structure
04/28/16Methods of forming 3d devices with dielectric isolation and a strained channel region
04/28/16Non-planar schottky diode and fabrication
04/28/16Methods of forming a tri-gate finfet device and the resulting device
04/28/16Multi-gate fets having corrugated semiconductor stacks and forming the same
04/28/16Fd devices in advanced semiconductor techniques
04/28/16Integrated circuits with an air gap and methods of producing the same
04/28/16Fin structures and multi-vt scheme based on tapered fin and method to form
04/21/16Methods, apparatus, and system for using filler cells in design of integrated circuit devices
04/21/16T-shaped fin isolation region and methods of fabrication
04/21/16Finfet semiconductor device having local buried oxide
04/21/16Semiconductor structure with self-aligned wells and multiple channel materials
04/21/16Contact liners for integrated circuits and fabrication methods thereof
04/21/16Method of utilizing trench silicide in a gate cross-couple construct
04/21/16Dielectric cover for a through silicon via
04/21/16Dummy metal structure and forming dummy metal structure
04/21/16Low energy etch process for nitrogen-containing dielectric layer
04/21/16Semiconductor structure including a die seal leakage detection material, the formation thereof and method including a test of a semiconductor structure
04/21/16Vertical breakdown protection layer
04/21/16Bond pad structure for low temperature flip chip bonding
04/21/16Top-side interconnection substrate for die-to-die interconnection
04/21/16Scr with fin body regions for esd protection
04/21/16Method for making high voltage integrated circuit devices in a fin-type process and resulting devices
04/21/16Fin device with blocking layer in channel region
04/21/16Multi-channel gate-all-around fet
04/21/16Ultra-low resistance gate structure for non-planar device via minimized work function material
04/21/16High mobility pmos and nmos devices having si-ge quantum wells
04/21/16Methods of forming a semiconductor circuit element and semiconductor circuit element
04/21/16Methods of post-process dispensation of plasma induced damage protection component
04/14/16Process for integrated circuit fabrication including a uniform depth tungsten recess technique
04/14/16Novel otprom for post-process programming using selective breakdown
04/14/16Semiconductor device having common contact and gate properties
04/14/16Semiconductor structure including a layer of a first metal between a diffusion barrier layer and a second metal and the formation thereof
04/14/16Interlayer ballistic conductor signal lines
04/14/16Low capacitance ballistic conductor signal lines
04/14/16Self aligned via fuse
04/14/16Method and structure for transistors using gate stack dopants with minimal nitrogen penetration
04/14/16Method of fabricating a mim capacitor with minimal voltage coefficient and a decoupling mim capacitor and analog/rf mim capacitor on the same chip with high-k dielectrics
04/14/16Profile control over a collector of a bipolar junction transistor
04/14/16Non-planar vertical dual source drift metal-oxide semiconductor (vdsmos)
04/14/16Dual-strained nanowire and finfet devices with dielectric isolation
04/14/16Level shifting an i/o signal into multiple voltage domains
04/07/16Dynamic multi-purpose external access points connected to core interfaces within a system on chip (soc)
04/07/16Method for defining an isolation region(s) of a semiconductor structure
04/07/16Dimension-controlled via formation processing
04/07/16Methods, apparatus and system for reduction of power consumption in a semiconductor device
04/07/16Flexible active matrix display
04/07/16Embedded metal-insulator-metal capacitor
04/07/16Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layers
04/07/16Suspended body field effect transistor
04/07/16Field effect transistor and fabrication
04/07/16Opc enlarged dummy electrode to eliminate ski slope at esige
04/07/16Tunneling field effect transistor and methods of making such a transistor
04/07/16Facilitating fabricating gate-all-around nanowire field-effect transistors
03/31/16Printing minimum width features at non-minimum pitch and resulting device
03/31/16Finfet semiconductor devices with replacement gate structures
03/31/16Method for creating self-aligned transistor contacts
03/31/16Semiconductor devices with replacement gate structures
03/31/16Finfet semiconductor device with isolated channel regions
03/31/16Tantalum carbide metal gate stack for mid-gap work function applications
03/24/16Bipolar junction transistors with an air gap in the shallow trench isolation
03/24/16Wafer slip detection during cmp processing
03/24/16Constrained nanosecond laser anneal of metal interconnect structures
03/24/16Methods for making robust replacement metal gates and multi-threshold devices in a soft mask integration scheme
03/24/16Nanowire compatible e-fuse
03/24/16Preventing epi damage for cap nitride strip scheme in a fin-shaped field effect transistor (finfet) device
03/17/16Recovering from uncorrected memory errors
03/17/16Method of forming a semiconductor device and according semiconductor device
03/17/16Wafer with improved plating current distribution
03/17/16Integrated circuits with metal-titanium oxide contacts and fabrication methods
03/17/16Overlay mark dependent dummy fill to mitigate gate height variation
03/17/16Patterning multiple, dense features in a semiconductor device using a memorization layer
03/17/16Method and device for an integrated trench capacitor
03/17/16Partial fin on oxide for improved electrical isolation of raised active regions



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