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Globalfoundries Inc patents


      
Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors


Ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating same

Globalfoundries

Ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating same

Method, computer system and computer-readable storage medium for creating a layout of an integrated circuit

Globalfoundries

Method, computer system and computer-readable storage medium for creating a layout of an integrated circuit

Replacement metal gate including dielectric gate material

Globalfoundries

Replacement metal gate including dielectric gate material



Search recent Press Releases: Globalfoundries Inc-related press releases
Count Application # Date Globalfoundries Inc patents (updated weekly) - BOOKMARK this page
12015021240207/30/15  new patent  Mask structures and methods of manufacturing
22015021318407/30/15  new patent  Method and modified cell architecture and the resulting device
32015021318507/30/15  new patent  Method, computer system and computer-readable storage medium for creating a layout of an integrated circuit
42015021406407/30/15  new patent  Forming cross-coupled line segments
52015021410507/30/15  new patent  Structure and forming silicide on fins
62015021411607/30/15  new patent  Low leakage pmos transistor
72015021432207/30/15  new patent  Semiconductor device with ferooelectric hafnium oxide and forming semiconductor device
82015021433007/30/15  new patent  Replacement low-k spacer
92015021433107/30/15  new patent  Replacement metal gate including dielectric gate material
102015021434507/30/15  new patent  Dopant diffusion barrier to form isolated source/drains in a semiconductor device
112015021436507/30/15  new patent  Multiwidth finfet with channel cladding
122015021436907/30/15  new patent  Methods of forming epitaxial semiconductor material on source/drain regions of a finfet semiconductor device and the resulting devices
132015021473307/30/15  new patent  Enhanced charge device model clamp
142015021405907/30/15  new patent  Integrated circuits with metal-insulator-semiconductor (mis) contact structures and methods for fabricating same
152015021411307/30/15  new patent  Methods for fabricating finfet integrated circuits with simultaneous formation of local contact openings
162015021412107/30/15  new patent  Ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating same
172015021422807/30/15  new patent  Iintegrated circuits with dual silicide contacts and methods for fabricating same
182015020675407/23/15 Gate contact with vertical isolation from source-drain
192015020684407/23/15 Integrated circuits having gate cap protection and methods of forming the same
202015019843507/16/15 Decoupling measurement of layer thicknesses of a plurality of layers of a circuit structure
212015020009307/16/15 Hardmask capping layer
222015020011107/16/15 Planarization scheme for finfet gate height uniformity control
232015020012807/16/15 Methods of forming isolated germanium-containing fins for a finfet semiconductor device
242015020013107/16/15 Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics by modified rf power ramp-up
252015020020507/16/15 Simplified multi-threshold voltage scheme for fully depleted soi mosfets
262015020024207/16/15 Method and device for an integrated trench capacitor
272015020025107/16/15 Mos transistor operated as otp cell with gate dielectric operating as an e-fuse element
282015020026007/16/15 Method to form wrap-around contact for finfet
292015020027007/16/15 Field effect transistors for high-performance and low-power applications
302015020029807/16/15 Modified tunneling field effect transistors and fabrication methods
312015020035307/16/15 Magnetic tunnel junction between metal layers of a semiconductor device
322015020014007/16/15 Methods for fabricating finfet integrated circuits using laser interference lithography techniques
332015020014207/16/15 Methods for fabricating integrated circuits with fully silicided gate electrode structures
342015019286607/09/15 Efficient optical proximity correction repair flow method and apparatus
352015019430707/09/15 Strained fin structures and methods of fabrication
362015019434207/09/15 Formation of carbon-rich contact liner material
372015019441907/09/15 Three-dimensional electrostatic discharge semiconductor device
382015019451707/09/15 Gate stack and contact structure
392015018766007/02/15 Balancing asymmetric spacers
402015018770207/02/15 Middle-of-the-line constructs using diffusion contact structures
412015018776207/02/15 Semiconductor device with a multiple nanowire channel structure and methods of variably connecting such nanowires for current density modulation
422015018789607/02/15 Silicide protection during contact metallization and resulting semiconductor structures
432015018790507/02/15 Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
442015018794507/02/15 Salicide protection during contact metallization and resulting semiconductor structures
452015018794707/02/15 Finfet with active region shaped structures and channel separation
462015017963206/25/15 Semiconductor device comprising an e-fuse and a fet
472015017964006/25/15 Common fabrication of different semiconductor devices with different threshold voltages
482015017975306/25/15 Novel e-fuse design for high-k metal-gate technology
492015017976606/25/15 Buried local interconnect in finfet structure
502015017964406/25/15 Finfet integrated circuits and methods for their fabrication
512015016882406/18/15 Euv pellicle frame with holes and forming
522015016981806/18/15 Pattern-based via redundancy insertion
532015017073506/18/15 Dual port sram bitcell structures with improved transistor arrangement
542015017100106/18/15 Methods of protecting a dielectric mask layer and related semiconductor devices
552015017108606/18/15 Selective growth of a work-function metal in a replacement metal gate of a semiconductor device
562015017097306/18/15 Methods for fabricating integrated circuits using self-aligned quadruple patterning
572015017108206/18/15 Integrated circuit and fabricating the same having a replacement gate structure
582015016218006/11/15 Method, storage medium and system for controlling the processing of lots of workpieces
592015016218806/11/15 Method of forming a dielectric film
602015016241406/11/15 Sandwich silicidation for fully silicided gate formation
612015016243506/11/15 Asymmetric channel growth of a cladding layer over fins of a field effect transistor (finfet) device
622015015523806/04/15 Making an efuse
632015014505905/28/15 Methods of forming an e-fuse for an integrated circuit product and the resulting integrated circuit product
642015014506105/28/15 Novel contact structure for a semiconductor device and methods of making same
652015014507105/28/15 Methods of forming spacers on finfets and other semiconductor devices
662015014500005/28/15 Integrated circuits with shallow trench isolations, and methods for producing the same
672015014634105/28/15 Ald dielectric films with leakage-reducing impurity layers
682015014696605/28/15 Methods and media for averaging contours of wafer feature edges
692015013723505/21/15 Finfet semiconductor device having local buried oxide
702015013719405/21/15 Inverted contact and methods of fabrication
712015013720305/21/15 Forming finfet cell with fin tip and resulting device
722015013723505/21/15 Finfet semiconductor device having local buried oxide
732015013723705/21/15 Undoped epitaxial layer for junction isolation in a fin field effect transistor (finfet) device
742015013725805/21/15 Forming a low votage antifuse device and resulting device
752015013727005/21/15 Superior integrity of a high-k gate stack by forming a controlled undercut on the basis of a wet chemistry
762015013727305/21/15 Method and device for self-aligned contact on a non-recessed metal gate
772015013730805/21/15 Self-aligned dual-height isolation for bulk finfet
782015013731605/21/15 Semiconductor device including a resistor and the formation thereof
792015013737205/21/15 Self forming barrier layer and forming
802015013855505/21/15 Overlay metrology system and method
812015014069505/21/15 Method and system for determining overlap process windows in semiconductors by inspection techniques
822015014075105/21/15 Modified, etch-resistant gate structure(s) facilitating circuit fabrication
832015014075605/21/15 Fabrication methods facilitating integration of different device architectures
842015014076105/21/15 Device isolation in finfet cmos
852015013737305/21/15 Integrated circuits and methods for fabricating integrated circuits with improved contact structures
862015013738505/21/15 Integrated circuits with close electrical contacts and methods for fabricating the same
872015014069705/21/15 Test macro for use with a multi-patterning lithography process
882015014069805/21/15 Test macro for use with a multi-patterning lithography process
892015012993405/14/15 Methods of forming substantially self-aligned isolation regions on finfet semiconductor devices and the resulting devices
902015012996205/14/15 Methods of forming replacement gate structures and fins on finfet devices and the resulting devices
912015012996405/14/15 Nanowire transistor device
922015012996605/14/15 Transistor including a gate electrode extending all around one or more channel regions
932015012997005/14/15 Methods and structures for eliminating or reducing line end epi material growth on gate structures
942015012998305/14/15 Fin-type transistor structures with extended embedded stress elements and fabrication methods
952015013002605/14/15 Printing minimum width features at non-minimum pitch and resulting device
962015013006305/14/15 Method to use self-repair cu barrier to solve barrier degradation due to ru cmp
972015013296205/14/15 Facilitating mask pattern formation
982015012997205/14/15 Methods of scaling thickness of a gate dielectric structure, methods of forming an integrated circuit, and integrated circuits
992015013006505/14/15 Method to etch cu/ta/tan selectively using dilute aqueous hf/h2so4 solution
1002015013291405/14/15 Methods for fabricating integrated circuits with robust gate electrode structure protection
1012015012314605/07/15 Increased space between epitaxy on adjacent fins of finfet
1022015012316605/07/15 Methods of forming finfet devices with alternative channel materials
1032015012318105/07/15 Capacitors positioned at the device level in an integrated circuit product and methods of making such capacitors
1042015012321105/07/15 Narrow diffusion break for a fin field effect (finfet) transistor device
1052015012321205/07/15 Planar metrology pad adjacent a set of fins of a fin field effect transistor device
1062015012321405/07/15 Methods of forming a finfet semiconductor device with undoped fins
1072015012325005/07/15 Methods of fabricating defect-free semiconductor structures
1082015012600805/07/15 Methods of forming stressed multilayer finfet devices with alternative channel materials
1092015012601005/07/15 Band engineered semiconductor device and manufacturing thereof
1102015012602305/07/15 Methods of forming gate structures with multiple work functions and the resulting products
1112015012602805/07/15 Methods for fabricating integrated circuits using surface modification to selectively inhibit etching
1122015012603405/07/15 Methods for fabricating integrated circuits including topographical features for directed self-assembly
1132015011515304/30/15 Detection of particle contamination on wafers
1142015011526704/30/15 Planar metrology pad adjacent a set of fins of a fin field effect transistor device
1152015011537004/30/15 Semiconductor device providing enhanced fin isolation and related methods
1162015011537104/30/15 Finfet semiconductor structures and methods of fabricating same
1172015011541804/30/15 Devices and methods of forming fins at tight fin pitches
1182015010857304/23/15 Semiconductor device including vertically spaced semiconductor channel structures and related methods
1192015010857704/23/15 Selective growth of a work-function metal in a replacement metal gate of a semiconductor device
1202015010858004/23/15 Methods of forming bipolar devices and an integrated circuit product containing such bipolar devices
1212015010858304/23/15 Densely packed standard cells for integrated circuit products, and methods of making same
1222015010858604/23/15 Transistor device with improved source/drain junction architecture and methods of making such a device
1232015010864604/23/15 Electro-migration enhancing self-forming barrier process in copper mettalization
1242015011131604/23/15 Method for detecting defects in a diffusion barrier layer
1252015011134904/23/15 Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and the formation thereof
1262015011348404/23/15 Methods of generating circuit layouts that are to be manufactured using sadp routing techniques
1272015010864704/23/15 Hybrid manganese and manganese nitride barriers for back-end-of-line metallization and methods for fabricating the same
1282015011137304/23/15 Reducing gate height variation in rmg process
1292015010241004/16/15 Semiconductor device including stress layer adjacent channel and related methods
1302015010241704/16/15 Double trench well formation in sram cells
1312015010242604/16/15 Three-dimensional transistor with improved channel mobility
1322015010282604/16/15 Design structures and methods for extraction of device channel width
1332015010491804/16/15 Facilitating fabricating gate-all-around nanowire field-effect transistors
1342015010494804/16/15 Facilitating etch processing of a thin film via partial implantation thereof
1352015010242204/16/15 Integrated circuits including finfet devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
1362015010530804/16/15 Aqua regia and hydrogen peroxide hcl combination to remove ni and nipt residues
1372015009719704/09/15 Finfet with sigma cavity with multiple epitaxial material regions
1382015009724604/09/15 Integrated circuit and fabricating the same having a replacement gate structure
1392015009724904/09/15 Cross coupling gate using mulitple patterning
1402015009725204/09/15 Simplified gate-first hkmg manufacturing flow
1412015009726304/09/15 Method and high yield contact integration scheme
1422015009934004/09/15 Methods for preventing oxidation damage during finfet fabrication
1432015009729104/09/15 Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
1442015009933604/09/15 Methods of manufacturing integrated circuits having finfet structures with epitaxially formed source/drain regions
1452015009109404/02/15 Devices and methods of forming finfets with self aligned fin formation
1462015009109704/02/15 Hardmask for a halo/extension implant of a static random access memory (sram) layout
1472015009387704/02/15 Method for manufacturing a semiconductor device by stopping planarization of insulating material on fins
1482015009388704/02/15 Methods for removing a native oxide layer from germanium susbtrates in the fabrication of integrated circuitsi
1492015009388904/02/15 Methods for removing a native oxide layer from germanium susbtrates in the fabrication of integrated circuits
1502015009391404/02/15 Methods for depositing an aluminum oxide layer over germanium susbtrates in the fabrication of integrated circuits
1512015008413103/26/15 Gate height uniformity in semiconductor devices
1522015008713403/26/15 Semiconductor isolation region uniformity
1532015008418303/26/15 Integrated circuits with protected resistors and methods for fabricating the same
1542015008714903/26/15 Methods for fabricating integrated circuits using improved masks
1552015007708603/19/15 Fin width measurement using quantum well structure
1562015007611103/19/15 Feature etching using varying supply of power pulses
1572015007660903/19/15 Methods of forming stressed layers on finfet semiconductor devices and the resulting devices
1582015007662203/19/15 Reducing gate expansion after source and drain implant in gate last process
1592015007665303/19/15 Overlay performance for a fin field effect transistor device
1602015007670503/19/15 Reduced capacitance interlayer structures and fabrication methods
1612015007806803/19/15 Integrated circuits with sram cells having additional read stacks
1622015007977303/19/15 Conformal doping for finfet devices
1632015007655903/19/15 Integrated circuits with strained silicon and methods for fabricating such circuits
1642015007656003/19/15 Integrated circuits including epitaxially grown strain-inducing fills doped with boron for improved robustness from delimination and methods for fabricating the same
1652015007661803/19/15 Integrated circuits with a corrugated gate, and methods for producing the same
1662015007662403/19/15 Integrated circuits having smooth metal gates and methods for fabricating same
1672015006951503/12/15 Integrated circuits having laterally confined epitaxial material overlying fin structures and methods for fabricating same
1682015006096003/05/15 Methods of forming contact structures on finfet semiconductor devices and the resulting devices
1692015006098303/05/15 Semiconductor structure including a split gate nonvolatile memory cell and a high voltage transistor, and the formation thereof
1702015006101403/05/15 Fin pitch scaling and active layer isolation
1712015006102703/05/15 Methods of forming gate structures for transistor devices for cmos applications and the resulting products
1722015006103203/05/15 Fabrication of nickel free silicide for semiconductor contact metallization
1732015006113503/05/15 Copper interconnect with cvd liner and metallic cap
1742015006299603/05/15 Embedded selector-less one-time programmable non-volatile memory
1752015006481203/05/15 Method of forming a semiconductor device employing an optical planarization layer
1762015006487203/05/15 Top corner rounding by implant-enhanced wet etching
1772015006763303/05/15 Color-insensitive rules for routing structures
1782015006104003/05/15 Self-aligned dielectric isolation for finfet devices
1792015006490303/05/15 Methods for fabricating integrated circuits using chemical mechanical planarization to recess metal
1802015006491203/05/15 Methods of forming integrated circuits and multiple critical dimension self-aligned double patterning processes
1812015005398102/26/15 Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device
1822015005407802/26/15 Methods of forming gate structures for finfet devices and the resulting smeiconductor products
1832015005408302/26/15 Strain engineering in semiconductor devices by using a piezoelectric material
1842015005413902/26/15 Through-silicon via with sidewall air gap
1852015005679602/26/15 Method for forming a semiconductor device having a metal gate recess
1862015005678102/26/15 Gate length independent silicon-on-nothing (son) scheme for bulk finfets
1872015005682002/26/15 Systems and methods of solvent temperature control for wafer coating processes
1882015004844602/19/15 Reduction of oxide recesses for gate height control
1892015005078702/19/15 Fully silicided gate formed according to the gate-first hkmg approach
1902015005079202/19/15 Extra narrow diffusion break for 3d finfet technologies
1912015005081102/19/15 Critical dimension and pattern recognition structures for devices manufactured using double patterning techniques
1922015005081202/19/15 Wafer-less auto clean of processing chamber
1932015005210802/19/15 Method, computer readable storage medium and computer system for obtaining snapshots of data
1942015005249402/19/15 Power rail layout for dense standard cell library
1952015004186902/12/15 Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
1962015004189802/12/15 Bulk finfet semiconductor-on-nothing integration
1972015004190502/12/15 Methods of forming replacement gate structures for transistors and the resulting devices
1982015004190602/12/15 Methods of forming stressed fin channel structures for finfet semiconductor devices
1992015004190902/12/15 Completing middle of line integration allowing for self-aligned contacts
2002015004485502/12/15 Methods of forming spacers on finfets and other semiconductor devices
2012015004486102/12/15 Gate silicidation
2022015004185802/12/15 3d transistor channel mobility enhancement
2032015004191002/12/15 Integrated circuits with a partially-depleted region formed over a bulk silicon substrate and methods for fabricating the same
2042015004191102/12/15 3d transistor channel mobility enhancement
2052015003501602/05/15 Nitride spacer for protecting a fin-shaped field effect transistor (finfet) device
2062015003501802/05/15 Devices and methods of forming bulk finfets with lateral seg for source and drain on dielectrics
2072015003505202/05/15 Contact power rail
2082015003505302/05/15 Device and a ldmos design for a finfet integrated circuit
2092015003507302/05/15 Enabling enhanced reliability and mobility for replacement gate planar and finfet structures
2102015003508602/05/15 Methods of forming cap layers for semiconductor devices with self-aligned contact elements and the resulting devices
2112015003697802/05/15 Blazed grating spectral purity filter and methods of making such a filter
2122015003794502/05/15 Epitaxially forming a set of fins in a semiconductor device
2132015003494102/05/15 Integrated circuits having finfet semiconductor devices and methods of fabricating the same to resist sub-fin current leakage
2142015003506202/05/15 Integrated circuits having finfets with improved doped channel regions and methods for fabricating same
2152015003760302/05/15 Articles including metal structures having maximized bond adhesion and bond reliability, and methods of forming the same
2162015004007802/05/15 Methods and systems for designing and manufacturing optical lithography masks
2172015004008002/05/15 Methods for modifying an integrated circuit layout design
2182015004009102/05/15 Methods for modifying an integrated circuit layout design
2192015002834801/29/15 Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (finfet) device
2202015002843101/29/15 Mol insitu pt rework sequence
2212015002848201/29/15 Device layout for reducing through-silicon-via stress
2222015002848901/29/15 Method for off-grid routing structures utilizing self aligned double patterning (sadp) technology
2232015002850001/29/15 Forming alignment mark and resulting mark
2242015003117901/29/15 Method of forming a semiconductor structure including silicided and non-silicided circuit elements
2252015003320101/29/15 Systems and methods for fabricating semiconductor device structures
2262015002166301/22/15 Finfet with insulator under channel
2272015002168301/22/15 Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
2282015002169101/22/15 Finfet with electrically isolated active region on bulk semiconductor substrate and fabricating same
2292015002169301/22/15 Enhancing transistor performance and reliability by incorporating deuterium into a strained capping layer
2302015002169501/22/15 Epitaxial block layer for a fin field effect transistor device
2312015002170201/22/15 Shallow trench isolation
2322015002170301/22/15 Gate oxide quality for complex mosfet devices
2332015002170401/22/15 Finfet work function metal formation
2342015002170901/22/15 Structures and methods integrating different fin device architectures
2352015002171201/22/15 Highly conformal extension doping in advanced multi-gate devices
2362015002455701/22/15 Semiconductor device having local buried oxide
2372015002456001/22/15 Gate encapsulation achieved by single-step deposition
2382015002457201/22/15 Process for faciltiating fin isolation schemes
2392015002457301/22/15 Methods of forming replacement fins for a finfet semiconductor device by performing a replacement growth process
2402015002458501/22/15 Systems and methods for fabricating gate structures for semiconductor devices
2412015002169401/22/15 Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating the same
2422015002171401/22/15 Integrated circuits having a metal gate structure and methods for fabricating the same
2432015002358301/22/15 Methods and systems for determining a dose-to-clear of a photoresist
2442015002457801/22/15 Methods for etching dielectric materials in the fabrication of integrated circuits
2452015001477701/15/15 Channel semiconductor alloy layer growth adjusted by impurity ion implantation
2462015001481301/15/15 Complex circuit element and capacitor utilizing cmos compatible antiferroelectric high-k materials
2472015001484301/15/15 Semiconductor device with improved metal pillar configuration
2482015001777401/15/15 Method of forming fins with recess shapes
2492015001780301/15/15 Customized alleviation of stresses generated by through-substrate via(s)



ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009



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