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Globalfoundries Inc
Globalfoundries Inc grand Cayman Cayman Islands
Globalfoundries Inc_20131212


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Globalfoundries Inc patents

Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors

Search recent Press Releases: Globalfoundries Inc-related press releases
Count Application # Date Globalfoundries Inc patents (updated weekly) - BOOKMARK this page
12016018138106/23/16  new patent  Trench epitaxial growth for a finfet device having reduced capacitance
22016018109206/23/16  new patent  Nitride spacer for protecting a fin-shaped field effect transistor (finfet) device
32016018109506/23/16  new patent  Silicon-germanium fin of height above critical thickness
42016018110506/23/16  new patent  Silicon-germanium (sige) fin formation
52016018120806/23/16  new patent  Discontinuous air gap crack stop
62016018125206/23/16  new patent  Deep trench polysilicon fin first
72016018128506/23/16  new patent  Uniform junction formation in finfets
82016018135906/23/16  new patent  Zig-zag trench structure to prevent aspect ratio trapping defect escape
92016018138406/23/16  new patent  Reduced trench profile for a gate
102016018139006/23/16  new patent  Semiconductor devices having low contact resistance and low current leakage
112016018139306/23/16  new patent  Bipolar junction transistors and methods of fabrication
122016018142606/23/16  new patent  Methods of forming epi semiconductor material in a trench formed above a semiconductor device and the resulting devices
132016018203706/23/16  new patent  Resonant radio frequency switch
142016017014006/16/16 Optoelectronic structures having multi-level optical waveguides and methods of forming the structures
152016017203806/16/16 Converting an xy tcam to a value tcam
162016017231406/16/16 Structure to prevent deep trench moat charging and moat isolation fails
172016017237806/16/16 Cmos gate contact resistance reduction
182016017246706/16/16 Replacement metal gate including dielectric gate material
192016017225106/16/16 Integrated circuits and methods of forming the same with effective dummy gate cap removal
202016017225506/16/16 Wafer processing apparatuses and methods of operating the same
212016017243206/16/16 Integrated circuits with capacitors and methods of producing the same
222016017249306/16/16 Integrated circuits with dual silicide contacts and methods for fabricating same
232016016385006/09/16 Ldmos finfet device and manufacture using a trench confined epitaxial growth process
242016015891206/09/16 Chemical mechanical polishing method and apparatus
252016016184006/09/16 Multiple threshold convergent opc model
262016016184106/09/16 Sampling for opc model building
272016016185706/09/16 Pellicle with aerogel support frame
282016016262306/09/16 Method, computer readable storage medium and computer system for creating a layout of a photomask
292016016262606/09/16 Lithography process window prediction based on design data
302016016339806/09/16 Method for creating an otprom array possessing multi-bit capacity with tddb stress reliability mechanism
312016016355106/09/16 Methods of forming metal silicide regions on semiconductor devices using an organic chelating material during a metal etch process
322016016355506/09/16 Methods of forming features having differing pitch spacing and critical dimensions
332016016355906/09/16 Method for recessing a carbon-doped layer of a semiconductor structure
342016016358406/09/16 Self-aligned double patterning process for two dimensional patterns
352016016358506/09/16 Methods of forming self-aligned contact structures on semiconductor devices and the resulting devices
362016016360106/09/16 Methods of forming replacement gate structures for semiconductor devices and the resulting devices
372016016360406/09/16 Methods of forming diffusion breaks on integrated circuit products comprised of finfet devices and the resulting products
382016016364406/09/16 Merged source/drain and gate contacts in sram bitcell
392016016364506/09/16 Semiconductor structure with bottom-free liner for top contact
402016016368506/09/16 Tunable scaling of current gain in bipolar junction transistors
412016016370206/09/16 Forming self-aligned nisi placement with improved performance and yield
422016016370506/09/16 Finfet work function metal formation
432016016370706/09/16 Epitaxially grown silicon germanium channel finfet with silicon underlayer
442016016373906/09/16 Multi-gate field effect transistor (fet) including isolated fin body
452016016381406/09/16 Replacement gate pfet materials having improved nbti performance
462016016381506/09/16 Method of forming a semiconductor device structure and such a semiconductor device structure
472016016381606/09/16 Method for forming air gap structure using carbon-containing spacer
482016016382106/09/16 Semiconductor structure including a ferroelectric transistor and the formation thereof
492016016382606/09/16 Finfet with wide unmerged source drain epi
502016016383106/09/16 Finfet device including a dielectrically isolated silicon alloy fin
512016016385906/09/16 Nitride layer protection between pfet source/drain regions and dummy gate during source/drain etch
522016016386206/09/16 Epitaxial block layer for a fin field effect transistor device
532016016386306/09/16 Channel cladding last process flow for forming a channel region on a finfet device
542016016387906/09/16 Semiconductor device including embedded crystalline back-gate bias planes, related design structure and fabrication
552016016571006/09/16 Method, apparatus and system for using free-electron laser compatible euv beam for semiconductor wafer processing
562016016572906/09/16 Electronic circuit assembly substrate and device thereof
572016016262106/09/16 Methods for retargeting vias and for fabricating semiconductor devices with retargeted vias
582016016262406/09/16 Methods for optical proximity correction in the design and fabrication of integrated circuits using extreme ultraviolet lithography
592016016382406/09/16 Integrated circuits including replacement gate structures and methods for fabricating the same
602016016383006/09/16 Method for reducing gate height variation due to overlapping masks
612016015492206/02/16 Optical proximity correction taking into account wafer topography
622016015579906/02/16 Increased surface area of epitaxial structures in a mixed n/p type fin semiconductor structure with multiple epitaxial heads
632016015580006/02/16 Fabricating stacked nanowire, field-effect transistors
642016015588906/02/16 Pressure transfer process for thin film solar cell fabrication
652016015555806/02/16 3d multipath inductor
662016015565406/02/16 Wafer carrier purge apparatuses, automated mechanical handling systems including the same, and methods of handling a wafer carrier during integrated circuit fabrication
672016014901505/26/16 Recessing rmg metal gate stack for forming self-aligned contact
682016014959505/26/16 Forward error correction synchronization
692016014120605/19/16 Self-aligned via process flow
702016014124205/19/16 Method and a high yield contact integration scheme
712016014125205/19/16 Methods of forming alignment marks and overlay marks on integrated circuit products employing finfet devices and the resulting alignment/overlay mark
722016014129105/19/16 Metal segments as landing pads and local interconnects in an ic device
732016014136805/19/16 Tall strained high percentage silicon-germanium fins
742016014137905/19/16 Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and fabrication methods
752016014139305/19/16 Meander resistor
762016014148905/19/16 Topological method to build self-aligned mtj without a mask
772016013357205/12/16 Methods of forming a protective layer on an insulating layer for protection during formation of conductive structures
782016013357805/12/16 Design rule clean layer marker
792016013362305/12/16 Methods of forming a combined gate and source/drain contact structure and the resulting device
802016013369205/12/16 Uniaxially-strained fd-soi finfet
812016013371605/12/16 Alternative gate dielectric films for silicon germanium and germanium channel materials
822016013371905/12/16 Methods of forming replacement gate structures on finfet devices and the resulting devices
832016013372005/12/16 Methods of forming replacement gate structures on finfet devices and the resulting devices
842016013372105/12/16 Selectively forming a protective conductive cap on a metal gate electrode
852016013372605/12/16 Methods of forming products with finfet semiconductor devices without removing fins in certain areas of the product
862016013372705/12/16 Semiconductor junction formation
872016013374005/12/16 Semiconductor device comprising a multi-layer channel region
882016012430805/05/16 Alternating space decomposition in circuit structure fabrication
892016012512105/05/16 Achieving a critical dimension target based on resist characteristics
902016012613505/05/16 Methods of forming an improved via to contact interface by selective formation of a metal silicide capping layer
912016012614105/05/16 Methods for forming finfets having a capping layer for reducing punch through leakage
922016012614605/05/16 Efficient main spacer pull back process for advanced vlsi cmos technologies
932016012619005/05/16 Methods of forming an improved via to contact interface by selective formation of a conductive capping layer
942016012624505/05/16 Embedded dram in replacement metal gate technology
952016012631605/05/16 Transistor structures and fabrication methods thereof
962016012633605/05/16 Method of improved ca/cb contact and device thereof
972016012635205/05/16 Hybrid orientation fin field effect transistor and planar field effect transistor
982016012635305/05/16 Finfet device including a uniform silicon alloy fin
992016012430805/05/16 Alternating space decomposition in circuit structure fabrication
1002016012612005/05/16 Work-in-progress substrate processing methods and systems for use in the fabrication of integrated circuits
1012016012613205/05/16 Methods for fabricating integrated circuits with isolation regions having uniform step heights
1022016012623905/05/16 Integrated circuits with resistor structures formed from mim capacitor material and methods for fabricating same
1032016011643504/28/16 Nanochannel electrode devices
1042016011724004/28/16 Performing secure address relocation within a multi-processor system sharing a same physical memory channel to external memory
1052016011743204/28/16 Method and assisted metal routing
1062016011743304/28/16 Integrated circuit timing variability reduction
1072016011813804/28/16 Programming an electrical fuse with a silicon-controlled rectifier
1082016011825104/28/16 Methods of forming doped epitaxial sige material on semiconductor devices
1092016011825504/28/16 Methods of forming strained epitaxial semiconductor material(s) above a strain-relaxed buffer layer
1102016011829804/28/16 Oxide mediated epitaxial nickel disilicide alloy contact formation
1112016011830404/28/16 Fabrication of nanowire structures
1122016011834104/28/16 Precut metal lines
1132016011835804/28/16 Direct injection molded solder process for forming solder bumps on wafers
1142016011838504/28/16 Replacement gate structures for transistor devices
1152016011838604/28/16 Semiconductor structure having finfet ultra thin body and methods of fabrication thereof
1162016011841404/28/16 Dual three-dimensional and rf semiconductor devices using local soi
1172016011845804/28/16 Metal-insulator-metal back end of line capacitor structures
1182016011846804/28/16 Multiple layer interface formation for semiconductor structure
1192016011847204/28/16 Methods of forming 3d devices with dielectric isolation and a strained channel region
1202016011847304/28/16 Non-planar schottky diode and fabrication
1212016011848004/28/16 Methods of forming a tri-gate finfet device and the resulting device
1222016011848304/28/16 Multi-gate fets having corrugated semiconductor stacks and forming the same
1232016011849904/28/16 Fd devices in advanced semiconductor techniques
1242016011829204/28/16 Integrated circuits with an air gap and methods of producing the same
1252016011850004/28/16 Fin structures and multi-vt scheme based on tapered fin and method to form
1262016011048904/21/16 Methods, apparatus, and system for using filler cells in design of integrated circuit devices
1272016011132004/21/16 T-shaped fin isolation region and methods of fabrication
1282016011132204/21/16 Finfet semiconductor device having local buried oxide
1292016011133504/21/16 Semiconductor structure with self-aligned wells and multiple channel materials
1302016011133904/21/16 Contact liners for integrated circuits and fabrication methods thereof
1312016011134104/21/16 Method of utilizing trench silicide in a gate cross-couple construct
1322016011135204/21/16 Dielectric cover for a through silicon via
1332016011136004/21/16 Dummy metal structure and forming dummy metal structure
1342016011137404/21/16 Low energy etch process for nitrogen-containing dielectric layer
1352016011138104/21/16 Semiconductor structure including a die seal leakage detection material, the formation thereof and method including a test of a semiconductor structure
1362016011138204/21/16 Vertical breakdown protection layer
1372016011138604/21/16 Bond pad structure for low temperature flip chip bonding
1382016011140604/21/16 Top-side interconnection substrate for die-to-die interconnection
1392016011141404/21/16 Scr with fin body regions for esd protection
1402016011142204/21/16 Method for making high voltage integrated circuit devices in a fin-type process and resulting devices
1412016011149104/21/16 Fin device with blocking layer in channel region
1422016011151304/21/16 Multi-channel gate-all-around fet
1432016011151404/21/16 Ultra-low resistance gate structure for non-planar device via minimized work function material
1442016011153904/21/16 High mobility pmos and nmos devices having si-ge quantum wells
1452016011154904/21/16 Methods of forming a semiconductor circuit element and semiconductor circuit element
1462016011186704/21/16 Methods of post-process dispensation of plasma induced damage protection component
1472016010464404/14/16 Process for integrated circuit fabrication including a uniform depth tungsten recess technique
1482016010454104/14/16 Novel otprom for post-process programming using selective breakdown
1492016010462104/14/16 Semiconductor device having common contact and gate properties
1502016010463804/14/16 Semiconductor structure including a layer of a first metal between a diffusion barrier layer and a second metal and the formation thereof
1512016010467004/14/16 Interlayer ballistic conductor signal lines
1522016010467204/14/16 Low capacitance ballistic conductor signal lines
1532016010467704/14/16 Self aligned via fuse
1542016010470704/14/16 Method and structure for transistors using gate stack dopants with minimal nitrogen penetration
1552016010476204/14/16 Method of fabricating a mim capacitor with minimal voltage coefficient and a decoupling mim capacitor and analog/rf mim capacitor on the same chip with high-k dielectrics
1562016010477004/14/16 Profile control over a collector of a bipolar junction transistor
1572016010477404/14/16 Non-planar vertical dual source drift metal-oxide semiconductor (vdsmos)
1582016010479904/14/16 Dual-strained nanowire and finfet devices with dielectric isolation
1592016010517904/14/16 Level shifting an i/o signal into multiple voltage domains
1602016009833204/07/16 Dynamic multi-purpose external access points connected to core interfaces within a system on chip (soc)
1612016009916804/07/16 Method for defining an isolation region(s) of a semiconductor structure
1622016009917104/07/16 Dimension-controlled via formation processing
1632016009923904/07/16 Methods, apparatus and system for reduction of power consumption in a semiconductor device
1642016009929704/07/16 Flexible active matrix display
1652016009930204/07/16 Embedded metal-insulator-metal capacitor
1662016009932104/07/16 Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layers
1672016009932904/07/16 Suspended body field effect transistor
1682016009933304/07/16 Field effect transistor and fabrication
1692016009933604/07/16 Opc enlarged dummy electrode to eliminate ski slope at esige
1702016009934304/07/16 Tunneling field effect transistor and methods of making such a transistor
1712016009934404/07/16 Facilitating fabricating gate-all-around nanowire field-effect transistors
1722016009356503/31/16 Printing minimum width features at non-minimum pitch and resulting device
1732016009369203/31/16 Finfet semiconductor devices with replacement gate structures
1742016009370403/31/16 Method for creating self-aligned transistor contacts
1752016009371303/31/16 Semiconductor devices with replacement gate structures
1762016009373903/31/16 Finfet semiconductor device with isolated channel regions
1772016009371103/31/16 Tantalum carbide metal gate stack for mid-gap work function applications
1782016008707303/24/16 Bipolar junction transistors with an air gap in the shallow trench isolation
1792016008256603/24/16 Wafer slip detection during cmp processing
1802016008684903/24/16 Constrained nanosecond laser anneal of metal interconnect structures
1812016008686003/24/16 Methods for making robust replacement metal gates and multi-threshold devices in a soft mask integration scheme
1822016008688603/24/16 Nanowire compatible e-fuse
1832016008695203/24/16 Preventing epi damage for cap nitride strip scheme in a fin-shaped field effect transistor (finfet) device
1842016007793903/17/16 Recovering from uncorrected memory errors
1852016007908603/17/16 Method of forming a semiconductor device and according semiconductor device
1862016007911603/17/16 Wafer with improved plating current distribution
1872016007916803/17/16 Integrated circuits with metal-titanium oxide contacts and fabrication methods
1882016007918003/17/16 Overlay mark dependent dummy fill to mitigate gate height variation
1892016007924203/17/16 Patterning multiple, dense features in a semiconductor device using a memorization layer
1902016007934203/17/16 Method and device for an integrated trench capacitor
1912016007939703/17/16 Partial fin on oxide for improved electrical isolation of raised active regions
1922016007173103/10/16 Finfet doping method with curvilinear trajectory implantation beam path
1932016007174203/10/16 Photoresist collapse forming a physical unclonable function
1942016007179103/10/16 Multimetal interlayer interconnects
1952016007183503/10/16 Metal gate for robust esd protection
1962016007184503/10/16 Directed self-assembly material growth mask for forming vertical nanowires
1972016007192803/10/16 Methods of forming gate structures for finfet devices and the resulting semiconductor products
1982016007193003/10/16 Multiple directed self-assembly material mask patterning for forming vertical nanowires
1992016007193203/10/16 Finfet structures having uniform channel size and methods of fabrication
2002016007194703/10/16 Method including a replacement of a dummy gate structure with a gate structure including a ferroelectric material
2012016007195403/10/16 Robust post-gate spacer processing and device
2022016007196203/10/16 Symmetrical lateral bipolar junction transistor and use of same in characterizing and protecting transistors
2032016007197803/10/16 Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer
2042016007197903/10/16 Fin device with blocking layer in channel region
2052016006188003/03/16 Methods, apparatus and system for tddb testing
2062016006316703/03/16 Method and system for via retargeting
2072016006412303/03/16 Temperature independent resistor
2082016006422803/03/16 Method of forming a semiconductor structure including a ferroelectric material and semiconductor structure including a ferroelectric transistor
2092016006423603/03/16 Methods of patterning features having differing widths
2102016006425003/03/16 Methods of forming metastable replacement fins for a finfet semiconductor device by performing a replacement growth process
2112016006435403/03/16 Method for electronic circuit assembly on a paper substrate
2122016006437103/03/16 Non-planar esd device for non-planar output transistor and common fabrication thereof
2132016006437203/03/16 Esd snapback based clamp for finfet
2142016006438203/03/16 Selective fusi gate formation in gate first cmos technologies
2152016006447103/03/16 Embedded capacitor
2162016006448403/03/16 Lateral bipolar junction transistors on a silicon-on-insulator substrate with a thin device layer thickness
2172016006451003/03/16 Device including a floating gate electrode and a layer of ferroelectric material and the formation thereof
2182016006451403/03/16 Borderless contact formation through metal-recess dual cap integration
2192016006452303/03/16 Semiconductor structure having a source and a drain with reverse facets
2202016006452603/03/16 Methods of forming alternative channel materials on finfet semiconductor devices
2212016006454403/03/16 Finfet semiconductor device with isolated fins made of alternative channel materials
2222016006428603/03/16 Integrated circuits and methods for fabricating integrated circuits
2232016006447203/03/16 Integrated circuits including a mimcap device and methods of forming the same for long and controllable reliability lifetime
2242016006451303/03/16 Integrated circuits with a bowed substrate, and methods for producing the same
2252016006451503/03/16 Methods of making integrated circuits and components thereof
2262016005438302/25/16 Semiconductor structure having test device
2272016005528102/25/16 Model-based generation of dummy features
2282016005607502/25/16 Precut metal lines
2292016005610402/25/16 Self-aligned back end of line cut
2302016005610602/25/16 Structure with self aligned resist layer on an interconnect surface and making same
2312016005623102/25/16 Semiconductor devices and fabrication methods thereof
2322016005623802/25/16 Raised source/drain epi with suppressed lateral epi overgrowth
2332016005626102/25/16 Embedded sigma-shaped semiconductor alloys formed in transistors
2342016005626302/25/16 Methods of forming a gate cap layer above a replacement gate structure
2352016005626502/25/16 Methods of making a self-aligned channel drift device
2362016005628802/25/16 Circuit element including a layer of a stress-creating material providing a variable stress
2372016005629402/25/16 Epitaxial growth of silicon for finfets with non-rectangular cross-sections
2382016005603302/25/16 Low temperature atomic layer deposition of oxides on compound semiconductors
2392016005607202/25/16 Multilayered contact structure having nickel, copper, and nickel-iron layers
2402016005625302/25/16 Integrated circuits with diffusion barrier layers and processes for preparing integrated circuits including diffusion barrier layers
2412016004705802/18/16 Metal plating system including gas bubble removal unit
2422016004930202/18/16 Method of forming a semiconductor circuit element and semiconductor circuit element
2432016004932702/18/16 Methods of fabricating beol interlayer structures
2442016004933202/18/16 Methods of forming contact structures for semiconductor devices and the resulting devices
2452016004937002/18/16 Methods of forming mis contact structures for semiconductor devices by selective deposition of insulating material and the resulting devices
2462016004939902/18/16 Gate structures for semiconductor devices with a conductive etch stop layer
2472016004940002/18/16 Threshold voltage control for mixed-type non-planar semiconductor devices
2482016004940102/18/16 Hybrid contacts for commonly fabricated semiconductor devices using same metal
2492016004940202/18/16 Semiconductor device having fins with in-situ doped, punch-through stopper layer and related methods

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Globalfoundries Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Globalfoundries Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by