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Globalfoundries, Inc. patents


      
Recent patent applications related to Globalfoundries, Inc.. Globalfoundries, Inc. is listed as an Agent/Assignee. Note: Globalfoundries, Inc. may have other listings under different names/spellings. We're not affiliated with Globalfoundries, Inc., we're just tracking patents.

ARCHIVE: New 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries, Inc.-related inventors



Globalfoundries

Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double…

Globalfoundries

Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and…

Search recent Press Releases: Globalfoundries, Inc.-related press releases
Count Application # Date Globalfoundries, Inc. patents (updated weekly) - BOOKMARK this page
12014023804508/28/14 new patent  Semiconductor device comprising a stacked die configuration including an integrated peltier element
22014024278808/28/14 new patent  Method of forming a high quality interfacial layer for a semiconductor device by performing a low temperature ald process
32014024523808/28/14 new patent  Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications
42014023950308/28/14 new patent  Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
52014023124508/21/14Adjustable current shield for electroplating processes
62014023190708/21/14Methods of inducing a desired stress in the channel region of a transistor by performing ion implantation/anneal processes on the gate electrode
72014023196008/21/14Polysilicon resistor formation
82014023243308/21/14Circuit element including a layer of a stress-creating material providing a variable stress and method for the formation thereof
92014023301408/21/14Infrared-based metrology for detection of stress and defects around through silicon vias
102014023188508/21/14Integrated circuits and methods for fabricating integrated circuits having metal gate electrodes
112014023192208/21/14Semiconductor gate structure for threshold voltage modulation and method of making same
122014023201008/21/14Integrated circuits and methods of forming the same with multi-level electrical connection
132014023505508/21/14Method for fabricating a semiconductor integrated circuit with a litho-etch, litho-etch process for etching trenches
142014022476408/14/14Chemical and physical templates for forming patterns using directed self-assembly materials
152014022516808/14/14Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device
162014022520108/14/14Edge and strap cell design for sram array
172014022527008/14/14Method for off-grid routing structures utilizing self aligned double patterning (sadp) technology
182014022784508/14/14Methods of forming multiple n-type semiconductor devices with different threshold voltages on a semiconductor substrate
192014022784908/14/14Methods of trimming nanowire structures
202014022785808/14/14Shallow trench isolation integration methods and devices formed thereby
212014022786908/14/14Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions
222014022787208/14/14Methods of forming conductive structures using a sacrificial liner layer
232014022787908/14/14Methods for fabricating integrated circuits with improved semiconductor fin structures
242014021746708/07/14Methods of forming substrates comprised of different semiconductor materials and the resulting device
252014021748008/07/14Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer
262014021754408/07/14Methods of forming a transistor device on a bulk substrate and the resulting device
272014021758808/07/14Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device
282014021759108/07/14Multi-layer barrier layer for interconnect structure
292014022075608/07/14Methods of forming semiconductor devices by forming a semiconductor layer above source/drain regions prior to removing a gate cap layer
302014022075908/07/14Methods for fabricating integrated circuits having gate to active and gate to gate interconnects
312014022076708/07/14Double-pattern gate formation processing with critical dimension control
322014022339008/07/14Retargeting semiconductor device shapes for multiple patterning processes
332014022339208/07/14Optimized optical proximity correction handling for lithographic fills
342014021748208/07/14Integrated circuits having replacement gate structures and methods for fabricating the same
352014021751708/07/14Integrated circuits including finfet devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
362014022077508/07/14Methods for fabricating integrated circuits having embedded electrical interconnects
372014022078608/07/14Methods for optical proximity correction in the design and fabrication of integrated circuits
382014021008807/31/14Method for reducing wettability of interconnect material at corner interface and device incorporating same
392014021117507/31/14Enhancing resolution in lithographic processes using high refractive index fluids
402014021541507/31/14Automated design layout pattern correction based on context-aware patterns
412014020956307/31/14Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein
422014021303307/31/14Methods for fabricating electrically-isolated finfet semiconductor devices
432014021303707/31/14Methods for fabricating integrated circuits having confined epitaxial growth regions
442014020328007/24/14Electrical test structure for devices employing high-k dielectrics or metal gates
452014020329807/24/14Strained silicon carbide channel for electron mobility of nmos
462014020333907/24/14Semiconductor device comprising self-aligned contact elements and a replacement gate electrode structure
472014020337607/24/14Finfet integrated circuits with uniform fin height and methods for fabricating the same
482014020340507/24/14Method to dynamically tune precision resistance
492014020344607/24/14Through silicon via device having low stress, thin film gaps and methods for forming the same
502014020381407/24/14Method and apparatus for measuring alpha particle induced soft errors in semiconductor devices
512014020615707/24/14Method of forming a semiconductor structure including a vertical nanowire
522014020828507/24/14Self-aligned double patterning via enclosure design
532014020327907/24/14Test structure and method to faciltiate development/optimization of process parameters
542014020344907/24/14Integrated circuits and methods of forming the same with metal layer connection to through-semiconductor via
552014020382707/24/14Integrated circuits and methods of forming the same with embedded interconnect connection to through-semiconductor via
562014019746807/17/14Methods of forming semiconductor device with self-aligned contact elements and the resulting device
572014019754407/17/14Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials
582014019749807/17/14Integrated circuits and methods for fabricating integrated circuits with improved silicide contacts
592014019984507/17/14Selective removal of gate structure sidewall(s) to facilitate sidewall spacer protection
602014019132407/10/14Methods of forming bulk finfet devices by performing a recessing process on liner materials to define different fin heights and finfet devices with such recessed liner materials
612014019133207/10/14Pfet devices with different structures and performance characteristics
622014019395707/10/14Reducing gate height variance during semiconductor device formation
632014018355107/03/14Blanket epi super steep retrograde well formation without si recess
642014018363807/03/14Methods of using a trench salicide routing layer
652014018372007/03/14Methods of manufacturing integrated circuits having a compressive nitride layer
662014018503007/03/14Asymmetric reticle heating of multilayer reticles eliminated by dummy exposures and related methods
672014018703607/03/14Integration of ru wet etch and cmp for beol interconnects with ru layer
682014018374507/03/14Gate electrode(s) and contact structure(s), and methods of fabrication thereof
692014017553906/26/14Canyon gate transistor and methods for its fabrication
702014017816006/26/14Overhead substrate handling and storage system
712014017882406/26/14Optimizing lithographic processes using laser annealing techniques
722014017556206/26/14Spacer divot sealing method and semiconductor device incorporating same
732014017909306/26/14Gate structure formation processes
742014016711906/19/14Methods of forming a sidewall spacer having a generally triangular shape and a semiconductor device having such a spacer
752014016712006/19/14Methods of forming a finfet semiconductor device by performing an epitaxial growth process
762014016726406/19/14Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structures
772014016726506/19/14Methods of forming a bi-layer cap layer on copper-based conductive structures and devices with such a cap layer
782014017053306/19/14Extreme ultraviolet lithography (euvl) alternating phase shift mask
792014017083906/19/14Methods of forming fins for a finfet device wherein the fins have a high germanium content
802014017353306/19/14Locally optimized coloring for cleaning lithographic hotspots
812014015905206/12/14Method and structure for transistor with reduced drain-induced barrier lowering and on resistance
822014015912506/12/14Contact landing pads for a semiconductor device and methods of making same
832014015912606/12/14Methods of forming a finfet semiconductor device with undoped fins
842014015916406/12/14Double sidewall image transfer process
852014015917106/12/14Methods of forming bulk finfet semiconductor devices by performing a liner recessing process to define fin heights and finfet devices with such a recessed liner
862014015919906/12/14High density serial capacitor device and methods of making such a capacitor device
872014016217606/12/14Semiconductor device resolution enhancement by etching multiple sides of a mask
882014016244706/12/14Finfet hybrid full metal gate with borderless contacts
892014015176006/05/14Doped flowable pre-metal dielectric
902014015180706/05/14Combination finfet and planar fet semiconductor device and methods of making such a device
912014015181606/05/14Novel contact structure for a semiconductor device and methods of making same
922014015181806/05/14Semiconductor device with a silicon dioxide gate insulation layer implanted with a rare earth element and methods of making such a device
932014014525705/29/14Semiconductor device having a metal recess
942014014527405/29/14Methods of forming replacement gate structures for nfet semiconductor devices and devices having such gate structures
952014014533205/29/14Methods of forming graphene liners and/or cap layers on copper-based conductive structures
962014014801105/29/14Method of forming semiconductor fins
972014014995205/29/14Trench silicide mask generation using designated trench transfer and trench block regions
982014014160505/22/14Finfet formation using double patterning memorization
992014013877905/22/14Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance
1002014014160505/22/14Finfet formation using double patterning memorization
1012014013877905/22/14Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance
1022014013173505/15/14Source and drain doping using doped raised source and drain regions
1032014013177105/15/14Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof
1042014013180505/15/14Transistor with embedded si/ge material having reduced offset and superior uniformity
1052014013188105/15/14Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection
1062014013183105/15/14Integrated ciruit including an fin-based diode and methods of its fabrication
1072014013481405/15/14Methods of manufacturing integrated circuits having finfet structures with epitaxially formed source/drain regions
1082014013482205/15/14Methods for fabricating integrated circuits including semiconductive resistor structures in a finfet architecture
1092014013173505/15/14Source and drain doping using doped raised source and drain regions
1102014013177105/15/14Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof
1112014013180505/15/14Transistor with embedded si/ge material having reduced offset and superior uniformity
1122014013188105/15/14Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection
1132014013183105/15/14Integrated ciruit including an fin-based diode and methods of its fabrication
1142014013481405/15/14Methods of manufacturing integrated circuits having finfet structures with epitaxially formed source/drain regions
1152014013482205/15/14Methods for fabricating integrated circuits including semiconductive resistor structures in a finfet architecture
1162014012479405/08/14Fabrication of reverse shallow trench isolation structures with super-steep retrograde wells
1172014012484105/08/14Methods of forming replacement gate structures on semiconductor devices and the resulting device
1182014012999905/08/14Method for selectively modeling narrow-width stacked device performance
1192014012479405/08/14Fabrication of reverse shallow trench isolation structures with super-steep retrograde wells
1202014012484105/08/14Methods of forming replacement gate structures on semiconductor devices and the resulting device
1212014012999905/08/14Method for selectively modeling narrow-width stacked device performance
1222014011741705/01/14Performance enhancement in transistors by providing a graded embedded strain-inducing semiconductor region with adapted angles with respect to the substrate surface
1232014011741805/01/14Three-dimensional silicon-based transistor comprising a high-mobility channel formed by non-masked epitaxy
1242014011741905/01/14Fin etch and fin replacement for finfet integration
1252014011750705/01/14Double trench well formation in sram cells
1262014012067705/01/14Methods of forming enhanced mobility channel regions on 3d semiconductor devices, and devices comprising same
1272014011741705/01/14Performance enhancement in transistors by providing a graded embedded strain-inducing semiconductor region with adapted angles with respect to the substrate surface
1282014011741805/01/14Three-dimensional silicon-based transistor comprising a high-mobility channel formed by non-masked epitaxy
1292014011741905/01/14Fin etch and fin replacement for finfet integration
1302014011750705/01/14Double trench well formation in sram cells
1312014012067705/01/14Methods of forming enhanced mobility channel regions on 3d semiconductor devices, and devices comprising same
1322014011079804/24/14Methods of forming a semiconductor device with low-k spacers and the resulting device
1332014011085404/24/14Semiconductor dies with reduced area consumption
1342014011341904/24/14Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material
1352014011342004/24/14Methods of avoiding shadowing when forming source/drain implant regions on 3d semiconductor devices
1362014011345504/24/14Method of forming a semiconductor structure including a wet etch process for removing silicon nitride
1372014011077204/24/14Integrated circuit decoupling capacitor arrangement
1382014011079404/24/14Facilitating gate height uniformity and inter-layer dielectric protection
1392014011079804/24/14Methods of forming a semiconductor device with low-k spacers and the resulting device
1402014011085404/24/14Semiconductor dies with reduced area consumption
1412014011341904/24/14Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material
1422014011342004/24/14Methods of avoiding shadowing when forming source/drain implant regions on 3d semiconductor devices
1432014011345504/24/14Method of forming a semiconductor structure including a wet etch process for removing silicon nitride
1442014011077204/24/14Integrated circuit decoupling capacitor arrangement
1452014011079404/24/14Facilitating gate height uniformity and inter-layer dielectric protection
1462014010342004/17/14Advanced faraday shield for a semiconductor device
1472014010657504/17/14Directed self-assembly of block copolymers using laser annealing
1482014010342004/17/14Advanced faraday shield for a semiconductor device
1492014010657504/17/14Directed self-assembly of block copolymers using laser annealing
1502014009753804/10/14Semiconductor device having a self-forming barrier layer at via bottom
1512014009789204/10/14Double patterning compatible colorless m1 route
1522014010080604/10/14Method and apparatus for matching tools based on time trace data
1532014009845904/10/14Capacitor and contact structures, and formation processes thereof
1542014009753804/10/14Semiconductor device having a self-forming barrier layer at via bottom
1552014009789204/10/14Double patterning compatible colorless m1 route
1562014010080604/10/14Method and apparatus for matching tools based on time trace data
1572014009845904/10/14Capacitor and contact structures, and formation processes thereof
1582014009753804/10/14Semiconductor device having a self-forming barrier layer at via bottom
1592014009789204/10/14Double patterning compatible colorless m1 route
1602014010080604/10/14Method and apparatus for matching tools based on time trace data
1612014009845904/10/14Capacitor and contact structures, and formation processes thereof
1622014008438303/27/14Methods of forming 3-d semiconductor devices using a replacement gate technique and a novel 3-d device
1632014008438303/27/14Methods of forming 3-d semiconductor devices using a replacement gate technique and a novel 3-d device
1642014007727403/20/14Integrated circuits with improved gate uniformity and methods for fabricating same
1652014007736803/20/14Repairing anomalous stiff pillar bumps
1662014007738003/20/14Bit cell with double patterned metal layer structures
1672014007881703/20/14Integrated circuits with sram cells having additional read stacks and methods for their fabrication
1682014007727403/20/14Integrated circuits with improved gate uniformity and methods for fabricating same
1692014007736803/20/14Repairing anomalous stiff pillar bumps
1702014007738003/20/14Bit cell with double patterned metal layer structures
1712014007881703/20/14Integrated circuits with sram cells having additional read stacks and methods for their fabrication
1722014007028303/13/14Field effect transistor and method of fabrication
1732014007028503/13/14Methods of forming semiconductor devices with self-aligned contacts and the resulting devices
1742014007032103/13/14Integrated circuits having boron-doped silicon germanium channels and methods for fabricating the same
1752014007032203/13/14Methods of forming different finfet devices with different threshold voltages and integrated circuit products containing such devices
1762014007035803/13/14Method of tailoring silicon trench profile for super steep retrograde well field effect transistor
1772014007040503/13/14Stacked semiconductor devices with a glass window wafer having an engineered coefficient of thermal expansion and methods of making same
1782014007028303/13/14Field effect transistor and method of fabrication
1792014007028503/13/14Methods of forming semiconductor devices with self-aligned contacts and the resulting devices
1802014007032103/13/14Integrated circuits having boron-doped silicon germanium channels and methods for fabricating the same
1812014007032203/13/14Methods of forming different finfet devices with different threshold voltages and integrated circuit products containing such devices
1822014007035803/13/14Method of tailoring silicon trench profile for super steep retrograde well field effect transistor
1832014007040503/13/14Stacked semiconductor devices with a glass window wafer having an engineered coefficient of thermal expansion and methods of making same
1842014006173203/06/14Method and device to achieve self-stop and precise gate height
1852014006181203/06/14Semiconductor device incorporating a multi-function layer into gate stacks
1862014006192503/06/14Low resistivity gate conductor
1872014006573403/06/14Method and system for determining overlap process windows in semiconductors by inspection techniques
1882014006580803/06/14Method of forming a material layer in a semiconductor structure
1892014006581103/06/14Replacement metal gate semiconductor device formation using low resistivity metals
1902014006581503/06/14Beol integration scheme for copper cmp to prevent dendrite formation
1912014006854303/06/14Method to enhance double patterning routing efficiency
1922014006582803/06/14Selective fin cut process
1932014006173203/06/14Method and device to achieve self-stop and precise gate height
1942014006181203/06/14Semiconductor device incorporating a multi-function layer into gate stacks
1952014006192503/06/14Low resistivity gate conductor
1962014006573403/06/14Method and system for determining overlap process windows in semiconductors by inspection techniques
1972014006580803/06/14Method of forming a material layer in a semiconductor structure
1982014006581103/06/14Replacement metal gate semiconductor device formation using low resistivity metals
1992014006581503/06/14Beol integration scheme for copper cmp to prevent dendrite formation
2002014006854303/06/14Method to enhance double patterning routing efficiency
2012014006582803/06/14Selective fin cut process
2022014005464902/27/14Semiconductor devices and methods of forming the semiconductor devices including a retrograde well
2032014005472302/27/14Isolation structures for finfet semiconductor devices
2042014005708902/27/14Hardmask layer with alternating nanolayers
2052014005709902/27/14Hardmask capping layer
2062014005741502/27/14Methods of forming a layer of silicon on a layer of silicon/germanium
2072014005743502/27/14Methods of forming a metal cap layer on copper-based conductive structures on an integrated circuit device
2082014005950602/27/14Method and apparatus for applying post graphic data system stream enhancements
2092014004891202/20/14Compressive stress transfer in an interlayer dielectric of a semiconductor device by providing a bi-layer of superior adhesion and internal stress
2102014005001702/20/14Device comprising a plurality of static random access memory cells and method of operation thereof
2112014005003302/20/14Memory cell assembly including an avoid disturb cell
2122014005122702/20/14Methods of forming isolation structures for semiconductor devices by performing a dry chemical removal process
2132014005123302/20/14Methods of thinning and/or dicing semiconducting substrates having integrated circuit products formed thereon
2142014005124002/20/14Methods of forming a replacement gate structure having a gate electrode comprised of a deposited intermetallic compound material
2152014004251002/13/14Capacitors positioned at the device level in an integrated circuit product and methods of making such capacitors
2162014004254902/13/14Methods of forming stress-inducing layers on semiconductor devices
2172014004255002/13/14Integrated circuits with improved spacers and methods for fabricating same
2182014004255102/13/14Sram integrated circuits with buried saddle-shaped finfet and methods for their fabrication
2192014004264102/13/14Middle-of-the-line constructs using diffusion contact structures
2202014004306102/13/14Computing multi-magnet based devices and methods for solution of optimization problems
2212014004488902/13/14Methods of making stressed material layers and a system for forming such layers
2222014004533002/13/14Methods of in-situ vapor phase deposition of self-assembled monolayers as copper adhesion promoters and diffusion barriers
2232014004647402/13/14Waferstart processes and systems for integrated circuit fabrication
2242014003501002/06/14Integrated circuit having a replacement gate structure and method for fabricating the same
2252014003509902/06/14Integrated circuits with metal-insulator-metal (mim) capacitors and methods for fabricating same
2262014003515102/06/14Integrated circuits and methods for fabricating integrated circuits using double patterning processes
2272014003808902/06/14Self-polarized mask and self-polarized mask application
2282014003840202/06/14Dual work function finfet structures and methods for fabricating the same
2292014003841202/06/14Interconnect formation using a sidewall mask layer
2302014002667501/30/14Detecting anomalous stiff pillar bumps formed above a metallization system
2312014002667601/30/14Detecting anomalous weak beol sites in a metallization system
2322014002782501/30/14Threshold voltage adjustment in a fin transistor by corner implantation
2332014002785901/30/14Methods of forming transistor devices with high-k insulation layers and the resulting devices
2342014002790201/30/14Repairing anomalous stiff pillar bumps
2352014002791001/30/14Method for reducing wettability of interconnect material at corner interface and device incorporating same
2362014002791801/30/14Cross-coupling based design using diffusion contact structures
2372014003063701/30/14Reticles for use in forming implant masking layers and methods of forming implant masking layers
2382014003087601/30/14Methods for fabricating high carrier mobility finfet structures
2392014002160401/23/14Integrated circuit devices with bump structures that include a protection layer
2402014002161301/23/14Multi-layer barrier layer for interconnect structure
2412014002421201/23/14Multi-layer barrier layer for interconnect structure
2422014002421301/23/14Processes for forming integrated circuits with post-patterning treament
2432014002157901/23/14Integrated circuit with a fin-based fuse, and related fabrication method
2442014001501501/16/14Finfet device with a graphene gate electrode and methods of forming same
2452014001505501/16/14Finfet structures and methods for fabricating the same
2462014001506001/16/14Stress enhanced cmos circuits and methods for their manufacture
2472014001790301/16/14Methods for fabricating integrated circuits with stressed semiconductor material
2482014000872001/09/14Integrated circuit and method for fabricating the same having a replacement gate structure
2492014001130201/09/14Spacer for a gate electrode having tensile stress and a method of forming the same


ARCHIVE: New 2014 2013 2012 2011 2010 2009



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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Globalfoundries, Inc. in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Globalfoundries, Inc. with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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