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Globalfoundries Inc patents


      
Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors




Search recent Press Releases: Globalfoundries Inc-related press releases
Count Application # Date Globalfoundries Inc patents (updated weekly) - BOOKMARK this page
12015024351508/27/15  new patent  Methods of patterning line-type features using a multiple patterning process that enables the use of tighter contact enclosure spacing rules
22015024356308/27/15  new patent  Integrated circuit having multiple threshold voltages
32015024356808/27/15  new patent  Inline residual layer detection and characterization post via post etch using cd-sem
42015024358208/27/15  new patent  New process flow for a combined ca and tsv oxide deposition
52015024360408/27/15  new patent  Cap layers for semiconductor devices with self-aligned contact elements
62015024365208/27/15  new patent  Integration fabrication of metal gate based multiple threshold voltage devices and circuits
72015024365808/27/15  new patent  Integrated circuits with varying gate structures and fabrication methods
82015024366008/27/15  new patent  Cmos structure having low resistance contacts and fabrication method
92015024376108/27/15  new patent  Method to improve reliability of replacement gate device
102015024376208/27/15  new patent  Method to improve reliability of replacement gate device
112015024378708/27/15  new patent  Method for a uniform compressive strain layer and device thereof
122015024378908/27/15  new patent  Semiconductor device with field-inducing structure
132015024255508/27/15  new patent  Methods for fabricating integrated circuits including generating photomasks for directed self-assembly
142015023610608/20/15 Method for creating self-aligned transistor contacts
152015023613308/20/15 Devices and methods of forming higher tunability finfet varactor
162015023613508/20/15 Method to improve reliability of replacement gate device
172015023437808/20/15 Automated mechanical handling systems for integrated circuit fabrication, system computers programmed for use therein, and methods of handling a wafer carrier having an inlet port and an outlet port
182015023583908/20/15 Methods for fabricating integrated circuits using directed self-assembly including lithographically-printable assist features
192015023589608/20/15 Methods for fabricating integrated circuits
202015023590608/20/15 Methods for etching dielectric materials in the fabrication of integrated circuits
212015022668108/13/15 Infrared-based metrology for detection of stress and defects around through silicon vias
222015022849008/13/15 Reduced threshold voltage-width dependency in transistors comprising high-k metal gate electrode structures
232015022855508/13/15 Structure and cancelling tsv-induced substrate stress
242015022858508/13/15 Self-forming barrier integrated with self-aligned cap
252015022859508/13/15 Methods for etching copper during the fabrication of integrated circuits
262015022863508/13/15 Integrated circuit device having supports for use in a multi-dimensional die stack
272015022864808/13/15 Finfet with multilayer fins for multi-value logic (mvl) applications and forming
282015022864908/13/15 Transistor with well tap implant
292015022870808/13/15 Tunable poly resistors for hybrid replacement gate technology and methods of manufacturing
302015022877608/13/15 Methods of forming contacts to semiconductor devices using a bottom etch stop layer and the resulting devices
312015022878108/13/15 Method for making semiconductor device with stressed semiconductor and related devices
322015022879208/13/15 Methods of forming a non-planar ultra-thin body semiconductor device and the resulting devices
332015022851108/13/15 Methods and systems for vibratory chemical mechanical planarization
342015022854308/13/15 Integrated circuits with a tungsten component and methods for producing such integrated circuits
352015022874908/13/15 Enabling enhanced reliability and mobility for replacement gate planar and finfet structures
362015022875508/13/15 Integrated circuits with relaxed silicon / germanium fins
372015022067608/06/15 Color-insensitive rules for routing structures
382015022160508/06/15 Etching of under bump mettallization layer and resulting device
392015022172608/06/15 Finfet with isolated source and drain
402015022174908/06/15 Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
412015022177008/06/15 Epitaxially forming a set of fins in a semiconductor device
422015021240207/30/15 Mask structures and methods of manufacturing
432015021318407/30/15 Method and modified cell architecture and the resulting device
442015021318507/30/15 Method, computer system and computer-readable storage medium for creating a layout of an integrated circuit
452015021406407/30/15 Forming cross-coupled line segments
462015021410507/30/15 Structure and forming silicide on fins
472015021411607/30/15 Low leakage pmos transistor
482015021432207/30/15 Semiconductor device with ferooelectric hafnium oxide and forming semiconductor device
492015021433007/30/15 Replacement low-k spacer
502015021433107/30/15 Replacement metal gate including dielectric gate material
512015021434507/30/15 Dopant diffusion barrier to form isolated source/drains in a semiconductor device
522015021436507/30/15 Multiwidth finfet with channel cladding
532015021436907/30/15 Methods of forming epitaxial semiconductor material on source/drain regions of a finfet semiconductor device and the resulting devices
542015021473307/30/15 Enhanced charge device model clamp
552015021405907/30/15 Integrated circuits with metal-insulator-semiconductor (mis) contact structures and methods for fabricating same
562015021411307/30/15 Methods for fabricating finfet integrated circuits with simultaneous formation of local contact openings
572015021412107/30/15 Ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating same
582015021422807/30/15 Iintegrated circuits with dual silicide contacts and methods for fabricating same
592015020675407/23/15 Gate contact with vertical isolation from source-drain
602015020684407/23/15 Integrated circuits having gate cap protection and methods of forming the same
612015019843507/16/15 Decoupling measurement of layer thicknesses of a plurality of layers of a circuit structure
622015020009307/16/15 Hardmask capping layer
632015020011107/16/15 Planarization scheme for finfet gate height uniformity control
642015020012807/16/15 Methods of forming isolated germanium-containing fins for a finfet semiconductor device
652015020013107/16/15 Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics by modified rf power ramp-up
662015020020507/16/15 Simplified multi-threshold voltage scheme for fully depleted soi mosfets
672015020024207/16/15 Method and device for an integrated trench capacitor
682015020025107/16/15 Mos transistor operated as otp cell with gate dielectric operating as an e-fuse element
692015020026007/16/15 Method to form wrap-around contact for finfet
702015020027007/16/15 Field effect transistors for high-performance and low-power applications
712015020029807/16/15 Modified tunneling field effect transistors and fabrication methods
722015020035307/16/15 Magnetic tunnel junction between metal layers of a semiconductor device
732015020014007/16/15 Methods for fabricating finfet integrated circuits using laser interference lithography techniques
742015020014207/16/15 Methods for fabricating integrated circuits with fully silicided gate electrode structures
752015019286607/09/15 Efficient optical proximity correction repair flow method and apparatus
762015019430707/09/15 Strained fin structures and methods of fabrication
772015019434207/09/15 Formation of carbon-rich contact liner material
782015019441907/09/15 Three-dimensional electrostatic discharge semiconductor device
792015019451707/09/15 Gate stack and contact structure
802015018766007/02/15 Balancing asymmetric spacers
812015018770207/02/15 Middle-of-the-line constructs using diffusion contact structures
822015018776207/02/15 Semiconductor device with a multiple nanowire channel structure and methods of variably connecting such nanowires for current density modulation
832015018789607/02/15 Silicide protection during contact metallization and resulting semiconductor structures
842015018790507/02/15 Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
852015018794507/02/15 Salicide protection during contact metallization and resulting semiconductor structures
862015018794707/02/15 Finfet with active region shaped structures and channel separation
872015017963206/25/15 Semiconductor device comprising an e-fuse and a fet
882015017964006/25/15 Common fabrication of different semiconductor devices with different threshold voltages
892015017975306/25/15 Novel e-fuse design for high-k metal-gate technology
902015017976606/25/15 Buried local interconnect in finfet structure
912015017964406/25/15 Finfet integrated circuits and methods for their fabrication
922015016882406/18/15 Euv pellicle frame with holes and forming
932015016981806/18/15 Pattern-based via redundancy insertion
942015017073506/18/15 Dual port sram bitcell structures with improved transistor arrangement
952015017100106/18/15 Methods of protecting a dielectric mask layer and related semiconductor devices
962015017108606/18/15 Selective growth of a work-function metal in a replacement metal gate of a semiconductor device
972015017097306/18/15 Methods for fabricating integrated circuits using self-aligned quadruple patterning
982015017108206/18/15 Integrated circuit and fabricating the same having a replacement gate structure
992015016218006/11/15 Method, storage medium and system for controlling the processing of lots of workpieces
1002015016218806/11/15 Method of forming a dielectric film
1012015016241406/11/15 Sandwich silicidation for fully silicided gate formation
1022015016243506/11/15 Asymmetric channel growth of a cladding layer over fins of a field effect transistor (finfet) device
1032015015523806/04/15 Making an efuse
1042015014505905/28/15 Methods of forming an e-fuse for an integrated circuit product and the resulting integrated circuit product
1052015014506105/28/15 Novel contact structure for a semiconductor device and methods of making same
1062015014507105/28/15 Methods of forming spacers on finfets and other semiconductor devices
1072015014500005/28/15 Integrated circuits with shallow trench isolations, and methods for producing the same
1082015014634105/28/15 Ald dielectric films with leakage-reducing impurity layers
1092015014696605/28/15 Methods and media for averaging contours of wafer feature edges
1102015013723505/21/15 Finfet semiconductor device having local buried oxide
1112015013719405/21/15 Inverted contact and methods of fabrication
1122015013720305/21/15 Forming finfet cell with fin tip and resulting device
1132015013723505/21/15 Finfet semiconductor device having local buried oxide
1142015013723705/21/15 Undoped epitaxial layer for junction isolation in a fin field effect transistor (finfet) device
1152015013725805/21/15 Forming a low votage antifuse device and resulting device
1162015013727005/21/15 Superior integrity of a high-k gate stack by forming a controlled undercut on the basis of a wet chemistry
1172015013727305/21/15 Method and device for self-aligned contact on a non-recessed metal gate
1182015013730805/21/15 Self-aligned dual-height isolation for bulk finfet
1192015013731605/21/15 Semiconductor device including a resistor and the formation thereof
1202015013737205/21/15 Self forming barrier layer and forming
1212015013855505/21/15 Overlay metrology system and method
1222015014069505/21/15 Method and system for determining overlap process windows in semiconductors by inspection techniques
1232015014075105/21/15 Modified, etch-resistant gate structure(s) facilitating circuit fabrication
1242015014075605/21/15 Fabrication methods facilitating integration of different device architectures
1252015014076105/21/15 Device isolation in finfet cmos
1262015013737305/21/15 Integrated circuits and methods for fabricating integrated circuits with improved contact structures
1272015013738505/21/15 Integrated circuits with close electrical contacts and methods for fabricating the same
1282015014069705/21/15 Test macro for use with a multi-patterning lithography process
1292015014069805/21/15 Test macro for use with a multi-patterning lithography process
1302015012993405/14/15 Methods of forming substantially self-aligned isolation regions on finfet semiconductor devices and the resulting devices
1312015012996205/14/15 Methods of forming replacement gate structures and fins on finfet devices and the resulting devices
1322015012996405/14/15 Nanowire transistor device
1332015012996605/14/15 Transistor including a gate electrode extending all around one or more channel regions
1342015012997005/14/15 Methods and structures for eliminating or reducing line end epi material growth on gate structures
1352015012998305/14/15 Fin-type transistor structures with extended embedded stress elements and fabrication methods
1362015013002605/14/15 Printing minimum width features at non-minimum pitch and resulting device
1372015013006305/14/15 Method to use self-repair cu barrier to solve barrier degradation due to ru cmp
1382015013296205/14/15 Facilitating mask pattern formation
1392015012997205/14/15 Methods of scaling thickness of a gate dielectric structure, methods of forming an integrated circuit, and integrated circuits
1402015013006505/14/15 Method to etch cu/ta/tan selectively using dilute aqueous hf/h2so4 solution
1412015013291405/14/15 Methods for fabricating integrated circuits with robust gate electrode structure protection
1422015012314605/07/15 Increased space between epitaxy on adjacent fins of finfet
1432015012316605/07/15 Methods of forming finfet devices with alternative channel materials
1442015012318105/07/15 Capacitors positioned at the device level in an integrated circuit product and methods of making such capacitors
1452015012321105/07/15 Narrow diffusion break for a fin field effect (finfet) transistor device
1462015012321205/07/15 Planar metrology pad adjacent a set of fins of a fin field effect transistor device
1472015012321405/07/15 Methods of forming a finfet semiconductor device with undoped fins
1482015012325005/07/15 Methods of fabricating defect-free semiconductor structures
1492015012600805/07/15 Methods of forming stressed multilayer finfet devices with alternative channel materials
1502015012601005/07/15 Band engineered semiconductor device and manufacturing thereof
1512015012602305/07/15 Methods of forming gate structures with multiple work functions and the resulting products
1522015012602805/07/15 Methods for fabricating integrated circuits using surface modification to selectively inhibit etching
1532015012603405/07/15 Methods for fabricating integrated circuits including topographical features for directed self-assembly
1542015011515304/30/15 Detection of particle contamination on wafers
1552015011526704/30/15 Planar metrology pad adjacent a set of fins of a fin field effect transistor device
1562015011537004/30/15 Semiconductor device providing enhanced fin isolation and related methods
1572015011537104/30/15 Finfet semiconductor structures and methods of fabricating same
1582015011541804/30/15 Devices and methods of forming fins at tight fin pitches
1592015010857304/23/15 Semiconductor device including vertically spaced semiconductor channel structures and related methods
1602015010857704/23/15 Selective growth of a work-function metal in a replacement metal gate of a semiconductor device
1612015010858004/23/15 Methods of forming bipolar devices and an integrated circuit product containing such bipolar devices
1622015010858304/23/15 Densely packed standard cells for integrated circuit products, and methods of making same
1632015010858604/23/15 Transistor device with improved source/drain junction architecture and methods of making such a device
1642015010864604/23/15 Electro-migration enhancing self-forming barrier process in copper mettalization
1652015011131604/23/15 Method for detecting defects in a diffusion barrier layer
1662015011134904/23/15 Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and the formation thereof
1672015011348404/23/15 Methods of generating circuit layouts that are to be manufactured using sadp routing techniques
1682015010864704/23/15 Hybrid manganese and manganese nitride barriers for back-end-of-line metallization and methods for fabricating the same
1692015011137304/23/15 Reducing gate height variation in rmg process
1702015010241004/16/15 Semiconductor device including stress layer adjacent channel and related methods
1712015010241704/16/15 Double trench well formation in sram cells
1722015010242604/16/15 Three-dimensional transistor with improved channel mobility
1732015010282604/16/15 Design structures and methods for extraction of device channel width
1742015010491804/16/15 Facilitating fabricating gate-all-around nanowire field-effect transistors
1752015010494804/16/15 Facilitating etch processing of a thin film via partial implantation thereof
1762015010242204/16/15 Integrated circuits including finfet devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
1772015010530804/16/15 Aqua regia and hydrogen peroxide hcl combination to remove ni and nipt residues
1782015009719704/09/15 Finfet with sigma cavity with multiple epitaxial material regions
1792015009724604/09/15 Integrated circuit and fabricating the same having a replacement gate structure
1802015009724904/09/15 Cross coupling gate using mulitple patterning
1812015009725204/09/15 Simplified gate-first hkmg manufacturing flow
1822015009726304/09/15 Method and high yield contact integration scheme
1832015009934004/09/15 Methods for preventing oxidation damage during finfet fabrication
1842015009729104/09/15 Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
1852015009933604/09/15 Methods of manufacturing integrated circuits having finfet structures with epitaxially formed source/drain regions
1862015009109404/02/15 Devices and methods of forming finfets with self aligned fin formation
1872015009109704/02/15 Hardmask for a halo/extension implant of a static random access memory (sram) layout
1882015009387704/02/15 Method for manufacturing a semiconductor device by stopping planarization of insulating material on fins
1892015009388704/02/15 Methods for removing a native oxide layer from germanium susbtrates in the fabrication of integrated circuitsi
1902015009388904/02/15 Methods for removing a native oxide layer from germanium susbtrates in the fabrication of integrated circuits
1912015009391404/02/15 Methods for depositing an aluminum oxide layer over germanium susbtrates in the fabrication of integrated circuits
1922015008413103/26/15 Gate height uniformity in semiconductor devices
1932015008713403/26/15 Semiconductor isolation region uniformity
1942015008418303/26/15 Integrated circuits with protected resistors and methods for fabricating the same
1952015008714903/26/15 Methods for fabricating integrated circuits using improved masks
1962015007708603/19/15 Fin width measurement using quantum well structure
1972015007611103/19/15 Feature etching using varying supply of power pulses
1982015007660903/19/15 Methods of forming stressed layers on finfet semiconductor devices and the resulting devices
1992015007662203/19/15 Reducing gate expansion after source and drain implant in gate last process
2002015007665303/19/15 Overlay performance for a fin field effect transistor device
2012015007670503/19/15 Reduced capacitance interlayer structures and fabrication methods
2022015007806803/19/15 Integrated circuits with sram cells having additional read stacks
2032015007977303/19/15 Conformal doping for finfet devices
2042015007655903/19/15 Integrated circuits with strained silicon and methods for fabricating such circuits
2052015007656003/19/15 Integrated circuits including epitaxially grown strain-inducing fills doped with boron for improved robustness from delimination and methods for fabricating the same
2062015007661803/19/15 Integrated circuits with a corrugated gate, and methods for producing the same
2072015007662403/19/15 Integrated circuits having smooth metal gates and methods for fabricating same
2082015006951503/12/15 Integrated circuits having laterally confined epitaxial material overlying fin structures and methods for fabricating same
2092015006096003/05/15 Methods of forming contact structures on finfet semiconductor devices and the resulting devices
2102015006098303/05/15 Semiconductor structure including a split gate nonvolatile memory cell and a high voltage transistor, and the formation thereof
2112015006101403/05/15 Fin pitch scaling and active layer isolation
2122015006102703/05/15 Methods of forming gate structures for transistor devices for cmos applications and the resulting products
2132015006103203/05/15 Fabrication of nickel free silicide for semiconductor contact metallization
2142015006113503/05/15 Copper interconnect with cvd liner and metallic cap
2152015006299603/05/15 Embedded selector-less one-time programmable non-volatile memory
2162015006481203/05/15 Method of forming a semiconductor device employing an optical planarization layer
2172015006487203/05/15 Top corner rounding by implant-enhanced wet etching
2182015006763303/05/15 Color-insensitive rules for routing structures
2192015006104003/05/15 Self-aligned dielectric isolation for finfet devices
2202015006490303/05/15 Methods for fabricating integrated circuits using chemical mechanical planarization to recess metal
2212015006491203/05/15 Methods of forming integrated circuits and multiple critical dimension self-aligned double patterning processes
2222015005398102/26/15 Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device
2232015005407802/26/15 Methods of forming gate structures for finfet devices and the resulting smeiconductor products
2242015005408302/26/15 Strain engineering in semiconductor devices by using a piezoelectric material
2252015005413902/26/15 Through-silicon via with sidewall air gap
2262015005679602/26/15 Method for forming a semiconductor device having a metal gate recess
2272015005678102/26/15 Gate length independent silicon-on-nothing (son) scheme for bulk finfets
2282015005682002/26/15 Systems and methods of solvent temperature control for wafer coating processes
2292015004844602/19/15 Reduction of oxide recesses for gate height control
2302015005078702/19/15 Fully silicided gate formed according to the gate-first hkmg approach
2312015005079202/19/15 Extra narrow diffusion break for 3d finfet technologies
2322015005081102/19/15 Critical dimension and pattern recognition structures for devices manufactured using double patterning techniques
2332015005081202/19/15 Wafer-less auto clean of processing chamber
2342015005210802/19/15 Method, computer readable storage medium and computer system for obtaining snapshots of data
2352015005249402/19/15 Power rail layout for dense standard cell library
2362015004186902/12/15 Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
2372015004189802/12/15 Bulk finfet semiconductor-on-nothing integration
2382015004190502/12/15 Methods of forming replacement gate structures for transistors and the resulting devices
2392015004190602/12/15 Methods of forming stressed fin channel structures for finfet semiconductor devices
2402015004190902/12/15 Completing middle of line integration allowing for self-aligned contacts
2412015004485502/12/15 Methods of forming spacers on finfets and other semiconductor devices
2422015004486102/12/15 Gate silicidation
2432015004185802/12/15 3d transistor channel mobility enhancement
2442015004191002/12/15 Integrated circuits with a partially-depleted region formed over a bulk silicon substrate and methods for fabricating the same
2452015004191102/12/15 3d transistor channel mobility enhancement
2462015003501602/05/15 Nitride spacer for protecting a fin-shaped field effect transistor (finfet) device
2472015003501802/05/15 Devices and methods of forming bulk finfets with lateral seg for source and drain on dielectrics
2482015003505202/05/15 Contact power rail
2492015003505302/05/15 Device and a ldmos design for a finfet integrated circuit



ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009



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