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Globalfoundries Inc patents

Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors




Date Globalfoundries Inc patents (updated weekly) - BOOKMARK this page
09/14/17 new patent  Photonics chip
09/14/17 new patent  Vertical nanowires formed on upper fin surface
09/14/17 new patent  Methods, apparatus and system for a passthrough-based architecture
09/14/17 new patent  Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor
09/14/17 new patent  Method, apparatus and system for a high density middle of line flow
09/14/17 new patent  Finfet semiconductor structures and methods of fabricating same
09/07/17In-situ euv collector cleaning utilizing a cryogenic process
09/07/17Processor with content addressable memory (cam) and monitor component
09/07/17Methods of forming conductive structures with different material compositions in a metallization layer
09/07/17Methods to form multi threshold-voltage dual channel without channel doping
09/07/17Method and structure for srb elastic relaxation
09/07/17Test method and structure for integrated circuits before complete metalization
09/07/17Method of forming super steep retrograde wells on finfet
09/07/17Field-effect transistors with a non-relaxed strained channel
09/07/17Common metal contact regions having different schottky barrier heights and methods of manufacturing same
08/31/17Sense amplifier and latching scheme
08/31/17Compensating for lithographic limitations in fabricating semiconductor interconnect structures
08/31/17Fin cutting process for manufacturing finfet semiconductor devices
08/31/17Electronic device including moat power metallization in trench
08/31/17Semiconductor devices with varying threshold voltage and fabrication methods thereof
08/31/17Finfet device with enlarged channel regions
08/31/17Method, apparatus, and system having super steep retrograde well with silicon and silicon germanium fins
08/31/17Method of forming a semiconductor device structure and semiconductor device structure
08/31/17Serial capacitor device with middle electrode contact
08/31/17Method, apparatus and system for improved nanowire/nanosheet spacers
08/31/17Etch stop for airgap protection
08/31/17Formation of work-function layers for gate electrode using a gas cluster ion beam
08/31/17Increased contact area for finfets
08/31/17Photodetector and methods of manufacture
08/24/17Interconnect reliability structures
08/24/17Method, apparatus, and system for targeted healing of write fails through bias temperature instability
08/24/17Integrated circuit (ic) design analysis and feature extraction
08/24/17Methods for gate formation in circuit structures
08/24/17Methods of forming field effect transistor (fet) and non-fet circuit elements on a semiconductor-on-insulator substrate
08/24/17Devices and methods of reducing damage during beol m1 integration
08/24/17Methods of performing concurrent fin and gate cut etch processes for finfet semiconductor devices and the resulting devices
08/24/17Methods of forming graphene contacts on source/drain regions of finfet devices
08/24/17Method, apparatus, and system for mol interconnects without titanium liner
08/24/17Interconnect structure and forming
08/24/17Reducing antenna effects in soi devices
08/24/17Metal layer tip to tip short
08/24/17Fin cut for taper device
08/17/17A photomask structure with an etch stop layer that enables repairs of drtected defects therein and extreme ultraviolet(euv) photolithograpy methods using the photomask structure
08/17/17Placing and routing implementing back bias in fdsoi
08/17/17Method wherein test cells and dummy cells are included into a layout of an integrated circuit
08/17/17Metal line layout based on line shifting
08/17/17Rapid heating process in the production of semiconductor components
08/17/17Integrated circuit having improved electromigration performance and forming same
08/17/17Finfet having notched fins and forming same
08/10/17Apparatus and vector s-parameter measurements
08/10/17Rule and process assumption co-optimization using feature-specific layout-based statistical analyses
08/10/17Memory built-in self-test (mbist) test time reduction
08/10/17Test strucutre for monitoring interface delamination
08/10/17Corrosion resistant chip sidewall connection with crackstop and hermetic seal
08/10/17Electrostatic discharge and passive structures integrated in a vertical gate fin-type field effect diode
08/10/17Field effect transistors
08/10/17Device with diffusion blocking layer in source/drain region
08/10/17Modified tunneling field effect transistors and fabrication methods
08/03/17System managing mobile sensors for continuous monitoring of pipe networks
08/03/17Gimbal assembly test system and method
08/03/17Multiple contact probe head disassembly method and system
08/03/17Application specific integrated circuit (asic) test screens and selection of such screens
08/03/17Gate cut with high selectivity to preserve interlevel dielectric layer
08/03/17Methods to form multi threshold-voltage dual channel without channel doping
08/03/17Method, apparatus, and system for e-fuse in advanced cmos technologies
Patent Packs
08/03/17Interconnect structure having tungsten contact copper wiring
08/03/17Dicing channels for glass interposers
08/03/17Switch improvement using layout optimization
08/03/17Transistor contacts self-aligned in two dimensions
08/03/17Bipolar junction transistors with extrinsic device regions free of trench isolation
08/03/17Method of forming super steep retrograde wells on finfet
08/03/17Gate stack for integrated circuit structure and forming same
08/03/17Epi facet height uniformity improvement for fdsoi technologies
08/03/17Semiconductor structure(s) with extended source/drain channel interfaces and methods of fabrication
08/03/17Methods to utilize piezoelectric materials as gate dielectric in high frequency rbts in an ic device
08/03/17Method, apparatus and system for voltage compensation in a semiconductor wafer
08/03/17Self-aligned local interconnect technology
07/27/17Electrodeposition systems and methods that minimize anode and/or plating solution degradation
07/27/17Resistance measurement-dependent integrated circuit chip reliability estimation
07/27/17Area and/or power optimization through post-layout modification of integrated circuit (ic) design blocks
Patent Packs
07/27/17Post-layout thermal-aware integrated circuit performance modeling
07/27/17Vertically stacked inductors and transformers
07/27/17Hybrid fin cut etching processes for products comprising tapered and non-tapered finfet semiconductor devices
07/27/17Fabrication of ic structure with metal plug
07/27/17Transistor structures and fabrication methods thereof
07/27/17High performance multiplexed latches
07/27/17Fin cut for taper device
07/20/17Sampling for opc model building
07/20/17Dual-bit 3-t high density mtprom array
07/20/17Stress memorization and defect suppression techniques for nmos transistor devices
07/20/17Self-aligned source/drain contact in replacement metal gate process
07/20/17Structure for beol metal levels with multiple dielectric layers for improved dielectric to metal adhesion
07/20/17Self-aligned device level contact structures
07/20/17Structures with thinned dielectric material
07/20/17Method, apparatus, and system for offset metal power rail for cell design
07/20/17Contact using multilayer liner
07/20/17Multiple threshold voltages using fin pitch and profile
07/20/17Environmentally aware mobile computing devices
07/13/17Signal detection metholodogy for fabrication control
07/13/17Content-addressable memory having multiple reference matchlines to reduce latency
07/13/17Using tensile mask to minimize buckling in substrate
07/13/17Metholodogy for profile control and capacitance reduction
07/13/17Semiconductor structure including a first transistor and a second transistor
07/13/17Fabrication of transistor-based semiconductor device using closed-loop fins
07/13/17Siloxane and organic-based mol contact patterning
07/13/17Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression
07/13/17Self aligned gate shape preventing void formation
07/13/17Method for characterization of a layered structure
07/13/17Method for making semiconductor device with filled gate line end recesses
07/06/17Methodology for early detection of ts to pc short issue
Social Network Patent Pack
07/06/17Test patterns for determining sizing and spacing of sub-resolution assist features (srafs)
07/06/17Replacement low-k spacer
07/06/17On-chip variable capacitor with geometric cross-section
07/06/17Electrical connection around a crackstop structure
07/06/17Replacement low-k spacer
06/29/17Device layer transfer with a preserved handle wafer section
06/29/17Process flow for a combined ca and tsv oxide deposition
06/29/17Self-aligned via forming to conductive line and related wiring structure
06/29/17Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an ic device
06/29/17Methods and devices for metal filling processes
Patent Packs
06/29/17Soi wafers with buried dielectric layers to prevent cu diffusion
06/29/17Transistor using selective undercut at gate conductor and gate insulator corner
06/22/17Electrostatic discharge protection structures for efuses
06/22/17Post-polish wafer cleaning
06/22/17Methods and devices for back end of line via formation
06/22/17Self aligned gate shape preventing void formation
06/22/17Semiconductor structure having silicon germanium fins and fabricating same
06/22/17Structure and fully depleted silicon on insulator structure for threshold voltage modification
06/22/17Methods of forming a protection layer on a semiconductor device and the resulting device
06/22/17Horizontal gate all around nanowire transistor bottom isolation
06/22/17Junction butting structure using nonuniform trench shape
06/15/17Waveguide structures
06/15/17Patterned magnetic shields for inductors and transformers
06/15/17Multiple patterning substrate
06/15/17Wafer handler for infrared laser release
06/15/17Gate tie-down enablement with inner spacer
06/15/17Gate contact with vertical isolation from source-drain
06/15/17Epi facet height uniformity improvement for fdsoi technologies
06/15/17Integrated circuits with spacer chamfering and methods of spacer chamfering
06/15/17Method of forming a semiconductor device structure and semiconductor device structure
06/15/17Method to adjust alley gap between large blocks for floorplan optimization
06/15/17Local interconnect structure including non-eroded contact via trenches
06/08/17Dual-bit 3-t high density mtprom array
06/08/17Gate tie-down enablement with inner spacer
06/08/17Strain engineering devices using partial depth films in through-substrate vias
06/08/17Trench based charge pump device
06/08/17Substrate resistor with overlying gate structure
06/08/17Integrated cmos wafers
06/08/17Metal gate structure and formation
06/08/17Germanium photodetector with soi doping source
Patent Packs
06/08/17Methods for producing integrated circuits with air gaps and integrated circuits produced from such methods
06/01/17Sram-like ebi structure design and implementation to capture mosfet source-drain leakage eariler
06/01/17Coupling inductors in an ic device using interconnecting elements with solder caps and resulting devices
06/01/17Mass spectrometry contaminant identification in semiconductor fabrication
06/01/17Wafer handler and methods of manufacture
06/01/17Amorphous metal interconnections by subtractive etch
06/01/17Raised e-fuse
06/01/17Tri-gate finfet device
06/01/17Methods of forming a contact structure for a vertical channel semiconductor device and the resulting device
06/01/17Replacement body finfet for improved junction profile with gate self-aligned junctions
06/01/17Semiconductor device including finfet and fin varactor
06/01/17Semiconductor device including finfet and fin varactor
05/25/17On-chip sensor for monitoring active circuits on integrated circuit (ic) chips
05/25/17Modeling localized temperature changes on an integrated circuit chip using thermal potential theory
05/25/17Temperature-aware integrated circuit design methods and systems
05/25/17Zig-zag trench structure to prevent aspect ratio trapping defect escape
05/25/17Hdp fill with reduced void formation and spacer damage
05/25/17Method, apparatus, and system for mol interconnects without titanium liner
05/25/17Method and structure for establishing interconnects in packages using thin interposers
05/25/17Extrusion-resistant solder interconnect structures and methods of forming
Social Network Patent Pack
05/25/17Memory device structure
05/25/17Replacement low-k spacer
05/25/17Semiconductor circuit element
05/25/17Poc process flow for conformal recess fill
05/18/17Additions of organic species to facilitate crosslinker removal during pspi cure
05/18/17Methods, apparatus, and systems for minimizing defectivity in top-coat-free lithography and improving reticle cd uniformity
05/18/17Multi-frequency inductors with low-k dielectric area
05/18/17Self-aligned conductive polymer pattern placement error compensation layer
05/18/17Gate structure cut after formation of epitaxial active regions
05/18/17Conductively doped polymer pattern placement error compensation layer
05/18/17Semiconductor fuses with nanowire fuse links and fabrication methods thereof
05/18/17Pattern placement error compensation layer
05/18/17Pattern placement error compensation layer in via opening
05/18/17Special construct for continuous non-uniform active region finfet standard cells
05/18/17Dummy gate used as interconnection and making the same
05/18/17Single and double diffusion breaks on integrated circuit products comprised of finfet devices
05/18/17Method, apparatus and system for improved performance using tall fins in finfet devices
05/18/17Methods of forming pmos and nmos finfet devices on cmos based integrated circuit products
05/18/17Methods of forming pmos finfet devices and multiple nmos finfet devices with different performance characteristics
05/18/17Interconnect structure including middle of line (mol) metal layer local interconnect on etch stop layer
Social Network Patent Pack
05/18/17Mosfet with asymmetric self-aligned contact
05/18/17Mosfet with asymmetric self-aligned contact
05/11/17Barrier structures for underfill blockout regions
05/11/17Chamferless via structures
05/11/17Alternative threshold voltage scheme via direct metal gate patterning for high performance cmos finfets
05/11/17Test structures and forming an according test structure
05/11/17Method, apparatus, and system for e-fuse in advanced cmos technologies
05/11/17Methods of self-forming barrier formation in metal interconnection applications
05/11/17Method, apparatus, and system for stacked cmos logic circuits on fins
05/11/17Reducing thermal runaway in inverter devices
05/11/17Advanced mosfet contact structure to reduce metal-semiconductor interface resistance
05/04/17In-situ contactless monitoring of photomask pellicle degradation
05/04/17Etch stop for airgap protection
05/04/17Anisotropic material damage process for etching low-k dielectric materials
05/04/17Trench silicide contacts with high selectivity process
05/04/17Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices
05/04/17Semiconductor structure with anti-efuse device
05/04/17Antenna diode circuit for manufacturing of semiconductor devices
05/04/17Trench silicide contacts with high selectivity process
05/04/17Semiconductor device with a memory device and a high-k metal gate transistor
05/04/17Metal resistor forming method using ion implantation
05/04/17Method of forming a gate contact structure for a semiconductor device
05/04/17Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts
05/04/17Etch stop for airgap protection
05/04/17Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices
05/04/17Trench silicide contacts with high selectivity process
05/04/17Fin field effect transistor complementary metal oxide semiconductor with dual strained channels with solid phase doping
05/04/17Fin field effect transistor complementary metal oxide semiconductor with dual strained channels with solid phase doping
05/04/17Stress memorization techniques for transistor devices
05/04/17Semiconductor structure including a varactor
Social Network Patent Pack
04/27/17Wafer level electrical test for optical proximity correction and/or etch bias
04/27/17Use of multivariate models to control manufacturing operations
04/27/17Method including a formation of a diffusion barrier and semiconductor structure including a diffusion barrier
04/27/17Unmerged epitaxial process for finfet devices with aggressive fin pitch scaling
04/27/17Unmerged epitaxial process for finfet devices with aggressive fin pitch scaling
04/27/17Method of forming a memory device structure and memory device structure
04/27/17Buffer layer for modulating vt across devices
04/27/17Finfet devices having fins with a tapered configuration and methods of fabricating the same
04/20/17Auto test grouping/clock sequencing for at-speed test
04/20/17Built-in self-test (bist) circuit and associated bist embedded memories
04/20/17Structures with thinned dielectric material
04/20/17Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor
04/20/17Semiconductor device with a gate contact positioned above the active region
04/20/17High doped iii-v source/drain junctions for field effect transistors
04/13/17Forming replacement low-k spacer in tight pitch fin field effect transistors
04/13/17Contacting soi substrates
04/13/17Co-fabricated bulk devices and semiconductor-on-insulator devices
04/13/17Forming replacement low-k spacer in tight pitch fin field effect transistors
04/13/17Forming stressed epitaxial layer using dummy gates
04/06/17Methods of error detection in fabrication processes
04/06/17Methods of error detection in fabrication processes
04/06/17Amophization induced metal-silicon contact formation
04/06/17Source/drain epitaxial electrical monitor
04/06/17Ic structure with angled interconnect elements
04/06/17Implementing stress in a bipolar junction transistor
03/30/17Programmable devices with current-facilitated migration and fabrication methods
03/30/17Programmable via devices with metal/semiconductor via links and fabrication methods thereof
03/30/17Self-aligned gate tie-down contacts with selective etch stop liner
03/30/17Three-dimensional semiconductor transistor with gate contact in active region







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