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Globalfoundries Inc patents


      
Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Inc-related inventors


Semiconductor isolation region uniformity

Globalfoundries

Semiconductor isolation region uniformity

Integrated circuits with protected resistors and methods for fabricating the same

Globalfoundries

Integrated circuits with protected resistors and methods for fabricating the same

Search recent Press Releases: Globalfoundries Inc-related press releases
Count Application # Date Globalfoundries Inc patents (updated weekly) - BOOKMARK this page
12015008413103/26/15 new patent  Gate height uniformity in semiconductor devices
22015008713403/26/15 new patent  Semiconductor isolation region uniformity
32015008418303/26/15 new patent  Integrated circuits with protected resistors and methods for fabricating the same
42015008714903/26/15 new patent  Methods for fabricating integrated circuits using improved masks
52015007708603/19/15Fin width measurement using quantum well structure
62015007611103/19/15Feature etching using varying supply of power pulses
72015007660903/19/15Methods of forming stressed layers on finfet semiconductor devices and the resulting devices
82015007662203/19/15Reducing gate expansion after source and drain implant in gate last process
92015007665303/19/15Overlay performance for a fin field effect transistor device
102015007670503/19/15Reduced capacitance interlayer structures and fabrication methods
112015007806803/19/15Integrated circuits with sram cells having additional read stacks
122015007977303/19/15Conformal doping for finfet devices
132015007655903/19/15Integrated circuits with strained silicon and methods for fabricating such circuits
142015007656003/19/15Integrated circuits including epitaxially grown strain-inducing fills doped with boron for improved robustness from delimination and methods for fabricating the same
152015007661803/19/15Integrated circuits with a corrugated gate, and methods for producing the same
162015007662403/19/15Integrated circuits having smooth metal gates and methods for fabricating same
172015006951503/12/15Integrated circuits having laterally confined epitaxial material overlying fin structures and methods for fabricating same
182015006096003/05/15Methods of forming contact structures on finfet semiconductor devices and the resulting devices
192015006098303/05/15Semiconductor structure including a split gate nonvolatile memory cell and a high voltage transistor, and the formation thereof
202015006101403/05/15Fin pitch scaling and active layer isolation
212015006102703/05/15Methods of forming gate structures for transistor devices for cmos applications and the resulting products
222015006103203/05/15Fabrication of nickel free silicide for semiconductor contact metallization
232015006113503/05/15Copper interconnect with cvd liner and metallic cap
242015006299603/05/15Embedded selector-less one-time programmable non-volatile memory
252015006481203/05/15Method of forming a semiconductor device employing an optical planarization layer
262015006487203/05/15Top corner rounding by implant-enhanced wet etching
272015006763303/05/15Color-insensitive rules for routing structures
282015006104003/05/15Self-aligned dielectric isolation for finfet devices
292015006490303/05/15Methods for fabricating integrated circuits using chemical mechanical planarization to recess metal
302015006491203/05/15Methods of forming integrated circuits and multiple critical dimension self-aligned double patterning processes
312015005398102/26/15Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device
322015005407802/26/15Methods of forming gate structures for finfet devices and the resulting smeiconductor products
332015005408302/26/15Strain engineering in semiconductor devices by using a piezoelectric material
342015005413902/26/15Through-silicon via with sidewall air gap
352015005679602/26/15Method for forming a semiconductor device having a metal gate recess
362015005678102/26/15Gate length independent silicon-on-nothing (son) scheme for bulk finfets
372015005682002/26/15Systems and methods of solvent temperature control for wafer coating processes
382015004844602/19/15Reduction of oxide recesses for gate height control
392015005078702/19/15Fully silicided gate formed according to the gate-first hkmg approach
402015005079202/19/15Extra narrow diffusion break for 3d finfet technologies
412015005081102/19/15Critical dimension and pattern recognition structures for devices manufactured using double patterning techniques
422015005081202/19/15Wafer-less auto clean of processing chamber
432015005210802/19/15Method, computer readable storage medium and computer system for obtaining snapshots of data
442015005249402/19/15Power rail layout for dense standard cell library
452015004186902/12/15Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
462015004189802/12/15Bulk finfet semiconductor-on-nothing integration
472015004190502/12/15Methods of forming replacement gate structures for transistors and the resulting devices
482015004190602/12/15Methods of forming stressed fin channel structures for finfet semiconductor devices
492015004190902/12/15Completing middle of line integration allowing for self-aligned contacts
502015004485502/12/15Methods of forming spacers on finfets and other semiconductor devices
512015004486102/12/15Gate silicidation
522015004185802/12/153d transistor channel mobility enhancement
532015004191002/12/15Integrated circuits with a partially-depleted region formed over a bulk silicon substrate and methods for fabricating the same
542015004191102/12/153d transistor channel mobility enhancement
552015003501602/05/15Nitride spacer for protecting a fin-shaped field effect transistor (finfet) device
562015003501802/05/15Devices and methods of forming bulk finfets with lateral seg for source and drain on dielectrics
572015003505202/05/15Contact power rail
582015003505302/05/15Device and a ldmos design for a finfet integrated circuit
592015003507302/05/15Enabling enhanced reliability and mobility for replacement gate planar and finfet structures
602015003508602/05/15Methods of forming cap layers for semiconductor devices with self-aligned contact elements and the resulting devices
612015003697802/05/15Blazed grating spectral purity filter and methods of making such a filter
622015003794502/05/15Epitaxially forming a set of fins in a semiconductor device
632015003494102/05/15Integrated circuits having finfet semiconductor devices and methods of fabricating the same to resist sub-fin current leakage
642015003506202/05/15Integrated circuits having finfets with improved doped channel regions and methods for fabricating same
652015003760302/05/15Articles including metal structures having maximized bond adhesion and bond reliability, and methods of forming the same
662015004007802/05/15Methods and systems for designing and manufacturing optical lithography masks
672015004008002/05/15Methods for modifying an integrated circuit layout design
682015004009102/05/15Methods for modifying an integrated circuit layout design
692015002834801/29/15Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (finfet) device
702015002843101/29/15Mol insitu pt rework sequence
712015002848201/29/15Device layout for reducing through-silicon-via stress
722015002848901/29/15Method for off-grid routing structures utilizing self aligned double patterning (sadp) technology
732015002850001/29/15Forming alignment mark and resulting mark
742015003117901/29/15Method of forming a semiconductor structure including silicided and non-silicided circuit elements
752015003320101/29/15Systems and methods for fabricating semiconductor device structures
762015002166301/22/15Finfet with insulator under channel
772015002168301/22/15Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
782015002169101/22/15Finfet with electrically isolated active region on bulk semiconductor substrate and fabricating same
792015002169301/22/15Enhancing transistor performance and reliability by incorporating deuterium into a strained capping layer
802015002169501/22/15Epitaxial block layer for a fin field effect transistor device
812015002170201/22/15Shallow trench isolation
822015002170301/22/15Gate oxide quality for complex mosfet devices
832015002170401/22/15Finfet work function metal formation
842015002170901/22/15Structures and methods integrating different fin device architectures
852015002171201/22/15Highly conformal extension doping in advanced multi-gate devices
862015002455701/22/15Semiconductor device having local buried oxide
872015002456001/22/15Gate encapsulation achieved by single-step deposition
882015002457201/22/15Process for faciltiating fin isolation schemes
892015002457301/22/15Methods of forming replacement fins for a finfet semiconductor device by performing a replacement growth process
902015002458501/22/15Systems and methods for fabricating gate structures for semiconductor devices
912015002169401/22/15Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating the same
922015002171401/22/15Integrated circuits having a metal gate structure and methods for fabricating the same
932015002358301/22/15Methods and systems for determining a dose-to-clear of a photoresist
942015002457801/22/15Methods for etching dielectric materials in the fabrication of integrated circuits
952015001477701/15/15Channel semiconductor alloy layer growth adjusted by impurity ion implantation
962015001481301/15/15Complex circuit element and capacitor utilizing cmos compatible antiferroelectric high-k materials
972015001484301/15/15Semiconductor device with improved metal pillar configuration
982015001777401/15/15Method of forming fins with recess shapes
992015001780301/15/15Customized alleviation of stresses generated by through-substrate via(s)
1002015001477601/15/15Finfet integrated circuits and methods for their fabrication
1012015001617401/15/15Integrated circuits with programmable electrical connections and methods for fabricating the same
1022015000853601/08/15Semiconductor device structure and forming a semiconductor device structure
1032015000975001/08/15Device including a dual port static random access memory cell and the formation thereof
1042015001085101/08/15Methods involving color-aware retargeting of individual decomposed patterns when designing masks to be used in multiple patterning processes
1052015001289601/08/15Methods for fabricating integrated circuits including generating photomasks for directed self-assembly
1062015000162701/01/15Spacer chamfering for a replacement metal gate device
1072015000163401/01/15Methods of forming bipolar devices and an integrated circuit product containing such bipolar devices
1082015000163501/01/15Methods of forming an e-fuse for an integrated circuit product and the resulting integrated circuit product
1092015000164001/01/15Transistor device with improved source/drain junction architecture and methods of making such a device
1102015000164201/01/15Field effect transistor and fabrication
1112015000613801/01/15Optical proximity correction for connecting via between layers of a device
1122015000159101/01/15Bulk finfet with partial dielectric isolation featuring a punch-through stopping layer under the oxide
1132015000163001/01/15Structure and methods of fabricating y-shaped dmos finfet
1142015000164301/01/15Integrated circuits having improved high-k dielectric layers and methods for fabrication of same
1152014037480712/25/14Method of device isolation in cladding si through in situ doping
1162014037491512/25/14Integration of optical components in integrated circuits
1172014037796512/25/14Directed self-assembly (dsa) formulations used to form dsa-based lithography films
1182014036775112/18/14Finfet spacer etch for esige improvement
1192014036778712/18/14Methods of forming transistors with retrograde wells in cmos applications and the resulting device structures
1202014036778812/18/14Methods of forming gate structures for cmos based integrated circuit products and the resulting devices
1212014036779012/18/14Methods of forming gate structures for cmos based integrated circuit products and the resulting devices
1222014036779412/18/14Device including an array of memory cells and well contact areas, and the formation thereof
1232014036779512/18/14Methods of forming different finfet devices having different fin heights and an integrated circuit product containing such devices
1242014037043912/18/14Methods and systems for reducing bubbles in layers of photoresist material
1252014037069712/18/14Removal of nitride bump in opening replacement gate structure
1262014036780312/18/14Finfet gate with insulated vias and making same
1272014036782612/18/14Making an efuse
1282014037044712/18/14Semiconductor device resolution enhancement by etching multiple sides of a mask
1292014037070512/18/14Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein
1302014035372812/04/14Method and a reduced capacitance middle-of-the-line (mol) nitride stack
1312014035373412/04/14Semiconductor devices and methods of fabrication with reduced gate and contact resistances
1322014035380212/04/14Methods for integration of pore stuffing material
1332014035380512/04/14Methods of semiconductor contaminant removal using supercritical fluid
1342014035707912/04/14Methods of forming conductive structures using a sacrificial material during a metal hard mask removal process
1352014035955112/04/14Systems and methods for semiconductor voltage drop analysis
1362014034664811/27/14Low-k nitride film and making
1372014034666211/27/14Forming modified cell architecture for finfet technology and resulting device
1382014034947811/27/14Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean process
1392014034659911/27/14Finfet semiconductor devices with local isolation features and methods for fabricating the same
1402014033961011/20/14Finfet device and fabrication
1412014033961211/20/14Using sacrificial oxide layer for gate length tuning and resulting device
1422014033962911/20/14Contact formation for ultra-scaled devices
1432014033964711/20/14Densely packed standard cells for integrated circuit products, and methods of making same
1442014034255611/20/14Reusing active area mask for trench transfer exposure
1452014033566811/13/14Contact landing pads for a semiconductor device and methods of making same
1462014032714611/06/14Methods for improving double patterning route efficiency
1472014032713911/06/14Contact liner and methods of fabrication thereof
1482014032715311/06/14Standard cell connection for circuit routing
1492014032938811/06/14Methods of patterning features having differing widths
1502014032714011/06/14Integrated circuits and methods for fabricating integrated circuits with improved contact structures
1512014032746511/06/14Structures and methods for testing integrated circuits and via chains therein
1522014031961710/30/14Methods of forming metal silicide regions on a semiconductor device
1532014032476910/30/14Document driven methods of managing the content of databases that contain information relating to semiconductor manufacturing operations
1542014031961410/30/14Finfet channel stress using tungsten contacts in raised epitaxial source and drain
1552014031962010/30/14Methods for fabricating integrated circuits with polycrystalline silicon resistor structures using a replacment gate process flow, and the integrated circuits fabricated thereby
1562014032420810/30/14System and monitoring wafer handling and a wafer handling machine
1572014031243410/23/14Finfet device with a graphene gate electrode and methods of forming same
1582014031537110/23/14Methods of forming isolation regions for bulk finfet semiconductor devices
1592014030631710/16/14Finfet fin height control
1602014030810810/16/14System for separately handling different size foups
1612014029994110/09/14Sram cell with reduced voltage droop
1622014030266010/09/14Local interconnect to a protection diode
1632014029184710/02/14Methods of forming a barrier system containing an alloy of metals introduced into the barrier system, and an integrated circuit product containing such a barrier system
1642014029566410/02/14Methods of forming masking layers for use in forming integrated circuit products
1652014028969509/25/14Evaluation of pin geometry accessibility in a layer of circuit
1662014026438609/18/14Performance enhancement in pmos and nmos transistors on the basis of silicon/carbon material
1672014026434209/18/14Semiconductor device including a resistor and the formation thereof
1682014026434709/18/14Transistor with embedded strain-inducing material formed in cavities based on an amorphization process and a heat treatment
1692014026434909/18/14Low thermal budget schemes in semiconductor device fabrication
1702014026446109/18/14Metal layer enabling directed self-assembly semiconductor layout designs
1712014026447909/18/14Methods of increasing space for contact elements by using a sacrificial liner and the resulting device
1722014026448609/18/14Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
1732014026448709/18/14Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
1742014026448909/18/14Wrap around stressor formation
1752014026461709/18/14Hk/mg process flows for p-type semiconductor devices
1762014026462609/18/14Method for forming a gate electrode of a semiconductor device, gate electrode structure for a semiconductor device and according semiconductor device structure
1772014026463109/18/14Methods of forming alignment marks and overlay marks on integrated circuit products employing finfet devices and the resulting alignment/overlay mark
1782014026463209/18/14Semiconductor structure including a transistor having a layer of a stress-creating material and the formation thereof
1792014026464109/18/14Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layers
1802014026473109/18/14Programmable e-fuse for an integrated circuit product
1812014026475809/18/14Methods of forming a protection layer to protect a metal hard mask layer during lithography reworking processes
1822014026487609/18/14Multi-layer barrier layer stacks for interconnect structures
1832014026487709/18/14Metallization systems of semiconductor devices comprising a copper/silicon compound as a barrier material
1842014026489009/18/14Novel pillar structure for use in packaging integrated circuit products and methods of making such a pillar structure
1852014027336509/18/14Methods of forming contacts to source/drain regions of finfet devices by forming a region that includes a schottky barrier lowering material
1862014027336909/18/14Methods of forming contacts to source/drain regions of finfet devices
1872014027338909/18/14Semiconductor device having controlled final metal critical dimension
1882014027339609/18/14Method of forming a semiconductor structure including a metal-insulator-metal capacitor
1892014027342309/18/14Methods of forming a semiconductor device with a nanowire channel structure by performing an anneal process
1902014027342909/18/14Methods of forming finfet devices with a shared gate structure
1912014027343609/18/14Methods of forming barrier layers for conductive copper structures
1922014027345509/18/14Hard mask removal during finfet formation
1932014027347309/18/14Methods of forming a masking layer for patterning underlying structures
1942014027347409/18/14Interconnection designs using sidewall image transfer (sit)
1952014028229609/18/14Hybrid performing full field optical proximity correction for finfet mandrel layer
1962014028230109/18/14Stitch insertion for reducing color density differences in double patterning technology (dpt)
1972014028230309/18/14Pattern-independent and hybrid matching/tuning including light manipulation by projection optics
1982014028230709/18/14Method and providing metric relating two or more process parameters to yield
1992014028232309/18/14Parameterized cell for planar and finfet technology design
2002014028233009/18/14Priority based layout versus schematic (lvs)
2012014028234509/18/14Via insertion in integrated circuit (ic) designs
2022014026461309/18/14Integrated circuits and methods for fabricating integrated circuits with active area protection
2032014026463309/18/14Finfet devices having a body contact and methods of forming the same
2042014026898309/18/14Otprom array with leakage current cancelation for enhanced efuse sensing
2052014026906009/18/14Integrated circuits and methods for operating integrated circuits with non-volatile memory
2062014027267709/18/14Methods for fabricating euv masks and methods for fabricating integrated circuits using such euv masks
2072014027329909/18/14Systems and methods for fabricating semiconductor device structures using different metrology tools
2082014027330609/18/14Methods for fabricating integrated circuits including multi-patterning of masks for extreme ultraviolet lithography
2092014027336709/18/14Integrated circuits and methods for fabricating integrated circuits with gate electrode structure protection
2102014027337509/18/14Methods for fabricating integrated circuits with semiconductor substrate protection
2112014027346309/18/14Methods for fabricating integrated circuits that include a sealed sidewall in a porous low-k dielectric layer
2122014027347509/18/14Methods for fabricating guide patterns and methods for fabricating integrated circuits using such guide patterns
2132014027351109/18/14Methods for fabricating integrated circuits including formation of chemical guide patterns for directed self-assembly lithography
2142014027766809/18/14Methods and systems for fabricating integrated circuits utilizing universal and local processing management
2152014025242409/11/14Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
2162014025242509/11/14Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
2172014025242909/11/14Contact geometry having a gate silicon length decoupled from a transistor length
2182014025248009/11/14Combination finfet and planar fet semiconductor device and methods of making such a device
2192014025248109/11/14Transistor including a gate electrode extending all around one or more channel regions
2202014025255709/11/14Method for forming a semiconductor device and semiconductor device structures
2212014025261709/11/14Barrier layer conformality in copper interconnects
2222014025266009/11/14Multilayer pattern transfer for chemical guides
2232014025390209/11/14Multiple patterning process for forming trenches or holes using stitched assist features
2242014025401809/11/14Scattering enhanced thin absorber for euv reflective reticle and a making
2252014025606409/11/14Methods of repairing damaged insulating materials by introducing carbon into the layer of insulating material
2262014025609709/11/14Methods for forming integrated circuit systems employing fluorine doping
2272014025613509/11/14Methods of removing gate cap layers in cmos applications
2282014025613709/11/14Method of forming a semiconductor structure including an implantation of ions into a layer of spacer material
2292014025773809/11/14Hierarchically divided signal path for characterizing integrated circuits
2302014025896009/11/14Integrating optimal planar and three-dimensional semiconductor design layouts
2312014025614109/11/14Methods for fabricating integrated circuits utilizing silicon nitride layers
2322014024669609/04/14Transistor with embedded strain-inducing material formed in cavities formed in a silicon/germanium substrate
2332014024669809/04/14Channel sige removal from pfet source/drain region for improved silicide formation in hkmg technologies without embedded sige
2342014024673409/04/14Replacement metal gate with mulitiple titanium nitride laters
2352014024673509/04/14Metal gate structure for semiconductor devices
2362014024677509/04/14Methods of forming non-continuous conductive layers for conductive structures on an integrated circuit product
2372014024679109/04/1414 lpm contact power rail
2382014024743809/04/14Reticle defect correction by second exposure
2392014024874909/04/14Stress memorization technique
2402014024876409/04/14Methods of forming structures on an integrated circuit product
2412014024877009/04/14Microwave-assisted heating of strong acid solution to remove nickel platinum/platinum residues
2422014024877809/04/14Methods of forming asymmetric spacers on various structures on integrated circuit products
2432014024660509/04/14Defect removal process
2442014023804508/28/14Semiconductor device comprising a stacked die configuration including an integrated peltier element
2452014024278808/28/14Method of forming a high quality interfacial layer for a semiconductor device by performing a low temperature ald process
2462014024523808/28/14Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications
2472014023950308/28/14Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
2482014023124508/21/14Adjustable current shield for electroplating processes
2492014023190708/21/14Methods of inducing a desired stress in the channel region of a transistor by performing ion implantation/anneal processes on the gate electrode



ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009



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