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Globalfoundries Inc patents


Recent patent applications related to Globalfoundries Inc. Globalfoundries Inc is listed as an Agent/Assignee. Note: Globalfoundries Inc may have other listings under different names/spellings. We're not affiliated with Globalfoundries Inc, we're just tracking patents.

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 new patent  Electroplating system and using electroplating system for controlling concentration of organic additives in electroplating solution

Electroplating techniques including an electroplating system and a method for using the electroplating system are provided. The electroplating system has: an electroplating apparatus for electroplating a workpiece, the electroplating apparatus has an electroplating tank configured to contain a solution including target organics; a first reservoir configured to receive the solution... Globalfoundries Inc

 new patent  Centering fixture for electrostatic chuck system

A centering fixture for centering a wafer on a chuck is provided. The centering fixture includes a body including an upper surface, a lower surface, an inner periphery and an outer periphery. A chuck seat is positioned in a lower portion of the inner periphery and configured to mate the... Globalfoundries Inc

 new patent  Amorphous carbon layer for cobalt etch protection in dual damascene back end of the line integrated circuit metallization integration

A method of forming an amorphous carbon (aC) layer as a barrier layer for preventing etching of metals in a dual damascene metallization process and the resulting device are provided. Embodiments include forming an inter-layer dielectric (ILD) layer over a substrate with the first ILD having recesses for a first... Globalfoundries Inc

 new patent  Wafer rigidity with reinforcement structure

Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures... Globalfoundries Inc

 new patent  Through silicon via sharing in a 3d integrated circuit

The present disclosure generally relates to semiconductor structures and, more particularly, to intelligent through silicon via sharing in 3D-IC integrated structures and methods of manufacture. The structure includes: a plurality of stacked dies each containing at least one macro device; and a layer structure positioned between the plurality of stacked... Globalfoundries Inc

 new patent  Method, apparatus, and system having super steep retrograde well with engineered dopant profiles

Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially... Globalfoundries Inc

 new patent  Common metal contact regions having different schottky barrier heights and methods of manufacturing same

Methods for forming a semiconductor device having dual Schottky barrier heights using a single metal and the resulting device are provided. Embodiments include a semiconductor substrate having an n-FET region and a p-FET region each having source/drain regions; a titanium silicon (Ti—Si) intermix phase Ti liner on an upper surface... Globalfoundries Inc

 new patent  Method and structure of forming self-aligned rmg gate for vfet

An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers, each of the sidewall spacers having vertically tapered... Globalfoundries Inc

 new patent  Stacked nanowire device width adjustment by gas cluster ion beam (gcib)

A method of making a nanowire device incudes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire... Globalfoundries Inc

Methods, apparatus and system for providing nmos-only memory cells

At least one method, apparatus and system disclosed involves a memory device having a memory cell comprising NMOS only transistors. An SRAM bit cell comprises a first pass gate (PG) NMOS transistor coupled to a first bit line signal and a word line signal; a second PG NMOS transistor coupled... Globalfoundries Inc

Static random access memory (sram) assist circuit

The present disclosure relates to semiconductor structures and, more particularly, to a static random access memory assist circuit and methods of implementation and manufacture. The structure includes at least one static random access memory (SRAM) cell and a read assist circuit structured to apply a negative voltage to the at... Globalfoundries Inc

Devices and methods of forming sadp on sram and saqp on logic

Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area;... Globalfoundries Inc

Interconnects with inner sacrificial spacers

Interconnect structures and methods of forming such interconnect structures. A spacer is formed inside an opening in a dielectric layer. After the spacer is formed, a conductive plug is formed inside the opening in the dielectric layer. After the conductive plug is formed, the spacer is removed to define an... Globalfoundries Inc

Method and placing a gate contact inside a semiconductor active region having high-k dielectric gate caps

A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a high-k dielectric liner and a core. Trench silicide (TS) is disposed on sides... Globalfoundries Inc

Semiconductor structure with self-aligned wells and multiple channel materials

Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of... Globalfoundries Inc

Heterogeneous integration of 3d si and iii-v vertical nanowire structures for mixed signal circuits fabrication

A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or SixGe1-x substrate; forming a conformal SiN, SiOxCyNz layer over side and bottom surfaces of the first... Globalfoundries Inc

Advanced process control methods for process-aware dimension targeting

Disclosed are methods of advanced process control (APC) for particular processes. A particular process (e.g., a photolithography or etch process) is performed on a wafer to create a pattern of features. A parameter is measured on a target feature and the value of the parameter is used for APC. However,... Globalfoundries Inc

Integrated circuit structure having gate contact and forming same

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the... Globalfoundries Inc

Soi wafers with buried dielectric layers to prevent cu diffusion

An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the... Globalfoundries Inc

Die-die stacking

A method includes forming a stack of semiconductor die. The stack includes a first semiconductor die, a second semiconductor die and a third semiconductor die. The first semiconductor die is stacked above the second semiconductor die and the third semiconductor die is stacked above the first semiconductor die. A first... Globalfoundries Inc

Thermally enhanced package to reduce thermal interaction between dies

A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a substrate; forming a lid over the IC chips; and forming a slit through the lid at a boundary between adjacent IC chips.... Globalfoundries Inc

Method and placing a gate contact inside an active region of a semiconductor

A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a liner and a core. Trench silicide (TS) is disposed on sides of the... Globalfoundries Inc

Stable and reliable finfet sram with improved beta ratio

Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the... Globalfoundries Inc

Differential sg/eg spacer integration with equivalent nfet/pfet spacer widths & dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage eg device on fdsoi

A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and... Globalfoundries Inc

Dual stress device and method

A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a... Globalfoundries Inc

Diagnosing failure locations of an integrated circuit with logic built-in self-test

A method and system of testing an integrated circuit (IC), using a multiple input shift register (MISR) with supporting hardware for diagnosing failure locations in an IC with built-in self-test (BIST) logic, including an On-Product MISR. The system includes BIST logic of a circuit under test (CUT) and a tester... Globalfoundries Inc

Method, apparatus and system for wide metal line for sadp routing

At least one method, apparatus and system disclosed involves a circuit layout for an integrated circuit device comprising a plurality of wider-than-default metal formations for a functional cell. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first pair of wide... Globalfoundries Inc

Forming a silicon based layer in a trench to prevent corner rounding

A method of preventing corner rounding for an alternate channel FINFET formed in trenches and the resulting devices are provided. Embodiments include providing a Si substrate; forming a trench in the Si substrate; forming a Si based layer with a flat upper surface in the trench; and forming a SiGe... Globalfoundries Inc

Device layer transfer with a preserved handle wafer section

Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section... Globalfoundries Inc

Methods for forming mask layers using a flowable carbon-containing silicon dioxide material

One method disclosed herein includes, among other things, forming a process layer on a substrate. A patterned mask layer is formed above the process layer. The patterned mask layer includes first openings exposing portions of the process layer. A carbon-containing silicon dioxide layer is formed above the patterned mask layer... Globalfoundries Inc

Fin diode with increased junction area

A diode includes a plurality of fins defined in a semiconductor substrate. An anode region is defined by a doped region in a first surface portion of each of the plurality of fins and in a second surface portion of the semiconductor substrate disposed between adjacent fins in the plurality... Globalfoundries Inc

Interconnects for vertical-transport field-effect transistors

Structures and fabrication methods for vertical-transport field-effect transistors. The structure includes a vertical-transport field-effect transistor having a source/drain region located in a semiconductor layer, a fin projecting from the source/drain region in the semiconductor layer, and a gate electrode on the semiconductor layer and coupled with the fin. The structure... Globalfoundries Inc

Vertical transistors and methods of forming same

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a fin having a first source/drain region and a second source/drain, the first source/drain region being over a substrate and below a central region of the fin, and the second source/drain region being... Globalfoundries Inc

Method of concurrently forming source/drain and gate contacts and related device

A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation... Globalfoundries Inc

Methods of forming a protection layer on an isolation region of ic products comprising finfet devices

One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a plurality of fins, forming a recessed layer of insulating material comprising a first insulating material in the trenches, wherein a portion of each of the plurality of... Globalfoundries Inc

01/04/18 / #20180006143

Tunneling field effect transistor

A tunneling field effect transistor device disclosed herein includes a substrate, a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above the substrate, and a second semiconductor material positioned above at least a portion of the gate region and above the... Globalfoundries Inc

01/04/18 / #20180006155

Forming defect-free relaxed sige fins

A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding... Globalfoundries Inc

01/04/18 / #20180005901

Semiconductor contact

A method for forming a semiconductor device comprises forming a gate stack on a channel region of a semiconductor, forming a source/drain region adjacent to the channel region, depositing a first insulator layer over the source/drain region, and removing a portion of the first insulator layer to form a first... Globalfoundries Inc

01/04/18 / #20180006140

Surface area and schottky barrier height engineering for contact trench epitaxy

Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of... Globalfoundries Inc

01/04/18 / #20180006141

Surface area and schottky barrier height engineering for contact trench epitaxy

Forming a contact is disclosed. A trench through an interlayer dielectric layer is opened down to a substrate. The interlayer dielectric layer is formed on the substrate such that the substrate is the bottom surface of the trench. A cleaning process of the trench is performed. The bottom surface of... Globalfoundries Inc

12/28/17 / #20170371002

Methods for crossed-fins finfet device for sensing and measuring magnetic fields

Methods for forming an efficient and effective crossed-fins FinFET device for sensing and measuring magnetic fields and resulting devices are disclosed. Embodiments include forming first-fins, parallel to and spaced from each other, in a first direction on a substrate; forming second-fins, parallel to and spaced from each other on the... Globalfoundries Inc

12/28/17 / #20170372924

Self-contained metrology wafer carrier systems

A self-contained metrology wafer carrier systems and methods of measuring one or more characteristics of semiconductor wafers are provided. A wafer carrier system includes, for instance, a housing configured for transport within the automated material handling system, the housing having a support configured to support a semiconductor wafer in the... Globalfoundries Inc

12/28/17 / #20170372949

Titanium silicide formation in a narrow source-drain contact

Aspects of the present invention relate to approaches for forming a narrow source-drain contact in a semiconductor device. A contact trench can be etched to a source-drain region of the semiconductor device. A titanium liner can be deposited in this contact trench such that it covers substantially an entirety of... Globalfoundries Inc

12/28/17 / #20170372959

Gate tie-down enablement with inner spacer

A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate... Globalfoundries Inc

12/28/17 / #20170373000

Interconnects having hybrid metallization

Disclosed are methods of forming integrated circuit (IC) structures with hybrid metallization interconnects. A dual damascene process is performed to form trenches in an upper portion of a dielectric layer and contact holes that extend from the trenches to a gate electrode and to contact plugs on source/drain regions. A... Globalfoundries Inc

12/28/17 / #20170373005

Anti-fuses with reduced programming voltages

Device structures for an anti-fuse and methods for manufacturing device structures for an anti-fuse. The anti-fuse includes a first terminal comprised of a fin. The fin includes a section with an edge and inclined surfaces that intersect at the edge. The anti-fuse further includes a second terminal covering the edge... Globalfoundries Inc

12/28/17 / #20170373007

Contact line having insulating spacer therein and forming same

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line... Globalfoundries Inc

12/28/17 / #20170373019

Method to mitigate chip package interaction risk on die corner using reinforcing tiles

A method for producing semiconductor devices including reinforcing metal tiles and the resulting semiconductor package are provided. Embodiments include forming one or more reinforcing metal tiles at corners of an upper portion of a metal stack of semiconductor die during manufacturing of the semiconductor die; and attaching the semiconductor die... Globalfoundries Inc

12/28/17 / #20170373024

Tamper detection for a chip package

Chip packages with improved tamper resistance and methods of using such chip packages to provide improved tamper resistance. A lead frame includes a die attach paddle, a plurality of outer lead fingers, and a plurality of inner lead fingers located between the outer lead fingers and the die attach paddle.... Globalfoundries Inc

12/28/17 / #20170373071

Vertical channel transistor-based semiconductor structure

A semiconductor memory structure includes adjacent cross-sectionally rectangular-shaped bottom source and drain electrodes, the electrodes including n-type electrode(s) and p-type electrode(s), and vertical channel transistors on one or more of the n-type electrode(s) and one or more of the p-type electrode(s); each vertical channel transistor including a vertical channel and... Globalfoundries Inc

12/28/17 / #20170373161

Method of forming a gate contact structure and source/drain contact structure for a semiconductor device

One illustrative method disclosed includes, among other things, forming a sacrificial S/D contact structure above an S/D region of a transistor device, removing at least a portion of a gate cap and at least a portion of a gate sidewall spacer to define a gate contact cavity that is positioned... Globalfoundries Inc

12/28/17 / #20170373144

Novel sti process for sdb devices

A shallow trench isolation (STI) structure is formed having a conventional STI trench structure formed of dielectric material extending into the substrate. A planarizing stack of nitride and oxide is formed above the STI trench structure (and optionally a dummy gate may be formed above this stack). After further conventional... Globalfoundries Inc

12/21/17 / #20170364626

Feed-forward for silicon inspections (dfm2cfm : design to silicon) & feed-back for weakpoint predictor decks (cfm2dfm : silicon to design) guided by marker classification, sampling, and higher dimensional analysis

A method and apparatus for selecting Si wafer WP based on individual or multiple DFM decks for Si-feed-forward and Si-feed-back analysis are provided. Embodiments include generating markers for a wafer from an individual DFM deck; generating UCF Indexes; determining whether a representative marker corresponding to a UCF is a candidate... Globalfoundries Inc

12/21/17 / #20170365302

Latching current sensing amplifier for memory array

A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as... Globalfoundries Inc

12/21/17 / #20170365341

Algorithmic n search/m write ternary content addressable memory (tcam)

The present disclosure relates to a content addressable memory (CAM), and more particularly, to an algorithmic ternary content addressable memory (TCAM) that instantiates multiple copies of X-Y TCAMs. The structure includes a content addressable memory (CAM) and an array which instantiates multiple replicated copies of the CAM in a row... Globalfoundries Inc

12/21/17 / #20170365471

Mask substrate structure

The present disclosure relates to lithographic masks and, more particularly, to a lithographic mask substrate structure and methods of manufacture. The mask includes a sub-resolution assist feature (SRAF) formed on a quartz substrate and composed of a patterned transition film and absorber layer.... Globalfoundries Inc

12/21/17 / #20170365504

Forming air gap

A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming conductive interconnects in an ILD including a high etch selectivity dielectric layer such as a silicon nitride with hydrogen component (SiNH) layer, and patterning an air gap mask... Globalfoundries Inc

12/21/17 / #20170365509

Devices and methods of forming asymmetric line/space with barrierless metallization

Devices and methods of fabricating integrated circuit devices for forming assymetric line/space with barrierless metallization are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, a dielectric matrix, and a hardmask, the dielectric matrix including a set of trenches etched into the dielectric matrix and... Globalfoundries Inc

12/21/17 / #20170365521

Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices

A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second... Globalfoundries Inc

12/21/17 / #20170365537

Thin film based fan out and multi die package platform

Thin film based fan out wafer level packaging and a method of manufacturing the same are disclosed. Embodiments include a method including forming tapered via holes in a first surface of a polymer film; forming a conductive pillar on the first surface of a semiconductor device; bonding a solderable surface... Globalfoundries Inc

12/21/17 / #20170365676

Device for improving performance through gate cut last process

Devices and methods of fabricating integrated circuit devices for increasing performance through gate cut last processes are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a plurality of fins, an STI layer, an oxide layer, and a gate material over the oxide layer,... Globalfoundries Inc

12/21/17 / #20170365680

Gate patterning for ac and dc performance boost

A method to reduce parasitic capacitance in a high-k dielectric metal gate (HKMG) transistor with raised source and drain regions (RSD) is provided including forming a multi-layer stack for an HKMG gate on a substrate, the multilayer stack including a gate electrode layer of amorphous silicon or polycrystalline silicon, forming... Globalfoundries Inc

12/21/17 / #20170365682

Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices

A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second... Globalfoundries Inc

12/21/17 / #20170365695

Fabrication of integrated circuit structures for bipolor transistors

Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming a seed layer on the TI and the second semiconductor region of the substrate, leaving... Globalfoundries Inc

12/21/17 / #20170365721

Diodes and fabrication methods thereof

Diodes and fabrication methods thereof are presented. The diodes include, for instance: a first semiconductor region disposed at least partially within a substrate, the first semiconductor region having a first conductivity type; and a second semiconductor region disposed at least partially within the first semiconductor region, the second semiconductor region... Globalfoundries Inc

Patent Packs
12/21/17 / #20170365725

Electrical and optical via connections on a same chip

The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a... Globalfoundries Inc

12/21/17 / #20170365775

Backside integration of rf filters for rf front end modules and design structure

A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of... Globalfoundries Inc

12/14/17 / #20170358541

Tiled-stress-alleviating pad structure

Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad structure.... Globalfoundries Inc

12/14/17 / #20170358562

Integrated display system with multi-color light emitting diodes (leds)

A display system is disclosed. The display system comprises a light emitting diode (LED) device and a backplane (BP) device. The LED device comprises a plurality of LEDs having LED terminals. An LED bonding surface comprising a dielectric layer with LED bonding surface contact pads is coupled to diode terminals... Globalfoundries Inc

12/14/17 / #20170358565

Standard cell layout and arranging a plurality of standard cells

The present disclosure provides an integrated circuit product including a plurality of standard cells, each standard cell of the plurality of standard cells being in abutment with at least one other standard cell of the plurality of standard cells, a continuous active region continuously extending across the plurality of standard... Globalfoundries Inc

12/14/17 / #20170358581

Non-volatile memory device employing a deep trench capacitor

A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set... Globalfoundries Inc

12/14/17 / #20170358585

Method, apparatus and system for fabricating self-aligned contact using block-type hard mask

At least one method, apparatus and system disclosed herein involves processing a semiconductor wafer using block mask design for manufacturing a finFET device. The gate structure comprising a source structure, and a drain structure of a transistor is formed. The gate structure is surrounded by an inter-layer dielectric (ILD) region.... Globalfoundries Inc

12/14/17 / #20170358619

Photodetector and forming the photodetector on stacked trench isolation regions

Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In one structure, a first trench isolation region is in and at the top surface of a substrate and a second trench isolation region is in... Globalfoundries Inc

12/14/17 / #20170358687

Formation of bottom junction in vertical fet devices

Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and... Globalfoundries Inc

12/14/17 / #20170358691

Reconfigurable mos varactor

Various particular embodiments include a semiconductor varactor structure including: a semiconductor substrate of a first conductivity type; a semiconductor area of a second conductivity type, different from the first conductivity type, within the semiconductor substrate; a field effect transistor (FET) structure within the semiconductor area; and a contact, contacting the... Globalfoundries Inc

12/14/17 / #20170359070

Semiconductor structure with back-gate switching

The present disclosure relates to semiconductor structures and, more particularly, to circuits with logical back-gate switching and methods of operation. The circuit includes at least one front-gate contact and digital back-gate potentials for logical function implementation on a back side of at least one device. The digital back-gate potentials are... Globalfoundries Inc

12/14/17 / #20170358662

Self-aligned finfet formation

A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material... Globalfoundries Inc

12/14/17 / #20170358666

Self-aligned finfet formation

A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material... Globalfoundries Inc

12/07/17 / #20170351666

Secure hyper transfer of large files

A system is disclosed having at least one computing device configured to send a computer file across a network by segmenting the computer file into identifiable segments and sending the segments in parallel across the network. The segmenting can be initiated while the computer file is generated. In another embodiment,... Globalfoundries Inc

12/07/17 / #20170351799

Semiconductor layout generation

Semiconductor layout generation includes: calculating, for a design rule constraint, a slack value for a subset of elements of a proposed semiconductor layout; generating a plurality of alternative layouts, where each of the alternative layouts includes a variation of interdependent characteristics of the subset of elements and a slack value... Globalfoundries Inc

Patent Packs
12/07/17 / #20170352145

Semiconductor wafer inspection using care area group-specific threshold settings for detecting defects

In the methods and systems, optical images of inspection care areas on a semiconductor wafer are acquired and analyzed to detect defects. However, during this analysis, the same threshold setting is not used for all inspection care areas. Instead, care areas are grouped into different care area groups, based on... Globalfoundries Inc

12/07/17 / #20170352407

Self pre-charging memory circuits

The present disclosure relates to semiconductor structures and, more particularly, to sensing circuit for a memory and methods of use. The memory includes a self-referenced sense amp that is structured to calibrate its individual pre-charge based on a trip-point, with autonomous pre-charge activation circuitry that starts pre-charging a sense-line on... Globalfoundries Inc

12/07/17 / #20170352591

Method for producing self-aligned line end vias and related device

A method for producing self-aligned line end vias and the resulting device are provided. Embodiments include trench lines formed in a dielectric layer; each trench line including a pair of self aligned line end vias; and a high-density plasma (HDP) oxide, silicon carbide (SiC) or silicon carbon nitride (SiCNH) formed... Globalfoundries Inc

12/07/17 / #20170352592

Integrated circuit structure having deep trench capacitor and through-silicon via and forming same

One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: providing a substrate having a front side and a back side, the substrate including: a deep trench (DT) capacitor within the substrate extending toward the back side of substrate, and a... Globalfoundries Inc

12/07/17 / #20170352611

Producing wafer level packaging using leadframe strip and related device

A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a mold with an active side of each die facing a surface of the mold; placing a leadframe strip on the mold, wherein the leadframe strip includes... Globalfoundries Inc

12/07/17 / #20170352618

Integrated circuit structure having deep trench capacitor and through-silicon via and forming same

One aspect of the disclosure relates to an interposer. The interposer may include: a first dielectric layer extending from a substrate in a direction away from a front side of the substrate; a back-end-of-the-line (BEOL) region extending from the substrate in a direction away from the back side of the... Globalfoundries Inc

12/07/17 / #20170352619

Interconnect structure with capacitor element and related methods

Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming an opening in a low-k dielectric layer; filling the opening with a high-k dielectric material; patterning the low-k dielectric layer outside of the opening and the high-k dielectric... Globalfoundries Inc

12/07/17 / #20170352654

Method of concurrently forming source/drain and gate contacts and related device

A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation... Globalfoundries Inc

12/07/17 / #20170352661

Semiconductor devices

The present disclosure relates to semiconductor structures and, more particularly, to segmented or cut finFET structures and methods of manufacture. The structure includes at least one logic finFET device having a fin of a first length, and at least one memory finFET device having a fin of a second length.... Globalfoundries Inc

11/30/17 / #20170345559

"interleaved transformer and making the same"

A high performance, on-chip transformer having interleaving primary and secondary windings to achieve higher coupling coefficient while providing desired impedance transformation is disclosed. The primary winding is formed of two or more parallel conductive winding paths or segments. The secondary winding is embedded within the parallel paths of the primary... Globalfoundries Inc

11/30/17 / #20170345719

Modulation of the morphology of epitaxial semiconductor material

Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural... Globalfoundries Inc

11/30/17 / #20170345752

Devices and methods of forming low resistivity noble metal interconnect

Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer... Globalfoundries Inc

11/30/17 / #20170345766

Devices and methods of forming low resistivity noble metal interconnect with improved adhesion

Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects with improved adhesion are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing... Globalfoundries Inc

11/30/17 / #20170345834

Soi memory device

A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer, and forming a memory device on the SOI substrate including forming... Globalfoundries Inc

11/30/17 / #20170345912

Methods of recessing a gate structure using oxidizing treatments during a recessing etch process

A method includes forming a gate structure embedded in a dielectric layer above a substrate. A first recessing etch process is performed to remove a first portion of the gate structure. An oxidizing treatment is performed to oxidize a second portion of the gate structure after removing the first portion.... Globalfoundries Inc

11/30/17 / #20170345913

Methods for performing a gate cut last scheme for finfet semiconductor devices

A method includes forming a placeholder gate structure embedded in a dielectric layer. The placeholder gate structure includes a sacrificial material. A first hard mask layer is formed above the dielectric layer. The first hard mask layer and the sacrificial material are the same material. A second hard mask layer... Globalfoundries Inc

11/30/17 / #20170345914

Methods for forming integrated circuits that include a dummy gate structure

A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a... Globalfoundries Inc

11/30/17 / #20170345934

Replacement body finfet for improved junction profile with gate self-aligned junctions

After forming an epitaxial semiconductor layer on portions of a semiconductor located on opposite sides of a sacrificial gate structure, dopants from the epitaxial semiconductor layer are diffused into the semiconductor fin to form a dopant-containing semiconductor fin. A sacrificial gate stack is removed to provide a gate cavity that... Globalfoundries Inc

11/30/17 / #20170346662

System, method and software program for tuneable equalizer adaptation using sample interpolation

Various embodiments of the present invention solve the problem of generating intermediate-time information useable to drive ZFE adaptation (for example, in connection with a digital receiver). Further, various embodiments of the present invention increase flexibility by enabling user-specified over-peaking and/or under-peaking (i.e. configurable equalizer tuning) with respect to a ZFE... Globalfoundries Inc

11/23/17 / #20170336467

Gate protection for hv-stress application

A test structure for a semiconductor device, comprising a device under test including a transistor, the transistor having a gate electrode, a source electrode, a drain electrode and a bulk electrode, a first fuse and a second fuse provided in series, wherein one terminal of the first fuse is connected... Globalfoundries Inc

11/23/17 / #20170338156

Apparatus and adjusting work-function metal thickness to provide variable threshold voltages in finfets

A method of adjusting work-function metal thickness includes providing a structure having a substrate, the substrate including a longitudinally extending array of fins disposed thereon. Spacers are then formed on sidewalls of fins of the array. Pillars are formed between and adjacent the spacers. A gate having dummy gate material... Globalfoundries Inc

11/23/17 / #20170338180

Method of making vertical and bottom bias e-fuses and related devices

A method for producing semiconductor devices including an electrical fuse (e-fuse) and the resulting device are provided. Embodiments include forming a gate electrode (PC); forming at least one gate contact (CB) over the PC; forming at least one source/drain contact (CA); and forming an e-fuse including a resistor metal (RM)... Globalfoundries Inc

11/23/17 / #20170338226

Controlling within-die uniformity using doped polishing material

Various embodiments include methods and integrated circuit structures. In some cases, an integrated circuit (IC) structure includes: a substrate; a set of fin structures overlying the substrate, the set of fin structures including a substrate base and a silicide layer over the substrate base; an oxide layer located between adjacent... Globalfoundries Inc

11/23/17 / #20170338235

Finfet circuit structures with vertically spaced transistors and fabrication methods

Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region,... Globalfoundries Inc

11/23/17 / #20170338247

Circuit structures with vertically spaced transistors and fabrication methods

Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region,... Globalfoundries Inc

11/23/17 / #20170338275

Light emitting diodes (leds) with stacked multi-color pixels for displays

A color stacked light emitting diode (LED) pixel is disclosed. The color stacked LED includes an LED pixel structure body, a base LED disposed on at least a portion of the LED pixel structure body, an intermediate LED disposed on the base LED, and a top LED disposed on the... Globalfoundries Inc

11/23/17 / #20170338276

Light emitting diodes (leds) with integrated cmos circuits

Disclosed is a multi-color semiconductor LED display with integrated with CMOS circuit components, such as thin film transistors (TFTs). LEDs of the display are disposed on a first major surface of a substrate while CMOS circuit components which are configured as circuitry for operating the display are disposed on a... Globalfoundries Inc

11/23/17 / #20170338277

Leds with three color rgb pixels for displays

Devices and methods of forming the devices are disclosed. The device includes a substrate and a color LED pixel disposed on the substrate. The color LED pixel includes a red LED, a green LED and a blue LED. Each of the color LED includes a specific color LED body disposed... Globalfoundries Inc

11/23/17 / #20170338325

Method, apparatus and system for providing nitride cap layer in replacement metal gate structure

We disclose a semiconductor device, comprising a semiconductor substrate; at least one gate structure disposed above the semiconductor substrate, wherein the gate structure comprises a gate structure cavity partially filled with at least one metal layer; and an ultraviolet (UV) cured high density plasma (HDP) nitride cap layer in the... Globalfoundries Inc

11/23/17 / #20170338329

Integrated circuit fabrication with boron etch-stop layer

Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element;... Globalfoundries Inc

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11/23/17 / #20170338343

High-voltage transistor device

A semiconductor device is provided comprising a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer and a transistor device, wherein the transistor device comprises a gate electrode formed by a... Globalfoundries Inc

11/23/17 / #20170338345

Soi finfet fins with recessed fins and epitaxy in source drain region

Fabrication method for a semiconductor device and structure are provided, which includes: providing an isolation layer at least partially disposed adjacent to at least one sidewall of a fin structure extended above a substrate structure, the fin structure including a channel region; recessing an exposed portion of the fin structure... Globalfoundries Inc

11/23/17 / #20170338350

Semiconductor device and method

The present disclosure provides a semiconductor device including a substrate, a gate structure formed over the substrate, the gate structure including a first ferroelectric material having a first remanent polarization and a second ferroelectric material having a second remanent polarization, the first remanent polarization being smaller than the second remanent... Globalfoundries Inc








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