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Globalfoundries, Inc. patents


      
Recent patent applications related to Globalfoundries, Inc.. Globalfoundries, Inc. is listed as an Agent/Assignee. Note: Globalfoundries, Inc. may have other listings under different names/spellings. We're not affiliated with Globalfoundries, Inc., we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries, Inc.-related inventors


Through-silicon via with sidewall air gap

Globalfoundries

Through-silicon via with sidewall air gap

Search recent Press Releases: Globalfoundries, Inc.-related press releases
Count Application # Date Globalfoundries, Inc. patents (updated weekly) - BOOKMARK this page
12015005398102/26/15 new patent  Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device
22015005407802/26/15 new patent  Methods of forming gate structures for finfet devices and the resulting smeiconductor products
32015005408302/26/15 new patent  Strain engineering in semiconductor devices by using a piezoelectric material
42015005413902/26/15 new patent  Through-silicon via with sidewall air gap
52015005679602/26/15 new patent  Method for forming a semiconductor device having a metal gate recess
62015005678102/26/15 new patent  Gate length independent silicon-on-nothing (son) scheme for bulk finfets
72015005682002/26/15 new patent  Systems and methods of solvent temperature control for wafer coating processes
82015004844602/19/15Reduction of oxide recesses for gate height control
92015005078702/19/15Fully silicided gate formed according to the gate-first hkmg approach
102015005079202/19/15Extra narrow diffusion break for 3d finfet technologies
112015005081102/19/15Critical dimension and pattern recognition structures for devices manufactured using double patterning techniques
122015005081202/19/15Wafer-less auto clean of processing chamber
132015005210802/19/15Method, computer readable storage medium and computer system for obtaining snapshots of data
142015005249402/19/15Power rail layout for dense standard cell library
152015004186902/12/15Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
162015004189802/12/15Bulk finfet semiconductor-on-nothing integration
172015004190502/12/15Methods of forming replacement gate structures for transistors and the resulting devices
182015004190602/12/15Methods of forming stressed fin channel structures for finfet semiconductor devices
192015004190902/12/15Completing middle of line integration allowing for self-aligned contacts
202015004485502/12/15Methods of forming spacers on finfets and other semiconductor devices
212015004486102/12/15Gate silicidation
222015004185802/12/153d transistor channel mobility enhancement
232015004191002/12/15Integrated circuits with a partially-depleted region formed over a bulk silicon substrate and methods for fabricating the same
242015004191102/12/153d transistor channel mobility enhancement
252015003501602/05/15Nitride spacer for protecting a fin-shaped field effect transistor (finfet) device
262015003501802/05/15Devices and methods of forming bulk finfets with lateral seg for source and drain on dielectrics
272015003505202/05/15Contact power rail
282015003505302/05/15Device and a ldmos design for a finfet integrated circuit
292015003507302/05/15Enabling enhanced reliability and mobility for replacement gate planar and finfet structures
302015003508602/05/15Methods of forming cap layers for semiconductor devices with self-aligned contact elements and the resulting devices
312015003697802/05/15Blazed grating spectral purity filter and methods of making such a filter
322015003794502/05/15Epitaxially forming a set of fins in a semiconductor device
332015003494102/05/15Integrated circuits having finfet semiconductor devices and methods of fabricating the same to resist sub-fin current leakage
342015003506202/05/15Integrated circuits having finfets with improved doped channel regions and methods for fabricating same
352015003760302/05/15Articles including metal structures having maximized bond adhesion and bond reliability, and methods of forming the same
362015004007802/05/15Methods and systems for designing and manufacturing optical lithography masks
372015004008002/05/15Methods for modifying an integrated circuit layout design
382015004009102/05/15Methods for modifying an integrated circuit layout design
392015002834801/29/15Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (finfet) device
402015002843101/29/15Mol insitu pt rework sequence
412015002848201/29/15Device layout for reducing through-silicon-via stress
422015002848901/29/15Method for off-grid routing structures utilizing self aligned double patterning (sadp) technology
432015002850001/29/15Forming alignment mark and resulting mark
442015003117901/29/15Method of forming a semiconductor structure including silicided and non-silicided circuit elements
452015003320101/29/15Systems and methods for fabricating semiconductor device structures
462015002166301/22/15Finfet with insulator under channel
472015002168301/22/15Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
482015002169101/22/15Finfet with electrically isolated active region on bulk semiconductor substrate and fabricating same
492015002169301/22/15Enhancing transistor performance and reliability by incorporating deuterium into a strained capping layer
502015002169501/22/15Epitaxial block layer for a fin field effect transistor device
512015002170201/22/15Shallow trench isolation
522015002170301/22/15Gate oxide quality for complex mosfet devices
532015002170401/22/15Finfet work function metal formation
542015002170901/22/15Structures and methods integrating different fin device architectures
552015002171201/22/15Highly conformal extension doping in advanced multi-gate devices
562015002455701/22/15Semiconductor device having local buried oxide
572015002456001/22/15Gate encapsulation achieved by single-step deposition
582015002457201/22/15Process for faciltiating fin isolation schemes
592015002457301/22/15Methods of forming replacement fins for a finfet semiconductor device by performing a replacement growth process
602015002458501/22/15Systems and methods for fabricating gate structures for semiconductor devices
612015002169401/22/15Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating the same
622015002171401/22/15Integrated circuits having a metal gate structure and methods for fabricating the same
632015002358301/22/15Methods and systems for determining a dose-to-clear of a photoresist
642015002457801/22/15Methods for etching dielectric materials in the fabrication of integrated circuits
652015001477701/15/15Channel semiconductor alloy layer growth adjusted by impurity ion implantation
662015001481301/15/15Complex circuit element and capacitor utilizing cmos compatible antiferroelectric high-k materials
672015001484301/15/15Semiconductor device with improved metal pillar configuration
682015001777401/15/15Method of forming fins with recess shapes
692015001780301/15/15Customized alleviation of stresses generated by through-substrate via(s)
702015001477601/15/15Finfet integrated circuits and methods for their fabrication
712015001617401/15/15Integrated circuits with programmable electrical connections and methods for fabricating the same
722015000853601/08/15Semiconductor device structure and forming a semiconductor device structure
732015000975001/08/15Device including a dual port static random access memory cell and the formation thereof
742015001085101/08/15Methods involving color-aware retargeting of individual decomposed patterns when designing masks to be used in multiple patterning processes
752015001289601/08/15Methods for fabricating integrated circuits including generating photomasks for directed self-assembly
762015000162701/01/15Spacer chamfering for a replacement metal gate device
772015000163401/01/15Methods of forming bipolar devices and an integrated circuit product containing such bipolar devices
782015000163501/01/15Methods of forming an e-fuse for an integrated circuit product and the resulting integrated circuit product
792015000164001/01/15Transistor device with improved source/drain junction architecture and methods of making such a device
802015000164201/01/15Field effect transistor and fabrication
812015000613801/01/15Optical proximity correction for connecting via between layers of a device
822015000159101/01/15Bulk finfet with partial dielectric isolation featuring a punch-through stopping layer under the oxide
832015000163001/01/15Structure and methods of fabricating y-shaped dmos finfet
842015000164301/01/15Integrated circuits having improved high-k dielectric layers and methods for fabrication of same
852014037480712/25/14Method of device isolation in cladding si through in situ doping
862014037491512/25/14Integration of optical components in integrated circuits
872014037796512/25/14Directed self-assembly (dsa) formulations used to form dsa-based lithography films
882014036775112/18/14Finfet spacer etch for esige improvement
892014036778712/18/14Methods of forming transistors with retrograde wells in cmos applications and the resulting device structures
902014036778812/18/14Methods of forming gate structures for cmos based integrated circuit products and the resulting devices
912014036779012/18/14Methods of forming gate structures for cmos based integrated circuit products and the resulting devices
922014036779412/18/14Device including an array of memory cells and well contact areas, and the formation thereof
932014036779512/18/14Methods of forming different finfet devices having different fin heights and an integrated circuit product containing such devices
942014037043912/18/14Methods and systems for reducing bubbles in layers of photoresist material
952014037069712/18/14Removal of nitride bump in opening replacement gate structure
962014036780312/18/14Finfet gate with insulated vias and making same
972014036782612/18/14Making an efuse
982014037044712/18/14Semiconductor device resolution enhancement by etching multiple sides of a mask
992014037070512/18/14Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein
1002014035372812/04/14Method and a reduced capacitance middle-of-the-line (mol) nitride stack
1012014035373412/04/14Semiconductor devices and methods of fabrication with reduced gate and contact resistances
1022014035380212/04/14Methods for integration of pore stuffing material
1032014035380512/04/14Methods of semiconductor contaminant removal using supercritical fluid
1042014035707912/04/14Methods of forming conductive structures using a sacrificial material during a metal hard mask removal process
1052014035955112/04/14Systems and methods for semiconductor voltage drop analysis
1062014034664811/27/14Low-k nitride film and making
1072014034666211/27/14Forming modified cell architecture for finfet technology and resulting device
1082014034947811/27/14Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean process
1092014034659911/27/14Finfet semiconductor devices with local isolation features and methods for fabricating the same
1102014033961011/20/14Finfet device and fabrication
1112014033961211/20/14Using sacrificial oxide layer for gate length tuning and resulting device
1122014033962911/20/14Contact formation for ultra-scaled devices
1132014033964711/20/14Densely packed standard cells for integrated circuit products, and methods of making same
1142014034255611/20/14Reusing active area mask for trench transfer exposure
1152014033566811/13/14Contact landing pads for a semiconductor device and methods of making same
1162014032714611/06/14Methods for improving double patterning route efficiency
1172014032713911/06/14Contact liner and methods of fabrication thereof
1182014032715311/06/14Standard cell connection for circuit routing
1192014032938811/06/14Methods of patterning features having differing widths
1202014032714011/06/14Integrated circuits and methods for fabricating integrated circuits with improved contact structures
1212014032746511/06/14Structures and methods for testing integrated circuits and via chains therein
1222014031961710/30/14Methods of forming metal silicide regions on a semiconductor device
1232014032476910/30/14Document driven methods of managing the content of databases that contain information relating to semiconductor manufacturing operations
1242014031961410/30/14Finfet channel stress using tungsten contacts in raised epitaxial source and drain
1252014031962010/30/14Methods for fabricating integrated circuits with polycrystalline silicon resistor structures using a replacment gate process flow, and the integrated circuits fabricated thereby
1262014032420810/30/14System and monitoring wafer handling and a wafer handling machine
1272014031243410/23/14Finfet device with a graphene gate electrode and methods of forming same
1282014031537110/23/14Methods of forming isolation regions for bulk finfet semiconductor devices
1292014030631710/16/14Finfet fin height control
1302014030810810/16/14System for separately handling different size foups
1312014029994110/09/14Sram cell with reduced voltage droop
1322014030266010/09/14Local interconnect to a protection diode
1332014029184710/02/14Methods of forming a barrier system containing an alloy of metals introduced into the barrier system, and an integrated circuit product containing such a barrier system
1342014029566410/02/14Methods of forming masking layers for use in forming integrated circuit products
1352014028969509/25/14Evaluation of pin geometry accessibility in a layer of circuit
1362014026438609/18/14Performance enhancement in pmos and nmos transistors on the basis of silicon/carbon material
1372014026434209/18/14Semiconductor device including a resistor and the formation thereof
1382014026434709/18/14Transistor with embedded strain-inducing material formed in cavities based on an amorphization process and a heat treatment
1392014026434909/18/14Low thermal budget schemes in semiconductor device fabrication
1402014026446109/18/14Metal layer enabling directed self-assembly semiconductor layout designs
1412014026447909/18/14Methods of increasing space for contact elements by using a sacrificial liner and the resulting device
1422014026448609/18/14Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
1432014026448709/18/14Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
1442014026448909/18/14Wrap around stressor formation
1452014026461709/18/14Hk/mg process flows for p-type semiconductor devices
1462014026462609/18/14Method for forming a gate electrode of a semiconductor device, gate electrode structure for a semiconductor device and according semiconductor device structure
1472014026463109/18/14Methods of forming alignment marks and overlay marks on integrated circuit products employing finfet devices and the resulting alignment/overlay mark
1482014026463209/18/14Semiconductor structure including a transistor having a layer of a stress-creating material and the formation thereof
1492014026464109/18/14Semiconductor device comprising contact structures with protection layers formed on sidewalls of contact etch stop layers
1502014026473109/18/14Programmable e-fuse for an integrated circuit product
1512014026475809/18/14Methods of forming a protection layer to protect a metal hard mask layer during lithography reworking processes
1522014026487609/18/14Multi-layer barrier layer stacks for interconnect structures
1532014026487709/18/14Metallization systems of semiconductor devices comprising a copper/silicon compound as a barrier material
1542014026489009/18/14Novel pillar structure for use in packaging integrated circuit products and methods of making such a pillar structure
1552014027336509/18/14Methods of forming contacts to source/drain regions of finfet devices by forming a region that includes a schottky barrier lowering material
1562014027336909/18/14Methods of forming contacts to source/drain regions of finfet devices
1572014027338909/18/14Semiconductor device having controlled final metal critical dimension
1582014027339609/18/14Method of forming a semiconductor structure including a metal-insulator-metal capacitor
1592014027342309/18/14Methods of forming a semiconductor device with a nanowire channel structure by performing an anneal process
1602014027342909/18/14Methods of forming finfet devices with a shared gate structure
1612014027343609/18/14Methods of forming barrier layers for conductive copper structures
1622014027345509/18/14Hard mask removal during finfet formation
1632014027347309/18/14Methods of forming a masking layer for patterning underlying structures
1642014027347409/18/14Interconnection designs using sidewall image transfer (sit)
1652014028229609/18/14Hybrid performing full field optical proximity correction for finfet mandrel layer
1662014028230109/18/14Stitch insertion for reducing color density differences in double patterning technology (dpt)
1672014028230309/18/14Pattern-independent and hybrid matching/tuning including light manipulation by projection optics
1682014028230709/18/14Method and providing metric relating two or more process parameters to yield
1692014028232309/18/14Parameterized cell for planar and finfet technology design
1702014028233009/18/14Priority based layout versus schematic (lvs)
1712014028234509/18/14Via insertion in integrated circuit (ic) designs
1722014026461309/18/14Integrated circuits and methods for fabricating integrated circuits with active area protection
1732014026463309/18/14Finfet devices having a body contact and methods of forming the same
1742014026898309/18/14Otprom array with leakage current cancelation for enhanced efuse sensing
1752014026906009/18/14Integrated circuits and methods for operating integrated circuits with non-volatile memory
1762014027267709/18/14Methods for fabricating euv masks and methods for fabricating integrated circuits using such euv masks
1772014027329909/18/14Systems and methods for fabricating semiconductor device structures using different metrology tools
1782014027330609/18/14Methods for fabricating integrated circuits including multi-patterning of masks for extreme ultraviolet lithography
1792014027336709/18/14Integrated circuits and methods for fabricating integrated circuits with gate electrode structure protection
1802014027337509/18/14Methods for fabricating integrated circuits with semiconductor substrate protection
1812014027346309/18/14Methods for fabricating integrated circuits that include a sealed sidewall in a porous low-k dielectric layer
1822014027347509/18/14Methods for fabricating guide patterns and methods for fabricating integrated circuits using such guide patterns
1832014027351109/18/14Methods for fabricating integrated circuits including formation of chemical guide patterns for directed self-assembly lithography
1842014027766809/18/14Methods and systems for fabricating integrated circuits utilizing universal and local processing management
1852014025242409/11/14Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
1862014025242509/11/14Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
1872014025242909/11/14Contact geometry having a gate silicon length decoupled from a transistor length
1882014025248009/11/14Combination finfet and planar fet semiconductor device and methods of making such a device
1892014025248109/11/14Transistor including a gate electrode extending all around one or more channel regions
1902014025255709/11/14Method for forming a semiconductor device and semiconductor device structures
1912014025261709/11/14Barrier layer conformality in copper interconnects
1922014025266009/11/14Multilayer pattern transfer for chemical guides
1932014025390209/11/14Multiple patterning process for forming trenches or holes using stitched assist features
1942014025401809/11/14Scattering enhanced thin absorber for euv reflective reticle and a making
1952014025606409/11/14Methods of repairing damaged insulating materials by introducing carbon into the layer of insulating material
1962014025609709/11/14Methods for forming integrated circuit systems employing fluorine doping
1972014025613509/11/14Methods of removing gate cap layers in cmos applications
1982014025613709/11/14Method of forming a semiconductor structure including an implantation of ions into a layer of spacer material
1992014025773809/11/14Hierarchically divided signal path for characterizing integrated circuits
2002014025896009/11/14Integrating optimal planar and three-dimensional semiconductor design layouts
2012014025614109/11/14Methods for fabricating integrated circuits utilizing silicon nitride layers
2022014024669609/04/14Transistor with embedded strain-inducing material formed in cavities formed in a silicon/germanium substrate
2032014024669809/04/14Channel sige removal from pfet source/drain region for improved silicide formation in hkmg technologies without embedded sige
2042014024673409/04/14Replacement metal gate with mulitiple titanium nitride laters
2052014024673509/04/14Metal gate structure for semiconductor devices
2062014024677509/04/14Methods of forming non-continuous conductive layers for conductive structures on an integrated circuit product
2072014024679109/04/1414 lpm contact power rail
2082014024743809/04/14Reticle defect correction by second exposure
2092014024874909/04/14Stress memorization technique
2102014024876409/04/14Methods of forming structures on an integrated circuit product
2112014024877009/04/14Microwave-assisted heating of strong acid solution to remove nickel platinum/platinum residues
2122014024877809/04/14Methods of forming asymmetric spacers on various structures on integrated circuit products
2132014024660509/04/14Defect removal process
2142014023804508/28/14Semiconductor device comprising a stacked die configuration including an integrated peltier element
2152014024278808/28/14Method of forming a high quality interfacial layer for a semiconductor device by performing a low temperature ald process
2162014024523808/28/14Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications
2172014023950308/28/14Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
2182014023124508/21/14Adjustable current shield for electroplating processes
2192014023190708/21/14Methods of inducing a desired stress in the channel region of a transistor by performing ion implantation/anneal processes on the gate electrode
2202014023196008/21/14Polysilicon resistor formation
2212014023243308/21/14Circuit element including a layer of a stress-creating material providing a variable stress and the formation thereof
2222014023301408/21/14Infrared-based metrology for detection of stress and defects around through silicon vias
2232014023188508/21/14Integrated circuits and methods for fabricating integrated circuits having metal gate electrodes
2242014023192208/21/14Semiconductor gate structure for threshold voltage modulation and making same
2252014023201008/21/14Integrated circuits and methods of forming the same with multi-level electrical connection
2262014023505508/21/14Method for fabricating a semiconductor integrated circuit with a litho-etch, litho-etch process for etching trenches
2272014022476408/14/14Chemical and physical templates for forming patterns using directed self-assembly materials
2282014022516808/14/14Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device
2292014022520108/14/14Edge and strap cell design for sram array
2302014022527008/14/14Method for off-grid routing structures utilizing self aligned double patterning (sadp) technology
2312014022784508/14/14Methods of forming multiple n-type semiconductor devices with different threshold voltages on a semiconductor substrate
2322014022784908/14/14Methods of trimming nanowire structures
2332014022785808/14/14Shallow trench isolation integration methods and devices formed thereby
2342014022786908/14/14Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions
2352014022787208/14/14Methods of forming conductive structures using a sacrificial liner layer
2362014022787908/14/14Methods for fabricating integrated circuits with improved semiconductor fin structures
2372014021746708/07/14Methods of forming substrates comprised of different semiconductor materials and the resulting device
2382014021748008/07/14Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer
2392014021754408/07/14Methods of forming a transistor device on a bulk substrate and the resulting device
2402014021758808/07/14Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device
2412014021759108/07/14Multi-layer barrier layer for interconnect structure
2422014022075608/07/14Methods of forming semiconductor devices by forming a semiconductor layer above source/drain regions prior to removing a gate cap layer
2432014022075908/07/14Methods for fabricating integrated circuits having gate to active and gate to gate interconnects
2442014022076708/07/14Double-pattern gate formation processing with critical dimension control
2452014022339008/07/14Retargeting semiconductor device shapes for multiple patterning processes
2462014022339208/07/14Optimized optical proximity correction handling for lithographic fills
2472014021748208/07/14Integrated circuits having replacement gate structures and methods for fabricating the same
2482014021751708/07/14Integrated circuits including finfet devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same
2492014022077508/07/14Methods for fabricating integrated circuits having embedded electrical interconnects



ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009



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