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Globalfoundries Singapore Pte Ltd
Globalfoundries Singapore Pte Ltd_20131212
  

Globalfoundries Singapore Pte Ltd patents

Recent patent applications related to Globalfoundries Singapore Pte Ltd. Globalfoundries Singapore Pte Ltd is listed as an Agent/Assignee. Note: Globalfoundries Singapore Pte Ltd may have other listings under different names/spellings. We're not affiliated with Globalfoundries Singapore Pte Ltd, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "G" | Globalfoundries Singapore Pte Ltd-related inventors




Date Globalfoundries Singapore Pte Ltd patents (updated weekly) - BOOKMARK this page
10/19/17 new patent  Piezoelectric micro-electromechanical system (mems)
10/19/17 new patent  Integrated circuit electrostatic discharge protection
10/12/17Methods for fabricating electronic devices including substantially hermetically sealed cavities and getter films
10/05/17Domain wall magnetic memory
10/05/17Integrated hall effect sensors with voltage controllable sensitivity
09/14/17Low cost high performance eeprom device
08/31/17Silicon controlled rectifier (scr) based esd protection device
08/17/17Reliable passivation for integrated circuits
08/17/17High density multi-time programmable resistive memory devices and forming thereof
08/17/17Compact and reliable changeable negative voltage transmission circuit
08/10/17Three-axis monolithic mems accelerometers and methods for fabricating same
07/20/17Integrated circuits with high voltage and high density capacitors and methods of producing the same
07/13/17Transistor with source-drain silicide pullback
07/06/17Integrated circuits with aluminum via structures and methods for fabricating the same
07/06/17Integrated led and led driver units and methods for fabricating the same
07/06/17Integrated circuits with electrostatic discharge protection
07/06/17Self-aligned high voltage ldmos
07/06/17High voltage device with low rdson
07/06/17Integrated circuits with gaps
07/06/17Ultra low voltage ring oscillator with redundant inverter
06/29/17Semiconductor device with improved narrow width effect and making thereof
06/22/17Semiconductor devices with cavities and methods for fabricating semiconductor devices with cavities
06/08/17Crack stop layer in inter metal layers
05/25/17P-channel multi-time programmable (mtp) memory cells
05/11/17Integrated circuits having multiple gate devices with dual threshold voltages and methods for fabricating such integrated circuits
05/04/17Integrated mems-cmos devices and integrated circuits with mems devices and cmos devices
05/04/17Stitched devices
05/04/17Integrated circuits having an anti-fuse device and methods of forming the same
05/04/17Spacer layer for magnetoresistive memory
04/20/17Low power embedded one-time programmable (otp) structures
04/13/17Magnetism-controllable dummy structures in memory device
03/30/17Integrated circuits with alignment marks and methods of producing the same
03/30/17Plasma discharge path
03/30/17Integrated two-terminal device and logic device with compact interconnects having shallow via for embedded application
03/23/17High voltage transistor
03/23/17Integrated magnetic random access memory with logic device
03/09/17Gate-grounded metal oxide semiconductor device
03/09/17Integrated circuits having tunnel transistors and methods for fabricating the same
03/02/17High voltage transistor with reduced isolation breakdown
02/23/17Photonic devices with through dielectric via interposer
02/09/17Integrated circuits having copper bonding structures with silicon carbon nitride passivation layers thereon and methods for fabricating same
01/26/17Mram chip magnetic shielding
01/26/173d mram with through silicon vias or through silicon trenches magnetic shielding
01/05/17Creation of wide band gap material for integration to soi thereof
12/15/16Pattern classification based proximity corrections for reticle fabrication
12/08/16Mram magnetic shielding with fan-out wafer level packaging
12/01/16Electronic devices including substantially hermetically sealed cavities and getter films and methods for fabricating the same
12/01/16Integrated circuits with overlay marks and methods of manufacturing the same
12/01/16Small pitch and high density contact array
12/01/16Magnetic shielding for mtj device or bit
12/01/16Integrated magnetic random access memory with logic device
11/24/16Stitched devices
11/24/16Wafer stack protection seal
11/24/16Interposers for integrated circuits with one-time programming and methods for manufacturing the same
11/24/16Interposers for integrated circuits with multiple-time programming and methods for manufacturing the same
11/24/16Extended drain metal-oxide-semiconductor transistor
11/10/16One quarter wavelength transmission line based electrostatic discharge (esd) protection for integrated circuits
11/03/16Low power memory cell with high sensing margin
11/03/16Integration of devices
10/27/16Lateral high voltage transistor
10/13/16Stt-mram bitcell for embedded flash applications
10/06/16Programmable active cooling device
10/06/16Vertical random access memory with selectors
09/29/16Storage layer for magnetic memory with high thermal stability
09/29/16Magnetic shielding of mram package
Patent Packs
09/29/16Integrated circuits with memory cells and methods of manufacturing the same
09/22/16Voltage-tunable magnetic devices for communication applications
09/22/16Integrated circuits using silicon on insulator substrates and methods of manufacturing the same
09/22/16Reliable contacts
09/22/16Integrated magnetically coupled devices and making the same
09/22/16Edge structure for backgrinding asymmetrical bonded wafer
09/22/16High thermal budget magnetic memory
09/22/16Bottom electrode for magnetic memory to increase tmr and thermal budget
09/15/16Integrated magnetic random access memory with logic device having low-k interconnects
09/15/16Split-gate flash memory with improved program efficiency
09/08/16Magnetic memory with tunneling magnetoresistance enhanced spacer layer
09/08/16Magnetic memory with tunneling magnetoresistance enhanced spacer layer
09/01/16Integration of spintronic devices with memory device
09/01/16Magnetic memory with high thermal budget
09/01/16Magnetic memory with high thermal budget
Patent Packs
08/25/16Compact rram structure with contact-less unit cell
08/18/16Corner transistor suppression
08/11/16Slot designs in wide metal lines
08/11/16Selector device for a non-volatile memory cell
08/04/16Magnetic memory cells with low switching current density
08/04/16High sensing margin resistive memory
08/04/16Magnetic memory cells with fast read/write speed
08/04/16Mram with metal-insulator-transition material
08/04/16Magnetic memory cells with high write current and read stability
08/04/16Voltage controlled spin switches for low power applications
06/30/16Low voltage semiconductor memory device and operation
06/30/16Etch bias control
06/30/16Integrated circuits with inactive gates and methods of manufacturing the same
06/30/16Integrated circuits, methods of forming the same, and methods of determining gate dielectric layer electrical thickness in integrated circuits
06/30/16Device without zero mark layer
06/30/16Through silicon vias
06/30/16Dual encapsulation integration scheme for fabricating integrated circuits with magnetic random access memory structures
06/23/16Cross technology reticle (ctr) or multi-layer reticle (mlr) cdu, registration, and overlay techniques
06/23/16Reliable passivation layers for semiconductor devices
06/23/16Field effect transistor with self-adjusting threshold voltage
06/16/16System and modular simulation of spin transfer torque magnetic random access memory devices
06/16/16Device substrates, integrated circuits and methods for fabricating device substrates and integrated circuits
06/09/16Defect isolation methods and systems
06/09/16Isolation scheme for high voltage device
06/09/16Scalable and reliable non-volatile memory cell
06/02/16Rc-stacked mosfet circuit for high voltage (hv) electrostatic discharge (esd) protection
06/02/16High voltage device with low rdson
06/02/16Split gate embedded memory technology and manufacturing thereof
05/26/16Methods for extreme ultraviolet mask defect mitigation by multi-patterning
05/19/16Cmp head structure
Social Network Patent Pack
05/19/16Cmp head structure
05/19/16Pellicles and devices comprising a photomask and the pellicle
05/19/16Reliable non-volatile memory device
05/12/16Methods for fabricating integrated circuits with improved active regions
05/12/16Test structure for monitoring liner oxidation
05/12/16Integrated circuits including magnetic core inductors and methods for fabricating the same
05/12/16Guard ring for memory array
05/12/16Integrated circuit structures with spin torque transfer magnetic random access memory having increased memory cell density and methods for fabricating the same
05/12/16Integrated circuit structures with spin torque transfer magnetic random access memory ultilizing aluminum metallization layers and methods for fabricating the same
05/05/16Method and bitcell modeling
Patent Packs
05/05/16Energy efficient three-terminal voltage controlled memory cell
04/28/16Uniform polishing with fixed abrasive pad
04/28/16Planar passivation for pads
04/21/16Integrated circuits with laterally diffused metal oxide semiconductor structures and methods for fabricating the same
04/21/16Integrated circuit structures with spin torque transfer magnetic random access memory and methods for fabricating the same
03/31/16Double gated flash memory
03/31/16Magnetic tunnel junction stack alignment scheme
03/24/16Non-volatile resistive random access memory crossbar devices with maximized memory element density and methods of forming the same
03/17/16Selector-resistive random access memory cell
03/10/16Silicon-on-insulator integrated circuit devices with body contact structures and methods for fabricating the same
03/03/16Integrated circuits with finfet nonvolatile memory
02/25/16High gain device
02/18/16Defect isolation methods and systems
02/04/16Integrated circuits having device contacts and methods for fabricating the same
02/04/16Finfet with stressors
01/28/16Resistive memory device
12/24/15Systems and methods for testing performance of memory modules
12/10/15Integrated circuits with hall effect sensors and methods for producing such integrated circuits
12/03/15Bandgap reference voltage generator circuits
12/03/15Methods for fabricating integrated circuits with nonvolatile memory devices
11/26/15Integrated circuits with laterally diffused metal oxide semiconductor structures and methods for fabricating the same
11/26/15Recessing and capping of gate structures with varying metal compositions
11/26/15Latch-up robust scr-based devices
11/19/15Thyristor random access memory
11/19/15Vertical random access memory with selectors
11/12/15Ldmos with improved breakdown voltage
10/29/15Equivalent fuse circuit for a one-time programmable read-only memory array
10/29/15Integrated circuits having nickel silicide contacts and methods for fabricating the same
10/29/15Integrated circuits with spin torque transfer magnetic random access memory and methods for fabricating the same
10/29/15Semiconductor device including an n-well structure
Patent Packs
10/22/15Cmp wafer edge control of dielectric
10/22/15Methods for fabricating integrated circutis and components thereof
10/15/15Methods for extreme ultraviolet mask defect mitigation by multi-patterning
10/15/15Silicon-on-insulator integrated circuit devices with body contact structures and methods for fabricating the same
10/15/15Ip protection
10/08/15Stress enhanced high voltage device
10/01/15Isolation for embedded devices
09/24/15System and methods for opc model accuracy management and disposition
09/24/15Method of forming split-gate cell for non-volative memory devices
09/17/15Integrated circuits with stressed semiconductor-on-insulator (soi) body contacts and methods for fabricating the same
09/10/15Split-gate flash memory exhibiting reduced interference
08/20/15Novel latch-up immunity nldmos
08/20/15Methods for fabricating integrated circuits with a high-voltage mosfet
08/20/15Novel compact charge trap multi-time programmable memory
08/20/15High voltage trench transistor
08/13/15Split gate embedded memory technology and manufacturing method thereof
08/06/15Layout for reticle and wafer scanning electron microscope registration or overlay measurements
08/06/151t sram/dram
08/06/151t sram/dram
08/06/15Device with isolation buffer
Social Network Patent Pack
08/06/15Fin selector with gated rram
07/30/15Simple and cost-free mtp structure
07/30/15Simple and cost-free mtp structure
07/02/15System and methods for opc model accuracy management and disposition
07/02/15Integrated circuits with improved gap fill dielectric and methods for fabricating same
07/02/15Through via contacts with insulated substrate
07/02/15Reliable interconnects
07/02/15Integrated circuits including copper pillar structures and methods for fabricating the same
07/02/15Three-dimensional non-volatile memory
07/02/15Multi-level memory cells and methods for forming multi-level memory cells
07/02/15Integrated circuits including a resistance element and gate-last techniques for forming the integrated circuits
07/02/15Compact localized rram cell structure realized by spacer technology
06/25/15Hybrid tsv and forming the same
06/25/15Integrated circuits with copper hillock-detecting structures and methods for detecting copper hillocks using the same
06/25/15Semiconductor wafers employing a fixed-coordinate metrology scheme and methods for fabricating integrated circuits using the same
06/25/15Three-dimensional integrated circuit structures providing thermoelectric cooling and methods for cooling such integrated circuit structures
06/25/15Sandwich damascene resistor
06/25/15Integrated circuits with a buried n layer and methods for producing such integrated circuits
06/18/15Tsv without zero alignment marks
06/18/15Integrated circuits having crack-stop structures and methods for fabricating the same
Social Network Patent Pack
06/11/15Finfet with isolation
06/11/15Wrap around phase change memory
05/28/15Integrated circuits having improved split-gate nonvolatile memory devices and methods for fabrication of same
05/28/15Low resistance contacts without shorting
05/28/15Methods for fabricating integrated circuits using chemical mechanical polishing
05/21/15High rectifying ratio diode
05/21/15Method for forming through silicon via with wafer backside protection
05/21/15Setup for multiple cross-section sample preparation
05/14/15Multi-time programmable device
05/07/15Fin-type memory
04/23/15High ion and low sub-threshold swing tunneling transistor
04/23/15Reliable passivation layers for semiconductor devices
04/23/15Cmp head structure
04/23/15Cmp head structure
04/09/15Grounding of silicon-on-insulator structure
04/09/15Semiconductor devices including avalanche photodetector diodes integrated on waveguides and methods for fabricating the same
03/26/15Guard ring for memory array
03/26/15Contact strap for memory array
03/26/15Wafer processing
03/26/15Wafer processing
03/19/15Reliable contacts
03/12/15Finfet
03/12/15Efficient integration of cmos with poly resistor
03/12/15Logic compatible memory
03/12/15Method for forming an air gap around a through-silicon via
03/05/15Package interconnects
03/05/15Pad solutions for reliable bonds
02/26/15Simple and cost-free mtp structure
02/26/15Late in-situ doped sige junctions for pmos devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations
02/26/15High voltage device
Social Network Patent Pack
02/26/15Arc residue-free etching
02/19/15Split gate embedded memory technology and manufacturing thereof
02/19/15Cmos compatible wafer bonding layer and process
02/05/15Low rdson device and manufacturing the same
01/29/153d high voltage charge pump
01/29/15Integrated circuits having device contacts and methods for fabricating the same
01/15/15Semiconductor devices including photodetectors integrated on waveguides and methods for fabricating the same
01/08/15Diffusion barrier and formation thereof
01/01/15Simple and cost-free mtp structure
01/01/15Integrated circuits having improved split-gate nonvolatile memory devices and methods for fabrication of same
12/25/14Cd control
11/27/14Transistor devices having an anti-fuse configuration and methods of forming the same
11/13/14Silicon-on-insulator integrated circuits with local oxidation of silicon and methods for fabricating the same
10/30/14Integrated circuits with laterally diffused metal oxide semiconductor structures
09/18/14Integration of low rdson ldmos with high sheet resistance poly resistor
09/18/14Fin selector with gated rram
09/18/14Nonvolative memory
09/18/14Layout for reticle and wafer scanning electron microscope registration or overlay measurements
09/18/14Fluorine-doped channel silicon-germanium layer
09/18/14Scalable and reliable non-volatile memory cell
09/18/14Back-gated non-volatile memory cell
09/18/14Esd protection circuit
09/18/14Lateral double-diffused high voltage device
09/18/14Through silicon vias
09/18/14Cross technology reticle (ctr) or multi-layer reticle (mlr) cdu, registration, and overlay techniques
09/18/14Resistive non-volatile memory
09/18/14Stackable non-volatile memory
09/18/14Etch failure prediction based on wafer resist top loss
09/18/14Surface topography enhanced pattern (step) matching







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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