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Imagination Technologies Limited
Imagination Technologies Limited_20131212
  

Imagination Technologies Limited patents

Recent patent applications related to Imagination Technologies Limited. Imagination Technologies Limited is listed as an Agent/Assignee. Note: Imagination Technologies Limited may have other listings under different names/spellings. We're not affiliated with Imagination Technologies Limited, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "I" | Imagination Technologies Limited-related inventors




Date Imagination Technologies Limited patents (updated weekly) - BOOKMARK this page
11/30/17Hardware data structure for tracking partially ordered and reordered transactions
11/30/17Assessing performance of a hardware design using formal evaluation logic
11/23/17Primitive processing in a graphics processing system
11/09/17Hardware implementation of a convolutional neural network
11/09/17Convolutional neural network hardware configuration
11/09/17Primitive processing in a graphics processing system with tag buffer storage of primitive identifiers
11/09/17Compressing and decompressing image data using compacted region transforms
11/02/17Directed placement of data in memory
11/02/17Method for handling exceptions in exception-driven system
11/02/17Verification of hardware designs to implement floating point power functions
11/02/17Generation of a control stream for a tile
10/26/17Sorting numbers in hardware
10/26/17Evaluating polynomials in hardware logic
10/26/17Communication interface between host system and state machine
10/26/17Circuit architecture mapping signals to functions for state machine execution
10/26/17Dedicated ray memory for ray tracing in graphics systems
10/26/17Comfort noise generation
10/19/17Partially and fully parallel normaliser
10/19/17Systems and methods of partial frame buffer updating
10/12/17Processors supporting atomic writes to multiword memory locations & methods
10/12/17Read discards in a processor system with write-back caches
10/12/17Apparatus and methods for out of order item selection and status updating
10/12/17Auto-tuning of an acoustic echo canceller
10/05/17Handling memory requests
10/05/17Noise enhanced histograms
09/28/17Unified multiply unit
09/28/17Exception handling in processor using branch delay slot instruction set architecture
09/28/17Learned feature motion detection
09/28/17Query resolver for global illumination of 3-d rendering
09/28/17Generating sparse sample histograms in image processing
09/21/17Check procedure for floating point operations
09/21/17Non-linear cache logic
09/21/17Hierarchy merging
09/21/17Auto-tuning of acoustic echo canceller
09/21/17Decoding frames
09/14/17Constant fraction integer multiplication
09/14/17Importance sampling for determining a light map
09/14/17Methods and graphics processing units for determining differential data for rays of a ray bundle
09/07/17Task assembly for simd processing
08/24/17Controlling analogue gain using digital gain estimation
08/17/17Receiver deactivation based on dynamic measurements
08/10/17Compacting results vectors between stages of graphics processing
08/03/17Stack pointer value prediction
08/03/17Control of pre-fetch traffic
08/03/17Identifying bugs in a counter using formal
08/03/17Sparse rendering in computer graphics
08/03/17Frustum rendering in computer graphics
07/20/17Dynamic power measurement using formal
07/20/17Execution of load instructions in a processor
07/20/17Rendering in computer graphics systems
07/20/17Echo path change detector
07/13/17Controlling the focus of a camera using focus statistics
07/06/17Scheduling execution of instructions on a processor having multiple hardware threads with different execution resources
07/06/17Face detection in an image data stream using skin colour patch constructs
07/06/17Memory management for systems for generating 3-dimensional computer images
06/22/17Lossy data compression
06/22/17Arbiter verification
06/22/17Deadlock detection in hardware design using assertion based verification
06/22/17Tile based computer graphics
06/22/17Multistage collector for outputs in multiprocessor systems
06/22/17Artefact detection and correction
06/22/17Allocation of tiles to processing engines in a graphics processing system
06/22/17Capturing an image
06/15/17Migration of data to register file cache
06/15/17Configurable fft architecture
Patent Packs
06/15/17Foveated rendering
06/08/17Digital signal processing data transfer
06/08/17Gpu virtualisation
06/08/17Relightable texture for use in rendering an image
06/08/17Intelligent power saving
06/01/17Modulo hardware generator
05/25/17Trailing or leading zero counter having parallel and combinational logic
05/25/17Tile-based graphics
05/25/17Just in time packet body provision for wireless transmission
05/11/17Fetch ahead branch target buffer
05/11/17Multi-line image processing with parallel processing units
05/11/17Hardware monitor to verify memory units
05/04/17Processors supporting endian agnostic simd instructions and methods
05/04/17Clock verification
04/27/17Systems and methods for processing images of objects using interpolation between keyframes
Patent Packs
04/27/17Systems and methods for processing images of objects using coarse surface normal estimates
04/27/17Systems and methods for processing images of objects using coarse intrinsic colour estimates
04/27/17Systems and methods for processing images of objects using global lighting estimates
04/27/17Systems and methods for processing images of objects using lighting keyframes
04/27/17Acoustic echo suppression
04/20/17System and rounding reciprocal square root results of input floating point numbers
04/13/17Variable length execution pipeline
04/13/17Prioritizing instructions based on type
04/13/17Asynchronous and concurrent ray tracing and rasterization rendering processes
03/30/17Fetch unit for predicting target for subroutine return instructions
03/30/17Tessellating patches of surface data in tile based computer graphics rendering
03/30/17Graphics renderer and rendering 3d scene in computer graphics using object pointers and depth values
03/23/17Data compression using spatial decorrelation
03/16/17Trailing or leading digit anticipator
03/16/17Task execution in a simd processing unit with parallel groups of processing lanes
03/16/17Encryption key updates in wireless communication systems
03/16/17Method and compressing and decompressing data
03/09/17Synchronising devices using clock signal delay estimation
03/09/17Memory address generation for digital signal processing
03/09/17Graphics processing processing sub-primitives using cached graphics data hierarchy
03/09/17Graphics processing processing sub-primitives using sub-primitive indications in a control stream
03/09/17Synchronising devices using clock signal time difference estimation
03/09/17Synchronising devices using clock signal delay comparison
03/02/17Processing of primitive blocks in parallel tiling engine pipes
03/02/17Bandwidth management
03/02/17Bandwidth management
03/02/17Nearend speech detector
02/09/17Hardware data structure for tracking ordered transactions
02/02/17Rounding floating point numbers
02/02/17Denoising filter
Social Network Patent Pack
02/02/17Estimating processor load using frame encoding times
02/02/17Identifying a network condition using estimated processor load
01/12/17Check pointing a shift register
01/12/17Check pointing a shift register using a circular buffer
01/12/17Atomic memory update unit & methods
01/05/17Clock frequency adjustment for semi-conductor devices
12/22/16Systems and methods for 3-d scene acceleration structure creation and updating
12/08/16Tessellation method
12/08/16Tessellation method using recursive sub-division of triangles
12/08/16Tessellation method using displacement factors
Patent Packs
12/08/16Sampling frequency offset calculation
12/08/16Minimizing inter-symbol interference in ofdm signals
12/08/16Complementary vectors
12/08/16Motion estimation using collocated blocks
12/08/16Method and time synchronisation in wireless networks
12/01/16Efficient modulo calculation
12/01/16Memory allocation in distributed memories for multiprocessing
12/01/16Error tracking and mitigation for motion compensation-based video compression
11/24/16Translation lookaside buffer
11/17/16Trailing or leading zero counter having parallel and combinational logic
11/17/16Graphics processor with non-blocking concurrent architecture
11/17/16Selective sub-carrier processing
11/10/16Performing constant modulo arithmetic
11/03/16Fault tolerant processor for real-time systems
11/03/16Control path verification of hardware design for pipelined process
10/27/16Deadlock detection in hardware design using assertion based verification
10/27/16Tiling a primitive in a graphics processing system by testing subsets of tiles in a rendering space
10/27/16Tiling a primitive in a graphics processing system
10/20/16Image synthesis
10/13/16Cache operation in a multi-threaded processor
10/13/16Modulo calculation using polynomials
10/06/16Speculative load issue
10/06/16Image filtering based on image gradients
10/06/16Untransformed display lists in a tile based rendering system
10/06/16Efficient demapping of constellations
09/29/16Controlling data flow between processors in a processing system
09/29/16Logging events with timestamps
09/29/16Simd processing module having multiple vector processing units
09/29/16Unified rasterization and ray tracing rendering environments
09/15/16Image noise reduction using lucas kanade inverse algorithm
Patent Packs
09/15/16Image noise reduction
09/08/16Systems and methods for distributed scalable ray processing
09/08/16Systems and methods for soft shadowing in 3-d rendering
09/08/16Graphics processing using directional representations of lighting at probe positions within a scene
09/01/16Crossing pipelined data between circuitry in different clock domains
09/01/16Register file having a plurality of sub-register files
09/01/16Low power detection of a voice control activation phrase
08/18/16Rendering views of a scene in a graphics processing unit
08/11/16Prioritising of instruction fetching in microprocessor systems
07/28/16Processing primitives which have unresolved fragments in a graphics processing system
07/21/16Arbiter verification
07/14/16Impulsive noise rejection
07/07/16Building acceleration structures with synthetic acceleration shapes for use in ray tracing
06/30/16Low density parity check decoder
06/30/16Unified multiply unit
06/23/16Multi-phased and multi-threaded program execution based on simd ratio
06/23/16Iq imbalance estimator
06/23/16In-band quality data
06/16/16Performing object detection in an image
06/09/16Random accessible lossless parameter data compression for tile based 3d computer graphics systems
Social Network Patent Pack
06/09/16Method and system for multisample antialiasing
06/09/16Low complexity soft output mimo decoder
06/09/16Proximity detection
06/02/16Migration of data to register file cache
06/02/16Method and system for wirelessly transmitting data
05/26/16Method, system and device for selecting a device to satisfy a user request
05/12/16Comfort noise generation
05/12/16Pure delay estimation
05/05/16Packet loss and bandwidth coordination
05/05/16Controlling operational characteristics of acoustic echo canceller
05/05/16Automatic tuning of a gain controller
04/28/16Apparatus and throttling hardware pre-fetch
04/28/16Symbol boundary detection
04/21/16Method, system and device for connecting similar users
04/21/16Small multiplier after initial approximation for operations with increasing precision
04/07/16Implementing fixed-point polynomials in hardware logic
04/07/16Using tiling depth information in hidden surface removal in a graphics processing system
03/31/16Variable length execution pipeline
03/31/16Detection of acoustic echo cancellation
03/31/16Rounding floating point numbers
Social Network Patent Pack
03/24/16Cache hashing
03/24/16Presenting pipelines of multicore processors as separate processor cores to a programming framework
03/24/16Data compression using entropy encoding
03/24/16Method and system for staggered parallelized video decoding
03/24/16Data compression using spatial decorrelation
03/10/16Efficient loading and storing of data
03/10/16Evaluation of polynomials with floating-point components
03/03/16Combining instructions from different branches for execution in a single processing element of a multithreaded processor
03/03/16Hardware data structure for tracking partially ordered and reordered transactions
03/03/16Hardware data structure for tracking ordered transactions
03/03/16Efficient interpolation
03/03/16Ray tracing system architectures and methods
02/25/16Method and scheduling the issue of instructions in a multithreaded processor
02/25/16Processors and methods for cache sparing stores
02/11/16Local irradiance estimation for use in rendering an image
02/11/16Surface normal estimation for use in rendering an image
02/11/16Determining diffuse image component values for use in rendering an image
02/11/16Performing a comparison computation in a computer system
02/11/16Implementing a square root operation in a computer system
02/04/16Method and ensuring data cache coherency
02/04/16Memory management for systems for generating 3-dimensional computer images
02/04/16Just in time packet body provision for wireless transmission
02/04/16Fast integer division
01/28/16Conditional branch prediction using a long history
01/21/16Encryption key updates in wireless communication systems
01/21/16Biasing selection of motion estimation vectors
01/14/16Check procedure for floating point operations
01/14/16Running a 32-bit operating system on a 64-bit processor
01/14/16Acoustic echo suppression
01/14/16Soundbar audio content control using image analysis
Social Network Patent Pack
12/31/15Profiling ray tracing renderers
12/24/15Replicating logic blocks to enable increased throughput
12/17/15Assigning primitives to tiles in a graphics processing system
12/17/15Setting a display list pointer for primitives in a tile-based graphics processing system
12/17/15Error detection in a motion estimation system
12/10/15Relightable texture for use in rendering an image
12/10/15Gamut mapping with blended scaling and clamping
12/03/15Decoding instructions that are modified by one or more other instructions
12/03/15Object tracking using momentum and acceleration vectors in a motion estimation system
12/03/15Allocation of primitives to primitive blocks
12/03/15Systems and methods of echo & noise cancellation in voice communication
11/26/15Restoring a register renaming map
11/26/15Graphics processor with non-blocking concurrent architecture
11/19/15Efficient tracking of decision-feedback equaliser coefficients
11/12/15Time stamp replication within a wireless network
11/05/15Approximating functions
11/05/15Noise enhanced histograms
11/05/15Adaptive span control
11/05/15Media controller
11/05/15Cadence analysis for a video signal having an interlaced format
10/22/15Allocating resources to threads based on speculation metric
10/22/15Compacting results vectors between stages of graphics processing
10/15/15Virtual camera for 3-d modeling applications
10/08/15Enhanced media quality management
10/08/15Auto-tuning of an acoustic echo canceller
10/08/15Auto-tuning of non-linear processor threshold
10/08/15Reordering of a beamforming matrix
10/08/15Reordering of a beamforming matrix based on encoding
10/01/15Prioritising events to which a processor is to respond







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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