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Imagination Technologies Limited
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Imagination Technologies Limited patents


Recent patent applications related to Imagination Technologies Limited. Imagination Technologies Limited is listed as an Agent/Assignee. Note: Imagination Technologies Limited may have other listings under different names/spellings. We're not affiliated with Imagination Technologies Limited, we're just tracking patents.

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Processing primitives which have unresolved fragments in a graphics processing system

A graphics processing system performs hidden surface removal and texturing/shading on fragments of primitives. The system includes a primary depth buffer (PDB) for storing depth values of resolved fragments, and a secondary depth buffer (SDB) for storing depth values of unresolved fragments. Incoming fragments are depth tested against depth values... Imagination Technologies Limited

Tessellation of patches of surfaces in a tile based rendering system

A method and apparatus are provided for tessellating patches of surfaces in a tile based three dimensional computer graphics rendering system. For each tile in an image a per tile list of primitive indices is derived for tessellated primitives which make up a patch. Hidden surface removal is then performed... Imagination Technologies Limited

Mip map compression

Methods and apparatus for compressing image data are described along with corresponding methods and apparatus for decompressing the compressed image data. An encoder unit, which generates the compressed image data, comprises an input arranged to receive a first image and a second image, wherein the second image is twice the... Imagination Technologies Limited

Clock synchronisation

A first device for playing media synchronously with a second device, includes a hardware clock having an adjustable clock frequency; a software clock configured to derive time in dependence on the hardware clock; a controller configured to: determine a synchronisation error between the software clock and a clock of the... Imagination Technologies Limited

Indirect branch prediction

Methods and indirect branch predictor logic units to predict the target addresses of indirect branch instructions. The method comprises storing in a table predicted target addresses for indirect branch instructions indexed by a combination of the indirect path history for previous indirect branch instructions and the taken/not-taken history for previous... Imagination Technologies Limited

Master synchronisation

A method at a first device for synchronising a first clock of the first device to a second clock of a second device, includes receiving a first message comprising an identifier from the second device; generating a first timestamp in dependence on the time at which the first message is... Imagination Technologies Limited

Method and time synchronisation in wireless networks

A wireless media distribution system is provided comprising an access point (6) for broadcasting media and a plurality of stations (2) for reception and playback of media. Each station is configured for receiving and decoding a timestamp in a beacon frame transmitted repeatedly from the access point. This is used... Imagination Technologies Limited

Reference synchronisation

A method at a first device for synchronising a first clock of the first device to a second clock of a second device, includes receiving a first message comprising an identifier from a third device; generating a first timestamp in dependence on the time at which the first message is... Imagination Technologies Limited

Low-area fixed-point polynomials

Methods of implementing fixed-point polynomials in hardware logic include distributing a defined error bound for the whole polynomial between operators in a data-flow graph for the polynomial by solving an optimization problem that outputs an accuracy parameter and a precision parameter for each node. Each operator is then itself optimized... Imagination Technologies Limited

Error bounded multiplication by invariant rationals

A hardware logic representation of a circuit to implement an operation to perform multiplication by an invariant rational is generated by truncating an infinite single summation array (which is represented in a finite way). The truncation is performed by identifying a repeating section and then discarding all but a finite... Imagination Technologies Limited

Low power detection of a voice control activation phrase

Methods of low power detection of an activation phrase are described. A microphone system comprises dedicated hardware logic for detecting a pre-defined activation phrase in an audio stream received via a microphone. If the pre-defined activation phrase is detected, the hardware logic sends a trigger signal to activate a module,... Imagination Technologies Limited

Aes hardware implementation

AES encryption or decryption, modifying the current key values and modifying the current state array by: processing the current state array using at least a portion of the current key values; generating key values based upon the current key values for use in a subsequent round; and updating the current... Imagination Technologies Limited

Approximating functions

A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising: an input for receiving an input variable in the... Imagination Technologies Limited

Fetching instructions in an instruction fetch unit

A method in an instruction fetch unit configured to initiate a fetch of an instruction bundle from a first memory and to initiate a fetch of an instruction bundle from a second memory, wherein a fetch from the second memory takes a predetermined fixed plurality of processor cycles, the method... Imagination Technologies Limited

Livelock recovery circuit

Livelock recovery circuits configured to detect livelock in a processor, and cause the processor to transition to a known safe state when livelock is detected. The livelock recovery circuits include detection logic configured to detect that the processor is in livelock when the processor has illegally repeated an instruction; and... Imagination Technologies Limited

Livelock detection in a hardware design using formal evaluation logic

A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in an instantiation of the hardware design; and assertion evaluation logic configured to periodically evaluate one or more... Imagination Technologies Limited

Augmented reality occlusion

A method for generating an augmented reality image from first and second images, wherein at least a portion of at least one of the first and the second image is captured from a real scene, the method comprising: identifying a confidence region in which a confident determination as to which... Imagination Technologies Limited

Method and compressing and decompressing data

Methods and apparatus are provided for compressing and decompressing image data by producing two sets of reduced size image data, generating a modulation value for each elementary of the area from the image data, the modulation value encoding information about how to combine the sets of reduced size image data... Imagination Technologies Limited

Executing memory requests out of order

An on-chip cache is described which receives memory requests and in the event of a cache miss, the cache generates memory requests to a lower level in the memory hierarchy (e.g. to a lower level cache or an external memory). Data returned to the on-chip cache in response to the... Imagination Technologies Limited

Deadlock detection in hardware design using assertion based verification

Methods and systems for detecting deadlock in a hardware design. The method comprises identifying one or more control signals in the hardware design; generating a state machine for each of the one or more control signals to track the state of the control signal; generating one or more assertions for... Imagination Technologies Limited

Hardware data structure for tracking partially ordered and reordered transactions

Methods and hardware data structures are provided for tracking ordered transactions in a multi-transactional hardware design comprising one or more slaves configured to receive transaction requests from a plurality of masters. The data structure includes one or more counters for keeping track of the number of in-flight transactions; a table... Imagination Technologies Limited

Assessing performance of a hardware design using formal evaluation logic

A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in an instantiation of the hardware design; and... Imagination Technologies Limited

Primitive processing in a graphics processing system

A graphics processing system has a rendering space which is divided into tiles. Primitives within the tiles are processed to perform hidden surface removal and to apply texturing to the primitives. The graphics processing system includes a plurality of depth buffers, thereby allowing a processing module to process primitives of... Imagination Technologies Limited

Hardware implementation of a convolutional neural network

A method in a hardware implementation of a Convolutional Neural Network (CNN), includes receiving a first subset of data having at least a portion of weight data and at least a portion of input data for a CNN layer and performing, using at least one convolution engine, a convolution of... Imagination Technologies Limited

Convolutional neural network hardware configuration

A method of configuring a hardware implementation of a Convolutional Neural Network (CNN), the method comprising: determining, for each of a plurality of layers of the CNN, a first number format for representing weight values in the layer based upon a distribution of weight values for the layer, the first... Imagination Technologies Limited

Primitive processing in a graphics processing system with tag buffer storage of primitive identifiers

A graphics processing system has a rendering space which comprises one or more tiles. The system comprises a processing module configured to perform hidden surface removal for primitives of a tile to determine primitive identifiers identifying the primitives which are visible at each of a plurality of sample positions in... Imagination Technologies Limited

Compressing and decompressing image data using compacted region transforms

There is a method of compressing image data comprising a set of image values each representing a position in image-value space so as to define an occupied region thereof. The method comprises selectively applying a series of compression transforms to subsets of the image data items to generate a transformed... Imagination Technologies Limited

Directed placement of data in memory

A method of storing computer executable instructions and data elements of a program in a plurality of memory blocks of an embedded system. The method includes receiving object code that comprises instructions that symbolically refer to one or more data elements; metadata that identifies the data elements in the object... Imagination Technologies Limited

Method for handling exceptions in exception-driven system

A method of processing exceptions in an exception-driven computing-based system that operates in either initialisation mode or exception-driven mode. The method includes, upon detecting an exception has occurred, causing the processor to execute exception handling instructions. When the system is operating in initialisation mode the exception handling instructions invoke a... Imagination Technologies Limited

Verification of hardware designs to implement floating point power functions

A method of exhaustively verifying a property of a hardware design to implement a floating point power function. The method includes, formally verifying that the hardware design is recurrent over sets of β input exponents, wherein β is an integer that is a multiple of the reciprocal of the exponent... Imagination Technologies Limited

Generation of a control stream for a tile

A method of processing primitives within a tiling unit of a graphics processing system is described. The method comprises determining whether a primitive falls within a tile based on positions of samples within each pixel. If it is determined that the primitive does fall within a tile based on the... Imagination Technologies Limited

Sorting numbers in hardware

An efficient hardware apparatus for calculating the maximum and/or minimum of two n-bit binary input values generates a number of separate select signals, each of which is then used to control the selection of a single bit from one of the two binary inputs. A select signal for an ith... Imagination Technologies Limited

Evaluating polynomials in hardware logic

An accurate implementation of a polynomial using floating-point or other rounded arithmetic can be generated using a plurality of hardware logic components which each implement an input polynomial such that the zeros in the input polynomial can be determined correctly. The number of different hardware logic components that are used... Imagination Technologies Limited

Communication interface between host system and state machine

A communications interface for interfacing between a host system and a state machine, the communications interface comprising: an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the... Imagination Technologies Limited

Circuit architecture mapping signals to functions for state machine execution

An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function;... Imagination Technologies Limited

10/26/17 / #20170309059

Dedicated ray memory for ray tracing in graphics systems

A ray tracing unit is implemented in a graphics rendering system. The ray tracing unit comprises: processing logic configured to perform ray tracing operations on rays, a dedicated ray memory coupled to the processing logic and configured to store ray data for rays to be processed by the processing logic,... Imagination Technologies Limited

10/26/17 / #20170309282

Comfort noise generation

A system for generating comfort noise for a stream of frames carrying an audio signal includes frame characterizing logic configured to generate a set of filter parameters characterising the frequency content of a frame; an analysis filter adapted using the filter parameters and configured to filter the frame so as... Imagination Technologies Limited

10/19/17 / #20170300297

Partially and fully parallel normaliser

Hardware logic arranged to normalise (or renormalise) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various... Imagination Technologies Limited

10/19/17 / #20170301057

Systems and methods of partial frame buffer updating

Aspects include a pixel source that produces data for a rendered surface divided into regions. A mapping identifies memory segments storing pixel data for each region of the surface. The mapping can identify memory segments storing pixel data from a prior rendered surface, for regions that were unchanged during rendering... Imagination Technologies Limited

10/12/17 / #20170293486

Processors supporting atomic writes to multiword memory locations & methods

A system and method process atomic instructions. A processor system includes a load store unit (LSU), first and second registers, a memory interface, and a main memory. In response to a load link (LL) instruction, the LSU loads first data from memory into the first register and sets an LL... Imagination Technologies Limited

10/12/17 / #20170293556

Read discards in a processor system with write-back caches

A system and method provide for a better way of managing a shared memory system. A multiprocessor system includes a first and second CPU, with each CPU having a private L1 cache. The system further includes a level 2 (L2) cache shared between the first CPU and the second CPU,... Imagination Technologies Limited

10/12/17 / #20170293646

Apparatus and methods for out of order item selection and status updating

An apparatus, system, and method provide a way for tracking the age of items stored within a queue. An apparatus includes an item storage array and an array of age-tracking bits. The item storage array stores data of valid items stored in the queue. The array of age-tracking bits is... Imagination Technologies Limited

10/12/17 / #20170295283

Auto-tuning of an acoustic echo canceller

A gain control system for dynamically tuning an echo canceller, the echo canceller being configured to estimate an echo of a far-end signal and subtract that estimate from a microphone signal to output an echo cancelled signal, the system comprising an echo measurement unit configured to calculate a ratio of... Imagination Technologies Limited

10/05/17 / #20170286151

Handling memory requests

A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the... Imagination Technologies Limited

10/05/17 / #20170287122

Noise enhanced histograms

Apparatus for binning an input value into one of a plurality of bins which collectively represent a histogram of input values, each of the plurality of bins representing a corresponding range of input values, the apparatus comprising: an input for receiving an input value; a noise source configured to generate... Imagination Technologies Limited

09/28/17 / #20170277514

Unified multiply unit

Embodiments disclosed pertain to apparatuses, systems, and methods for performing multi-precision single instruction multiple data (SIMD) operations on integer, fixed point and floating point operands. Disclosed embodiments pertain to a circuit that is capable of performing concurrent multiply, fused multiply-add, rounding, saturation, and dot products on the above operand types.... Imagination Technologies Limited

09/28/17 / #20170277539

Exception handling in processor using branch delay slot instruction set architecture

A processor employs hardware to save the program counter value of the next instruction to be executed in a branch instruction when an exception occurs. This is the branch target address in the case where the exception occurs in the delay slot of a taken branch. The value is saved... Imagination Technologies Limited

09/28/17 / #20170277941

Learned feature motion detection

A data processing device for detecting motion in a sequence of frames each comprising one or more blocks of pixels, includes a sampling unit configured to determine image characteristics at a set of sample points of a block, a feature generation unit configured to form a current feature for the... Imagination Technologies Limited

09/28/17 / #20170278297

Query resolver for global illumination of 3-d rendering

Rendering system combines point sampling and volume sampling operations to produce rendering outputs. For example, to determine color information for a surface location in a 3-D scene, one or more point sampling operations are conducted in a volume around the surface location, and one or more sampling operations of volumetric... Imagination Technologies Limited

09/28/17 / #20170280069

Generating sparse sample histograms in image processing

Apparatus for binning an input value into an array of bins, each bin representing a range of input values and the bins collectively representing a histogram of input values, the apparatus comprising: an input for receiving the input value; a memory for storing the array; and a binning controller configured... Imagination Technologies Limited

09/21/17 / #20170269902

Check procedure for floating point operations

Method and computer system for implementing an operation on ≧1 floating point input, in accordance with a rounding mode, e.g. using a Newton-Raphson technique. The floating point result comprises a p-bit mantissa. An unrounded proposed mantissa result is determined using the Newton-Raphson technique, wherein a p-bit rounded proposed mantissa result,... Imagination Technologies Limited

09/21/17 / #20170270046

Non-linear cache logic

Cache logic for generating a cache address from a binary memory address comprising a first binary sequence of a first predefined length and a second binary sequence of a second predefined length, the cache logic comprising: a plurality of substitution units each configured to receive a respective allocation of bits... Imagination Technologies Limited

09/21/17 / #20170270146

Hierarchy merging

A hierarchy is a multi-level linked structure of nodes, wherein the hierarchy represents data relating to a set of one or more items to be processed. Where there are multiple input hierarchies, it may improve the efficiency of the processing of the items to merge the input hierarchies to form... Imagination Technologies Limited

09/21/17 / #20170272579

Auto-tuning of acoustic echo canceller

A gain control system for dynamically tuning an echo canceller, the echo canceller being configured to estimate an echo of a far-end signal and subtract that echo estimate from a microphone signal to output an echo cancelled signal, the gain control system comprising a monitoring unit configured to estimate an... Imagination Technologies Limited

09/21/17 / #20170272769

Decoding frames

A system for decoding a data stream, comprising: a first decoder configured to decode the data stream at a first rate so as to generate a first stream of frames for playback and arranged to continue generating the first stream despite encountering an error in a particular frame; a second... Imagination Technologies Limited

09/14/17 / #20170262258

Constant fraction integer multiplication

where a, b and k are fixed integers.... Imagination Technologies Limited

09/14/17 / #20170263043

Importance sampling for determining a light map

A bounce light map for a scene is determined for use in rendering the scene in a graphics processing system. Initial lighting indications representing lighting within the scene are determined. For a texel position of the bounce light map, the initial lighting indications are sampled using an importance sampling technique... Imagination Technologies Limited

09/14/17 / #20170263044

Methods and graphics processing units for determining differential data for rays of a ray bundle

Graphics processing system configured to perform ray tracing. Rays are bundled together and processed together. When differential data is needed by a shader, the data of a true ray in the bundle can be used rather than processing separate tracker rays.... Imagination Technologies Limited

09/07/17 / #20170256020

Task assembly for simd processing

A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation... Imagination Technologies Limited

08/24/17 / #20170243598

Controlling analogue gain using digital gain estimation

A gain control system for controlling gain applied to an audio signal includes a power estimator configured to estimate the power of a digital signal derived from the audio signal, a digital gain estimator configured to determine, in dependence on the estimated power, a digital gain which would modify the... Imagination Technologies Limited

08/17/17 / #20170238255

Receiver deactivation based on dynamic measurements

Apparatuses, methods, apparatuses, and systems for of selectively deactivating portions of a receiver based on dynamic measurements are disclosed. One embodiment of a method includes receiving, by the receiver, a wireless signal, identifying a packet within the wireless signal, determining whether the packet cannot be decoded with a reliability greater... Imagination Technologies Limited

08/10/17 / #20170228920

Compacting results vectors between stages of graphics processing

Ray tracing, and more generally, graphics operations taking place in a 3-D scene, involve a plurality of constituent graphics operations. Responsibility for executing these operations can be distributed among different sets of computation units. The sets of computation units each can execute a set of instructions on a parallelized set... Imagination Technologies Limited

08/03/17 / #20170220353

Stack pointer value prediction

Methods and apparatus for predicting the value of a stack pointer which store data when an instruction is seen which grows the stack. The information which is stored includes a size parameter which indicates by how much the stack is grown and one or both of: the register ID currently... Imagination Technologies Limited

08/03/17 / #20170220471

Control of pre-fetch traffic

Methods and systems for improved control of traffic generated by a processor are described. In an embodiment, when a device generates a pre-fetch request for a piece of data or an instruction from a memory hierarchy, the device includes a pre-fetch identifier in the request. This identifier flags the request... Imagination Technologies Limited

08/03/17 / #20170220707

Identifying bugs in a counter using formal

A method of detecting a bug in a counter of a hardware design that includes formally verifying, using a formal verification tool, an inductive assertion from a non-reset state of an instantiation of the hardware design. The inductive assertion establishes a relationship between the counter and a test bench counter... Imagination Technologies Limited

Patent Packs
08/03/17 / #20170221177

Sparse rendering in computer graphics

A graphics processing system comprising: a tiling unit configured to tile a first view of a scene into a plurality of tiles and generate a list of primitives associated with each tile; a processing unit configured to identify a first subset of the tiles that are each associated with at... Imagination Technologies Limited

08/03/17 / #20170221261

Frustum rendering in computer graphics

A graphics processing system comprising: a tiling unit configured to tile a first view of a scene into a plurality of tiles; a processing unit configured to identify a first subset of the tiles that are associated with regions of the scene that are viewable in a second view; and... Imagination Technologies Limited

07/20/17 / #20170205864

Dynamic power measurement using formal

Methods, systems and hardware monitors for verifying that an integrated circuit defined by a hardware design meets a power requirement including detecting whether a power consuming transition has occurred for one or more flip-flops of an instantiation of the hardware design; in response to detecting that a power consuming transition... Imagination Technologies Limited

07/20/17 / #20170206086

Execution of load instructions in a processor

Techniques for executing a load instruction in a processor are described. In one example, load instructions which are detected to have an offset (or displacement) of zero are sent directly to a data cache, bypassing the address generation stage thereby reducing pipeline length. Load instructions having a nonzero offset can... Imagination Technologies Limited

07/20/17 / #20170206706

Rendering in computer graphics systems

A graphics system has a rendering space divided into a plurality of rectangular areas, each being sub-divided into a plurality of smaller rectangular areas of a plurality of pixels. Data is received representing a tiled set of polygons to be rendered in a selected one of the rectangular areas. For... Imagination Technologies Limited

07/20/17 / #20170208170

Echo path change detector

An echo path monitoring system for controlling an adaptive filter configured to estimate an echo of a far-end signal comprised in a microphone signal, the system comprising a comparison generator configured to compare the microphone signal with the estimated echo to obtain a first comparison and compare an error signal,... Imagination Technologies Limited

07/13/17 / #20170201675

Controlling the focus of a camera using focus statistics

Apparatus for controlling the focus of a camera arranged to capture a sequence of frames, includes an image processor configured to: form an image characteristic for a plurality of blocks of a first frame, each block comprising one or more pixels of the first frame; and calculate an image parameter... Imagination Technologies Limited

07/06/17 / #20170192779

Scheduling execution of instructions on a processor having multiple hardware threads with different execution resources

A method and apparatus are provided for executing instructions of a multi-threaded processor having multiple hardware threads with differing hardware resources comprising the steps of receiving a plurality of streams of instructions and determining which hardware threads are able to receive instructions for execution, determining whether a thread determined to... Imagination Technologies Limited

07/06/17 / #20170193281

Face detection in an image data stream using skin colour patch constructs

A data processing system for performing face detection on a stream of frames of image data, the data processing system comprising: a skin patch identifier configured to identify one or more patches of skin colour in a first frame and characterise each patch in the first frame using a respective... Imagination Technologies Limited

07/06/17 / #20170193631

Memory management for systems for generating 3-dimensional computer images

A memory management system for generating 3-dimensional computer images is provided. The memory management system includes a device for subdividing an image into a plurality of rectangular areas, a memory for storing object data pertaining to objects in the image which fall in each rectangular area, a device for storing... Imagination Technologies Limited

06/22/17 / #20170177227

Lossy data compression

A lossy method of compressing data, such as image data, which uses wrap-around wavelet compression is described. Each data value is divided into two parts and the first parts, which comprise the most significant bits from the data values, are compressed using wrap-around wavelet compression. Depending upon the target compression... Imagination Technologies Limited

06/22/17 / #20170177521

Arbiter verification

Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The... Imagination Technologies Limited

06/22/17 / #20170177753
06/22/17 / #20170178280

Tile based computer graphics

A method and system for generating and shading a computer graphics image in a tile based computer graphics system is provided. Geometry data is supplied and a plurality of primitives are derived from the geometry data. One or more modified primitives are then derived from at least one of the... Imagination Technologies Limited

06/22/17 / #20170178282

Multistage collector for outputs in multiprocessor systems

Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the... Imagination Technologies Limited

Patent Packs
06/22/17 / #20170178295

Artefact detection and correction

An artefact detector detects artefacts in a video sequence comprising interpolated frames generated by performing motion estimation. The detector comprises a pixel processor which processes pixel values in first and second input frames of the video sequence to identify respective blocks of pixels representing an image feature. A feature-matching module... Imagination Technologies Limited

06/22/17 / #20170178386

Allocation of tiles to processing engines in a graphics processing system

A graphics processing system processes primitive fragments using a rendering space which is sub-divided into tiles. The graphics processing system comprises processing engines configured to apply texturing and/or shading to primitive fragments. The graphics processing system also comprises a cache system for storing graphics data for primitive fragments, the cache... Imagination Technologies Limited

06/22/17 / #20170180651

Capturing an image

An imaging device for capturing an image of a scene, comprising: an image sensor; an optical arrangement operable to focus light from a portion of the scene onto the image sensor whilst preventing light from other portions of the scene from being focused onto the sensor; a controller configured to... Imagination Technologies Limited

06/15/17 / #20170168949

Migration of data to register file cache

Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a... Imagination Technologies Limited

06/15/17 / #20170168989

Configurable fft architecture

A device for performing a Fast Fourier Transform (FFT) on an input dataset includes an FFT pipeline having a first stage configured to receive the input dataset, a plurality of intermediate stages and a final stage, each stage having a stage input; a computational element; and a stage output; a... Imagination Technologies Limited

06/15/17 / #20170169602

Foveated rendering

Foveated rendering for rendering an image uses a ray tracing technique to process graphics data for a region of interest of the image, and a rasterisation technique is used to process graphics data for other regions of the image. A rendered image can be formed using the processed graphics data... Imagination Technologies Limited

06/08/17 / #20170160947

Digital signal processing data transfer

A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations... Imagination Technologies Limited

06/08/17 / #20170161204

Gpu virtualisation

A method of GPU virtualization comprises allocating each virtual machine (or operating system running on a VM) an identifier by the hypervisor and then this identifier is used to tag every transaction deriving from a GPU workload operating within a given VM context (i.e. every GPU transaction on the system... Imagination Technologies Limited

06/08/17 / #20170161938

Relightable texture for use in rendering an image

Relightable free-viewpoint rendering allows a novel view of a scene to be rendered and relit based on multiple views of the scene from multiple camera viewpoints. An initial texture can be segmented into materials and an initial coarse colour estimate is determined for each material. Scene geometry is estimated from... Imagination Technologies Limited

06/08/17 / #20170164285

Intelligent power saving

A device comprising: a transceiver operable in a first or second mode and configured to receive packets from a remote device, each packet comprising an indication of whether or not the remote device has a further packet to transmit, wherein: in the first mode the transceiver: (i) sends a polling... Imagination Technologies Limited

06/01/17 / #20170153871

Modulo hardware generator

A method of generating a hardware design to calculate a modulo value for any input value in a target input range with respect to a constant value d using one or more range reduction stages. The hardware design is generated through an iterative process that selects the optimum component for... Imagination Technologies Limited

05/25/17 / #20170147289

Trailing or leading zero counter having parallel and combinational logic

A trailing/leading zero counter is described which comprises a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block comprises two blocks of section hardware logic... Imagination Technologies Limited

05/25/17 / #20170148130

Tile-based graphics

A tile-based graphics system has a rendering space sub-divided into a plurality of tiles which are to be processed. Graphics data items, such as parameters or texels, are fetched into a cache for use in processing one of the tiles. Indicators are determined for the graphics data items, whereby the... Imagination Technologies Limited

05/25/17 / #20170150397

Just in time packet body provision for wireless transmission

Wireless transmission is performed by storing, in a local memory, a header in association with reference(s) to memory locations in a separate, shared memory storing a payload for a given transmission. Each header can be associated with a QoS queue. When a selected payload is to be transmitted, a PHY... Imagination Technologies Limited

05/11/17 / #20170132009

Fetch ahead branch target buffer

A fetch ahead branch target buffer is used by a branch predictor to determine a target address for a branch instruction based on a fetch pointer for a previous fetch bundle, i.e. a fetch bundle which is fetched prior to a fetch bundle which includes the branch instruction. An entry... Imagination Technologies Limited

05/11/17 / #20170132750

Multi-line image processing with parallel processing units

An image processing system is described herein in which a multi-line processing block has multiple inputs and multiple outputs. In order to provide the multiple outputs the multi-line processing block has multiple processing units operating in parallel on the multiple inputs. The multiple outputs of the multi-line processing block are... Imagination Technologies Limited

05/11/17 / #20170133104

Hardware monitor to verify memory units

Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic... Imagination Technologies Limited

05/04/17 / #20170123792

Processors supporting endian agnostic simd instructions and methods

A processor includes a register and a load store unit (LSU). The LSU loads data into the register from a memory. When in little endian mode, bytes from sequentially increasing memory addresses are loaded in order of corresponding sequentially increasing byte memory addresses from a first end (right end) of... Imagination Technologies Limited

05/04/17 / #20170124237

Clock verification

Methods and systems for verifying a derived clock using assertion-based verification. The method comprises counting the number of full or half cycles of a fast clock that occur between the rising edge and the falling edge of a slow clock (i.e. during the ON phase of the slow clock); counting... Imagination Technologies Limited

04/27/17 / #20170116708

Systems and methods for processing images of objects using interpolation between keyframes

An image processing system and method for determining an intrinsic colour component of one or more objects present in a sequence of frames, for use in rendering the object(s), are described. Some of the frames of the sequence are to be used as lighting keyframes. A lighting estimate for a... Imagination Technologies Limited

04/27/17 / #20170116737

Systems and methods for processing images of objects using coarse surface normal estimates

An image processing system and method for determining a set of surface normals of one or more objects for use in rendering the object(s) is described. One or more input images are received, each representing a view of the object(s). A depth image is received representing depth values of the... Imagination Technologies Limited

04/27/17 / #20170116754

Systems and methods for processing images of objects using coarse intrinsic colour estimates

An image processing system and method for determining an intrinsic colour component of one or more objects for use in rendering the object(s) is described herein. One or more input images are received, each representing a view of the object(s), wherein values of each of the input image(s) are separable... Imagination Technologies Limited

04/27/17 / #20170116755

Systems and methods for processing images of objects using global lighting estimates

An image processing system and method for determining an intrinsic colour component of one or more objects for use in rendering the object(s) is described. One or more input images are received, each representing a view of the object(s), wherein values of the input image(s) are separable into intrinsic colour... Imagination Technologies Limited

04/27/17 / #20170116756

Systems and methods for processing images of objects using lighting keyframes

An image processing system and method for determining an intrinsic colour component of one or more objects present in a sequence of frames, for use in rendering the object(s), is described. At least some of the frames of the sequence are to be used as lighting keyframes. A lighting estimate... Imagination Technologies Limited

04/27/17 / #20170118326

Acoustic echo suppression

A controller for an echo suppressor configured to suppress a residual echo of a far-end signal included in a primary error signal, the controller adapted for operation with a primary adaptive filter configured to form a primary echo estimate of the far-end signal included in a microphone signal and an... Imagination Technologies Limited








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