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Imec patents


Recent patent applications related to Imec. Imec is listed as an Agent/Assignee. Note: Imec may have other listings under different names/spellings. We're not affiliated with Imec, we're just tracking patents.

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Magnetic random access memory device having magnetic tunnel junction

The disclosed technology generally relates to semiconductor devices and more particularly to semiconductor devices comprising a magnetic tunnel junction (mtj). In an aspect, a method of forming a magnetoresistive random access memory (mram) includes forming a layer stack above a substrate, where the layer stack includes a ferromagnetic reference layer, a tunnel barrier layer and a ferromagnetic free layer and a spin-orbit-torque (sot)-generating layer. ... Imec

Semiconductor device and manufacturing method therefor

The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The semiconductor device includes a substrate; two fins located on the substrate and extending along a first direction; an isolation material layer surrounding the fins, comprising a first isolation regions located at an end region between the two fins along the first direction, and a second isolation region located at sides of the fins along a second direction that is different from the first direction, wherein an upper surface of the first isolation region substantially align with an upper surfaces of the fins, and an upper surface of the second isolation region is lower than the upper surface of the fins; and a first insulating layer on the first isolation region. ... Imec

Method of forming nanowires

The disclosed technology generally relates semiconductor devices and more particularly to semiconductor devices comprising nanowires. In one aspect, a method of fabricating a semiconductor device includes providing a semiconductor substrate having one or more elongated structures thereon and forming a strained layer of semiconductor material on at least one surface of the elongated structures, and annealing the strained layer to form a semiconductor nanowire.. ... Imec

Memory device for a dynamic random access memory

The disclosed technology relates to a memory device for a dynamic random access memory, or dram. In one aspect, the memory device includes a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed. ... Imec

Memory structure comprising scratchpad memory

The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. ... Imec

Biometric sensor and biometric analysis system including the same

A biometric sensor that measures biometric information and a biometric analysis system including the biometric sensor are provided. The biometric sensor may include: a light source configured to emit light toward a region of interest of an object under examination, the light being diffused at the region of interest; a collimator that includes a though-hole and is configured to collimate the diffused light received from the region of interest; and a spectrometer configure to analyze the diffused light transmitted by the collimator.. ... Imec

System and method for generating a depth map using differential patterns

The present disclosure relates to an imaging system and a method of generating a depth map. The method comprises generating a first candidate depth map in response to a first pair of images associated with a first textured pattern, generating a second candidate depth map in response to a second pair of images associated with a second textured pattern different from the first textured pattern, determining one of pixels in a same location of the first and second candidate depth maps that is more reliable than the other; and generating a depth map based on the one pixel.. ... Imec

Electrically contacting and interconnecting photovoltaic cells

A method and module for electrically contacting a photovoltaic cell and for electrically interconnecting such cell is disclosed. In one aspect, the method includes providing a woven fabric comprising a plurality of electrically conductive wires being provided in a single one of a warp direction and a weft direction. ... Imec

Method and system for emotion-triggered capturing of audio and/or image data

The present disclosure relates to a method for emotion-triggered capturing of audio and/or image data by an audio and/or image capturing device. The method includes receiving and analyzing a time-sequential set of data including first physiological data representing a first physiological parameter corresponding to a first person, a second physiological data representing a second physiological parameter corresponding to a second person, and voice audio data including a voice of at least one of the first and the second person, to determine whether a simultaneous change of emotional state of a first person and a second person occurs and transmitting a trigger signal to the capturing device. ... Imec

Method for manufacturing a si-based high-mobility cmos device with stacked channel layers, and resulting devices

A device and method for manufacturing a si-based high-mobility cmos device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a iii-v semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with iii-v semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the iii-v semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth.. ... Imec

High aspect ratio channel semiconductor device and method of manufacturing same

The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. ... Imec

Sequential integration process

A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. ... Imec

Selective fin cut

The present disclosure relates to methods and structures that involve the use of directed self-assembly to selectively remove at least one fin or fin section from a pattern of parallel fins in a semiconductor structure.. . ... Imec

Method for bonding and interconnecting integrated circuit devices

A method for bonding and interconnecting two or more ic devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple ic devices are provided with metal contact structures. ... Imec

03/08/18 / #20180068898

Semi-sequential 3d integration

Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.. ... Imec

03/01/18 / #according to an aspect of the present inventive concept there is provided a reconfigurable sensor circuit comprising:
03/01/18 / #20180062660

Digital phase locked loop and method for operating the same

The present disclosure relates to a digital phase locked loop (dpll) for phase locking an output signal to a reference clock signal. The dpll comprises a phase detector for detecting a phase error of a feedback signal with respect to the reference clock signal. ... Imec

03/01/18 / #20180061741

Semiconductor die package and method of producing the package

A package including a first die embedded in a reconstructed wafer obtainable by the known fo-wlp or ewlb technologies is disclosed. In one aspect and in addition to the first die, a through substrate via insert is embedded in the wafer, the tsv insert being a separate element, possibly a silicon die with metal filled vias interconnecting contacts on the front and back sides of the insert. ... Imec

03/01/18 / #20180061712

Method of transferring a semiconductor layer

The disclosed technology generally relates to manufacturing of semiconductor devices, and more particularly to manufacturing of a semiconductor device by transferring an active layer from a donor substrate. One aspect is a method of manufacturing a semiconductor device includes providing a donor wafer for transferring an active layer, comprising a group iv, a group iii-iv or a group ii-vi semiconductor material, to a handling wafer. ... Imec

03/01/18 / #20180059529

Lithographic mask for euv lithography

The disclosure is related to a lithographic mask for euv lithography, to a method for producing the mask, to a method for printing a pattern with the mask, to a stepper/scanner configured to print a pattern with the mask as well as to a computer-implemented method for calculating a deformation of the pattern. The mask comprises an absorber pattern, which is intentionally deformed in the 2-dimensional plane of the euv mask, with respect to the intended pattern. ... Imec

02/15/18 / #20180047621

Formation of a transition metal nitride

A use of an amine-containing silane for forming a transition metal nitride is provided. In this use, the amine of the amine-containing silane is the source of at least some, preferably most and most preferably all of the nitrogen present in the transition metal nitride.. ... Imec

02/15/18 / #20180047560

Method for performing a wet treatment of a substrate

A method for performing a wet treatment of a structure is described in the present disclosure. An example method includes obtaining a structure comprising a first surface, wherein the first surfaces comprises a feature fixed at least at a first end to the first surface from which it protrudes, and wherein a sidewall of the feature faces and is positioned away from a second surface by a gap g, performing a wet treatment of the structure and subsequently, drying the structure, wherein performing the wet treatment comprises rinsing the structure by exposing it to a rinsing liquid comprising water, and exposing the structure, subsequently, to a sequence of liquids.. ... Imec

02/15/18 / #20180046899

Hardware implementation of a temporal memory system

A hardware implementation of a temporal memory system is disclosed. One aspect includes at least one array of memory cells logically organized in rows and columns, wherein each of the memory cells is adapted for storing a scalar value and adapted for changing the stored scalar value. ... Imec

02/15/18 / #20180046139

Lens-free imaging

Embodiments described herein relate to lens-free imaging. One example embodiment may include a lens-free imaging device for imaging a moving sample. ... Imec

02/15/18 / #20180043283

Method of forming micro-pipes on a substrate and a structure formed thereof

A method for producing a structure including, on a main surface of a substrate, at least one elongated cavity having openings at opposing ends. The method includes providing a substrate having a main surface. ... Imec

01/25/18 / #20180027176

Method and a system for eye tracking

According to an aspect of the present inventive concept there is provided a method for eye tracking, comprising: capturing a sequence of digital images of an eye of a user; outputting data including said sequence of images to an image processing unit; processing said data by the image processing unit to determine a sequence of positions of the eye, each position being indicative of a gaze direction, acquiring biosignal data representing an activity of the eye; and in response to detecting closing of the eye based on the acquired biosignal data, pausing at least one of said capturing, said outputting and said processing. A system for implementing the method is also disclosed.. ... Imec

01/25/18 / #20180025911

Monolithic integration of semiconductor materials

A method for forming a semiconductor structure by bonding a donor substrate to a carrier substrate is disclosed herein. The donor substrate may include a plurality of semiconductor layers epitaxially grown on top of one another in, and optionally above, a trench of the donor substrate. ... Imec

01/25/18 / #20180024618

Power control in integrated circuits

An integrated circuit device comprising a power control unit for controlling the power of a power isle is disclosed. The power control unit comprises (i) a power gating switch implemented in the beol portion for switching on/off the power to the power isle, (ii) a state recovery circuit comprising a memory element in the feol portion or beol portion and a transistor configuration in the beol portion, and (iii) a wake-up/sleep circuit in the beol portion adapted for receiving an identifier. ... Imec

01/18/18 / #20180020170

Method and a device for acquiring an image having two-dimensional spatial resolution and spectral resolution

The present disclosure relates to devices and methods for acquiring an image having two-dimensional spatial resolution and spectral resolution. An example method comprises: acquiring a frame using rows of photo-sensitive areas on a sensor surface detecting incident light from an object imaged by an optical system onto an image plane, wherein rows of photo-sensitive areas are arranged to receive different wavelengths; moving the sensor surface in a direction perpendicular to a longitudinal direction of the rows; repeating the acquiring and moving for acquiring a plurality of frames recording different spectral information for respective positions on the object; and combining information from the plurality of frames to form multiple channels of an image, wherein each channel is formed based on detected light in respective rows and represent a two-dimensional image of the object for a different wavelength.. ... Imec

01/11/18 / #20180011443

Large area lens-free imaging device

Embodiments described herein relate to a large area lens-free imaging device. One example is a lens-free device for imaging one or more objects. ... Imec

01/04/18 / #20180003667

Solid state electrolyte

A solid state electrolyte and method of preparation is provided. The solid state electrolyte includes a plasticized polymer matrix with non-dissolved salt crystals embedded in the polymer matrix and wherein the non-dissolved crystals are suitable for dissolving ions in the plasticized polymer. ... Imec

12/28/17 / #20170373649

Methods and devices for ramping a switched capacitor power amplifier

A method for ramping a switched capacitor power amplifier is disclosed, where the switched capacitor power amplifier comprises a plurality of capacitors in a capacitor bank, and where a number of the capacitors in the capacitor bank are activated. The method comprises changing the number of capacitors in the capacitor bank that are activated, maintaining the changed number of activated capacitors in the capacitor bank for a period of time, and repeating the changing and maintaining, where a length of the period of time is varied between at least two repetitions of the maintaining.. ... Imec

12/21/17 / #20170366334

Circuit and method for processing data

Systems and methods for processing data including a first and second component are described. An example circuit includes a processing stage arranged to calculate absolute values of the first component and the second component, and to output, at a first output, a maximum value of the absolute value of the first component and the absolute value of the second component, and, at a second output, a minimum value of the absolute value of the first component and the absolute value of the second component. ... Imec

12/14/17 / #20170358742

Resistive switching memory cell

The disclosed technology generally relates to semiconductor devices and more particularly to memory or storage devices based on resistive switching, and to methods of making and using such devices. In one aspect, a resistive switching memory device includes a first electrode and a second electrode having interposed therebetween a first inner region and a second inner region, where the first and second inner regions contacting each other. ... Imec

12/07/17 / #20170352766

Method for forming a vertical hetero-stack and a device including a vertical hetero-stack

Embodiments described herein include a method for forming a vertical hetero-stack and a device including a vertical hetero-stack. An example method is used to form a vertical hetero-stack of a first nanostructure and a second nanostructure arranged on an upper surface of the first nanostructure. ... Imec

12/07/17 / #20170352587

Method for interrupting a line in an interconnect

A method for forming a pattern for an integrated circuit is disclosed. In one aspect, the method includes (a) providing a hardmask layer; (b) overlaying the hard mask layer with a set of parallel material lines delimiting gaps therebetween; and (c) providing a spacer layer following the shape of the material layer. ... Imec

12/07/17 / #20170351035

Light coupler

Embodiments described herein relate to a light coupler, a photonic integrated circuit, and a method for manufacturing a light coupler. The light coupler is for optically coupling to an integrated waveguide and for out-coupling a light signal propagating in the integrated waveguide into free space. ... Imec

12/07/17 / #20170351034

Device and method for performing lens-free imaging

Embodiments described herein relate to an imaging device, a method for imaging an object, and a photonic integrated circuit. The imaging device includes at least one photonic integrated circuit. ... Imec

11/30/17 / #20170341078

Microbubble generator device, systems and method to fabricate

The present disclosure relates to microbubble generator devices for deflecting objects in a liquid, systems for sorting objects that utilize such devices, and methods for fabricating such devices. At least one embodiment relates to a micro-fluidic device for deflecting objects in a liquid. ... Imec

11/16/17 / #20170331652

Receiver including a plurality of high-pass filters

Embodiments described herein include a receiver, a method, and a plurality of high-pass filters for demodulating a radio frequency (rf) signal. An example receiver includes a plurality of high-pass filters. ... Imec

11/16/17 / #20170330801

Method of forming gate of semiconductor device and semiconductor device having same

The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. ... Imec

11/16/17 / #20170326552

Compact fluid analysis device and method to fabricate

The present disclosure relates to a fluid analyzing device that includes a sensing device for analyzing a fluid sample. The sensing device includes a microchip configured for sensing the fluid sample, and a closed micro-fluidic component for propagating the fluid sample to the microchip. ... Imec

11/16/17 / #20170326551

Fluid analysis device

The present disclosure relates to a fluid analysis device which comprises a sensing device for analyzing a fluid sample, the sensing device comprising a micro-fluidic component for propagating the fluid sample and a microchip configured for sensing the fluid sample in the micro-fluidic component; a sealed fluid compartment containing a further fluid, the compartment being fluid-tight connected to the sensing device and adapted for providing the further fluid to the micro-fluidic component when the sealed fluid compartment is opened; and an inlet for providing the fluid sample to the micro-fluidic component. Further, the present disclosure relates to a method for sensing a fluid sample using the fluid analysis device.. ... Imec

11/16/17 / #20170326546

Compact glass-based fluid analysis device and method to fabricate

The present disclosure relates to devices and methods for analyzing a fluid sample. An example device comprises a fluidic substrate comprising a micro-fluidic component embedded therein, for propagating a fluid sample; a needle or inlet for providing the fluid sample which is fluidically connected to the micro-fluidic component; a lid attached to the fluidic substrate thereby at least partly covering the fluidic substrate and at least partly closing the micro-fluidic component; wherein the fluidic substrate is a glass fluidic substrate and wherein the lid is a microchip. ... Imec

11/09/17 / #20170322516

Autofocus system and method in digital holography

At least one embodiment relates to an autofocus method for determining a focal plane for at least one object. The method includes reconstructing a holographic image of the at least one object such as to provide a reconstructed image at a plurality of different focal depths. ... Imec

10/12/17 / #20170294448

Integrated circuit power distribution network

An integrated circuit (ic) power distribution network is disclosed. In one aspect, the ic includes a stack of layers formed on a substrate. ... Imec

09/28/17 / #20170278752

Self-aligned gate contact

The disclosed technology generally relates to semiconductor devices, and more specifically to electrical contacts to a transistor device, and a method of making such electrical contacts. In one aspect, a method of forming one or more self-aligned gate contacts in a semiconductor device includes providing a substrate having formed thereon at least one gate stack, where the gate stack includes a gate dielectric and a gate electrode formed over an active region in or on the substrate, and where the substrate further has formed thereon a spacer material coating lateral sides of the at least one gate stack. ... Imec

09/21/17 / #20170271002

Resistance change memory device configured for state evaluation based on reference cells

The disclosed technology generally relates to memory devices and more particularly to memory devices based on resistance change, and to systems and methods for evaluating states of memory cells of the memory devices. In one aspect, a memory device includes a plurality of memory cells arranged in an array, where each memory cell comprises a memory element configured to be switched between at least two resistance states. ... Imec

09/14/17 / #20170263700

Iii-nitride based semiconductor device with low vulnerability to dispersion and backgating effects

The present disclosure is related to a iii-nitride semiconductor device comprising a base substrate, a buffer layer, a channel layer, a barrier layer so that a 2-dimensional charge carrier gas is formed or can be formed near the interface between the channel layer and the barrier layer, and at least one set of a first and second electrode in electrical contact with the 2-dimensional charge carrier gas, wherein the device further comprises a mobile charge layer (mcl) within the buffer layer or near the interface between the buffer layer and the channel layer, when the device is in the on-state. The device further comprises an electrically conductive path between one of the electrodes and the mobile charge layer. ... Imec

09/07/17 / #20170256451

Self-aligned interconnects

An interconnect structure and a method for forming it is disclosed. In one aspect, the method includes the steps of providing a first entity. ... Imec

07/20/17 / #20170205578

Polarization independent processing in integrated photonics

A photonic integrated circuit comprises an input interface adapted for receiving an optical input signal and splitting it into two distinct polarization modes and furthermore adapted for rotating the polarization of one of the modes for providing the splitted signals in a common polarization mode. The pic also comprises a combiner adapted for combining the first mode signal and the second mode signal into a combined signal and a decohering means adapted for transforming at least one of the first mode signal and the second mode signal such that the first mode signal and the second mode signal are received by the combiner in a mutually incoherent state. ... Imec

07/06/17 / #20170196120

Liquid cooling of electronic devices

A liquid cooling system for cooling an electronic device comprising a chip or a chip package comprising a chip is described. The liquid cooling system comprises an inlet plenum comprising a coolant feeding channel oriented substantially parallel with the plane of a main surface to be cooled of the chip and a plurality of inlet cooling channels fluidically connected to the coolant feeding channel and arranged vertically for impinging a liquid coolant directly on said main surface of the chip. ... Imec

07/06/17 / #20170195586

User device

A user device including a camera, a spectrometer module, and a processing unit is disclosed. In one aspect, the camera is adapted to acquire at least one image of a scenery which falls within a field of view of the camera. ... Imec

07/06/17 / #20170194487

High voltage tolerant ldmos

An ldmos device in finfet technology is disclosed. In one aspect, the device includes a first region substantially surrounded by a second region of different polarity. ... Imec

07/06/17 / #20170194246

Mimcap structure in a semiconductor device package

The disclosed technology relates generally to a semiconductor device package comprising a metal-insulator-metal capacitor (mimcap). In one aspect, the mimcap comprises portions of a first and second metallization layers in a stack of metallization layers, e.g., copper metallization layers formed by single damascene processes. ... Imec

06/29/17 / #20170184452

Spectrometer module

A spectrometer module comprising a plurality of separate electronic circuit modules is disclosed. Each separate electronic module comprises an integrated sensor circuit including a light sensitive area occupying part of an area of the integrated sensor circuit, the integrated sensor circuit being arranged to detect incident light. ... Imec

06/22/17 / #20170180170

Phase tracking receiver

The present disclosure relates to a method for demodulating a modulated signal and a receiver. The receiver comprises: a phase detector with a first and second input, the first input being adapted to receive a modulated input signal; a comparator comprising an input coupled to an output of the phase detector; a frequency-offset cancellation block comprising an input coupled to an output of the comparator. ... Imec

06/22/17 / #20170179976

Circuit and method for converting analog signal to digital value representation

A circuit and a method for converting an analog signal to a digital value representation is disclosed. In one aspect, the circuit includes an incremental sigma-delta analog-to-digital converter (adc). ... Imec

06/22/17 / #20170179974

Circuit for stabilizing a digital-to-analog converter reference voltage

The disclosure relates to a circuit for stabilizing a digital-to-analog converter reference voltage. One example embodiment is a circuit for stabilizing a voltage on a reference node. ... Imec

06/22/17 / #20170179937

Delay control circuit

The present disclosure relates to a delay control circuit arranged for adding delay to a signal. The delay control circuit includes a driver circuit arranged to receive a first signal and to output a second signal. ... Imec

06/22/17 / #20170179891

Small signal amplifier

An amplifier circuit, a voltage sensing apparatus, and an amplification method are disclosed. The amplifier circuit comprises (1) an input stage comprising a first set of transistors to which an input signal to be amplified is applied, the transistors of the first set comprising a semiconductor body, and (2) a processing stage comprising a second set of transistors for processing the signal from the input stage and generating an output signal. ... Imec

06/22/17 / #20170179378

Semiconductor device with integrated magnetic tunnel junction

The disclosed technology generally relates to semiconductor devices and more particularly to semiconductor devices having an integrated magnetic tunnel junction (mtj), and relates to methods of fabricating the semiconductor devices. In one aspect, a semiconductor device includes a stack including successive layers of: a first metallization layer, a first dielectric layer, a second metallization layer, a second dielectric layer, and a third metallization layer. ... Imec

06/22/17 / #20170179373

Spin torque majority gate device

The disclosed technology relates generally to magnetic devices, and more particularly to spin torque majority gate devices such as spin torque magnetic devices (stmg), and to methods of fabricating the same. In one aspect, a majority gate device includes a plurality of input zones and an output zone. ... Imec

06/22/17 / #20170179283

Multi-gate tunnel field-effect transistor (tfet)

A tunnel field-effect transistor (tfet) is provided comprising a source-channel-drain structure of a semiconducting material. The source-channel-drain structure comprises a source region being n-type or p-type doped, a drain region oppositely doped than the source region and an intrinsic or lowly doped channel region situated between the source region and the drain region. ... Imec

06/22/17 / #20170179281

Self-aligned nanostructures for semiconductor devices

A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate. ... Imec

06/22/17 / #20170179272

Method of fabricating an enhancement mode group iii-nitride hemt device and a group iii-nitride structure fabricated therefrom

The disclosure relates to a method of fabricating an enhancement mode group iii-nitride hemt device and a group iii-nitride structure fabricated therefrom. One example embodiment is a method for fabricating an enhancement mode group iii-nitride hemt device. ... Imec

06/22/17 / #20170178971

Method for manufacturing a si-based high-mobility cmos device with stacked channel layers, and resulting devices

A device and method for manufacturing a si-based high-mobility cmos device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a iii-v semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with iii-v semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the iii-v semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth.. ... Imec

06/22/17 / #20170178910

Method for differential heating of elongate nano-scaled structures

The present disclosure is related to a method of fabricating a semiconductor device involving the production of at least two non-parallel nano-scaled structures on a substrate. These structures are heated to different temperatures by exposing them simultaneously to polarized light having a wavelength and polarization such that a difference in absorption of light occurs in the first and second nanostructure. ... Imec

06/22/17 / #20170178712

Pinch-off ferroelectric memory

The disclosed technology relates generally to non-volatile memory devices, and more particularly to ferroelectric non-volatile memory devices. In one aspect, a non-volatile memory cell includes a pinch-off ferroelectric memory fet and at least one select device electrically connected in series to the pinch-off ferroelectric memory fet.. ... Imec

06/22/17 / #20170178698

Memory cell

The present disclosure relates to a memory cell, a memory array, and methods for writing a memory cell. In an example embodiment, a memory cell comprises a first transistor, a second transistor, and a differential sense amplifier. ... Imec

06/22/17 / #20170177092

System for hand gesture detection

A system for hand gesture detection is provided, comprising: a wrist wear adapted to be worn about a wrist of a user of the system and including a set of skin electrodes adapted to face the wrist; an impedance measurement circuit adapted to measure at least a first impedance in a first portion of the wrist and a second impedance in a second portion of the wrist which second portion is circumferentially displaced in relation to said first portion, wherein the first impedance is measured via a first electrode group including four skin electrodes of said set of skin electrodes and the second impedance is measured via a second electrode group including four skin electrodes of said set of skin electrodes, and a processing circuit adapted to detect a hand gesture of the user based on the first and the second impedance measured by the impedance measurement circuit.. . ... Imec

06/22/17 / #20170173325

Method and stimulation system for stimulating a human leg

A method for stimulating a human leg, a stimulation system, and a garment including the stimulation system are disclosed. The method comprises: measuring, by a measuring unit, an electrical characteristic indicative of a physiological condition in a portion of the leg via a subset of skin electrodes comprised in a plurality of skin electrodes integrated in a leg part of a garment arranged to be worn about at least a part of the human leg; determining, by evaluating the measured electrical characteristic, if the portion of the leg is to be stimulated; and if it is determined that the portion is to be stimulated, applying a stimulation via a subset of stimulation units, comprised in a plurality of stimulation units being arranged in the leg part of the garment, such that the portion of the leg is stimulated. ... Imec

06/22/17 / #20170172511

System and method for acquisition of biosignals with motion sensor-based artifact compensation

The disclosure relates to systems and methods for acquisition of biosignals with motion sensor-based artifact compensation. One example embodiment is a system for acquisition of biosignals from a subject. ... Imec

06/22/17 / #20170172447

Sensor, system, and holder arrangement for biosignal activity measurement

The disclosure relates to a sensor, a system, and a holder arrangement for biosignal activity measurement. One example embodiment includes a sensor module for brain activity measurement. ... Imec

06/22/17 / #20170172425

Method for detecting at least one of a heart rate and a respiratory rate of a subject

A method for detecting at least one of a heart rate and a respiratory rate of a subject is disclosed. In one aspect, the method includes transmitting a radio frequency signal towards the subject and receiving a reflected signal from the subject, the reflected signal being doppler-shifted due to at least one of the heart rate and the respiratory rate. ... Imec

06/15/17 / #20170170815

Apparatus and method for monitoring performance of integrated circuit

The present disclosure discloses an apparatus and method for monitoring performance of an integrated circuit. The apparatus includes a delay line, which receives a pulse signal. ... Imec

06/15/17 / #20170170390

Magnetic memory device having buffer layer

The disclosed technology generally relates to magnetic memory devices, and more particularly to spin transfer torque magnetic random access memory (stt-mram) devices having a magnetic tunnel junction (mtj), and further relates to methods of fabricating the stt-mram devices. In an aspect, a magnetoresistive random access memory (mram) device has a magnetic tunnel junction (mtj). ... Imec

06/15/17 / #20170170314

Drain extension region for tunnel fet

A tunnel field-effect transistor comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region doped with a dopant element having a first dopant type and a first doping concentration; a drain region doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region situated between the source region and the drain region and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel region and extending at the source side up to at least an interface between the source region and the channel region, a drain extension region in the channel region or on top thereof, the drain extension region being formed from a material suitable for creating, and having a length/thickness ratio such that, in use, it creates a charged layer, in the off-state of the tfet, with a charge opposite to the charge of the majority carriers in the drain region.. . ... Imec

06/15/17 / #20170170313

Method of producing a pre-patterned structure for growing vertical nanostructures

A method of producing a pre-patterned structure comprising at least one cavity for growing a vertical nanostructure is disclosed. The method includes providing at least one protruding structure that extends upwardly from a main surface of a substrate. ... Imec

06/15/17 / #20170170289

Transistor device with reduced hot carrier injection effect

The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices such as metal-oxide-semiconductor (mos) transistor devices. In one aspect, a transistor device comprises a channel region in a substrate partially delimited by a source and a drain junction at a main surface of the substrate. ... Imec

06/15/17 / #20170167992

Method for inspecting a pattern of features on a semiconductor die

The present disclosure is related to a method for detection of defects in a printed pattern of geometrical features on a semiconductor die, the pattern comprising an array of features having a nominal pitch, the method comprising determining deviations from the nominal pitch in the printed pattern, and comparing the printed pattern with another version of the pattern, the other version having the same or similar pitch deviations as the printed pattern. According to various embodiments, the other version of the pattern may a printed pattern on a second die, or it may be a reference pattern, obtained by shifting features of the array in a version having no or minimal pitch deviations, so that the pitch deviations in the reference pattern are the same or similar to the pitch deviations in the printed pattern under inspection.. ... Imec

06/15/17 / #20170167921

Spectral detector and image sensor including the same

A spectral detector includes a plurality of spectral detection units, each of the spectral detection units including an optical signal processor configured to deliver an optical signal incident to the spectral detection unit to an outside of the spectral detection unit, and a resonator configured to modulate a spectrum of an optical signal incident to the optical signal processor by interacting with the optical signal processor, at least some of the resonators of the plurality of spectral detection units having different lengths from each other, and a number of optical signal processors included in each respective spectral detection unit varying according to a length of the resonator included in the respective spectral detection unit.. . ... Imec

06/08/17 / #20170162686

Field-effect transistor comprising germanium and manufacturing method thereof

The disclosed technology generally relates to semiconductor devices, and more particularly to transistors comprising germanium (ge) in the channel, and to methods of manufacturing thereof. In one aspect, a field-effect transistor (fet) comprises an active region comprising germanium (ge) and a gate stack formed on the active region. ... Imec

06/01/17 / #20170153143

Bragg grating, and spectroscopy device including the bragg grating

Provided are a bragg grating and a spectroscopy device including the same. The bragg grating is disposed at each of opposite ends of a resonator for reflecting light of a certain wavelength band and includes a core member extending from a waveguide of the resonator in a lengthwise direction of the waveguide; a plurality of first refractive members protruding from the core member and spaced apart from each other along the lengthwise direction; and a second refractive member filling spaces between the first refractive members and having a refractive index different from a refractive index of the first refractive members.. ... Imec

05/18/17 / #20170141199

Method for forming a field effect transistor device having an electrical contact

A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. ... Imec

05/04/17 / #20170121814

Apparatus and method for delivering a gaseous precursor to a reaction chamber

The disclosure relates to an apparatus and method for delivering a precursor to a reaction chamber. One example embodiment is an apparatus for delivering a precursor to a reaction chamber. ... Imec

04/27/17 / #20170115201

Method and device for drug screening

The present disclosure relates to devices and methods configured to perform drug screening on cells. At least one embodiment relates to a lens-free device for performing drug screening on cells. ... Imec

04/20/17 / #20170107683

Loader work machine

A loader work machine has a base frame including a cabin; a loader work apparatus attached to the base frame; and two traveling apparatuses supporting the base frame, and including: a track frame connected to the base frame; a drive wheel driving a traveling belt; front and rear idlers arranged in a front-back direction below the drive wheel and supported by the track frame; and one or more track rollers arranged between the front and rear idlers and supported by the track frame, the traveling belt stretched around the drive wheel, idlers, and track rollers. The base frame includes: a lower frame connected to two track frames and interposed between the traveling apparatuses; an upper frame provided with the loader work apparatus; and a slewing apparatus connecting the upper and lower frames. ... Imec

04/13/17 / #20170103889

Method for producing a pillar structure in a semiconductor layer

A method for producing a pillar structure in a semiconductor layer, the method including providing a structure including, on a main surface, a semiconductor layer. A patterned hard mask layer stack is provided on the semiconductor layer that includes a first layer in contact with the semiconductor layer and a second layer overlying and in contact with the first layer. ... Imec

04/13/17 / #20170100064

Device and method for non-invasive measuring of analytes

The present disclosure relates to devices and methods for non-invasive measuring of analytes. At least one embodiment relates to a wearable system for non-invasive measuring of a concentration of an analyte in skin tissue. ... Imec

03/30/17 / #20170091094

Low-layer memory for a computing platform

The present disclosure relates to low-layer memory for a computing platform. An example embodiment includes a memory hierarchy being directly connectable to a processor. ... Imec

03/23/17 / #20170083469

Inter-cluster data communication network for a dynamic shared communication platform

The disclosure relates to a data communication network connecting a plurality of computation clusters. The data communication network is arranged for receiving via n data input ports, n>1, input signals from first clusters of the plurality and for outputting output signals to second clusters of the plurality via m data output ports, m>1. ... Imec

03/23/17 / #20170082544

Semiconductor device for detecting fluorescent particles

The present disclosure relates to semiconductor devices for detecting fluorescent particles. At least one embodiment relates to an integrated semiconductor device for detecting fluorescent tags. ... Imec

03/23/17 / #20170082421

Integrated spectrometers with single pixel detector

An integrated waveguide based spectrometer is described. The spectrometer comprises a sensing region for receiving multi-wavelength radiation for irradiating a sample in the sensing region, a wavelength demultiplexing element arranged for capturing said multi-wavelength radiation after interaction with the sample and for providing a number of wavelength demultiplexed radiation outputs or a number of different groups of wavelength demultiplexed radiation outputs, an integrated modulator for differently modulating the different demultiplexed radiation outputs or different groups of demultiplexed radiation outputs, and a multiplexer element for multiplexing the differently modulated demultiplexed radiation outputs or the differently grouped demultiplexed radiation outputs.. ... Imec

03/16/17 / #20170077869

Reconfigurable photovoltaic module

The present disclosure relates to reconfigurable voltaic modules. One example embodiment includes a photovoltaic module. ... Imec

03/16/17 / #20170076936

Method and apparatus for cleaning a semiconductor substrate

Disclosed are systems and methods for cleaning semiconductor substrates, wherein a nucleation structure having nucleation sites is mounted facing a surface of the substrate to be cleaned. The substrate and structure are brought into contact with a cleaning liquid, which is subsequently subjected to acoustic waves of a given frequency. ... Imec

03/16/17 / #20170071552

Bio-impedance spectroscopy system and method for bio-impedance measurement

The present disclosure is directed to an impedance spectroscopy system for bio-impedance measurement. The impedance spectroscopy system includes a signal generator configured to generate a signal with a broadband frequency spectrum and to generate an analog injection current from the signal with the broadband frequency spectrum. ... Imec

03/16/17 / #20170071510

Implantable sensor

A sensor for sensing a substance such as for example glucose. The sensor is implantable in the body of a living creature. ... Imec

03/09/17 / #20170069770

Texturing monocrystalline silicon substrates

A method for preparing a monocrystalline silicon substrate surface for a subsequent texturing step, the method comprising: removing contaminants from the surface by contacting the surface with a cleaning solution; etching the pre-cleaned surface with an aqueous solution comprising from 12 to 19% by weight, of koh and/or naoh; rinsing the etched surface with an aqueous medium at ph from 7 to 10; and contacting the rinsed etched surface with ozonated deionized water at ph from 2 to 4.5, thereby converting the rinsed etched surface into a prepared surface. A method for texturing the prepared surface is also provided.. ... Imec

03/09/17 / #20170069486

Directed self-assembly using trench assisted chemoepitaxy

The present disclosure relates to directed self-assembly using trench assisted chemoepitaxy. An example embodiment includes a method of forming a pre-patterned structure for directing a self-assembly of a self-assembling material that includes a first and a second component having different chemical natures. ... Imec

03/02/17 / #20170062431

Method of forming a junction field effect transistor

The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (jfet). In one aspect, a method of fabricating a jfet includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type. ... Imec

03/02/17 / #20170062421

Buried interconnect for semiconductor circuits

A semiconductor circuit comprises a front end of line (feol) comprising a plurality of transistors, each of which having a source region, a drain region and a gate region arranged between the source region and the drain region and comprising a gate electrode. The semiconductor circuit also comprises a buried interconnect that is arranged in the feol and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. ... Imec

03/02/17 / #20170059791

Method for coupling an optical fiber to an optical or optoelectronic component

A method for optically and mechanically coupling an optical fiber to an optical or optoelectronic component on a substrate is provided. The method comprises: providing an optical fiber comprising a core and a cladding, the core being exposed at an end face of the optical fiber; forming a polymer waveguide core on the end face, the polymer waveguide core extending from the fiber core; bringing the polymer waveguide core in proximity of the optical or optoelectronic component; providing a liquid optical material, the liquid optical material embedding the polymer waveguide core; and curing the liquid optical material, thereby forming a polymer cladding layer encapsulating the polymer waveguide core and mechanically attaching the optical fiber to the optical or optoelectronic component.. ... Imec

03/02/17 / #20170055903

Electrode holding arrangement and manufacturing method thereof

The present disclosure describes methods and devices relating to electrode holding arrangements for bioelectric use. An example electrode holding arrangement includes a piece of flexible material configured to be fixed to a body part and at least one electrode spring element. ... Imec

02/23/17 / #20170054021

Al-poor barrier for ingaas semiconductor structure

The present disclosure relates to a semiconductor structure and a method of preparation including a silicon monocrystalline substrate, and a iii-v structure abutting the silicon monocrystalline substrate. The semiconductor structure includes an inagabas structure overlaying the iii-v structure, where a is from 0.40 to 1, b from 0 to 0.60, and a+b equal to 1.00. ... Imec

02/09/17 / #20170040331

Ferroelectric memory device and fabrication method thereof

The disclosed technology generally relates to semiconductor devices, and more particularly to a non-volatile ferroelectric memory device and to methods of fabricating the same. In one aspect, a non-volatile memory device includes a high dielectric constant layer (high-k) layer or a metal layer on a semiconductor substrate. ... Imec

02/09/17 / #20170040321

Gate-all-around nanowire device and method for manufacturing such a device

The disclosed technology generally relates to a semiconductor device, and more particularly to a gate all around (gaa) semiconductor device and a method for fabricating the same. In one aspect, a semiconductor device has a vertical stack of nanowires formed on a substrate, wherein the vertical stack of nanowires comprises an n-type nanowire and a p-type nanowire each extending in a longitudinal direction parallel to a main surface of the substrate. ... Imec

02/09/17 / #20170040168

Methods and mask structures for substantially defect-free epitaxial growth

Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, mask structure includes a first level defining a first trench extending through the first level, wherein a bottom of the first trench is defined by a semiconductor substrate, and a second level on top of the first level, wherein the second level defines a plurality of second trenches positioned at a non-zero angle with respect to the first trench.. ... Imec

02/02/17 / #20170033183

Strained group iv channels

Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. ... Imec

02/02/17 / #20170031318

Apparatus and method for performing in-line lens-free digital holography of an object

The present disclosure relates to apparatuses and methods for performing in-line lens-free digital holography of objects. At least one embodiment relates to an apparatus for performing in-line lens-free digital holography of an object. ... Imec

01/26/17 / #20170025314

Semiconductor devices comprising multiple channels and method of making same

The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices comprising multiple channels. In one aspect, a method of fabricating a transistor device comprises forming on the substrate a plurality of vertically repeating layer stacks each comprising a first layer, a second layer and a third layer stacked in a predetermined order, wherein each of the first, second and third layers is formed of silicon, silicon germanium or germanium and has a different germanium concentration compared to the other two of the first, second and third layers. ... Imec

01/19/17 / #20170019115

All digital phase locked loop

An all-digital phase-locked loop (ad-pll) and related methods and computer readable medium are provided. The ad-pll comprises a reference phase generator for receiving a digital signal and splitting the digital signal into an integer part and a fractional part, an estimator block for estimating a control signal, and a digital-to-time converter for receiving the estimated control signal and a reference clock signal and for deriving a delayed reference clock signal. ... Imec

01/12/17 / #20170011956

Method for producing an integrated circuit device with enhanced mechanical properties

Devices and methods for producing an integrated circuit device, comprising a front-end-of-line (feol) portion and a back-end-of-line (beol) portion, are disclosed. The metallization layers comprise dielectric layers, preferably low-k dielectric layers, with metal conductors and/or interconnect structures incorporated within the dielectric layers. ... Imec

01/12/17 / #20170010231

Gas sensor with frequency measurement of impedance

The present disclosure relates to methods and devices for gas sensing. A gas sensor includes a sensing element comprising at least an ionic liquid. ... Imec

01/05/17 / #20170005654

Switching circuit

A conversion circuit is disclosed. In one aspect, the conversion circuit includes a first input terminal for receiving a digital signal. ... Imec

01/05/17 / #20170005132

Integrated circuit and method for manufacturing integrated circuit

An integrated circuit for an imaging device including an array of photo-sensitive areas is disclosed. In one aspect the integrated circuit includes a first multi-layer structure and a second multi-layer structure arranged over a first and a second photo-sensitive area, respectively. ... Imec

01/05/17 / #20170005018

Method and device for inspection of a semiconductor device

A method for inspection of a semiconductor device is disclosed. In one aspect, the method includes performing a processing step in manufacturing of the semiconductor device, wherein a compound is at least in contact with the semiconductor device. ... Imec

01/05/17 / #20170005000

Method for bonding and interconnecting integrated circuit devices

A method for bonding and interconnecting two or more ic devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple ic devices are provided with metal contact structures. ... Imec

01/05/17 / #20170003454

Adiabatic coupler

A system for selectively adiabatically coupling electromagnetic waves from one waveguide to another waveguide is described. It comprises a first waveguide portion and a second waveguide portion having substantially different surface normal cross-sections. ... Imec

01/05/17 / #20170003227

Integrated waveguide structure for fluorescence analysis

The present disclosure relates to structures, systems, and methods for characterizing one or more fluorescent particles. At least one embodiment relates to an integrated waveguide structure. ... Imec








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