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Inotera Memories Inc patents

Recent patent applications related to Inotera Memories Inc. Inotera Memories Inc is listed as an Agent/Assignee. Note: Inotera Memories Inc may have other listings under different names/spellings. We're not affiliated with Inotera Memories Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "I" | Inotera Memories Inc-related inventors




Date Inotera Memories Inc patents (updated weekly) - BOOKMARK this page
06/01/17Fault isolation detecting faults in a circuit
05/18/17Semiconductor structure and fabricating method thereof
04/27/17Semiconductor package and forming the same
04/20/17Wafer level package with tsv-less interposer
03/09/17Memory device and fabricating method thereof
03/02/17Method for manufacturing a wafer level package
02/02/17Electrostatic chuck and temperature-control the same
02/02/17Multi-device package and manufacturing method thereof
02/02/17Memory device and fabricating method thereof
01/12/17Recoverable device for memory base product
12/29/16Wafer level package and fabrication method thereof
12/22/16Wafer level package and fabrication method thereof
12/22/16Semiconductor device and manufacturing method thereof
12/15/16Package-on-package assembly and manufacturing the same
12/08/16Package structure and manufacturing method thereof
12/08/16Wafer level package and fabrication method thereof
12/08/16Connector structure and manufacturing method thereof
12/08/16Multi-device package and manufacturing method thereof
12/01/16Fan-out wafer level package and fabrication method thereof
11/24/16Memory device
11/17/16Recess array device with reduced contact resistance
09/29/16Probe unit for test tools and manufacturing the same
09/29/16Semiconductor device having buried wordlines
05/12/16Method of fabricating source/drain region and semiconductor structure having source/drain region fabricated by the same
04/14/16Transistor structure and manufacturing the same
03/31/16Non-floating vertical transistor structure
03/24/16Sample stack structure and preparing the same
12/03/15Semiconductor device and manufacturing the same
12/03/15Cylinder-shaped storage node with single-layer supporting structure
12/03/15Semiconductor device and fabrication method therefor
12/03/15Vertical transistor and method to form vertical transistor contact node
10/15/15Semiconductor device
09/24/15Method for increasing pattern density
09/24/15Patterned structure of semiconductor device and fabricating the same
08/27/15Semiconductor device capable of suppressing warping
07/30/15Dynamic random access memory unit and fabrication method thereof
07/30/15Manufacturing capacitor lower electrode and semiconductor storage device using the same
07/23/15Manufacturing capacitor structure and semiconductor device using the same
07/16/15Carrier arrangement system and arranging carriers
06/18/15Method for manufacturing high-strength structural stacked caacitor
06/18/15Method for forming self-aligned isolation trenches in semiconductor substrate and semiconductor device
04/16/15Overhead hoist transport system
04/02/15Lifting device and automatic handling system thereof
03/19/15Semiconductor device having through-silicon via
03/19/15Memory device and manufacturing the same
10/23/14Memory cell having a recessed gate and manufacturing method thereof
10/23/14Stacked capacitor structure and a fabricating fabricating the same
10/16/14Method of testing semiconductor device and semiconductor testing system
10/16/14Method for fabricating a semiconductor memory
10/02/14Semiconductor device and manufacturing method therefor
09/18/14Wafer and film coating using the same
09/11/14Stack capacitor structure and manufacturing method thereof
08/07/14Method of manufacturing isolation structure
05/08/14Semiconductor layout structure
05/01/14Semiconductor structure
04/24/14Random access memory device and manufacturing nodes thereof
04/24/14Overhead buffer device and wafer transport system
03/27/14Capacitor structure
09/26/13Manufacturing high capacitance capacitor structure
09/12/13Shallow trench isolation in dynamic random access memory and manufacturing method thereof
08/22/13Spin-on dielectric method with multi-stage ramping temperature
08/08/13Manufacturing random access memory
08/08/13Manufacturing memory capacitor without moat structure
07/04/13High-k metal gate random access memory
07/04/13Method of forming isolation area and structure thereof
Patent Packs
07/04/13Capacitor having multi-layered electrodes
07/04/13Memory capacitor having a robust moat and manufacturing method thereof
05/30/13Method for operating an automatic handling system applied to many wafer processing apparatuses
03/21/13Method of planar imaging on semiconductor chips using focused ion beam
03/21/13Door detection system
03/14/13Overhead hoist transport system
03/14/13Spin transfer torque random access memory
03/07/13Method for adjusting trench depth of substrate
01/31/13Nand type flash memory for increasing data read/write reliability
01/31/13Nand type flash memory for increasing data read/write reliability
01/31/13Manufacturing memory structure
12/27/12Bidirectional wafer carrying pod and wafer transfer system
12/27/12Fault detection semiconductor manufacturing processes and system architecture thereof
12/27/12Method and system of compressing raw fabrication data for fault determination
12/13/12Dram cell having buried bit line and manufacturing method thereof
Patent Packs
11/08/12Automatic handling system applied to many wafer processing devices
10/25/12Method of making an array columnar hollow semiconductor structure
10/04/12Specimen grid holder and focused ion beam system or dual beam system having the same
08/02/12Semiconductor structure and fault location detecting system
08/02/12Vertical transistor for random-access memory and manufacturing method thereof
05/10/12Transport system having multilayer tracks and controlling method thereof
05/03/12Memory device and fabrication thereof
04/26/12Rotary transport system and controlling method thereof
04/26/12Specification establishing controlling semiconductor process
02/09/12Developer spraying device for reducing usage quantity of developer
01/19/12Semiconductor device and manufacturing method thereof
01/05/12Method for automatically shifting a base line
12/29/11Manufacturing fin-fet having floating body
10/27/11Cell with surrounding word line structures and manufacturing method thereof
10/20/11Method for detecting variance in semiconductor processes
06/30/11Integrated alignment and overlay mark, and detecting errors of exposed positions thereof
06/23/11Method of searching for key semiconductor operation with randomization for wafer position
06/16/11Method of cleaning showerhead
06/09/11Vertical pmos field effect transistor and manufacturing method thereof
06/02/11Device for preventing current-leakage
05/12/11Low parasitic capacitance bit line process for stack dram
05/12/11Method for predicting and warning of wafer acceptance test value
05/05/11Vertical transistor and manufacturing method thereof
04/21/11Method for manufacturing capacitor lower electrodes of semiconductor memory
04/21/11Fault detection and classification wafer acceptance test parameters
04/14/11Management system and management system for judging correctness of substance in a bottle
04/14/11Single-side implanting process for capacitors of stack dram
04/07/11Multi-track handling and storage apparatus and method thereof
04/07/11Process using oxide supporter for manufacturing a capacitor lower electrode of a micro stacked dram
03/31/11Method for manufacturing capacitor lower electrodes of semiconductor memory
Social Network Patent Pack
03/31/11System for temporarily supplying power and a method thereof
03/17/11Manufacturing double-side capacitor of stack dram
03/03/11Self-alignment recess channel dynamic random access memory
01/13/11Method for evaluating efficacy of prevention maintenance for a tool
10/28/10Wafer cleaning machine and cleaning method thereof
10/28/10Transistor structure with high reliability and manufacturing the same
10/07/10Method of adjusting wafer processing sequence
09/16/10Method for monitoring fabrication parameter
09/16/10Method for finding the correlation between the tool pm and the product yield
09/09/10In-line wafer measurement data compensation method
Patent Packs
09/02/10Monitoring multi tools
08/26/10Automatic product distribution system and a method thereof
08/12/10Method for planning a semiconductor manufacturing process based on users' demands
08/05/10Liquid supplying device and using the same
07/15/10Method of cleaning contact lenses via sonication
06/17/10Portable wafer inspection system
05/20/10Chemical treatment apparatus
05/13/10Memory device and fabrication method thereof
04/22/10Furnace temperature control thermal budget balance
04/15/10Method of searching for key semiconductor operation with randomization for wafer position
04/08/10Preparation an electron tomography sample with embedded markers and a reconstructing a three-dimensional image
04/08/10Automatic recovery and transport system and execution method therefor
04/01/10System for monitoring temperature and slope of a wafer and a method thereof
03/25/10Device for removing a stopper of a photoresist bottle
03/25/10Method for cleaning a high resolution scanning electron microscope sample with a low power ion beam
03/25/10Automatic transport system and control method thereof
03/25/10Automatic wafer storage system and a controlling the system
03/25/10Method for automatically shifting a base line
03/18/10Mini clean room for preventing wafer pollution and using method thereof
02/25/10Method for determining tool's production quality
02/25/10Method for projecting wafer product overlay error and wafer product critical dimension
02/04/10Gas-liquid separation system and method thereof
01/28/10Method for changing physical vapor deposition film form
01/28/10Wafer cassette transportation method and system thereof
01/28/10Cross-fab material control system and control method thereof
01/21/10Photoresist solution dispensing volume monitoring system and method thereof
01/21/10Observation wafer ion implantation defect
01/14/10Method for detecting variance in semiconductor processes
01/07/10Fault detection and classification wafer acceptance test parameters
12/31/09Method for predicting cycle time
Patent Packs
12/10/09Method for prognostic maintenance in semiconductor manufacturing equipments
11/05/09Machine fault detection method
11/05/09Assessment process improvement decisions
10/15/09Fuzzy control adjusting a semiconductor machine
10/08/09Method and system for detecting tool errors to stop a process recipe for a single chamber
10/01/09Memory device and fabrication thereof
08/20/09Fabrication memory device
08/06/09Holding apparatus
08/06/09System and monitoring manufacturing process
07/30/09Coolant recycling system
05/28/09Method for fabricating semiconductor device
05/14/09Circuit structure of integrated circuit







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Inotera Memories Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Inotera Memories Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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