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Intel Corporation patents


Recent patent applications related to Intel Corporation. Intel Corporation is listed as an Agent/Assignee. Note: Intel Corporation may have other listings under different names/spellings. We're not affiliated with Intel Corporation, we're just tracking patents.

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Gesture-controlled virtual reality systems and methods of controlling the same

Gesture-controlled virtual reality systems and methods of controlling the same are disclosed herein. An example apparatus includes at least two of an on-body sensor, an off-body sensor, and an RF local triangulation system to detect at least one of a position or a movement of a body part of a... Intel Corporation

Sensors-based automatic reconfiguration of multiple screens in wearable devices and flexible displays

Embodiments for providing a wearable device are generally described herein. A wearable device may include a processor having memory and communicatively coupled to a plurality of display areas; and an orientation sensing module communicatively coupled to the processor to determine at least one of an orientation and a location of... Intel Corporation

Multiplier pipelining optimization with a postponed estimation correction

One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has... Intel Corporation

Technologies for fast low-power startup of a computing device

Technologies for fast low-power startup include a computing device with a processor having a power management integrated circuit. The computing device initializes platform components into a low-power state and determines, in a pre-boot firmware environment, the battery state of the computing device. The computing device determines a minimum-power startup (MPS)... Intel Corporation

Latency and bandwidth efficiency improvement for read modify write when a read operation is requested to a partially modified write only cacheline

Methods and apparatus relating to techniques to improve/optimize latency and bandwidth efficiency for read modify write operations when a read operation is requested to a partially modified write only cacheline are described. In an embodiment, a first cache stores data from one or more cachelines of a second cache in... Intel Corporation

Computing apparatus and method with persistent memory

Apparatuses, methods and storage medium associated with computing that include usage and backup of persistent memory are disclosed herein. In embodiments, an apparatus for computing may comprise one or more processors and persistent memory to host operation of one or more virtual machines; and one or more page tables to... Intel Corporation

Self-learning statistical natural language processing for automatic production of virtual personal assistants

Technologies for natural language request processing include a computing device having a semantic compiler to generate a semantic model based on a corpus of sample requests. The semantic compiler may generate the semantic model by extracting contextual semantic features or processing ontologies. The computing device generates a semantic representation of... Intel Corporation

Mapping application functional blocks to multi-core processors

One embodiment provides a system to identify a “best” usage of a given set of CPU cores to maximize the performance of a given application. The application is parsed into a number of functional blocks, and the system maps the functional blocks to CPU cores to maximize application performance. The... Intel Corporation

Flexible counter system for memory protection

The present disclosure is directed to a flexible counter system for memory protection. In general, a counter system for supporting memory protection operations in a device may be made more efficient utilizing flexible counter structures. A device may comprise a processing module and a memory module. A flexible counter system... Intel Corporation

Hybrid compression scheme for efficient storage of synaptic weights in hardware neuromorphic cores

Systems, apparatuses and methods may provide a hybrid compression scheme to store synaptic weights in neuromorphic cores. The hybrid compression scheme utilizes a run-length encoding (RLE) compression approach, a dictionary-based encode compression scheme, and a compressionless encoding scheme to store the weights for valid synaptic connections in a synaptic weight... Intel Corporation

Pre-synaptic learning using delayed causal updates

A processor or integrated circuit includes a memory to store weight values for a plurality neuromorphic states and a circuitry coupled to the memory. The circuitry is to detect an incoming data signal for a pre-synaptic neuromorphic state and initiate a time window for the pre-synaptic neuromorphic state in response... Intel Corporation

Methods and apparatus to predict sports injuries

A disclosed example method to predict an injury for a target player on a target date includes determining a first probability of injury of the target player based on probabilities of injuries of second players having similarities with the target player; determining a second probability of injury of the target... Intel Corporation

Spiral near field communication (nfc) antenna coil

A Near Field Communications (NFC) antenna coil, having a first loop; and a second loop connected to the first loop to form a spiral shape, wherein the first loop and the second loop have different sizes to be mutually couplable with a first antenna pairing coil and a second antenna... Intel Corporation

Land side and die side cavities to reduce package z-height

A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed... Intel Corporation

Pillar resistor structures for integrated circuitry

Formation of a resistor pillar may be integrated with a replacement gate transistor process by concurrently forming the resistor pillar and sacrificial gate out of a same material, such as polysilicon. Pillar resistor contacts may also be concurrently formed with one or more transistor contacts.... Intel Corporation

Techniques for forming transistors on the same die with varied channel materials

Techniques are disclosed for forming transistors on the same substrate with varied channel materials. The techniques include forming a replacement material region in the substrate, such region used to form a plurality of fins therefrom, the fins used to form transistor channel regions. In an example case, the substrate may... Intel Corporation

Enhanced overlaid code division multiple access (cdma)

A base station can obtain channel quality conditions for mobile devices in a scheduling interval and identify a channel quality, a target transmission scheme, and a transmission power level for each of the mobile devices. The base station can assign a unique orthogonal CDMA code and can force the mobile... Intel Corporation

Hash table entries insertion method and apparatus using virtual buckets

The present disclosure describes a process and apparatus for improving insertions of entries into a hash table. A large number of smaller virtual buckets may be combined together and associated with buckets used for hash table entry lookups and/or entry insertion. On insertion of an entry, hash table entries associated... Intel Corporation

Call handling based on user profile identification

Technologies for handling a call based on user identification include determining a personal profile identification for a user of a communal mobile communication device and initiating a call to a personal communication device using a phone number of the personal communication device and the personal profile identification. The personal communication... Intel Corporation

Transmission of encrypted image data

In one example, a system for transmitting encrypted data includes a processor to select a virtual channel to be encrypted between an application processor and an image sensor during an initialization process. The processor can also transmit a virtual channel command corresponding to the selected virtual channel to the image... Intel Corporation

Technologies for selective content licensing and secure playback

Technologies for selectively licensing segments of source content are described. In some embodiments the technologies enable a user of a client device to select, license, and use one or more segments of source content, without the need to obtain a license to the source content as a whole. Systems, methods,... Intel Corporation

Emergency evacuation service

Various systems and methods for providing an emergency evacuation service are described herein. An apparatus to provide an emergency evacuation service comprises an emergency event detection module to detect the existence of an emergency event at a venue; a transceiver to request and receive evacuation instructions from an emergency evacuation... Intel Corporation

Method for efficient channel estimation and beamforming in fdd system by exploiting uplink-downlink correspondence

A method for selecting at least one parameter for downlink data transmission with a mobile user equipment. The method is executable by a wireless communication base station having multiple antennas configured to communicate wirelessly with the mobile user equipment. The method receives an uplink probing signal from the mobile user... Intel Corporation

Apparatus, system and dynamic allocation using a grant frame

Some demonstrative embodiments include apparatuses, devices, systems and methods of dynamically scheduling a transmit opportunity. For example, a first wireless station may be configured to generate a grant frame including a duration field and a dynamic allocation information field, the dynamic allocation information field including an allocation duration subfield, the... Intel Corporation

Multi-stage reduction of impact forces

Multi-stage reduction of impact forces are disclosed. An example apparatus to reduce impact energy of an aircraft during landing includes a rotatable landing leg having a proximal end near an axis of rotation and a distal end opposite the proximal end, a first flexible portion of the proximal end, where... Intel Corporation

Apparatus and method to reduce power losses in an integrated voltage regulator

Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to... Intel Corporation

Convertible computing device

An apparatus may include a first panel having a first user interface that includes a keyboard. The apparatus may also include a second panel coupled via a hinge to the first panel in a clamshell structure. The second panel may include a first display side to present information in a... Intel Corporation

Tap zones for near field coupling devices

Described herein are techniques related to near field coupling and more particularly using near field coupling related taps to indicate user selections on input/output devices. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.... Intel Corporation

Generating and displaying supplemental information and user interactions on interface tiles of a user interface

Technologies for displaying supplemental interface tiles on a user interface of a computing device include determining supplemental information and/or available user interactions associated with a user interface tile displayed on the user interface. A supplemental interface tile is displayed in association with the user interface tile in response to a... Intel Corporation

Deduplication-based data security

Providing data security includes: in response to a request to write data content to a storage, generating encrypted data content based on the data content; attempting to obtain a reference to the encrypted data content in the storage; in the event that the reference to the encrypted data content is... Intel Corporation

Power management and monitoring for storage devices

In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining... Intel Corporation

Auto-configurable host pluggable computing

Apparatuses, methods and storage medium associated with auto-configurable host pluggable computing, are disclosed herein. In embodiments, a user defined configuration parameters may be stored in a host system. When a pluggable computing device is connected to the host system; the pluggable computing device may read the configuration parameters from the... Intel Corporation

Latency by persisting data relationships in relation to corresponding data in persistent memory

A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a relationship between a group of addresses being stored in the PM according to a set of instructions when executed. The memory controller is further to retrieve the... Intel Corporation

Cryptographic pointer address encoding

A computing device includes technologies for securing indirect addresses (e.g., pointers) that are used by a processor to perform memory access (e.g., read/write/execute) operations. The computing device encodes the indirect address using metadata and a cryptographic algorithm. The metadata may be stored in an unused portion of the indirect address.... Intel Corporation

Secure direct memory access

Examples are disclosed for establishing a secure destination address range responsive to initiation of a direct memory access (DMA) operation. The examples also include allowing decrypted content obtained as encrypted content from a source memory to be placed at a destination memory based on whether destination memory addresses for the... Intel Corporation

04/12/18 / #20180101624

Methods for reducing delay on integrated circuits

Configuration data for an integrated circuit may be generated using logic design equipment to implement an circuit design on the integrated circuit. Implementing the circuit design may include placing functional blocks at optimal locations that increase the maximum operating frequency of the integrated circuit implementing the optimal circuit design. Logic... Intel Corporation

04/12/18 / #20180101680

Cluster anomaly detection using function interposition

Systems and methods may provide for identifying a runtime behavioral pattern of an application and detecting an anomaly in the runtime behavioral pattern. In addition, a security event may be triggered in response to the anomaly. In one example, the anomaly is detected with regard to one or more of... Intel Corporation

04/12/18 / #20180101688

Trust-enhanced attribute-based encryption

Embodiments are directed to protecting, and recovering protected information, with attribute-based encryption. a predefined attribute policy defines one or more combinations of recipient attributes that entitle the recipient entity to attain access to the protected information. A set of at least one trust criterion is derived from the predefined attribute... Intel Corporation

04/12/18 / #20180102149

Double-polarity memory read

Circuits, systems, and methods for double-polarity reading of double-polarity stored data information are described. In one embodiment, a method involves applying a first voltage with a first polarity to a plurality of the memory cells. The method involves applying a second voltage with a second polarity to one or more... Intel Corporation

04/12/18 / #20180102162

Reconfigurable clocking architecture

Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to... Intel Corporation

04/12/18 / #20180102282

Means to decouple the diffusion and solubility switch mechanisms of photoresists

Embodiments of the invention include photoresist materials and methods of patterning photoresist materials. In an embodiment a photoresist material comprises a plurality of molecular glasses (MGs). In an embodiment, a glass transition temperature Tg of the photoresist material is less than an activation temperature needed to deblock blocking groups from... Intel Corporation

04/12/18 / #20180103034

User profile selection using contextual authentication

In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that are associated with user profile selection using contextual authentication. In various embodiments, a first user of a computing device may be authenticated and have an access control state corresponding to a first user profile established, the computing... Intel Corporation

04/12/18 / #20180103099

Cloud data storage location monitoring

Technologies for monitoring data storage location for cloud data include a cloud monitoring server configured to communicate with one or more cloud customer computing devices and cloud service providers. The cloud monitoring server receives monitoring requests from the cloud customer computing devices and retrieves provider information from the cloud service... Intel Corporation

04/12/18 / #20180103129

Packet flow classification

Technologies for packet flow classification on a computing device include a hash table including a plurality of hash table buckets in which each hash table bucket maps a plurality of keys to corresponding traffic flows. The computing device performs packet flow classification on received data packets, where the packet flow... Intel Corporation

04/12/18 / #20180103230

Method and system of adjusting video quality based on viewer distance to a display

A system, article, and method of adjusting video quality based on viewer distance to a display... Intel Corporation

04/12/18 / #20180103300

Transcoder enabled cloud of remotely controlled devices

Various embodiments are directed to one or more transcoder devices in communication with an input device such as a remote control device and multiple destination devices in which the transcoder device(s) facilitate communication between the remote control and the various destination devices in the vicinity. The transcoder device(s) can also... Intel Corporation

04/12/18 / #20180103362

Dynamically associated neighbor awareness networking (nan) discovery windows for fine timing measurement

Certain embodiments herein relate to a dynamic pre-association between Neighbor Awareness Networking (NAN) discovery windows and fine timing measurement (FTM) communications. A wireless station may trigger An FTM procedure during a NAN discovery window by the transmission of a NAN Service Discovery Frame (SDF). In addition to the FTM communications,... Intel Corporation

04/12/18 / #20180103396

Apparatus, method and system of communicating a wide-bandwidth data frame

Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating a wide-bandwidth data frame. For example, an apparatus may include a controller to generate at least one wide-bandwidth data frame to be transmitted over a wide-bandwidth millimeter-Wave (mmWave) channel, the wide-bandwidth mmWave channel including a plurality of mmWave channels;... Intel Corporation

04/12/18 / #20180103543

Flexible printed circuit boards and related methods

Flexible printed circuit boards and related methods are disclosed herein. An example printed circuit board includes a controller interface coupled to a surface of the printed circuit board between a first end of the printed circuit board and a second end of the printed circuit board. The example printed circuit... Intel Corporation

04/05/18 / #20180092607

Monitoring, analysis, and feedback of anatomical pressure measurements

Techniques are provided for monitoring, analysis, and feedback of pressure measurements associated with anatomical regions of a subject user. A methodology implementing the techniques according to an embodiment includes receiving pressure measurement samples from a user-wearable device. The samples are associated with anatomical stress locations of the user, such as,... Intel Corporation

04/05/18 / #20180094945

Navigation systems and associated methods

Navigation systems and associated methods for providing navigation services are provided. Information associated with a desired route for a vehicle, such as a route between a current location and a desired destination, may be determined. Additionally, contextual information associated with the vehicle may be identified. Based upon the desired route... Intel Corporation

04/05/18 / #20180095127

Systems, methods, and apparatuses for implementing testing of fault repairs to a through silicon via (tsv) in two-level memory (2lm) stacked die subsystems

Stacked semiconductor packages and methods for performing bare die testing on a functional silicon die in a stacked semiconductor package are described. In an example, a stacked semiconductor package includes a functional silicon die, a test controller having signature accumulation logic embedded therein, and a fabric to route transactions between... Intel Corporation

04/05/18 / #20180095160

Method and device for radar signal detection

This disclosure relates to a method for radar signal detection, the method comprising: scanning a radio channel by a scanning filter in a first frequency subband to provide an incoming signal; detecting a potential radar signal in the incoming signal based on prior knowledge of a structure of the radar... Intel Corporation

04/05/18 / #20180095178

Methods and devices for compensating misadjustment of a gnss device

This disclosure relates to a control device for compensating misadjustment of a tunable code loop filter of a portable global navigation satellite system (GNSS) device due to movement of the GNSS device, the control device comprising: a waveform estimator configured to estimate a signal-to-noise ratio (SNR) waveform based on an... Intel Corporation

04/05/18 / #20180095278

Techniques for image projection

Various embodiments are generally directed to techniques for image projection, such as in a computer-mediated reality system, for instance. Some embodiments are particularly directed to a computer-mediated reality system that is able to create an eyebox array for viewing images or sequences of images (e.g. video), the eyebox array created... Intel Corporation

04/05/18 / #20180095468

Methods and apparatus to wirelessly power an unmanned aerial vehicle

Methods, apparatus, systems and articles of manufacture to wirelessly power an unmanned aerial vehicle are disclosed. An example unmanned aerial vehicle (UAV) includes a first electrode assembly to capacitively couple to a first power cable. The example UAV includes a second electrode assembly to capacitively couple to a second power... Intel Corporation

04/05/18 / #20180095500

Tap-to-dock

A novel docking process introduces a new handshake scheme between a first device (referred to herein as the “Dockee”) and a docking device (referred to simply as the “Dock”) to communicate a user's intention to connect the Dockee and the Dock (i.e., dock the Dockee to the Dock). The handshake... Intel Corporation

04/05/18 / #20180095503

Compartment for magnet placement

An apparatus is provided which comprises: a chassis compartment having a bottom surface and walls orthogonal to the bottom, wherein the chassis compartment comprises: a rectangular opening, which may be designed to accept a microelectromechanical (MEMS) device and four slots, which may be designed to accept one or more magnet(s),... Intel Corporation

04/05/18 / #20180095509

Enhanced power management for support of priority system events

Embodiments are generally directed to enhanced power management for support of priority system events. An embodiment of a system includes a processing element; a memory including a registry for information regarding one or more system events that are designated as priority events; a mechanism to track operation of events that... Intel Corporation

04/05/18 / #20180095514

Compensation control for variable power rails

In an embodiment, a processor includes a first power rail, a first component coupled to the first power rail, and a compensation control unit. The compensation control unit is to: detect a request to change a voltage level of the first power rail by a first voltage change amount; in... Intel Corporation

04/05/18 / #20180095524

Interaction mode selection based on detected distance between user and machine interface

An embodiment of an interaction mode selection apparatus may include a distance estimator to estimate a distance between a user and a part of a machine interface, and an interaction selector communicatively coupled to the distance estimator to select one or more active interaction modes from two or more available... Intel Corporation

04/05/18 / #20180095525

Gesture experiences in multi-user environments

Systems, apparatuses and methods may leverage technology that recognizes a set of one or more hands in one more frames of a video signal during a first gesture control interaction between the set of one or more hands and an electronic device. Moreover, one or more additional body parts may... Intel Corporation

04/05/18 / #20180095550

Position determining techniques for virtual reality systems

Technology for determining a position of a device based on an acceleration of the device sensed by an accelerometer, an angular velocity sensed by a gyroscope, and a distance of the device from a fixed magnetic field source determined from a magnetic field strength sensed by a magnetometer.... Intel Corporation

04/05/18 / #20180095674

Selective data compression/decompression for intermemory transfer interface

In one embodiment, an inter-memory transfer interface having selective data compression/decompression in accordance with the present description, selects from multiple candidate processes, a compression/decompression process to compress a region of data from a near memory before transmitting the compressed data to the far memory. In another aspect, the inter-memory transfer... Intel Corporation

Patent Packs
04/05/18 / #20180095681

Utilization of non-volatile random access memory for information storage in response to error conditions

Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to utilize non-volatile random access memory for information storage in response to error conditions are disclosed. Example methods disclosed herein include accessing, with a power control unit associated with a processor, first information describing available capacities of respective reserved... Intel Corporation

04/05/18 / #20180095689

Method and avoiding bus contention after initialization failure

In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory device comprising a plurality of NAND flash memory units. The storage device is to determine that the NAND flash memory device did not pass an initialization procedure; identify a first addressing scheme that is implemented by... Intel Corporation

04/05/18 / #20180095692

Selective memory mode authorization enforcement

In one embodiment, a memory interface employs selective memory mode authorization enforcement in accordance with the present description to ensure that memory modes of operation which have not been authorized, are not permitted to proceed. In one embodiment, mode control logic receives from memory control logic of the memory interface,... Intel Corporation

04/05/18 / #20180095720

Storage device with fine grained search capability

A storage device is described. The storage device includes non volatile memory having data storage resources organized into slots to store chunks of data. The storage device includes memory to store a data pointer table having groups of pointers to the slots. Each of the groups correspond to a respective... Intel Corporation

04/05/18 / #20180095728

Low energy consumption mantissa multiplication for floating point multiply-add operations

A floating point multiply-add unit having inputs coupled to receive a floating point multiplier data element, a floating point multiplicand data element, and a floating point addend data element. The multiply-add unit including a mantissa multiplier to multiply a mantissa of the multiplier data element and a mantissa of the... Intel Corporation

04/05/18 / #20180095740

Initializing a system on a chip

In one example, a system on a chip can include an embedded controller and a security controller that can detect, during an initialization process, a request for embedded controller firmware stored in block storage from the embedded controller via a transmission link. The security controller can also retrieve the embedded... Intel Corporation

04/05/18 / #20180095750

Hardware accelerators and methods for offload operations

Methods and apparatuses relating to offload operations are described. In one embodiment, a hardware processor includes a core to execute a thread and offload an operation; and a first and second hardware accelerator to execute the operation, wherein the first and second hardware accelerator are coupled to shared buffers to... Intel Corporation

04/05/18 / #20180095756

Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers

A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate a packed data register of the plurality of packed data registers that is to store a source packed memory address information. The source packed memory... Intel Corporation

04/05/18 / #20180095758

Systems and methods for executing a fused multiply-add instruction for complex numbers

Disclosed embodiments relate to executing a vector-complex fused multiply-add Instruction. In one example, a method includes fetching an instruction, a format of the instruction including an opcode, a first source operand identifier, a second source operand identifier, and a destination operand identifier, wherein each of the identifiers is to identify... Intel Corporation

04/05/18 / #20180095761

Fused adjacent memory stores

A processing device includes a store instruction identification unit to identify a pair of store instructions among a plurality of instructions in an instruction queue. The pair of store instructions include a first store instruction and a second store instruction. The first data of the first store instruction corresponds to... Intel Corporation

04/05/18 / #20180095765

Supporting binary translation alias detection in an out-of-order processor

In one implementation, a processing device is provided that includes a memory to store instructions and a processor core to execute the instructions. The processor core is to receive a sequence of instructions reordered by a binary translator for execution. A first load of the sequence of instructions is identified.... Intel Corporation

04/05/18 / #20180095793

Methods and apparatus to schedule operations for resource sharing in computing systems

Methods and apparatus to schedule operations in computing systems are disclosed. An example method includes determining, by executing an instruction with a processor, that an operation identifier is inactive, the operation identifier assigned to a first operation, the operation identifier utilized by the processor to allocate computing resources of a... Intel Corporation

04/05/18 / #20180095802

Hardware stress indicators based on accumulated stress values

In one embodiment, a method comprises determining, at a plurality of instances in time, a value of at least one stress characteristic of a hardware resource; determining an accumulated stress value of the hardware resource, the accumulated stress value comprising the sum of a plurality of incremental stress values, an... Intel Corporation

04/05/18 / #20180095806

Technologies for fast boot with adaptive memory pre-training

Technologies for an advanced driver assist system (ADAS) with adaptive memory pre-training include a computing device and a safety microcontroller in communication with a serial link and a general-purpose I/O (GPIO) link. Out of reset, the computing device determines whether a full memory training signal is raised via the GPIO... Intel Corporation

04/05/18 / #20180095812

Memory integrity violation analysis method and apparatus

Methods, apparatus, and system to analyze a memory integrity violation and determine whether its cause was hardware or software based.... Intel Corporation

Patent Packs
04/05/18 / #20180095815

Trace hub logic with automatic event triggering

Technologies for execution trace with automatic event triggering include a computing device that includes an execution trace hub. The trace hub observes execution trace packets and determines whether the execution trace packets match one or more event trigger rules. If an execution packet matches an event trigger rule, the trace... Intel Corporation

04/05/18 / #20180095821

Extended application of error checking and correction code in memory

ECC (error checking and correction) can be extended to allow an ECC code to correct memory subarray errors. A memory device includes multiple input/output (I/O) connectors to interface with an external device such as a controller. The memory device includes multiple arrays or subarrays that are specifically mapped to I/O... Intel Corporation

04/05/18 / #20180095822

Handling open circuits while writing data by moving them to the least vulnerable location in an error correction code codeword

Systems, apparatuses and methods may provide for recording, if a non-volatile memory (NVM) location satisfies an open circuit condition, open circuit location information associated with the NVM location. Additionally, a shift of one or more bits may be conducting during a write of a codeword to the NVM location to... Intel Corporation

04/05/18 / #20180095823

System and granular in-field cache repair

A cache controller id disclosed, The cache controller includes circuitry to receive a request to access data in a target location of a last level cache of a processor on a processor package, identify an in-field failure in the target location of the last level cache, perform, in response to... Intel Corporation

04/05/18 / #20180095832

System and granular reset management without reboot

A system for granular reset management without reboot is disclosed. The system may include a subsystem, a processor including a reset management circuit coupled to the subsystem. The reset management circuit may include circuitry to receive a command to reset the subsystem, determine whether the subsystem can be reset without... Intel Corporation

04/05/18 / #20180095844

Protocol aware testing engine for high speed link integrity testing

Embodiments are generally directed to a protocol aware testing engine for high speed link integrity testing. An embodiment of a processor includes a processing core for processing data; and a protocol aware testing engine, wherein the protocol aware testing engine includes a protocol aware packet generator to generate test packets... Intel Corporation

04/05/18 / #20180095875

System and replacement in associative memories using weighted plru trees

A processor includes an associative memory including ways organized in an asymmetric tree structure, a replacement control unit including a decision node indicator whose value determines the side of the tree structure to which a next memory element replacement operation is directed, and circuitry to cause, responsive to a miss... Intel Corporation

04/05/18 / #20180095877

Processing scattered data using an address buffer

An example apparatus for processing scattered data includes an address buffer to receive a plurality of vector addresses corresponding to input vector data comprising scattered samples to be processed. The apparatus also includes a multi-bank memory to receive the input vector data and send output vector data. The apparatus further... Intel Corporation

04/05/18 / #20180095881

System and communication using a register management array circuit

A system for communication using a register management array circuit is disclosed, including a processor, including a processing core, the processing core including a local core register, a register management array circuit coupled to the local core register, and a remote circuit coupled to the register management array circuit, the... Intel Corporation

04/05/18 / #20180095883

Systems and methods for enhancing bios performance by alleviating code-size limitations

Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit... Intel Corporation

04/05/18 / #20180095884

Mass storage cache in non volatile level of multi-level system memory

An apparatus is described. The apparatus includes a memory controller comprising logic circuitry to implement a mass storage cache in a non volatile region of a system memory. The non volatile region of the system memory is to support execution of program code directly out of the non volatile region... Intel Corporation

04/05/18 / #20180095889

Technologies for reduced control and status register access latency

Technologies for control and status register (CSR) access include a computing device that starts a firmware initialization phase. The firmware accesses a CSR at an abstract CSR address. The computing device determines whether an upper part of the CSR address matches a cached upper part of a previously accessed CSR... Intel Corporation

04/05/18 / #20180095890

Accessing memory coupled to a target node from an initiator node

Provided are a method, apparatus, and a system in which an initiator node is configured to communicate with a target node that is coupled to a memory. At system initialization time, a memory address map of the initiator node is generated to include addresses corresponding to the memory to which... Intel Corporation

04/05/18 / #20180095892

Processors, methods, systems, and instructions to determine page group identifiers, and optionally page group metadata, associated with logical memory addresses

A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate source memory address information, and the instruction to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to... Intel Corporation

04/05/18 / #20180095894

Supporting oversubscription of guest enclave memory pages

Implementations of the disclosure provide for supporting oversubscription of guest enclave memory pages. In one implementation, a processing device comprising a memory controller unit to access a secure enclave and a processor core, operatively coupled to the memory controller unit. The processing device is to identify a target memory page... Intel Corporation

04/05/18 / #20180095895

System and cache replacement using conservative set dueling

A processor includes a set associative cache and a cache controller. The cache controller makes an initial association between first and second groups of sampled sets in the cache and first and second cache replacement policies. Follower sets in the cache are initially associated with the more conservative of the... Intel Corporation

04/05/18 / #20180095897

Techniques to protect fuses against non-destructive attacks

Embodiments may be generally directed to techniques to encrypt and decrypt data in a first fuse block array using an encryption key of a second fuse block array, the second fuse block array having the encryption key comprising a plurality of segments of bits, an inverse encryption key comprising a... Intel Corporation

04/05/18 / #20180095898

Multi-tenant encryption for storage class memory

Various embodiments are generally directed to the providing for mutual authentication and secure distributed processing of multi-party data. In particular, an experiment may be submitted to include the distributed processing of private data owned by multiple distrustful entities. Private data providers may authorize the experiment and securely transfer the private... Intel Corporation

04/05/18 / #20180095899

Multi-crypto-color-group vm/enclave memory integrity method and apparatus

Embodiments of apparatus, method, and storage medium associated with MCCG memory integrity for securing/protecting memory content/data of VM or enclave are described herein. In some embodiments, an apparatus may include one or more encryption engines to encrypt a unit of data to be stored in a memory in response to... Intel Corporation

04/05/18 / #20180095900

Multi-device system

One embodiment provides an apparatus. The apparatus includes an input output memory management unit (I/O MMU), a non-secure operating system (OS) driver, a secure OS driver and a virtual machine monitor (VMM). The I/OMMU is to couple an I/O Controller to a memory. The I/O Controller is coupled to a... Intel Corporation

04/05/18 / #20180095902

Enforcing memory operand types using protection keys

Enforcing memory operand types using protection keys is generally described herein. A processor system to provide sandbox execution support for protection key rights attacks includes a processor core to execute a task associated with an untrusted application and execute the task using a designated page of a memory; and a... Intel Corporation

04/05/18 / #20180095906

Hardware-based shared data coherency

Apparatuses, systems, and methods for coherently sharing data across a multi-node network is described. A coherency protocol for such data sharing can include identifying a memory access request from a requesting node for an I/O block of data in a shared I/O address space of a multi-node network, determining a... Intel Corporation

04/05/18 / #20180095909

Extended platform with additional memory module slots per cpu socket and configured for increased performance

PCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU,... Intel Corporation

04/05/18 / #20180095910

Preserving deterministic early valid across a clock domain crossing

A clock domain crossing can occur earlier in time by detection of when a data signal will coincide with a TSV (time slot valid) signal but the valid signal associated with the data signal will not coincide with a TSV. In response to such a detection, the domain crossing circuit... Intel Corporation

04/05/18 / #20180095913

Generation of processor interrupts using averaged data

In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine... Intel Corporation

04/05/18 / #20180095923

Link-physical layer interface adapter

An interface adapter to identify a first ready signal from a first link layer-to-physical layer (LL-PHY) interface of a first communication protocol indicating readiness of a physical layer of the first protocol to accept link layer data. The interface adapter generates a second ready signal compatible with a second LL-PHY... Intel Corporation

04/05/18 / #20180095925

Voltage modulated control lane

A computing component is provided with physical layer logic to receive data on a physical link including a plurality of lanes, where the data is received from a particular component on one or more data lanes of the physical link. The physical layer is further to receive a stream signal... Intel Corporation

04/05/18 / #20180095927

High performance interconnect physical layer

A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.... Intel Corporation

04/05/18 / #20180095929

Scratchpad memory with bank tiling for localized and random data access

An apparatus for localized and random data access is described herein. The apparatus includes a multi-bank memory, a queue, and an output buffer. The multi-bank memory is to store addresses locations of imaging data. The queue corresponds to each bank of the multi-bank memory, and the queue is to store... Intel Corporation

04/05/18 / #20180095935

Binary vector factorization

There is disclosed in an example, a processor, having: decode circuitry to decode instructions from an instruction stream; a data cache unit including circuitry to cache data for the processor; and a compute unit having an approximate matrix multiplication (AMM) circuit comprising: a data receptor to receive a weight vector... Intel Corporation

Social Network Patent Pack
04/05/18 / #20180096116

Technologies for authorizing a user to a protected system

Technologies for user authorization include a compute device configured to determine one or more physical attributes of a non-electronic physical object and authorize a user to a protected system based on the determined physical attributes of the non-electronic physical object. The physical attributes may include, for example, an acoustic signature,... Intel Corporation

04/05/18 / #20180096137

Using a second device to enroll a secure application enclave

A method, apparatus, and computer-readable medium are provided to determine whether to enroll a computing device as a provider of a secure application enclave for a secure an application. The following information is obtained from a second computing device: a device identifier for a first computing device, application information, and... Intel Corporation

04/05/18 / #20180096147

System, performing on-demand binary analysis for detecting code reuse attacks

In one embodiment, a binary translator to perform binary translation of code is to: perform a first binary analysis of a first code block to determine whether a second control transfer instruction is included in the first code block, where the first code block includes a return target of a... Intel Corporation

04/05/18 / #20180096177

Systems, methods, and apparatuses for implementing late fusing of processor features using a non-volatile memory

In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing late fusing of processor features using a non-volatile memory. For instance, there is disclosed in accordance with one embodiment a functional semiconductor package, including: a processor core configurable via a plurality of configuration registers; a non-volatile... Intel Corporation

04/05/18 / #20180096205

Robust monitoring of gauges

Methods, systems, and storage media for robust monitoring a gauge are disclosed herein. In an embodiment, a digital image of a gauge may be received to identify an analog value indicator of the gauge and to form an indicator representation corresponding to the analog value indicator. Robust optical character recognition... Intel Corporation

04/05/18 / #20180096261

Unsupervised machine learning ensemble for anomaly detection

An anomaly detection model generator accesses sensor data generated by a plurality of sensors, determines a plurality of feature vectors from the sensor data, and executes a plurality of unsupervised anomaly detection machine learning algorithms in an ensemble using the plurality of feature vectors to generate a set of predictions.... Intel Corporation

04/05/18 / #20180096460

Methods, apparatus and articles of manufacture to use biometric sensors to control an orientation of a display

Methods, systems and articles of manufacture for a portable electronic device that uses biometric content to determine an orientation in which a display device is presenting content are disclosed. Example electronic devices include a display device, a biometric sensor to capture a biometric sample, and an orientation determination tool to... Intel Corporation

04/05/18 / #20180096501

Technologies for motion-compensated virtual reality

Technologies for motion-compensated virtual reality include a virtual reality compute device of a vehicle. The virtual reality compute device is configured to render a virtual reality content to an occupant of the vehicle and determine a motion of the vehicle based at least on sensor data generated by one or... Intel Corporation

04/05/18 / #20180096528

Automatic placement of augmented reality models

An embodiment of an augmented reality model placement apparatus may include a location identifier to identify one or more candidate locations in a three-dimensional (3D) model for an augmented reality (AR) model based on the 3D model, the AR model, and placement constraints for the AR model, a location ranker... Intel Corporation

04/05/18 / #20180096529

Augmented reality rendered structured content

Systems, apparatuses and methods may provide a technology-based way to adapt non-augmented realty (AR) content from a content platform for display in an AR environment. More particularly, systems, apparatuses and methods may provide a way to render an AR environment including some portion of the adapted non-AR content based on... Intel Corporation

Patent Packs
04/05/18 / #20180096554

Vending machine interface

Various systems and methods for providing a vending machine interface system are provided herein. A vending machine interface system installed in a vending machine includes a peripheral interface to receive data from a peripheral payment device connected to the vending machine, the data indicating an amount received; an inventory interface... Intel Corporation

04/05/18 / #20180096667

Transmitting display data

In some examples, a system can include a microcontroller to initialize a counter to a predetermined value for each image component of an image data slice. The microcontroller can also store a number of received bits for each image component in a data structure and generate a pre-allocation signal indicating... Intel Corporation

04/05/18 / #20180096695

Technologies for privately processing voice data

Technologies for privately processing voice data include a compute device configured to continually or periodically capture voice data of a user by the compute device. The captured voice data is processed to remove or reduce the user's privacy-sensitive information. For example, the compute device fragments the captured voice data to... Intel Corporation

04/05/18 / #20180096719

Staggering initiation of refresh in a group of memory devices

Memory refresh includes timing offsets for different memory devices, to initiate refresh of different memory devices at different times. A memory controller sends a refresh command to cause refresh of multiple memory devices. In response to the refresh command, the multiple memory devices initiate refresh with timing offsets relative to... Intel Corporation

04/05/18 / #20180096735

Systems, methods, and apparatuses for implementing testing of a far memory subsystem within two-level memory (2lm) stacked die subsystems

In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing testing of a far memory subsystem within Two-Level Memory (2LM) stacked die subsystems. For instance, there is in accordance with one embodiment a stacked semiconductor package which includes: a functional silicon die; a test controller having... Intel Corporation

04/05/18 / #20180096737

Methods and predictable protocol aware testing on memory interface

Methods and apparatus for predictable protocol aware testing on a memory interface are are shown. An apparatus to support a protocol aware testing on a memory interface may include a digital controller to receive a plurality of read request commands from a unit under test. The digital controller further to... Intel Corporation

04/05/18 / #20180096764

Hybrid magnetic material structures for electronic devices and circuits

Embodiments are generally directed to hybrid magnetic material structures for electronic devices and circuits. An embodiment of an inductor includes a first layer of magnetic film material applied on a substrate, one or more conductors placed on the first layer of magnetic film material, and a second layer of magnetic... Intel Corporation

04/05/18 / #20180096776

Integrated inductor with adjustable coupling

Embodiments are generally directed to an integrated inductor with adjustable coupling. In some embodiments, an integrated inductor includes a first conductor and a second conductor; a first strip of magnetic material film below the first conductor and the second conductor; and a second strip of magnetic material film above the... Intel Corporation

04/05/18 / #20180096862

Complex cavity formation in molded packaging structures

Molded electronics package cavities are formed by placing a sacrificial material in the mold and then decomposing, washing, or etching away this sacrificial material. The electronics package that includes this sacrificial material is then overmolded, with little or no change needed in the overmolding process. Following overmolding, the sacrificial material... Intel Corporation

04/05/18 / #20180096891

Self-aligned contacts

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and... Intel Corporation

04/05/18 / #20180096946

Semiconductor packages having a fiducial marker and methods for aligning tools relative to the fiducial marker

Electronic device package technology is disclosed. In one example, an electronic device includes a plurality of dies stacked on a substrate and a reference die on the plurality of dies and having a fiducial marker that indicates a spatial position of the plurality of dies for alignment of an electronics... Intel Corporation

04/05/18 / #20180096955

Electronic component guard ring

Guard ring technology is disclosed. In one example, an electronic component guard ring can include a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component. The guard ring can also include an opening... Intel Corporation

04/05/18 / #20180096959

Semi-conductor package structure

Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent... Intel Corporation

04/05/18 / #20180096971

Systems, methods, and apparatuses for implementing die recovery in two-level memory (2lm) stacked die subsystems

In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing die recovery in Two-Level Memory (2LM) stacked die subsystems. For instance, there is disclosed in accordance with one embodiment a stacked semiconductor package having therein: a processor functional silicon die at a first layer of the... Intel Corporation

04/05/18 / #20180096975

High density package on package devices created through a self assembly monolayer assisted laser direct structuring process on mold compound

A high density package on package electrical device is disclosed. The electrical device comprises a first integrated circuit package comprising a substrate, an integrated circuit component attached to the substrate, and a molding compound covering the component, wherein the top of the molding compound has a redistribution layer of metal... Intel Corporation

04/05/18 / #20180096977

Apparatus for micro pick and bond

Embodiments of the invention include systems and methods for transferring micro LEDs. In an embodiment, the system for transferring micro LEDs, may include a donor substrate bank that is capable of supporting a plurality of donor substrates on which a plurality of micro LEDs are formed. In an embodiment, the... Intel Corporation

04/05/18 / #20180096979

A stacked semiconductor package having fault detection and a identifying a fault in a stacked package

A stacked semiconductor package comprising a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, and two or more memory dies forming a corresponding two or more memory layers of the stacked semiconductor package. A plurality of Through Silicon Vias (TSVs) are formed through the two or... Intel Corporation

04/05/18 / #20180097003

Wrap-around trench contact structure and methods of fabrication

A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions,... Intel Corporation

04/05/18 / #20180097056

Three capacitor stack and associated methods

A three capacitor stack and associated methods are shown. An exemplary capacitor device may include a first capacitor stack that includes a first plurality of layers of reference electrodes interleaved with first capacitor electrodes, a second capacitor stack on the first capacitor stack that includes a second plurality of layers... Intel Corporation

04/05/18 / #20180097269

Waveguide bundle fabrication in suspended media targeting bend-induced strain relief

An apparatus comprises a plurality of waveguides, wherein the waveguides include a dielectric material; an outer shell; and a supporting feature within the outer shell, wherein the waveguides are arranged separate from each other within the outer shell by the supporting feature.... Intel Corporation

04/05/18 / #20180097270

Transformer based on-package power combiner

Embodiments are generally directed to a transformer based on-package power combiner. An embodiment of a power combiner includes multiple primary coils on a first metal layer of a package; a secondary coil on a second metal layer of the package, the secondary coil including multiple secondary coil portions, wherein each... Intel Corporation

04/05/18 / #20180097284

Actuatable and adaptable metamaterials integrated in package

Embodiments of the invention include a reconfigurable communication system, that includes a substrate and a metamaterial shield formed over the substrate. In an embodiment, the metamaterial shield surrounds one or more components on the substrate. Additionally, a plurality of first piezoelectric actuators may be formed on the substrate. The first... Intel Corporation

04/05/18 / #20180097369

Methods, apparatus, systems and articles of manufacture to charge a battery based on an electronic device skin temperature

Methods, apparatus, systems, and articles of manufacture for a battery charging device are disclosed. Example battery charging devices include a temperature sensor to sense a skin temperature of an electronic device in which the battery is installed, and a current controller to control a magnitude of a charging current to... Intel Corporation

04/05/18 / #20180097391

Method to reuse the pulse discharge energy during li-ion fast charging for better power flow efficiency

A battery charger for charging a battery with voltage from an input supply and method for using are disclosed. In one embodiment, the battery charger comprises a power path to drive the battery during a pulse charging sequence in a first mode and to reverse power flow from the battery... Intel Corporation

04/05/18 / #20180097392

System, safe a4wp polling

The disclosure relates to a method, apparatus and system to wirelessly charge a device without creating fire hazard or other risks to nearby sensitive objects. An exemplary embodiment includes a memory circuitry and a chipset. The chipset communicates with the memory circuitry and is configured to selectively communicate with one... Intel Corporation

04/05/18 / #20180097393

Fabric device for charging

An electronic device may include a charging pad have a plurality of metal contacts, and a fiber device having a plurality of non-conductive material and a plurality of conductive material. At least one of the plurality of conductive material may be aligned with at least one of the plurality of... Intel Corporation

04/05/18 / #20180097394

Wireless charging system and method

A wireless charging system and a method for tuning the wireless charging system is described. The system can include matching circuitry coupled to a transmission coil and a controller coupled to the matching circuitry. The transmission coil can have a load inductance. The controller can control the matching circuitry to... Intel Corporation

04/05/18 / #20180097458

Piezoelectric package-integrated motor

Embodiments of the invention include a self-propelled sensor system. In an embodiment, the self-propelled sensor system includes a piezoelectrically actuated motor that is integrated with a substrate. In an embodiment, the self-propelled sensor system may also include a sensor and an integrated circuit electrically coupled to the piezoelectrically actuated motor.... Intel Corporation

04/05/18 / #20180097535

Scalable stochastic successive approximation register analog-to-digital converter

Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate first bits and second bits based... Intel Corporation

04/05/18 / #20180097585

Scheduling acknowledgements to received sub-frames in a multi-sim user equipment using a shared transmit chain when receiving data continuously on each sim

A multi-SIM wireless device checks whether each of the (e.g., two) SIMs has received sub-frames in successive intervals prior to a current interval. If such a condition is satisfied by all the SIMs, the wireless device allocates several successive (transmit) intervals to a first SIM before allocating next successive (transmit)... Intel Corporation

Patent Packs
04/05/18 / #20180097593

Station (sta) and usage of phase noise compensation based on operational parameters

Embodiments of a station (STA) and method for communication in accordance with phase noise compensation are generally described herein. The STA may determine, based at least partly on one or more operational parameters, whether to perform phase noise compensation of data symbols of a received protocol data unit (PDU). For... Intel Corporation

04/05/18 / #20180097614

Cascading multivariate quadratic identification schemes for chain of trust

A method, computing system, and computer-readable medium comprising instructions to establish a chain of trust for components of a computing environment. A respective public/private key pair is generated using a multivariate quadratic function F for each component of the computing environment. In response to a challenge from a verifier, a... Intel Corporation

04/05/18 / #20180097615

Energy-efficient dual-rail keeperless domino datapath circuits

Described is an apparatus comprising precharge paths including first clocked transistors having gates coupled to a clock signal path, first terminals coupled to a first power rail, and second terminals coupled to one or more first junction nodes. The precharge paths lack a keeper circuitry, have a configurable keeper circuitry,... Intel Corporation

04/05/18 / #20180097618

Linear masking circuits for side-channel immunization of advanced encryption standard hardware

Described is an apparatus comprising an S-box circuitry operable to convert a value on an input into a value on an output in accordance with an Advanced Encryption Standard (AES) Rijndael S-box matrix. The apparatus also comprises a pseudo-random number generation (PRG) circuitry operable to provide a sequence of pseudo-random... Intel Corporation

04/05/18 / #20180097625

Parallel computation techniques for accelerated cryptographic capabilities

Computing devices and techniques for performing modular exponentiation for a data encryption process are described. In one embodiment, for example, an apparatus may include at least one memory logic for an encryption unit to perform encryption according to RSA encryption using a parallel reduction multiplier (PRM) MM process, at least... Intel Corporation

04/05/18 / #20180097626

Secure account access control

Various systems and methods for providing secure account access controls for executors are described herein. A system for secure account access control includes a communication circuit to receive, from a client computer associated with a human client: an encrypted payload, the encrypted payload encrypted with a representative key associated with... Intel Corporation

04/05/18 / #20180097630

Techniques for secure authentication

Various embodiments are generally directed to techniques for secure message authentication and digital signatures, such as with a cipher-based hash function, for instance. Some embodiments are particularly directed to a secure authentication system that implements various aspects of the cipher-based hash function in dedicated hardware or circuitry. In various embodiments,... Intel Corporation

04/05/18 / #20180097652

Appliance state recognition device and methods

Embodiments herein relate to recognition of an appliance state based on sensor data and determination of a response based at least in part on the appliance state. In various embodiments, an apparatus to recognize an appliance state may include a sensor data module to identify sensor data in one or... Intel Corporation

04/05/18 / #20180097665

Supply voltage adaptation via decision feedback equalizer

Some embodiments include apparatus and methods using a first latch in a decision feedback equalizer (DFE), a second latch in the DFE, and circuity coupled to the first and second latches. The second latch includes a first input node coupled to an output node of the first latch. The circuitry... Intel Corporation

04/05/18 / #20180097675

Low rate interface for narrow band wireless transmissions

A mobile communication device may include a storage element and a baseband processing component operatively coupled to the storage element. The baseband processing component may generate representations of one or more symbols, provide the representations of the one or more symbols through an interface to a buffer element to process,... Intel Corporation

04/05/18 / #20180097693

Package integrated security features

Embodiments of the invention include a physiological sensor system. According to an embodiment the sensor system may include a package substrate, a plurality of sensors formed on the substrate, a second electrical component, and an encryption bank formed along a data transmission path between the plurality of sensors and the... Intel Corporation

04/05/18 / #20180097728

Virtual switch acceleration using resource director technology

A virtual switch configured to switch packets between virtual switch ports based on classifier sub-tables. The virtual switch reserves blocks of last level cache for classifier sub-table storage. The virtual switch also maintains a global sub-table priority map for the classifier sub-tables. The global sub-table priority map indicates usage frequency... Intel Corporation

04/05/18 / #20180097743

Apparatus and methods for implementing cluster-wide operational metrics access for coordinated agile scheduling

Apparatus, methods, and system for implementing cluster-wide operational metrics access for coordinated agile scheduling. One embodiment of the apparatus includes a memory to store instructions; a processing circuitry to execute instructions; and an interface circuitry. The interface circuitry to provide metrics associated with the apparatus to one or more subscriber... Intel Corporation

04/05/18 / #20180097809

Securing access to cloud components

Particular embodiments described herein provide for receiving a request from a first cloud component in a cloud network, wherein the request is to access a key and the key allows the first cloud component to access located trusted execution environment of a second cloud component in the cloud network and... Intel Corporation

04/05/18 / #20180097822

Technologies for analyzing uniform resource locators

Technologies for analyzing a Uniform Resource Locator (URL) include a multi-stage URL analysis system. The multi-stage URL analysis system analyzes the URL using a multi-stage analysis. In the first stage, the multi-stage URL analysis system analyzes the URL using an ensemble lexical analysis. In the second stage, the multi-stage URL... Intel Corporation

04/05/18 / #20180097825

System monitor

One embodiment provides an apparatus. The apparatus includes detector circuitry and monitor logic local to a computing device. The detector circuitry is to generate local sensor data based, at least in part, on a sensor signal received from a sensor incorporated in the local computing device. The monitor logic is... Intel Corporation

04/05/18 / #20180097843

Networked peer device round-robin security controller

A round-robin network security system implemented by a number of peer devices included in a plurality of networked peer devices. The round-robin security system permits the rotation of the system security controller among at least a portion of the peer devices. Each of the peer devices uses a defined trust... Intel Corporation

04/05/18 / #20180098073

Method and system of video coding using projected motion vectors

Techniques related to video coding perform by using projected motion vectors.... Intel Corporation

04/05/18 / #20180098082

Motion estimation using hybrid video imaging system

Techniques are provided for motion estimation using hybrid video imaging based on frame-based capture and event-based capture. A methodology implementing the techniques according to an embodiment includes receiving a sequence of pixel events, generated asynchronously by an event-based video camera, and receiving a sequence of image frames generated by a... Intel Corporation

04/05/18 / #20180098083

Method and system of hardware accelerated video coding with per-frame parameter control

Techniques are provided that are related to hardware accelerated video coding with per-frame parameter control.... Intel Corporation

Social Network Patent Pack
04/05/18 / #20180098108

Technologies for structured media playback

Technologies for structured media playback include one or more physical media objects, which may be placed on a substrate including a matrix of position sensor tags. Each of the physical media objects is configured to sense one or more position sensor tags and transmit tag information received from the sensed... Intel Corporation

04/05/18 / #20180098136

Push telemetry data accumulation

The present disclosure is directed to push telemetry data accumulation. A system may comprise at least telemetry circuitry configured to push telemetry data (e.g., provide telemetry data without first receiving a request). An example system may comprise one or more devices that include at least one set of telemetry circuitry.... Intel Corporation

04/05/18 / #20180098182

Systems, methods, and devices for dual-mode communication in a personal area network

Communication devices and techniques for facilitating dual-mode communication within a single wireless communication device are described. In one embodiment, for example, an apparatus may include at least one memory and logic for a wireless communication device, at least a portion of the logic comprised in hardware coupled to the at... Intel Corporation

04/05/18 / #20180098191

Sharing of environmental data for client device usage

Embodiments are generally directed to sharing of environmental data for client device usage. An embodiment of a client device includes a processor; an environmental sensor to sense an environmental condition, an output of the sensor being a local environmental sensor value; and a wireless receiver to receive environmental data for... Intel Corporation

04/05/18 / #20180098229

Methods and arrangements to relay packets via wi-fi direct

Logic may enable client devices or access points to relay medium access control (MAC) frames. Logic may extend the range of IEEE 802.11 devices, such as IEEE 802.11ah devices.... Intel Corporation

04/05/18 / #20180098244

Systems, methods, and devices for coexistence of heterogeneous bandwidth communications

Communication devices and techniques for facilitating coexistence between networks operating at different bandwidths are described. In one embodiment, for example, an apparatus may include at least one memory and logic for a narrowband communication device, at least a portion of the logic comprised in hardware coupled to the at least... Intel Corporation

04/05/18 / #20180098277

Reduced power consuming mobile devices method and apparatus

Apparatus and method to facilitate power consumption reduction in one or both of a first and second device are disclosed herein. In some embodiments, the first device may include one or more antennas that is to receive first audio data captured by the second device; and one or more processors... Intel Corporation

04/05/18 / #20180098318

Physical uplink control channel (pucch) resource allocation (ra) for a hybrid automatic retransmission re-quest-acknowledge (harq-ack) transmission

A user equipment (UE) is disclosed. The UE can identify a downlink control channel. The UE can determine when the downlink control channel is an enhanced physical downlink control channel (EPDCCH). The UE can select an enhanced physical uplink control channel (PUCCH) resource allocation for a hybrid automatic retransmission re-quest-acknowledge... Intel Corporation

04/05/18 / #20180098320

Reducing hardware precision time measurement inaccuracy

Aspects of the embodiments are directed to systems, methods, and devices, such as an upstream device that includes an input/output port. The input/output port configured to receive a message from an output port of a downstream device; transmit a plurality of acknowledgement messages to the downstream device; and transmit a... Intel Corporation

04/05/18 / #20180098336

Methods and devices for channel selection and access coordination

This disclosure relates to a method for primary channel selection by a first access point type communication device (AP) of a group of APs, the method comprising: detecting, by the first AP, a central frequency location and a bandwidth of a primary channel selected by at least one second AP... Intel Corporation

04/05/18 / #20180098377

Fingerprint analysis of wireless signals for automatic disconnect of wireless display

A wireless device may disconnect a wireless connection to a remote device. The wireless device may include a memory device and one or more processors coupled to the memory device. The processors may generate a first wireless fingerprint of the wireless device, wherein the first wireless fingerprint comprises a first... Intel Corporation

04/05/18 / #20180098421

Local stress-relieving devices, systems, and methods for electronic assemblies

Electronic device package technology is disclosed. In one example, an electronic device includes a substrate having at least one electronic component mounted thereon and a heatsink thermally coupled to the electronic component. A plurality of fasteners attaches the heatsink to the substrate. At least one of the substrate, the heatsink,... Intel Corporation

04/05/18 / #20180098428

Non-planar on-package via capacitor

Embodiments are generally directed to non-planar on-package via capacitor. An embodiment of an embedded capacitor includes a first plate that is formed in a package via; a dielectric layer that is applied on the first plate; and a second plate that is formed in a cavity in the dielectric layer,... Intel Corporation

04/05/18 / #20180098436

Integrated circuit package substrate

Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more... Intel Corporation








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