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Intel Corporation patents


Recent patent applications related to Intel Corporation. Intel Corporation is listed as an Agent/Assignee. Note: Intel Corporation may have other listings under different names/spellings. We're not affiliated with Intel Corporation, we're just tracking patents.

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Package testing system and method with contact alignment

Embodiments of the present disclosure provide techniques and configurations for a package testing system. In some embodiments, the system may comprise a printed circuit board (PCB), including one or more sensors disposed adjacent to a corner of the PCB to face a package to be tested, to detect an electrical... Intel Corporation

Manufacturing advanced test probes

Embodiments relate to the formation of test probes. One method includes providing a bulk sheet of an electrically conductive material. A laser is used to cut through the bulk sheet in a predetermined pattern to form a test probe. Other embodiments are described and claimed.... Intel Corporation

Automatic adjustment of head mounted display straps

Embodiments are generally directed to automatic adjustment of head mounted display straps. An embodiment of a head mounted display apparatus includes a display unit; a strap harness including one or more straps; one or more pressure sensors; a microcontroller; and one or more automatic adjustment mechanisms for the one or... Intel Corporation

Electronic device having a controller to enter a low power mode

An electronic device may be provided that includes a first controller, a second controller, and a bus to connect between the first controller and the second controller. The electronic device may also include a first signal line between the first controller and the second controller, and the first controller to... Intel Corporation

Independent power control of processing cores

Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.... Intel Corporation

Systems and methods for hosting web applications within remote management hardware and/or firmware

A system and method are disclosed for remote management, including systems and methods for hosting web applications within remote management hardware and/or firmware. In one embodiment, a system includes a microcontroller to configure a processor, the microcontroller including a memory. The system further includes a network interface coupled to the... Intel Corporation

Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality

Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to... Intel Corporation

Techniques for improving output-packet-similarity between primary and secondary virtual machines

Examples may include intercepting packets outputted from a primary virtual machine (PVM) hosted by a first server and converting one or more fields of protocol headers for each intercepted packet such that output-packet-similarity may be increased between the PVM outputted packets and packets outputted by a secondary virtual machine (SVM)... Intel Corporation

Execution context migration method and apparatus

Methods, apparatuses and storage medium associated with migration between processors by a computing device are disclosed. In various embodiments, a portable electronic device having an internal processor and internal memory may be attached to a dock. The dock may include another processor as well other memory. The attachment of the... Intel Corporation

Multimodal interface

Particular embodiments described herein provide for an electronic device that can receive data from an operating system in an electronic device, where the data is related to hardware that is in communication with the electronic device through a multimodal interface and communicate the data and/or related data to a local... Intel Corporation

Systems and methods for faster read after write forwarding using a virtual address

Methods for read after write forwarding using a virtual address are disclosed. A method includes determining when a virtual address has been remapped from corresponding to a first physical address to a second physical address and determining if all stores occupying a store queue before the remapping have been retired... Intel Corporation

Create page locality in cache controller cache allocation

A cache controller is to allocate memory within set-associative cache that includes a plurality of sets of ways. The cache controller is to request to assign an entry for a system address in the set-associative cache and execute a function to determine a set, from a series of sets within... Intel Corporation

Memory scanning methods and apparatus

Memory scanning methods and apparatus are disclosed. An example apparatus includes scan manager to identify a physical memory address that has recently been accessed. The physical memory address is identified as having been recently accessed when an access has occurred within a threshold of a current time. The apparatus also... Intel Corporation

Secure public cloud

A method, system, computer-readable media, and apparatus for ensuring a secure cloud environment is provided, where public cloud services providers can remove their code from the Trusted Computing Base (TCB) of their cloud services consumers. The method for ensuring a secure cloud environment keeps the Virtual Machine Monitor (VMM), devices,... Intel Corporation

Apparatus and shared resource partitioning through credit management

An apparatus is provided which comprises: a first engine buffer to receive a first engine request; a first engine register coupled to the first engine buffer, wherein the first engine register is to store first engine credits associated with the first engine buffer; a second engine buffer to receive a... Intel Corporation

Brightness control for spatially adaptive tone mapping of high dynamic range (hdr) images

Techniques are provided for spatially adaptive tone mapping with dynamic brightness control. A methodology implementing the techniques according to an embodiment includes converting luminance data, from a received HDR image, to a logarithm domain and decomposing the converted data into a base layer, and one or more detail layers. The... Intel Corporation

Systems and methods for contextually augmented video creation and sharing

An augmented reality (AR) device includes a 3D video camera to capture video images and corresponding depth information, a display device to display the video data, and an AR module to add a virtual 3D model to the displayed video data. A depth mapping module generates a 3D map based... Intel Corporation

Techniques for enforcing a depth order policy for graphics in a display scene

Various embodiments are generally directed an apparatus and method for processing an encrypted graphic with a decryption key associated with a depth order policy including a depth position of a display scene, generating a graphic from the encrypted graphic when the encrypted graphic is successfully decrypted using the decryption key... Intel Corporation

Optimized display image rendering

In one example, a head mounted display system includes detecting a position of a head of a user of the head mounted display, predicting a position of the head of the user of the head mounted display at a time after a time that the position of the head of... Intel Corporation

Performance of additional refresh operations during self-refresh mode

Embodiments are generally directed to performance of additional refresh operations during self-refresh mode. An embodiment of a memory device includes one or more memory banks, a mode register set, the mode register set including a first set of mode register bits, and a control logic to provide control operations for... Intel Corporation

Zn doped solders on cu surface finish for thin fli application

Embodiments of the invention include a semiconductor device and methods of forming the semiconductor device. In an embodiment the semiconductor device comprises a semiconductor die with one or more die contacts. Embodiments include a reflown solder bump on one or more of the die contacts. In an embodiment, an intermetallic... Intel Corporation

Lps solder paste based low cost fine pitch pop interconnect solutions

Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid... Intel Corporation

Bumpless build-up layer package with a pre-stacked microelectronic devices

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a... Intel Corporation

Method of fabricating an optical module that includes an electronic package

Some forms include an electronic package that includes a photo-detecting receiver IC and a receiver IC. The electronic package includes a mold that encloses the photo-detecting receiver IC and the receiver IC. The photo-detecting receiver IC and the receiver IC are adjacent to one another without touching one another. Other... Intel Corporation

Self-aligned gate edge and local interconnect and method to fabricate same

Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor... Intel Corporation

Tungsten gates for non-planar transistors

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a... Intel Corporation

Techniques for forming non-planar germanium quantum well devices

Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure... Intel Corporation

Method for fabricating transistor with thinned channel

A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.... Intel Corporation

Configurable constellation mapping to control spectral efficiency versus signal-to-noise ratio

Mixed mode constellation mapping to map a data block to a block of sub-carriers based on a configurable set of one or more constellation mapping schemes, and corresponding mixed mode least likelihood ratio (LLR) de-mapping based on the configurable set of one or more modulation schemes. The set may be... Intel Corporation

Techniques for storing or accessing a key-value item

Examples may include techniques for storing or accessing a key-value (KV) item stored in a memory that is part of a memcached system. A KV server coupled with a network input/output device may be capable of allocating one or more item slots from the memory and indicating to logic or... Intel Corporation

Content based video encoding for wireless display

Techniques related to content based encoding of video content for transmission and display via a remote device are discussed. Such techniques may include collecting graphics properties for graphics layers of a frame of a video sequence, determining encode settings based on the graphics properties, and coding the frame of the... Intel Corporation

Determining chroma quantization parameters for video coding

Techniques related to determining chroma quantization parameters for video coding are discussed. Such techniques may include generating first and second chroma quantization parameter offsets for first and second picture of a video sequence having a hierarchical coding structure such that the second chroma quantization parameter offset is greater than or... Intel Corporation

Method of fabricating a stretchable computing device

Some forms relate to a stretchable computing device that includes a stretchable body; a first electronic component embedded within the stretchable body; a second electronic component embedded within the stretchable body; and wherein the first electronic component and the second electronic component are connected by stretchable electrical connectors that include... Intel Corporation

Flexible integrated circuit that includes an antenna

A flexible integrated circuit that includes a first dielectric layer having a first section at one polarity and a second section at an opposing polarity, wherein the first section and the second section are separated by dielectric material within first dielectric layer; a second dielectric layer having a first side... Intel Corporation

Apparatus and programming non-volatile memory using a multi-cell storage cell group

Provided are an apparatus, method, and system for programming a multi-cell storage cell group. A non-volatile memory has storage cells. Each storage cell is programmed with information using a plurality of threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller... Intel Corporation

02/08/18 / #20180039497

Apparatus and method to reverse and permute bits in a mask register

An apparatus and method are described for performing a bit reversal and permutation on mask values. For example, a processor is described to execute an instruction to perform the operations of: reading a plurality of mask bits stored in a source mask register, the mask bits associated with vector data... Intel Corporation

02/08/18 / #20180039498

Method for a delayed branch implementation by using a front end track table

A method for a delayed branch implementation by using a front end track table. The method includes receiving an incoming instruction sequence using a global front end, wherein the instruction sequence includes at least one branch, creating a delayed branch in response to receiving the one branch, and sing a... Intel Corporation

02/08/18 / #20180039528

Techniques for handling errors in persistent memory

Examples may include a basic input/output system (BIOS) for a computing platform communicating with a controller for a non-volatile dual in-line memory module (NVDIMM). Communication between the BIOS and the controller may include a request for the controller to scan and identify error locations in non-volatile memory at the NVDIMM.... Intel Corporation

02/08/18 / #20180039593

Optimized credit return mechanism for packet sends

Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is... Intel Corporation

02/08/18 / #20180039782

Anti-theft in firmware

Methods, systems and storage media are disclosed for enhanced system boot processing that authenticates boot code based on biometric information of the user before loading the boot code to system memory. For at least some embodiments, the bio-metric authentication augments authentication of boot code based on a unique platform identifier.... Intel Corporation

02/08/18 / #20180039863

Neural network classification through decomposition

A classification system is described which may include neural network decomposition logic (“NND”), which may perform classification using a neural network (“NN”). The NND may decompose a classification decision into multiple sub-decision spaces. The NND may perform classification using an NN that has fewer neurons than the NND utilizes for... Intel Corporation

02/08/18 / #20180039864

Fast and accurate skin detection using online discriminative modeling

Techniques related to performing skin detection in an image are discussed. Such techniques may include generating skin and non-skin models based on a skin dominant region and another region, respectively, of the image and classifying individual pixels of the image via a discriminative skin likelihood function based on the skin... Intel Corporation

02/08/18 / #20180040104

Restoring color and infrared images from mosaic data

Methods, apparatuses and systems may provide for creating a reference signal for a restoration process using a plurality of pixels corresponding to various color channels within a spatial neighborhood of a target pixel location. Additionally, first weights may be set in pixel locations within the spatial neighborhood to control contributions... Intel Corporation

02/08/18 / #20180040256

Methods and apparatus to develop in-vehicle experiences in simulated environments

Methods, apparatus, systems and articles of manufacture are disclosed to develop driving simulations. An example apparatus includes a vehicle configuration engine to retrieve first tier environment parameters associated with a simulation type, and generate second tier environment parameters associated with the simulation type, a simulation modifier (SM) source engine to... Intel Corporation

02/08/18 / #20180040367

Apparatus and endurance friendly programming using lower voltage thresholds

Provided are a method and apparatus for endurance friendly programming using lower voltage thresholds. A non-volatile memory has storage cells organized as pages programmed using a first number of threshold voltage levels. The storage cells are organized into storage cell groups to which data is written. Each storage cell group... Intel Corporation

02/08/18 / #20180040536

Single base multi-floating surface cooling solution

An apparatus including a primary device and at least one secondary device coupled to a substrate; a heat exchanger disposed on the primary device and on the at least one secondary device, wherein the heat exchanger includes at least one portion disposed over an area corresponding to the primary device... Intel Corporation

02/08/18 / #20180040637

High voltage three-dimensional devices having dielectric liners

High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top... Intel Corporation

02/08/18 / #20180041003

Chip on chip (coc) package with interposer

Embodiments herein may relate to a chip-on-chip (CoC) package that includes a first integrated circuit (IC) die with an active side coupled with an active side of a second IC die. The CoC package may further include a substrate with a conductive metal post extending from a side of the... Intel Corporation

02/08/18 / #20180041294

Techniques to manage channel prediction

A system, apparatus, method and article to manage channel prediction for a wireless communication system are described. The apparatus may include a media access control processor to perform channel prediction, and a transceiver to communicate information using the channel prediction. Other embodiments are described and claimed.... Intel Corporation

02/08/18 / #20180041513

Technologies for secure server access using a trusted license agent

Technologies for secure server access include a client computing device that loads a license agent into a secure enclave established by a processor of the client computing device. The license agent receives a request from an application to access a remote server device. The license agent opens a secure connection... Intel Corporation

02/08/18 / #20180041557

Cloud computing for mobile client devices

Apparatuses, methods and storage medium associated with cloud computing for mobile client devices are disclosed herein. In embodiments, a cloud server may include one or more processors, and a mobile computing operating system to host execution of an application. The cloud server may also include a cloud application server to... Intel Corporation

02/08/18 / #20180041766

Lossless pixel compression for random video memory access

A system for lossless pixel compression for random video memory access is described herein. The system includes an encoder and a decoder. The system also includes a memory that is to store instructions and that is communicatively coupled to the encoder and decoder. Further the system includes a processor. The... Intel Corporation

02/08/18 / #20180041770

Techniques for hardware video encoding

An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder comprises at least a fixed function dual hierarchical motion estimation search units, dual integer motion estimation search units, and a fractional motion estimation search unit. Moreover, the hardware bit... Intel Corporation

02/08/18 / #20180042029

Multi-phase wireless sounding

System and techniques for multi-phase wireless sounding are described herein. A first set of stations may be selected by an access point from a plurality of stations known to the access point. The access point may then transmit a first sounding request to members of the first set of stations.... Intel Corporation

02/01/18 / #20180031137

Auto range control for active illumination depth camera

A method and apparatus for auto range control are described. In one embodiment, the apparatus comprises a projector configured to project a sequence of light patterns on an object; a first camera configured to capture a sequence of images of the object illuminated with the projected light patterns; a controller... Intel Corporation

02/01/18 / #20180031873

Feedback controlled closed loop on-chip isolator

Embodiments herein relate to a photonic integrated circuit (PIC) with an on-chip optical isolator. The PIC may comprise a laser, a waveguide coupled with the laser, and a closed loop resonator coupled to the laser through the waveguide. A magneto-optical (MO) layer is over and in contact with the waveguide... Intel Corporation

02/01/18 / #20180032169

Silver nanowire touch sensor component

Apparatus and/or methods may provide a substrate and a sensor pattern formed on the substrate based on a visibility level for a touch sensor application. The sensor pattern may include a specified inter-pattern spacing and a specified pattern width to provide the visibility level. For example, the specified inter-pattern spacing... Intel Corporation

02/01/18 / #20180032332

Three source operand floating-point addition instruction with operand negation bits and intermediate and final result rounding

A processor of an aspect includes a decode unit to decode a three source floating point addition instruction indicating a first source operand having a first floating point data element, a second source operand having a second floating point data element, and a third source operand having a third floating... Intel Corporation

02/01/18 / #20180032334

Method and performing a vector bit reversal and crossing

An apparatus and method for performing a vector bit reversal and crossing. For example, one embodiment of a processor comprises: a first source vector register to store a first plurality of source bit groups, wherein a size for the bit groups is to be specified in an immediate of an... Intel Corporation

02/01/18 / #20180032339

Cross-level prefetch for shared multi-level libraries

In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that are associated with receiving a call from an application at a shared library, accessing a first resource based at least in part on the first call, and storing a prefetch entry in a prefetch engine based at... Intel Corporation

02/01/18 / #20180032342

Loop vectorization methods and apparatus

Loop vectorization methods and apparatus are disclosed. An example method includes generating a first control mask for a set of iterations of a loop by evaluating a condition of the loop, wherein generating the first control mask includes setting a bit of the control mask to a first value when... Intel Corporation

02/01/18 / #20180032374

Application launch booster

The time required to launch an application may be reduced by increasing the performance of the system upon receiving an input indicative of a request to launch an application and decreasing the performance of the system upon receiving a notification that the Application has successfully launched. On Android® platforms, a... Intel Corporation

02/01/18 / #20180032414

High performance persistent memory

Embodiments are generally directed to high capacity energy backed memory with off device storage. A memory device includes a circuit board; multiple memory chips that are installed on the circuit board; a controller to provide for backing up contents of the memory chips when a power loss condition is detected;... Intel Corporation

02/01/18 / #20180032429

Techniques to allocate regions of a multi-level, multi-technology system memory to appropriate memory access initiators

A method is described. The method includes recognizing different latencies and/or bandwidths between different levels of a system memory and different memory access requestors of a computing system. The system memory includes the different levels and different technologies. The method also includes allocating each of the memory access requestors with... Intel Corporation

02/01/18 / #20180032710

Identity-based content access control

In embodiments, apparatuses, methods and storage media are described that are associated with performing identity-based access control for content. A content consumption device may be configured to control access to presented content based on identities of one or more content consumers that are physically proximate to the device. The content... Intel Corporation

Patent Packs
02/01/18 / #20180032765

Methods, systems and apparatus to improve radio frequency identification (rfid) tag communication

Methods, systems, apparatus, and articles of manufacture are disclosed to improve radio frequency identification (RFID) tag communication. An example disclosed apparatus includes an RFID reader monitor to activate a first RFID reader and deactivate a second RFID reader during a first tag data acquisition at a first time, and deactivate... Intel Corporation

02/01/18 / #20180032844

Object recognition based on boosting binary convolutional neural network features

Techniques related to implementing convolutional neural networks for object recognition are discussed. Such techniques may include generating a set of binary neural features via convolutional neural network layers based on input image data and applying a strong classifier to the set of binary neural features to generate an object label... Intel Corporation

02/01/18 / #20180032857

Method and performing different types of convolution operations with the same processing elements

A method for implementing a convolutional neural network (CNN) accelerator on a target includes utilizing one or more processing elements to perform convolution. A configuration of the CNN accelerator is modified to change filters implemented by the CNN accelerator and to change formatting of output data. The one or more... Intel Corporation

02/01/18 / #20180033116

Apparatus and software-agnostic multi-gpu processing

An apparatus and method are described for a software agnostic multi-GPU implementation. For example, one embodiment of an apparatus comprises: a plurality of physical graphics processor units (pGPUs) to execute graphics commands; a graphics driver to receive graphics commands generated from applications via a graphics application programming interface (API); a... Intel Corporation

02/01/18 / #20180033593

Fine alignment system for electron beam exposure system

Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a method of fine alignment of an e-beam tool includes projecting an electron image of a plurality of apertures of an e-beam column over an X-direction alignment feature of a wafer while moving the... Intel Corporation

02/01/18 / #20180033648

Embedded semiconductive chips in reconstituted wafers, and systems containing same

A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of... Intel Corporation

02/01/18 / #20180033692

Previous layer self-aligned via and plug patterning for back end of line (beol) interconnects

Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an integrated circuit includes a first layer disposed above a substrate. The first layer of the interconnect structure includes a grating of alternating metal lines and dielectric... Intel Corporation

02/01/18 / #20180033707

Selective metallization of an integrated circuit (ic) substrate

Embodiments of the present disclosure describe selective metallization of an integrated circuit (IC) substrate. In one embodiment, an integrated circuit (IC) substrate may include a dielectric material and metal crystals having a polyhedral shape dispersed in the dielectric material and bonded with a ligand that is to ablate when exposed... Intel Corporation

02/01/18 / #20180033741

Electronic package that includes multi-layer stiffener

An electronic package that includes a substrate and a die attached to the substrate. The electronic package further includes a stiffener that is attached to the substrate adjacent to the die. The stiffener is formed of a first layer made from one material and a second layer made from a... Intel Corporation

02/01/18 / #20180033875

Forming a non-planar transistor having a quantum well channel

In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer... Intel Corporation

02/01/18 / #20180034136

Wearable electronic device with detachable antenna support

Embodiments herein relate to the detection and switchable use of a detachable GNSS antenna with a wearable electronic device. In various embodiments, a wearable electronic apparatus may include a multi-band antenna to receive satellite positioning signals in a first frequency band and local radio frequency communication signals in a second... Intel Corporation

02/01/18 / #20180034946

Apparatus, system and controlling data flow over a communication network

Some demonstrative embodiments include apparatuses, systems and/or methods of controlling data flow over a communication network. For example, an apparatus may include a communication unit to communicate between first and second devices a transfer response, the transfer response in response to a transfer request, the transfer response including a transfer... Intel Corporation

02/01/18 / #20180035302

Higher order mu-mimo for lte-a

An access node of a 3GPP LTE-based wireless communication network comprises a transmitter portion that transmits downlink control information (DCI) to at least one wireless station of a plurality of wireless stations wirelessly accessing the node as a Multi-User Multiple Input Multiple Output (MU-MIMO) wireless communication network. The DCI comprises... Intel Corporation

02/01/18 / #20180035368

Blacklisting techniques for detected set event evaluation

Blacklisting techniques for detected set event evaluation are described. In one embodiment, for example, user equipment (UE) may comprise at least one radio frequency (RF) transceiver, at least one RF antenna, and logic, at least a portion of which is in hardware, the logic to receive a measurement control message... Intel Corporation

02/01/18 / #20180035410

Resource allocation techniques for device-to-device (d2d) communications

Resource allocation techniques for D2D communications are described. In one embodiment, for example, user equipment may comprise one or more radio frequency (RF) transceivers, one or more RF antennas, and logic, at least a portion of which is in hardware, the logic to receive a D2D control information (D2DCI) message... Intel Corporation

Patent Packs
02/01/18 / #20180035431

Multiband central controller and multiband network operations

Embodiments of a multiband central controller, a multiband communication station and methods for multiband network operations are generally described herein. In some embodiments, the central controller may be configured for multiband operations within non-coextensive frequency bands. The central controller may transmit a response frame to a receiving station that includes... Intel Corporation

02/01/18 / #20180035572

Power thermal awareness solution

One embodiment provides an apparatus. The apparatus includes power thermal awareness solution (PTAS) logic to select a model from a plurality of models based, at least in part, on a configuration of a cooling zone; and determine a cooling zone volumetric airflow based, at least in part, on the selected... Intel Corporation

01/25/18 / #20180020982

Wellness monitoring using a patch system

Discussed generally herein are methods and devices including or providing a wellness monitoring system. The wellness monitoring system can include a first patch including a flexible, stretchable first substrate, a first adhesive on the first substrate, the first adhesive configured to attach the first patch to skin of a user,... Intel Corporation

01/25/18 / #20180021677

Floor-based game management

Systems and methods may provide for determining an identity of an interchangeable overlay adjacent to a detection mat of a floor-based game management apparatus and detecting foot-based user input via an array of sensors distributed across a surface of the detection mat. Additionally, game-related user feedback may be output via... Intel Corporation

01/25/18 / #20180024306

Technologies for blind mating for sled-rack connections

Technologies for blind mating of optical connectors in a rack of a data center are disclosed. In the illustrative embodiment, a sled can be slid into a rack and an optical connector on the sled will blindly mate with a corresponding optical connector on the rack. The illustrative optical connector... Intel Corporation

01/25/18 / #20180024739

Memory sharing for physical accelerator resources in a data center

Examples may include sleds for a rack in a data center including physical accelerator resources and memory for the accelerator resources. The memory can be shared between the accelerator resources. One or more memory controllers can be provided to couple the accelerator resources to the memory to provide memory access... Intel Corporation

01/25/18 / #20180024752

Technologies for low-latency compression

Technologies for low-latency compression in a data center are disclosed. In the illustrative embodiment, a storage sled compresses data with a low-latency compression algorithm prior to storing the data. The latency of the compression algorithm is less than the latency of the storage device, so that the latency of the... Intel Corporation

01/25/18 / #20180024756

Technologies for enhanced memory wear leveling

Technologies for enhanced memory wear leveling is disclosed. In the illustrative embodiment, a storage controller on a storage sled performs wear leveling across several storage devices. For example, the storage controller may copy hot data from one storage device that has a high number of erasures to another storage device... Intel Corporation

01/25/18 / #20180024757

Accelerator resource allocation and pooling

Examples may include techniques to allocate physical accelerator resources from pools of accelerator resources. In particular, virtual computing devices can be composed from physical resources and physical accelerator resources dynamically allocated to the virtual computing devices. The present disclosure provides that physical accelerator resources can be dynamically allocated, or composed,... Intel Corporation

01/25/18 / #20180024761

Apparatus for data retention and supply noise mitigation using clamps

An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node... Intel Corporation

01/25/18 / #20180024764

Technologies for accelerating data writes

Technologies for accelerating data writes include a managed node that includes a network interface controller that includes a power loss protected buffer and non-volatile memory. The managed node is to receive, through the network interface controller, a write request from a remote device. The write request includes a data block.... Intel Corporation

01/25/18 / #20180024771

Storage sled and techniques for a data center

Examples may include a sled for a rack of a data center including physical storage resources. The sled comprises an array of storage devices and an array of memory. The storage devices and memory are directly coupled to storage resource processing circuits which are themselves, directly coupled to dual-mode optical... Intel Corporation

01/25/18 / #20180024775

Technologies for storage block virtualization for non-volatile memory over fabrics

Technologies for storage block virtualization include multiple computing devices in communication over an optical fabric. A computing device receives a non-volatile memory (NVM) I/O command from an application via an optical fabric interface. The NVM I/O command is indicative of one or more virtual data storage blocks. The computing device... Intel Corporation

01/25/18 / #20180024776

Technologies for performing partially synchronized writes

Technologies for managing partially synchronized writes include a managed node. The managed node is to issue a write request to write a data block, on behalf of a workload, to multiple data storage devices connected to a network, pause execution of the workload, receive an initial acknowledgment associated with one... Intel Corporation

01/25/18 / #20180024838

Techniques to detect non-enumerable devices via a firmware interface table

Embodiments are generally directed to apparatuses, method, techniques, and so forth including a memory coupled to processing circuitry, wherein the memory stores a firmware interface table and the firmware interface table comprises an entry to identify a non-enumerable resource. Embodiments include accessing the firmware interface table to identify the non-enumerable... Intel Corporation

01/25/18 / #20180024854

Technologies for virtual machine migration

Technologies for virtual machine migration are disclosed. A plurality of virtual machines may be established on a source node at varying tiers of quality-of-service. The source node may identify a set of virtual machines from the plurality of virtual machines having a lower or lowest tier of quality-of-service. Additionally, the... Intel Corporation

01/25/18 / #20180024855

Live migration of virtual machines from/to host computers with graphics processors

Apparatuses, methods and storage medium associated with live migration of VMs from/to host computers with graphics virtualization are disclosed herein. In embodiments, an apparatus may include a VMM having a memory manager to manage accesses of system memory of the apparatus, including tracking of modified memory pages of the system... Intel Corporation

01/25/18 / #20180024861

Technologies for managing allocation of accelerator resources

Technologies for dynamically managing the allocation of accelerator resources include an orchestrator server. The orchestrator server is to assign a workload to a managed node for execution, determine a predicted demand for one or more accelerator resources to accelerate the execution of one or more jobs within the workload, provision,... Intel Corporation

01/25/18 / #20180024864

Memory module for a data center compute sled

Examples may include a sled for a rack of a data center including physical compute resources. The sled comprises a processor component and a unitary memory module comprising a memory controller and a quantity of memory based on the processor component. The unitary memory module can comprise a quantity of... Intel Corporation

01/25/18 / #20180024867

Technologies for dynamic allocation of tiers of disaggregated memory resources

Technologies for dynamically allocating tiers of disaggregated memory resources include a compute device. The compute device is to obtain target performance data, determine, as a function of target performance data, memory tier allocation data indicative of an allocation of disaggregated memory sleds to tiers of performance, in which one memory... Intel Corporation

01/25/18 / #20180024878

Extracting selective information from on-die dynamic random access memory (dram) error correction code (ecc)

Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request... Intel Corporation

01/25/18 / #20180024925

Increasing invalid to modified protocol occurrences in a computing system

An example system on a chip (SoC) includes a processor, a cache, and a main memory. The SoC can include a first memory to store data in a memory line, wherein the memory line is set to an invalid state. The processor can include a processor coupled to the first... Intel Corporation

01/25/18 / #20180024937

Caching and tiering for cloud storage

Various systems and methods for caching and tiering in cloud storage are described herein. A system for managing storage allocation comprises a storage device management system to maintain an access history of a plurality of storage blocks of solid state drives (SSDs) managed by the storage device management system; and... Intel Corporation

01/25/18 / #20180024940

Systems and methods for accessing a unified translation lookaside buffer

Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes... Intel Corporation

01/25/18 / #20180024947

Technologies for a low-latency interface to data storage

Technologies for a low-latency interface with data storage of a storage sled in a data center are disclosed. In the illustrative embodiment, a storage sled stores metadata including the location of data in a storage device in low-latency non-volatile memory. When accessing data, the storage sled may access the metadata... Intel Corporation

01/25/18 / #20180024955

Computer architecture to provide flexibility and/or scalability

Apparatus, systems, and/or methods may include a peripheral component interconnect express (PCIe) link to directly couple a slot with a network fabric. The slot may be defined by a surface and/or may accommodate a hardware module. A rack unit implementation may be utilized, such as a one rack unit (1U)... Intel Corporation

01/25/18 / #20180024960

Techniques to support multiple interconnect protocols for a common set of interconnect connectors

Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of... Intel Corporation

01/25/18 / #20180025032

Image storage and retrieval based on eye movements

Various embodiments are generally directed to creating and using an index based on eye movements of the human eye to store and retrieve images in an image database. An apparatus comprises a processor circuit and a storage communicatively coupled to the processor circuit and storing instructions operative on the processor... Intel Corporation

01/25/18 / #20180025183

Management of authenticated variables

An embodiment includes an apparatus comprising: an out-of-band cryptoprocessor coupled to secure non-volatile storage; and at least one storage medium having firmware instructions stored thereon for causing, during runtime and after an operating system for the apparatus has booted, the cryptoprocessor to (a) store a key within the secure non-volatile... Intel Corporation

01/25/18 / #20180025465

Gpu accelerated address translation for graphics virtualization

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing GPU (Graphics Processing Unit) accelerated address translation for graphics virtualization. In one embodiment, such a system includes a main memory having a plurality of machine physical addresses; a graphics processor unit having graphics... Intel Corporation

Social Network Patent Pack
01/25/18 / #20180025506

Avatar-based video encoding

Techniques are disclosed for performing avatar-based video encoding. In some embodiments, a video recording of an individual may be encoded utilizing an avatar that is driven by the facial expression(s) of the individual. In some such cases, the resultant avatar animation may accurately mimic facial expression(s) of the recorded individual.... Intel Corporation

01/25/18 / #20180025562

Smart door

A device associated with a door for implementing a smart door system is proposed in this disclosure. The device comprises a sensor circuit comprising one or more sensors configured to collect information associated with an object in a predefined area surrounding the door. The device further comprises a processing circuit... Intel Corporation

01/25/18 / #20180025720

Optimizations to decoding of wfst models for automatic speech recognition

A method in a computing device for decoding a weighted finite state transducer (WFST) for automatic speech recognition is described. The method includes sorting a set of one or more WFST arcs based on their arc weight in ascending order. The method further includes iterating through each arc in the... Intel Corporation

01/25/18 / #20180025764

Magnetic field-assisted memory operation

In one embodiment, a magnetoresistance random access memory (MRAM) such as a spin transfer torque (STT) random access memory (RAM), for example, has a subarray of bitcells and an electro-magnet positioned adjacent the subarray. A magnetic field is directed through a ferromagnetic device of bitcells of the first subarray to... Intel Corporation

01/25/18 / #20180025771

Directed per bank refresh command

A memory device includes a per bank refresh counter applicable to multiple banks in a group. The memory device increments a row address counter only when the per bank refresh counter is reset. The memory device receives a per bank refresh command from an associated memory controller, and performs a... Intel Corporation

01/25/18 / #20180025773

Precharging and refreshing banks in memory device with bank group architecture

Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in... Intel Corporation

01/25/18 / #20180026097

N-channel gallium nitride transistors

The present description relates to n-channel gallium nitride transistors which include a recessed gate electrode, wherein the polarization layer between the gate electrode and the gallium nitride layer is less than about 1 nm. In additional embodiments, the n-channel gallium nitride transistors may have an asymmetric configuration, wherein a gate-to... Intel Corporation

01/25/18 / #20180026477

Power management system

A power supply system includes at least one power supply module and at least one redundant power supply module. A power supply module may include a charging resistor in parallel with an OR-ing device to keep all filter capacitors charged as long as at least one power supply module remains... Intel Corporation

01/25/18 / #20180026631

Biasing scheme for high voltage circuits using low voltage devices

Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the... Intel Corporation

01/25/18 / #20180026651

Technologies for performing low-latency decompression with tree caching

Technologies for performing low-latency decompression include a managed node to parse, in response to a determination that a read tree descriptor does not match a cached tree descriptor, the read tree descriptor to construct one or more tables indicative of codes in compressed data. Each code corresponds to a different... Intel Corporation

Patent Packs
01/25/18 / #20180026652

Technologies for efficiently compressing data with multiple hash tables

Technologies for compressing data with multiple hash tables include a compute device. The compute device is to produce, for each of multiple string prefixes of different string prefix sizes, an associated hash. Each string prefix defines a set of consecutive symbols in a string that starts at a present position... Intel Corporation

01/25/18 / #20180026653

Technologies for efficiently compressing data with run detection

Technologies for efficiently compressing data with run detection include a compute device. The compute device is to produce a hash as a function of a symbol at a present position and a predefined number of symbols after the present position in an input stream, determine whether the symbol at the... Intel Corporation

01/25/18 / #20180026654

Technologies for high-performance single-stream lz77 compression

Technologies for high-performance single-stream data compression include a computing device that updates an index data structure based on an input data stream. The input data stream is divided into multiple chunks. Each chunk has a predetermined length, such as 136 bytes, and overlaps the previous chunk by a predetermine amount,... Intel Corporation

01/25/18 / #20180026655

Technologies for performing speculative decompression

Technologies for performing speculative decompression include a managed node to decode a variable size code at a present position in compressed data with a deterministic decoder and concurrently perform speculative decodes over a range of subsequent positions in the compressed data, determine the position of the next code, determine whether... Intel Corporation

01/25/18 / #20180026656

Technologies for heuristic huffman code generation

Technologies for heuristic Huffman code generation include a computing device that generates a weighted list of symbols for a data block. The computing device determines a threshold weight and identifies one or more lightweight symbols in the list that have a weight less than or equal to the threshold weight.... Intel Corporation

01/25/18 / #20180026695

Extending association beamforming training

Apparatuses, computer readable media, and methods for extending association beamforming training are disclosed. An apparatus is disclosed including processing circuitry. The processing circuitry being configured to decode an enhanced directional multi-gigabit (EDMG) beacon comprising a multiplier field and a length field of an association beamforming training (A-BFT) interval. The processing... Intel Corporation

01/25/18 / #20180026711

Communication system

A system is provided where one of a broadband termination unit or a gateway unit is supplied with power by the other one of the broadband termination unit or the gateway unit. Supplying may be done via a universal serial bus cable like a universal serial bus Type-C cable.... Intel Corporation

01/25/18 / #20180026730

Patch system for in-situ therapeutic treatment

Discussed generally herein are methods and devices including or providing a patch system that can help in diagnosing a medical condition and/or provide therapy to a user. A body-area network can include a plurality of communicatively coupled patches that communicate with an intermediate device. The intermediate device can provide data... Intel Corporation

01/25/18 / #20180026749

Apparatus, system and communicating a single carrier (sc) transmission

Some demonstrative embodiments include apparatus, system and method of communicating a Single Carrier (SC) transmission. For example, an apparatus of a SC Physical Layer (PHY) transmitter may include a spatial stream parser to distribute encoded bits of a Physical Layer Convergence Procedure (PLCP) Service Data Unit (PSDU) to a plurality... Intel Corporation

01/25/18 / #20180026775

Methods and devices for self-interference cancelation

A communication circuit arrangement includes a signal path circuit configured to separately apply a kernel dimension filter and a delay tap dimension filter to an input signal for an amplifier to obtain an estimated interference signal, a cancelation circuit configured to subtract the estimated interference signal from a received signal... Intel Corporation

01/25/18 / #20180026835

Techniques to control system updates and configuration changes via the cloud

Embodiments are generally directed apparatuses, methods, techniques and so forth determine an access level of operation based on an indication received via one or more network links from a pod management controller, and enable or disable a firmware update capability for a firmware device based on the access level of... Intel Corporation

01/25/18 / #20180026851

Technologies for data center multi-zone cabling

Technologies for connecting data cables in a data center are disclosed. In the illustrative embodiment, racks of the data center are grouped into different zones based on the distance from the racks in a given zone to a network switch. All of the racks in a given zone are connected... Intel Corporation

01/25/18 / #20180026868

Methods and apparatus to reduce static and dynamic fragmentation impact on software-defined infrastructure architectures

Techniques for reducing fragmentation in software-defined infrastructures are described. A compute node, including one or more processor circuits, may be configured to access one or more remote resources via a fabric, the compute node may be configured to receive a dynamic tolerated fragmentation for the one or more remote resources.... Intel Corporation

01/25/18 / #20180026882

Techniques to process packets in a dual-mode switching environment

Various embodiments are generally directed to an apparatus, method and other techniques to receive a packet via an optical fabric, the packet comprising a switch mode indicator, determine a switch mode for the packet based on the switch mode indicator, and process the packet in accordance with a first protocol... Intel Corporation

01/25/18 / #20180026904

Technologies for allocating resources within a self-managed node

Technologies for dynamically allocating resources within a self-managed node include a self-managed node to receive quality of service objective data indicative of a performance objective of one or more workloads assigned to the self-managed node. Each workload includes one or more tasks. The self-managed node is also to execute the... Intel Corporation

01/25/18 / #20180026907

Technologies for allocating ephemeral data storage among manged nodes

Technologies for allocating ephemeral data storage among managed nodes include an orchestrator server to receive ephemeral data storage availability information from the managed nodes, receive a request from a first managed node of the managed nodes to allocate an amount of ephemeral data storage as the first managed node executes... Intel Corporation

01/25/18 / #20180026908

Techniques to configure physical compute resources for workloads via circuit switching

Embodiments are generally directed apparatuses, methods, techniques and so forth to select two or more processing units of the plurality of processing units to process a workload, and configure a circuit switch to link the two or more processing units to process the workload, the two or more processing units... Intel Corporation

01/25/18 / #20180026912

Methods and composite node malleability for disaggregated architectures

Techniques for increasing malleability in software-defined infrastructures are described. A compute node, including one or more processor circuits, may be configured to access one or more remote resources via a fabric, the compute node may be configured to monitor utilization of the one or more remote resources. The compute node... Intel Corporation

01/25/18 / #20180026981

Secure sensor data transport and processing

The present disclosure is directed to secure sensor data transport and processing. End-to-end security may prevent attackers from altering data during the sensor-based security procedure. For example, following sensor data capture execution in a device may be temporarily suspended. During the suspension of execution, sensor interface circuitry in the device... Intel Corporation

01/25/18 / #20180027059

Technologies for distributing data to improve data throughput rates

Technologies for managing distributed data to improve data throughput rates include a managed node to distribute a dataset over multiple data storage devices coupled to a network. Each data storage device has a peak data throughput rate. The managed node is further to request a corresponding portion of the dataset... Intel Corporation

01/25/18 / #20180027062

Technologies for dynamically managing resources in disaggregated accelerators

Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic... Intel Corporation

01/25/18 / #20180027063

Techniques to determine and process metric data for physical resources

Various embodiments are generally directed to an apparatus, method and other techniques for communicating metric data between a plurality of management controllers for sleds via an out-of-band (OOB) network, the sleds comprising physical resources and the metric data to indicate one or more metrics for the physical resources. Embodiments may... Intel Corporation

01/25/18 / #20180027066

Technologies for managing the efficiency of workload execution

Technologies for managing the efficiency of workload execution in a managed node include a managed node that includes one or more processors that each include multiple cores. The managed nodes is to execute threads of workloads assigned to the managed node, generate telemetry data indicative of an efficiency of execution... Intel Corporation

01/25/18 / #20180027067

Methods and sdi support for fast startup

Techniques for fast startup for composite nodes in software-defined infrastructures (SDI) are described. A SDI system may include an SDI manager component, including one or more processor circuits to access one or more remote resources, the SDI manager component may including a node manager to determine, based upon one or... Intel Corporation

01/25/18 / #20180027093

Methods and sdi support for automatic and transparent migration

Techniques for migration for composite nodes in software-defined infrastructures (SDI) are described. A SDI system may include a SDI manager component, including one or more processor circuits, configured to access one or more remote resources, the SDI manager component may include a partition manager configured to receive a request to... Intel Corporation

01/25/18 / #20180027177

Workload scheduler for computing devices with camera

Techniques are disclosed to control a camera device such that memory contention and power consumption is reduced during video processing routines, generally referred to herein as media tasks. In particular, a workload scheduler is implemented in a camera HAL and is configured to dispatch captured image frames in an alternating... Intel Corporation

01/25/18 / #20180027251

Decoder for playing big frames

The decode time of big frames may be reduced by starting big frame decoding much earlier than normal decoding order. In a multi-threaded decoder, decoding one frame can be divided into several stages and stages of different frames can run in parallel like a pipeline. The first stage may be... Intel Corporation

01/25/18 / #20180027310

Interchangeable charm messaging wearable electronic device for wireless communication

Particular embodiments described herein provide for a wearable electronic device, such as a bracelet, coupled to a plurality of electronic components (which may include any type of components, elements, circuitry, etc.). One particular implementation of a wearable electronic device may include a bracelet portion, and at least one charm device... Intel Corporation

01/25/18 / #20180027312

Technologies for switching network traffic in a data center

Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory... Intel Corporation

01/25/18 / #20180027313

Technologies for optical communication in rack clusters

Technologies for optical communication in a rack cluster in a data center are disclosed. In the illustrative embodiment, a network switch is connected to each of 1,024 sleds by an optical cable that enables communication at a rate of 200 gigabits per second. The optical cable has low loss, allowing... Intel Corporation

Patent Packs
01/25/18 / #20180027376

Configurable computing resource physical location determination

Examples may include techniques to determine locations of a physical resource in a data center. A data center can include a number of racks having sled spaced. The sled spaces accommodate sleds having one or more physical resources disposed on each sled. The racks and sleds can include a beacon... Intel Corporation

01/25/18 / #20180027442

Periodic channel state information reporting for time division duplex (tdd) carrier aggregation systems

Technology for a user equipment (UE) operable to report periodic channel state information (CSI) to an eNodeB is disclosed. The UE can determine a reporting period (Npd) of a serving cell of the UE. The UE can determine a Time-Division Duplex (TDD) uplink-downlink (UL-DL) configuration of a primary cell of... Intel Corporation

01/25/18 / #20180027516

Evolved node-b and user equipment and methods for operation in a coverage enhancement mode

Embodiments of an eNB to operate in accordance with a coverage enhancement mode are disclosed herein. The eNB may comprise hardware processing circuitry to, during a legacy sub-frame, transmit a system information block (SIB) in legacy SIB frequency resources according to a legacy SIB transmission format and refrain from transmission... Intel Corporation

01/25/18 / #20180027679

Disaggregated physical memory resources in a data center

Examples may include sleds for a rack in a data center including physical compute resources and memory for the physical compute resources. The memory can be disaggregated, or organized into near and far memory. A first sled can comprise the physical compute resources and a first set of physical memory... Intel Corporation

01/25/18 / #20180027682

Thermally efficient compute resource apparatuses and methods

Examples may include racks for a data center and sleds for the racks, the sleds arranged to house physical resources for the data center. The sleds can house physical resources and heat sinks thermally coupled to the physical resources. The physical resources are arranged on the sleds and the heat... Intel Corporation

01/25/18 / #20180027684

Storage sled for data center

Examples may include a sled for a rack of a data center including physical storage resources. The sled comprises an array of storage devices and an array of memory. The storage devices and memory are directly coupled to storage resource processing circuits which are themselves, directly coupled to dual-mode optical... Intel Corporation

01/25/18 / #20180027685

Storage sled for a data center

Examples may include a sled for a rack of a data center including physical storage resources. The sled comprises mounting flanges to enable robotic insertion and removal from a rack and storage device mounting slots to enable robotic insertion and removal of storage devices into the sled. The storage devices... Intel Corporation

01/25/18 / #20180027686

Robotically serviceable computing rack and sleds

Examples may include racks for a data center and sleds for the racks, the sleds arranged to house physical resources for the data center. The sleds and racks can be arranged to be autonomously manipulated, such as, by a robot. The sleds and racks can include features to facilitate automated... Intel Corporation

01/25/18 / #20180027687

Technologies for sled architecture

A sled for operation in a corresponding rack of a data center includes a chassis-less circuit board substrate having one or more physical resources coupled to a top side of the chassis-less circuit board and one or more memory devices coupled to a bottom side of the chassis-less circuit board.... Intel Corporation

01/25/18 / #20180027700

Technologies for rack architecture

A rack for supporting a sleds includes a pair of elongated support posts and pairs of elongated support arms that extend from the elongated support posts. Each pair of the elongated support arms defines a sled slot to receive a corresponding sled. To do so, each elongated support arm includes... Intel Corporation

01/25/18 / #20180027703

Technologies for rack cooling

Technologies for rack cooling includes monitoring a temperature of a sled mounted in a rack and controlling a cooling system of the rack based on the temperature of the sled. The cooling system includes a cooling fan array, which may be controlled to cool the sled. Additionally, if needed, one... Intel Corporation








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