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Invensas Corporation
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Invensas Corporation patents

Recent patent applications related to Invensas Corporation. Invensas Corporation is listed as an Agent/Assignee. Note: Invensas Corporation may have other listings under different names/spellings. We're not affiliated with Invensas Corporation, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "I" | Invensas Corporation-related inventors




Date Invensas Corporation patents (updated weekly) - BOOKMARK this page
04/27/17 new patent  Dram adjacent row disturb mitigation
04/27/17 new patent  Wire bond wires for interference shielding
04/27/17 new patent  Anchoring structure of fine pitch bva
04/27/17 new patent  Microelectronic package for wafer-level chip scale packaging with fan-out
04/27/17 new patent  Rear-face illuminated solid state image sensors
04/13/17Fan-out wafer-level packaging using metal foil lamination
04/13/17Embedded wire bond wires
04/06/17Microelectronic interconnect element with decreased conductor spacing
04/06/17Hd color imaging using monochromatic cmos image sensors integrated in 3d package
04/06/17Interposers and fabrication methods that use nanoparticle inks and magnetic fields
03/30/17Capacitive coupling of integrated circuit die components
03/23/17Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies
03/23/17Compact semiconductor package and related methods
03/23/17Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
03/16/17Wafer-level flipped die stacks with leadframes or metal foil interconnects
03/16/17Making electrical components in handle wafers of integrated circuit packages
03/09/17Microelectronic assembly with redistribution structure formed on carrier
03/09/17Wafer-level packaging using wire bond wires in place of a redistribution layer
03/09/173d-joining of microelectronic components with conductively self-adjusting anisotropic matrix
03/09/17Microelectronic package with horizontal and vertical interconnections
03/02/17Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
02/23/17Low cte interposer
02/23/17Tall and fine pitch interconnects
02/16/17Structures and methods for low temperature bonding
02/09/17Integrated circuits protected by substrates with cavities, and methods of manufacture
02/09/17Interconnections for a substrate associated with a backside reveal
02/09/17Methods and structures to repair device warpage
02/02/17Stacked die integrated circuit
01/26/17Microelectronic element with bond elements to encapsulation surface
01/19/17Flipped die stack assemblies with leadframe interconnects
01/19/17Microelectronic assemblies with cavities, and methods of fabrication
01/19/17Microelectronic assemblies formed using metal silicide, and methods of fabrication
01/19/17Flipped die stack
01/12/17Structures and methods for low temperature bonding
12/29/16Structures and methods for reliable packages
12/29/16Laminated interposers and packages with embedded trace interconnects
12/15/16Reversed build-up substrate for 2.5d
11/24/16Through-dielectric-vias (tdvs) for 3d integrated circuits in silicon
11/17/16Conductive connections, structures with such connections, and methods of manufacture
11/10/16Reliable device assembly
11/10/16Ball bonding metal wire bond wires to metal pads
11/10/16New 2.5d microelectronic assembly and method with circuit structure formed on carrier
11/10/16Method for preparing low cost substrates
11/10/16Wire bond support structure and microelectronic package including wire bonds therefrom
11/10/16Ssi pop
11/03/16Coupling of side surface contacts to a circuit platform
11/03/16Wafer-level packaging using wire bond wires in place of a redistribution layer
11/03/16Making multilayer 3d capacitors using arrays of upstanding rods or ridges
10/27/16Preferred state encoding in non-volatile memories
10/27/16Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates
10/20/16Reliable packaging and interconnect structures
10/20/16High performance compliant substrate
10/20/16Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
10/20/16Reconstituted wafer-level package dram
10/06/16Circuit assemblies with multiple interposer substrates, and methods of fabrication
10/06/16Warpage reduction in structures with electrical circuitry
09/29/16Thermal vias disposed in a substrate proximate to a well thereof
09/22/16Integrated circuit assemblies with reinforcement frames, and methods of manufacture
09/22/16Tunable composite interposer
09/22/16Stub minimization for wirebond assemblies without windows
09/15/16Reduced load memory module
09/15/16Stub minimization for assemblies without wirebonds to package substrate
09/15/16Polymer member based interconnect
09/08/16Method for package-on-package assembly with wire bonds to encapsulation surface
09/08/16Microelectronic package with consolidated chip structures
Patent Packs
09/08/16Embedded graphite heat spreader for 3dic
09/08/16Batch process fabrication of package-on-package microelectronic assemblies
09/08/16Pressing of wire bond wire tips to provide bent-over tips
09/01/16Device and localized underfill
08/25/16Microelectronic assemblies formed using metal silicide, and methods of fabrication
08/25/16Substrate-to-carrier adhesion without mechanical adhesion between abutting surfaces thereof
08/25/16Localized sealing of interconnect structures in small gaps
08/11/16Multi-die wirebond packages with elongated windows
08/04/16Off substrate kinking of bond wire
07/28/16Interposers and fabrication methods that use nanoparticle inks and magnetic fields
07/28/16Support mounted electrically interconnected die assembly
07/14/16Inverted optical device
07/07/16Thermal vias disposed in a substrate without a liner layer
07/07/16Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
06/30/16Retention optimized memory device using predictive data inversion
Patent Packs
06/30/16Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
06/30/16Contact structures with porous networks for solder connections, and methods of fabricating same
06/16/16Bond via array for thermal conductivity
06/16/16Memory module in a package
06/16/16Image sensor device
06/09/16Substrate-less stackable package with wire-bond interconnect
06/09/16Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies
06/09/16Microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
06/02/16Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication
05/12/16Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
05/05/16Substrates and methods of manufacture
04/21/16Methods of forming 3-d circuits with integrated passive devices
04/14/16Semiconductor die mount by conformal die coating
03/31/16Stub minimization using duplicate sets of signal terminals
03/31/16Compact microelectronic assembly having reduced spacing between controller and memory packages
03/31/16Bga ballout partition techniques for simplified layout in motherboard with multiple power supply rail
03/17/16Carrier-less silicon interposer
03/17/16Use of underfill tape in microelectronic components, and microelectronic components with cavities coupled to through-substrate vias
03/17/16Electronic structures strengthened by porous and non-porous layers, and methods of fabrication
03/17/16Polymer member based interconnect
03/17/16Bva interposer
03/17/16Batch process fabrication of package-on-package microelectronic assemblies
03/10/16Paddle for materials processing
03/10/16Multichip modules and methods of fabrication
02/18/16Making electrical components in handle wafers of integrated circuit packages
02/18/16Device and an integrated ultra-high-density device
02/18/16Multiple bond via arrays of different wire heights on a same substrate
02/11/16Device and localized underfill
02/11/16Porous alumina templates for electronic packages
02/04/16Reconfigurable pop
Social Network Patent Pack
02/04/16Die stacking techniques in bga memory package for small footprint cpu and memory motherboard design
02/04/16Microelectronic package with stacked microelectronic units and manufacture thereof
01/28/16Electrical connector between die pad and z-interconnect for stacked die assemblies
01/21/16Embedded packaging with preformed vias
01/21/16Selective die electrical insulation by additive process
01/14/16Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
12/31/15Microelectronic package having wire bond vias and stiffening layer
12/31/15Multiple bond via arrays of different wire heights on a same substrate
12/24/15Back-end-of-line stack for a stacked device
12/24/15Microelectronic package with consolidated chip structures
Patent Packs
12/17/15Co-support for xfd packaging
12/17/15Wafer leveled chip packaging structure and method thereof
12/17/15Making multilayer 3d capacitors using arrays of upstanding rods or ridges
12/10/15Integrated interposer solutions for 2d and 3d ic packaging
12/03/15Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor
12/03/15Low cte component with wire bond interconnects
12/03/15Wire bond support structure and microelectronic package including wire bonds therefrom
12/03/15Structure and integrated circuits packaging with increased density
11/26/15Method and structures for heat dissipating interposers
11/26/15Compact semiconductor package and related methods
11/19/15Holding of interposers and other microelectronic workpieces in position during assembly and other processing
11/19/15Structure for microelectronic packaging with bond elements to encapsulation surface
11/12/15Conductive connections, structures with such connections, and methods of manufacture
11/12/15Conductive connections, structures with such connections, and methods of manufacture
11/12/15Method of thinning a wafer to provide a raised peripheral edge
11/12/15Circuit assemblies with multiple interposer substrates, and methods of fabrication
11/05/15Making electrical components in handle wafers of integrated circuit packages
10/22/15Single package dual channel memory with co-support
10/22/15Bowl-shaped solder structure
10/15/15Light emitting diode device with reconstituted led components on substrate
10/15/15High performance light emitting diode with vias
10/01/15Batch process fabrication of package-on-package microelectronic assemblies
09/24/15Capacitors using porous alumina structures
09/24/15Method and structures for via substrate repair and assembly
09/24/15Stacked die integrated circuit
09/17/15Integrated circuits protected by substrates with cavities, and methods of manufacture
09/17/15Via structure for signal equalization
09/17/15Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication
09/17/15Integrated circuit assemblies with reinforcement frames, and methods of manufacture
09/17/15Optical enhancement of light emitting devices
Patent Packs
09/10/15Methods and structure for carrier-less thin wafer handling
09/10/15Thermal vias disposed in a substrate without a liner layer
09/10/15Package-on-package assembly with wire bond vias
09/10/15Thermal vias disposed in a substrate proximate to a well thereof
08/27/15Z-connection using electroless plating
08/20/15Advanced device assembly structures and methods
08/13/15Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates
08/13/15Front facing piggyback wafer assembly
07/30/15Retention optimized memory device using predictive data inversion
07/30/15Microelectronic unit and package with positional reversal
07/23/15Fine pitch bva using reconstituted wafer with area array accessible for testing
07/16/15Stub minimization for multi-die wirebond assemblies with parallel windows
07/16/15Stackable microelectronic package structures
07/02/15Reduced stress tsv and interposer structures
07/02/15Stackable microelectronic package structures
06/25/15Stub minimization with terminal grids offset from center of package
06/18/15High yield substrate assembly
06/18/15Quantum efficiency of multiple quantum wells
06/11/15Tunable composite interposer
06/11/15Metal pvd-free conducting structures
Social Network Patent Pack
06/04/15Carrier-less silicon interposer using photo patterned polymer as substrate
06/04/15Warpage reduction in structures with electircal circuitry
05/28/15Die stacks with one or more bond via arrays
05/28/15Substrate-to-carrier adhesion without mechanical adhesion between abutting surfaces thereof
05/28/15Multiple bond via arrays of different wire heights on a same substrate
05/28/15High strength through-substrate vias
05/21/15Via in substrate with deposited layer
05/14/15Off substrate kinking of bond wire
05/14/15Severing bond wire by kinking and twisting
05/14/15Non-crystalline inorganic light emitting diode
05/14/15Heat spreading substrate with embedded interconnects
05/07/15Microelectronic package and manufacture thereof
04/30/15Embedded heat spreader for package with multiple microelectronic elements and face-down connection
04/30/15Co-support for xfd packaging
04/16/15Cavities containing multi-wiring structures and devices
04/09/15Method for preparing low cost substrates
04/09/15Interconnections for a substrate associated with a backside reveal
04/09/15Bowl-shaped solder structure
04/02/15Rear-face illuminated solid state image sensors
04/02/15Multi-die wirebond packages with elongated windows
Social Network Patent Pack
03/26/15Microelectronic interconnect element with decreased conductor spacing
03/19/15Microelectronic element with bond elements to encapsulation surface
03/12/15Substrate-less stackable package with wire-bond interconnect
02/26/15Semiconductor die having fine pitch electrical interconnects
02/12/15Micro mechanical anchor for 3d architecture
02/12/15Ultra high performance interposer
02/12/15Embedded packaging with preformed vias
02/12/15Method of fabricating low cte interposer without tsv structure
02/12/15Microelectronic package with integrated bearing surfaces
02/05/15Structure for microelectronic packaging with bond elements to encapsulation surface
01/15/15Thin wafer handling and known good die test method
01/15/15Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
01/15/15Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
01/15/15Microelectronic assembly with thermally and electrically conductive underfill
01/15/15Method for package-on-package assembly with wire bonds to encapsulation surface
01/01/15Semiconductor device and manufacturing same
12/25/14Reliable device assembly
12/18/14Memory module in a package
12/11/14Single package dual channel memory with co-support
11/20/14Metal pvd-free conducting structures
11/13/14Methods of forming 3-d circuits with integrated passive devices
11/06/14Stub minimization for wirebond assemblies without windows
11/06/14Stub minimization for multi-die wirebond assemblies with parallel windows
10/23/14Retention optimized memory device using predictive data inversion
10/23/14Method of processing a device substrate
09/18/14Porous alumina templates for electronic packages
09/18/14Microelectronic elements with master/slave configurability
09/18/14Low cte interposer without tsv structure
09/18/14Capacitors using porous alumina structures
09/18/14In-package fly-by signaling
Social Network Patent Pack
08/28/14Microelectronic unit and package with positional reversal
08/28/14Microelectronic package with consolidated chip structures
08/28/14Multilayer wiring board for an electronic device
08/28/14Carrier-less silicon interposer
08/14/14Microelectronic assembly with multi-layer support structure
08/07/14Wafer leveled chip packaging structure and method thereof
08/07/14Reduced stress tsv and interposer structures
08/07/14Multi-die wirebond packages with elongated windows
08/07/14Microelectronic package having wire bond vias and stiffening layer
08/07/14Method of making wire bond vias and microelectronic package having wire bond vias
07/31/14Microelectronic package with stacked microelectronic units and manufacture thereof
07/31/14Semiconductor die mount by conformal die coating
07/24/14Microelectronic package and manufacture thereof
07/17/14Stackable microelectronic package structures
07/03/14Stub minimization using duplicate sets of signal terminals
06/26/14Non-crystalline inorganic light emitting diode
06/26/14Surface modified tsv structure and methods thereof
06/26/14Structure for microelectronic packaging with bond elements to encapsulation surface
06/26/14Thin wafer handling
06/26/14Methods and structure for carrier-less thin wafer handling
06/19/14Method and structures for heat dissipating interposers
06/19/14Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
06/19/14Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
06/12/14High performance package on package
06/12/14Method and structures for via substrate repair and assembly
06/05/14Advanced device assembly structures and methods
05/22/14Flip chip package for dram with two underfill materials
05/22/14Chips with high fracture toughness through a metal ring
05/15/14Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques







ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009



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