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Lattice Semiconductor Corporation patents

Recent patent applications related to Lattice Semiconductor Corporation. Lattice Semiconductor Corporation is listed as an Agent/Assignee. Note: Lattice Semiconductor Corporation may have other listings under different names/spellings. We're not affiliated with Lattice Semiconductor Corporation, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "L" | Lattice Semiconductor Corporation-related inventors

Date Lattice Semiconductor Corporation patents (updated weekly) - BOOKMARK this page
05/25/17 new patent  Replica cascode bias voltage-controlled oscillators
05/18/17Beamforming based on adjacent beams systems and methods
05/18/17Beam splitting systems and methods
05/11/17Stream creation with limited topology information
04/06/17Compressed video playback with raw data assist
03/30/17Dynamic control of pixel color formats used to encode color video streams
03/23/17Echo cancellation for high speed full duplex data transmissions
03/16/17Near-field communications with multiple transmit and multiple receive antennae
03/16/17Communication of multimedia data streams over multiple communication lanes
03/02/17Maintaining synchronization of encryption process across devices by sending frame numbers
02/23/17Method of transmitting and receiving audio signals and apparatus thereof
02/09/17Acoustic gesture recognition systems and methods
02/02/17Wireless control of unmanned aerial vehicle with distance ranging and channel sensing
01/12/17Crowbar current elimination
01/05/17Driving data of multiple protocols through a single set of pins
12/22/16Phase tracking for clock and data recovery
11/24/16Delay specific routings for programmable logic devices
11/17/16Area-efficient memory mapping techniques for programmable logic devices
11/03/16Programmable circuits for correcting scan-test circuitry defects in integrated circuit designs
11/03/16Clock placement for programmable logic devices
09/29/16Enhanced echo cancellation in full-duplex communication
09/22/16Full duplex radio in wireless tunneling system
09/22/16Apparatus for role identification and power supply control in a wireless tunneling system
09/22/16Embedding low-speed communications in a high speed wireless tunneling system
09/22/16Multi-gigabit wireless tunneling system
09/01/16Phase locked loop with sub-harmonic locking prevention functionality
09/01/16Successive approximation register-based analog-to-digital converter with increased time frame for digital-to-analog capacitor settling
08/25/16Spectrum shaping voltage to current converter
08/25/16Techniques for fractional-n phase locked loops
08/18/16Partially depopulated interconnection arrays for packaged semiconductor devices and printed circuit boards
08/04/16Hotswap operations for programmable logic devices
07/28/16Registers for post configuration testing of programmable logic devices
07/14/16Radio frequency interference reduction in multimedia interfaces
07/07/16I/q imbalance correction for the combination of multiple radio frequency frontends
06/23/16Reconfigurable and scalable hardware management architecture
06/23/16Sharing a common resource via multiple interfaces
05/26/16Cable with circuitry for communicating performance information
05/12/16Class ab amplifier with programmable quiescent current
05/12/16Meta-stability prevention for oscillators
04/28/16Configuring an electronic device based on a transaction
04/28/16Level shifter with low static power dissipation
04/21/16Memory circuit having non-volatile memory cell and methods of using
04/07/16Leakage-current abatement circuitry for memory arrays
01/28/16Clock to out path optimization
01/28/16Bus-based clock to out path optimization
01/28/16Shared logic for multiple registers with asynchronous initialization
01/28/16Flexible ripple mode device implementation for programmable logic devices
01/28/16Multiple mode device implementation for programmable logic devices
01/21/16High speed complementary nmos lut logic
01/14/16System-level dual-boot capability in systems having one or more devices without native dual-boot capability
01/07/16Driving data of multiple protocols through a single set of pins
12/31/15Efficient constant multiplier implementation for programmable logic devices
12/31/15Mixed-width memory techniques for programmable logic devices
12/31/15Sram with two-level voltage regulator
12/24/15Trigger detection for post configuration testing of programmable logic devices
12/24/15Holdtime correction using input/output block delay
12/24/15Pvt compensation scheme for output buffers
12/03/15Logic absorption techniques for programmable logic devices
11/26/15Embedded memory testing using back-to-back write/read operations
11/19/15Elements to counter transmitter circuit performance limitations
11/12/15Partition based design implementation for programmable logic devices
10/29/15Configurable test address and data generation for multimode memory built-in self-testing
10/08/15Transistor matching for generation of precise current ratios
09/03/15Component placement with repacking for programmable logic devices
08/06/15Collector current driver for a bipolar junction transistor temperature transducer
Patent Packs
07/16/15Communicating with mipi-compliant devices using non-mipi interfaces
07/09/15Hot-socket circuitry
06/25/15Clock assignments for programmable logic device
06/25/15Group based routing in programmable logic device
06/04/15Esd protection using shared rc trigger
05/07/15Partially depopulated interconnection arrays for packaged semiconductor devices and printed circuit boards
04/02/15Serdes interface architecture for multi-processor systems
01/22/15Stable supply-side reference over extended voltage range with hot-plugging compatibility
11/13/14Semiconductor defect characterization
08/21/14Low-voltage current sense amplifer
05/15/14Highly secure and extensive scan testing of integrated circuits
04/17/14Leakage-current abatement circuity for memory arrays
04/17/14Loss of signal detection for high-speed serial links
04/17/14Configuration of selected modules of a hardware block within a programmable logic device
01/09/14Phase locked loop circuit with selectable feedback paths
Patent Packs
10/03/13Dual-port sram with bit line clamping
09/26/13Delaying data signals

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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Lattice Semiconductor Corporation in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Lattice Semiconductor Corporation with additional patents listed. Browse our Agent directory for other possible listings. Page by