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Lntel Corporation patents


Recent patent applications related to Lntel Corporation. Lntel Corporation is listed as an Agent/Assignee. Note: Lntel Corporation may have other listings under different names/spellings. We're not affiliated with Lntel Corporation, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "L" | Lntel Corporation-related inventors


Processors, methods, systems, and instructions to support live migration of protected containers

A processor includes a decode unit to decode an instruction that is to indicate a page of a protected container memory, and a storage location outside of the protected container memory. An execution unit, in response to the instruction, is to ensure that there are no writable references to the... Lntel Corporation

Instruction and logic to provide vector scatter-op and gather-op functionality

Instructions and logic provide vector scatter-op and/or gather-op functionality. In some embodiments, responsive to an instruction specifying: a gather and a second operation, a destination register, an operand register, and a memory address; execution units read values in a mask register, wherein fields in the mask register correspond to offset... Lntel Corporation

Blockchain system with nucleobase sequencing as proof of work

A sequence mining platform (SMP) comprises a processor, at least one machine-accessible storage medium responsive to the processor, and a sequence manager in the machine-accessible storage medium. The sequence manager is configured to use processing resources to determine a sequence of nucleobases in a nucleic acid. The storage medium also... Lntel Corporation

Method and performing a shift and exclusive or operation in a single instruction

Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.... Lntel Corporation

Packed data operation mask concatenation processors, methods, systems, and instructions

A method of an aspect includes receiving a packed data operation mask concatenation instruction. The packed data operation mask concatenation instruction indicates a first source having a first packed data operation mask, indicates a second source having a second packed data operation mask, and indicates a destination. A result is... Lntel Corporation

Method, apparatus and instructions for parallel data conversions

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first... Lntel Corporation

No-locality hint vector memory access processors, methods, systems, and instructions

A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a no-locality hint vector memory access instruction. The no-locality hint vector memory access instruction to indicate a packed data register of the plurality of packed data registers that is to have a... Lntel Corporation

Drone control registration

A drone includes technology for tracking controllers. A controller registration module (CRM) in the drone enables the drone to receive a first controller identifier from a first remote device. In response to receiving the first controller identifier, the CRM registers the first remote device as the current controller for the... Lntel Corporation

Instructions and logic to provide simd sm3 cryptographic hashing functionality

Instructions and logic provide SIMD SM3 cryptographic hashing functionality. Some embodiments include a processor comprising: a decoder to decode instructions for a SIMD SM3 message expansion, specifying first and second source data operand sets, and an expansion extent. Processor execution units, responsive to the instruction, perform a number of SM3... Lntel Corporation

Mechanism for management controllers to learn the control plane hierarchy in a data center environment

Mechanisms to enable management controllers to learn the control plane hierarchy in data center environments. The data center is configured in a physical hierarchy including multiple pods, racks, trays, and sleds and associated switches. Management controllers at various levels in a control plane hierarchy and associated with switches in the... Lntel Corporation

Optimized credit return mechanism for packet sends

Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is... Lntel Corporation

Ring protocol for low latency interconnect switch

Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer... Lntel Corporation

Processors, methods, systems, and instructions to transcode variable length code points of unicode characters

A processor includes a plurality of packed data registers. The processor also includes a decode unit to decode a packed variable length code point length determination instruction. The instruction is to indicate a first source packed data that is to have a plurality of packed variable length code points that... Lntel Corporation

Mfence and lfence micro-architectural implementation method and system

A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The... Lntel Corporation

Multiply add functional unit capable of executing scale, round, getexp, round, getmant, reduce, range and class instructions

A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruction.... Lntel Corporation

Floating point round-off amount determination processors, methods, systems, and instructions

A method of an aspect includes receiving a floating point round-off amount determination instruction. The instruction indicates a source of one or more floating point data elements, indicates a number of fraction bits after a radix point, and indicates a destination storage location. A result including one or more result... Lntel Corporation

Sending packets using optimized pio write sequences without sfences

Method and apparatus for sending packets using optimized PIO write sequences without sfences. Sequences of Programmed Input/Output (PIO) write instructions to write packet data to a PIO send memory are received at a processor supporting out of order execution. The PIO write instructions are received in an original order and... Lntel Corporation

Methods and migrating keys

A destination data processing system (DPS) receives a key migration block from a source DPS. The key migration block includes an encrypted version of a primary key. The destination DPS receives user input that identifies (a) an authentication policy and (b) a context policy. The destination DPS collects authentication data... Lntel Corporation

Enhanced positioning system using hybrid filter

The disclosure generally relates to an enhanced positioning system and method using a combination or hybrid filter. In one embodiment, Time-Of-Flight (ToF) measurements are used to determine an approximate location for a mobile device in relationship to one or more Access Points. The ToF combined with known and unknown variables... Lntel Corporation

Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions

An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the... Lntel Corporation

Time-delayed latch

A device, system, and method are described. In one embodiment, the device includes a latch. The latch at different times is located in at least a rest position and a non-rest position. The latch receiving a manipulation force to move the latch from the rest position to the non-rest position.... Lntel Corporation

Monitoring accesses of a thread to multiple memory controllers and selecting a thread processor for the thread based on the monitoring

A method of an aspect includes running a plurality of threads on a plurality of thread processors. Memory accesses, of a thread of the plurality that is running on a first thread processor of the plurality, are monitored to both a first memory through a first memory controller and a... Lntel Corporation

Rack level pre-installed interconnect for enabling cableless server/storage/networking deployment

Apparatus and methods for rack level pre-installed interconnect for enabling cableless server, storage, and networking deployment. Plastic cable waveguides are configured to couple millimeter-wave radio frequency (RF) signals between two or more Extremely High Frequency (EHF) transceiver chips, thus supporting millimeter-wave wireless communication links enabling components in the separate chassis... Lntel Corporation

Processors, methods, and systems to implement partial register accesses with masked full register accesses

A method includes receiving a packed data instruction indicating a first narrower source packed data operand and a narrower destination operand. The instruction is mapped to a masked packed data operation indicating a first wider source packed data operand that is wider than and includes the first narrower source operand,... Lntel Corporation

Method, apparatus and instructions for parallel data conversions

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first... Lntel Corporation

Method, apparatus and instructions for parallel data conversions

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first... Lntel Corporation

Method, apparatus and instructions for parallel data conversions

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first... Lntel Corporation

Method, apparatus and instructions for parallel data conversions

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first... Lntel Corporation

Sm4 acceleration processors, methods, systems, and instructions

A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4... Lntel Corporation

Techniques for selectively reducing power levels of ports and core switch logic in infiniband switches

Methods for performing power management of InfiniBand (IB) switches and apparatus and software configured to implement the methods. Power management datagrams (MADs) are used to inform IB switches that host servers connected to the IB switch's ports are to transition to a reduced-power or offline state or have returned to... Lntel Corporation

Methods and apparatus to support dynamic adjustment of graphics processing unit frequency

Disclosed methods support dynamic adjustment of graphics processing unit (GPU) frequency. According to one embodiment, a program comprises workload to execute, at least in part, on a GPU of a data processing system. A predetermined memory/compute ratio for the program is automatically retrieved, in response to the program being called... Lntel Corporation

Method and cross device automatic calibration

The disclosure relates to automatic calibration for cross devices in Wi-Fi fingerprint based areas. In an exemplary embodiment, an online device scans and obtains multiple signal strength value (RSSIoi) from local access points. The online device may access a fingerprint database and obtain a set of fingerprints. Each fingerprint includes... Lntel Corporation

Control mechanism and a hybrid hinge for electronic devices

A control mechanism and method for a hybrid hinge for electronic devices are disclosed. A particular embodiment includes: a hybrid hinge for an electronic device, the hybrid hinge comprising: a pivot; and an auxiliary component including one or more electro-magnetic or electro-mechanical devices and a variable electrical power source, the... Lntel Corporation

Floating point scaling processors, methods, systems, and instructions

A method of an aspect includes receiving a floating point scaling instruction. The floating point scaling instruction indicates a first source including one or more floating point data elements, a second source including one or more corresponding floating point data elements, and a destination. A result is stored in the... Lntel Corporation

Method and shuffling data

Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the... Lntel Corporation

02/02/17 / #20170034618

System and data transmission and power supply capability over an audio jack for mobile devices

A system and method for data transmission and power supply capability over an audio jack for mobile devices are disclosed. A particular embodiment includes: a peripheral device including an energy storage component, a microphone using a microphone bias voltage, and a select switch configured to provide a first switch position... Lntel Corporation

01/26/17 / #20170026149

Lane error detection and lane removal mechanism to reduce the probability of data corruption

Method, apparatus, and systems for detecting lane errors and removing errant lanes in multi-lane links. Data comprising link packets is split into a plurality of bitstreams and transmitted over respective lanes of a multi-lane link in parallel. The bitstream data is received at multiple receive lanes of a receiver port... Lntel Corporation

01/26/17 / #20170026150

Efficient link layer retry protocol utilizing implicit acknowledgements

Methods, apparatus, and systems for implementing a link layer retry protocol utilizing implicit ACKnowledgements (ACKs). Peer link interfaces are configured to facilitate confirmed error-free delivery of link-layer packets through use of implicit ACKs, while also providing retransmission of packets for which errors are detected and guaranteeing the link control data... Lntel Corporation

01/26/17 / #20170026300

Method and system for flexible credit exchange within high performance fabrics

Method, apparatus, and systems for implementing flexible credit exchange within high performance fabrics. Available buffer space in a receive buffer on a receive-side of a link is managed and tracked at the transmit-side of the link using credits. Peer link interfaces coupled via a link are provided with receive buffer... Lntel Corporation

01/19/17 / #20170017465

Sending packets using optimized pio write sequences without sfences

Method and apparatus for sending packets using optimized PIO write sequences without sfences. Sequences of Programmed Input/Output (PIO) write instructions to write packet data to a PIO send memory are received at a processor supporting out of order execution. The PIO write instructions are received in an original order and... Lntel Corporation

01/19/17 / #20170017487

Processors, methods, systems, and instructions to store source elements to corresponding unmasked result elements with propagation to masked result elements

A processor of an aspect includes a decode unit to decode an instruction that indicates a first source packed data operand including a first plurality of data elements, a source mask including a plurality of mask elements, and a destination storage location. An execution unit, in response to the instruction,... Lntel Corporation

01/19/17 / #20170017488

Processors, methods, systems, and instructions to store consecutive source elements to unmasked result elements with propagation to masked result elements

A processor of an aspect includes a decode unit to decode an instruction indicating a first source packed data operand including at least four data elements, a source mask including at least four mask elements, and a destination storage location. An execution unit, in response to the instruction, stores a... Lntel Corporation








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