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Lsi Corporation
Lsi Corporation_20100107
Lsi Corporation_20100114
Lsi Corporation_20100128
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Lsi Corporation patents

Recent patent applications related to Lsi Corporation. Lsi Corporation is listed as an Agent/Assignee. Note: Lsi Corporation may have other listings under different names/spellings. We're not affiliated with Lsi Corporation, we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "L" | Lsi Corporation-related inventors

Search recent Press Releases: Lsi Corporation-related press releases
Count Application # Date Lsi Corporation patents (updated weekly) - BOOKMARK this page
12015033918911/26/15  new patent  Fixed point conversion of llr values based on correlation
22015033174811/19/15 Method to dynamically update llrs in an ssd drive and/or controller
32015033176511/19/15 Coordination techniques for redundant array of independent disks storage controllers
42015033177311/19/15 Sideband logic for monitoring pcie headers
52015033275511/19/15 Memory cell having built-in read and write assist
62015033374511/19/15 Voltage comparator
72015032359511/12/15 System for reducing test time using embedded test compression cycle balancing
82015032413611/12/15 Storage system having fifo storage and reserved storage
92015032429511/12/15 Temporal tracking of cache data
102015032430011/12/15 System and methods for efficient i/o processing using multi-level out-of-band hinting
112015032526611/12/15 Multi-dimensional optimization of read channel
122015031709011/05/15 System and life management for low endurance ssd nand devices used as secondary cache
132015031720411/05/15 Systems and methods for efficient data refresh in a storage device
142015031721911/05/15 Logical volume migration in single server high availability environments
152015031801411/05/15 Multiplexed communication in a storage device
162015031803011/05/15 Multiplexed synchronous serial port communication with skew control for storage device
172015031874011/05/15 Electromagnetic energy transfer using tunable inductors
182015031901811/05/15 Slicer trim methodology and device
192015030973210/29/15 Selectively configuring hard-disk drive system
202015030987210/29/15 Data recovery once ecc fails to correct the data
212015031203710/29/15 Data scrambling initialization
222015031206010/29/15 Decision feedback equalization slicer with enhanced latch sensitivity
232015031206810/29/15 Simplified and effective offset calibration circuit for rxlos in serdes
242015030193410/22/15 Flash-based data storage with dual map-based serialization
252015030195610/22/15 Data storage system with caching using application field to carry data block protection information
262015030259310/22/15 Front-end architecture for image processing
272015030288710/22/15 Cross-talk measurement in array reader magnetic recording system
282015030291810/22/15 Word line decoders for dual rail static random access memories
292015030339610/22/15 Method and system for an organic light emitting diode structure
302015030394310/22/15 Systems and methods for puncture based data protection
312015030394710/22/15 Systems and methods for protected portion data processing
322015029380810/15/15 Soft read handling of read noise
332015029473910/15/15 Online histogram and soft information learning
342015028642110/08/15 Read policy for system data of solid state drives
352015028643810/08/15 System, method and computer-readable medium for dynamically configuring an operational mode in a storage controller
362015028652310/08/15 Systems and methods for differential message scaling in a decoding process
372015028652810/08/15 Error correction code (ecc) selection in nand flash controllers with multiple error correction codes
382015028660010/08/15 Arbitration monitoring for serial attached small computer system interface systems during discovery
392015028660410/08/15 Device abstracted zone management of serial attached small computer system interface topologies
402015028747810/08/15 Bad memory unit detection in a solid state drive
412015027939810/01/15 Locking a disk-locked clock using timestamps of successive servo address marks in a spiral servo track
422015027941510/01/15 Systems and methods for skew tolerant multi-head data processing
432015027942110/01/15 Adaptive calibration of noise predictive finite impulse response filter based on decoder convergence
442015026887109/24/15 Read disturb handling in nand flash
452015026902509/24/15 Write redirection in redundant array of independent disks systems
462015026905409/24/15 Multiple core execution trace buffer
472015026909709/24/15 System and elastic despreader memory management
482015026930409/24/15 System and employing signoff-quality timing analysis information concurrently in multiple scenarios to reduce total power within a circuit design
492015026942509/24/15 Dynamic hand gesture recognition with selective enabling based on detected hand velocity
502015026999009/24/15 Memory sense amplifier and column pre-charger
512015026163609/17/15 Data transformations to improve rom yield and programming time
522015026259209/17/15 Systems and methods for distortion characterization
532015026259809/17/15 Systems and methods for head position estimation
542015026266709/17/15 Low power hit bitline driver for content-addressable memory
552015026271009/17/15 Method and system for reducing memory test time utilizing a built-in self-test architecture
562015026294909/17/15 Method for fabricating equal height metal pillars of different diameters
572015026295009/17/15 Method for fabricating equal height metal pillars of different diameters
582015026373209/17/15 Systems and methods for voltage level shifting in a device
592015026384809/17/15 Cdr relock with corrective integral register seeding
602015025510109/10/15 Track misregistration sensitive initialization of joint equalizer
612015025510909/10/15 Non-decision directed magnetoresistive asymetry estimation
622015025511309/10/15 Online iteration resource allocation for large sector format drive
632015025514809/10/15 Bit line write assist for static random access memory architectures
642015025619609/10/15 Soft decoding of polar codes
652015025636309/10/15 Integrated pam4/nrz n-way parallel digital unrolled decision feedback equalizer (dfe)
662015025636409/10/15 Group delay based back channel post cursor adaptation
672015024955509/03/15 Serdes pvt detection and closed loop adaptation
682015024213308/27/15 Storage workload hinting
692015024268108/27/15 System and image processing
702015024331008/27/15 Systems and methods for multi-head separation determination
712015024331108/27/15 Systems and methods for synchronization hand shaking in a storage device
722015024332108/27/15 Reading data from hard disks having reduced preambles
732015024332208/27/15 Systems and methods for multi-head servo data processing
742015024336308/27/15 Adjusting log likelihood ratio values to compensate misplacement of read voltages
752015024353408/27/15 Copper wire bonding apparatus using a purge gas to enhance ball bond reliability
762015024361708/27/15 Method for flip-chip bonding using copper pillars
772015023442308/20/15 Baud rate phase detector with no error latches
782015023570508/20/15 System to control a width of a programming threshold voltage distribution width when writing hot-read data
792015023672608/20/15 Refresh, run, aggregate decoder recovery
802015023687508/20/15 Method and pre-cursor intersymbol interference correction
812015022731408/13/15 Systems and methods for last written page handling in a memory device
822015022740308/13/15 Decoding electronic non-volatile computer storage apparatus
832015022741808/13/15 Hot-read data aggregation and code selection
842015022748608/13/15 Method to facilitate fast context switching for partial and extended path extension to remote expanders
852015022830208/13/15 Zero phase start estimation in readback signals
862015022830308/13/15 Read channel sampling utilizing two quantization modules for increased sample bit width
872015022830408/13/15 Systems and methods for end of fragment marker based data alignment
882015022933108/13/15 Systems and methods for area efficient data encoding
892015022933308/13/15 Systems and methods for rank deficient encoding
902015022933708/13/15 Mitigation of write errors in multi-level cell flash memory through adaptive error correction code decoding
912015022015308/06/15 Gesture recognition system with finite state machine control of cursor detector and dynamic gesture detector
922015022038808/06/15 Systems and methods for hard error reduction in a solid state memory device
932015022045208/06/15 System, method and computer-readable medium for dynamically mapping a non-volatile memory store
942015022074408/06/15 System for execution of security related functions
952015022080408/06/15 Image processor with edge selection functionality
962015022133308/06/15 Reader separation dependent linear and track density push for array reader based magnetic recording
972015021388107/30/15 Integrated read/write tracking in sram
982015020575207/23/15 High density mapping for multiple converter samples in multiple lane interface
992015020631807/23/15 Method and image enhancement and edge verificaton using at least one additional image
1002015020657807/23/15 Area-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail sram memories
1012015020764807/23/15 Modular low power serializer-deserializer
1022015020807607/23/15 Multi-core architecture for low latency video decoder
1032015019912907/16/15 System and providing data services in direct attached storage via multiple de-clustered raid pools
1042015019914007/16/15 Interleaving codewords over multiple flash planes
1052015019914907/16/15 Framework for balancing robustness and latency during collection of statistics from soft reads
1062015019922707/16/15 Fault detection and identification in a multi-initiator system
1072015019924407/16/15 Intelligent i/o cache rebuild in a storage controller
1082015019926907/16/15 Enhanced ssd caching
1092015019999107/16/15 Multiple track detection
1102015020068107/16/15 Segmented digital-to-analog converter with overlapping segments
1112015019356407/09/15 System and using clock chain signals of an on-chip clock controller to control cross-domain paths
1122015019421907/09/15 Capacitance coupling parameter estimation in flash memories
1132015019510807/09/15 Receiver with pipelined tap coefficients and shift control
1142015019535707/09/15 Enhancing active link utilization in serial attached scsi topologies
1152015018631707/02/15 Method and detecting the initiator/target orientation of a smart bridge
1162015018738407/02/15 Two-dimensional magnetic recording reader offset estimation
1172015018738507/02/15 Systems and methods for multi-head balancing in a storage device
1182015018855107/02/15 Clock recovery using quantized phase error samples using jitter frequency-dependent quantization thresholds and loop gains
1192015018857607/02/15 Systems and methods for efficient targeted symbol flipping
1202015017814906/25/15 Method to distribute user data and error correction data over different page types by leveraging error rate variations
1212015017815206/25/15 Preventing programming errors from occurring when programming flash memory cells
1222015017820106/25/15 System for efficient caching of swap i/o and/or similar i/o pattern(s)
1232015017831206/25/15 Attribute-based assistance request system for sequentially contacting nearby contacts without having them divulge their presence or location
1242015017921306/25/15 Servo channel with equalizer adaptation
1252015018051206/25/15 Systems and methods of converting detector output to multi-level soft information
1262015016945806/18/15 System and methods for caching a small size i/o to improve caching device endurance
1272015017067606/18/15 Skew-aware disk format for array reader based magnetic recording
1282015017070606/18/15 Systems and methods for ati characterization
1292015016086906/11/15 Systems and methods for multi-dimensional data processor operational marginalization
1302015016088606/11/15 Method and system for programmable sequencer for processing i/o for various pcie disk drives
1312015016104506/11/15 Slice formatting and interleaving for interleaved sectors
1322015016205706/11/15 Multiple retry reads in a read channel of a memory
1332015016278106/11/15 Illumination-based charging system for portable devices
1342015016336306/11/15 Low complexity tone/voice discrimination method using a rising edge of a frequency power envelope
1352015015411406/04/15 System and method to interleave memory
1362015015413806/04/15 Wide port emulation at serial attached scsi expanders
1372015015502106/04/15 Area-efficient process-and-temperature-adaptive self-time scheme for performance and power improvement
1382015014574005/28/15 Integrated frequency multiplier and slot antenna
1392015014692005/28/15 Gesture recognition method and apparatus utilizing asynchronous multithreaded processing
1402015014939505/28/15 Incremental updates for ordered multi-field classification rules when represented by a tree of longest prefix matching tables
1412015014969805/28/15 Eliminating or reducing programming errors when programming flash memory cells
1422015014984005/28/15 Read retry for non-volatile memories
1432015014985505/28/15 Bit-line defect detection using unsatisified parity code checks
1442015014985605/28/15 Decoding with log likelihood ratios stored in a controller
1452015014987105/28/15 Flash channel with selective decoder likelihood dampening
1462015013785505/21/15 Current to voltage converter
1472015013886305/21/15 Interleaved write assist for hierarchical bitline sram architectures
1482015013886405/21/15 Memory architecture with alternating segments and multiple bitlines
1492015013887605/21/15 Global bitline write assist for sram architectures
1502015013948705/21/15 Image processor with static pose recognition module utilizing segmented region of interest
1512015014316405/21/15 I/o request mirroring in a clustered storage system
1522015014319605/21/15 Systems and methods for faid follower decoding
1532015014320205/21/15 Systems and methods for soft decision generation in a solid state memory system
1542015013137305/14/15 Incremental programming pulse optimization to reduce write errors
1552015013461305/14/15 Systems and methods for lost synchronization data set reprocessing
1562015013485505/14/15 Decoupling host and device address maps for a peripheral component interconnect express controller
1572015013500605/14/15 System and write hole protection for a multiple-node storage cluster
1582015013503105/14/15 Dynamic per-decoder control of log likelihood ratio and decoding parameters
1592015013503205/14/15 Detection/erasure of random write errors using converged hard decisions
1602015012787105/07/15 Updated io memory management unit identity settings for dma remapping
1612015012788305/07/15 Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory
1622015012800605/07/15 Device quality metrics using unsatisfied parity checks
1632015011709704/30/15 Systems and methods for sub-zero threshold characterization in a memory cell
1642015011722604/30/15 Method and system for session based data monitoring for wireless edge content caching networks
1652015012098104/30/15 Data interface for point-to-point communications between devices
1662015012098904/30/15 Tracking and utilizing second level map index for recycling of solid state drive blocks
1672015012108804/30/15 Method of managing aligned and unaligned data bands in a self encrypting solid state drive
1682015012117304/30/15 Systems and methods for internal disk drive data compression
1692015010905204/23/15 Closed-loop adaptive voltage scaling for integrated circuits
1702015011016504/23/15 Transmitter training using receiver equalizer coefficients
1712015011320504/23/15 Systems and methods for latency based data recycling in a solid state memory system
1722015011331204/23/15 System and detecting server removal from a cluster to enable fast failover of storage
1732015011331804/23/15 Systems and methods for soft data utilization in a solid state memory system
1742015011333504/23/15 Sending failure information from a solid state drive (ssd) to a host device
1752015011335404/23/15 Generating soft decoding information for flash memory error correction using hard decision patterns
1762015010360404/16/15 Memory array architectures having memory cells with shared write assist circuitry
1772015010396104/16/15 Digital frequency band detector for clock and data recovery
1782015010657704/16/15 De-interleaving on an as-needed basis
1792015010666604/16/15 Speculative bit error rate calculator
1802015010667504/16/15 Systems and methods for multi-algorithm concatenation encoding and decoding
1812015009761104/09/15 Voltage follower having a feed-forward device
1822015010081004/09/15 Adaptive power-down of disk drives based on predicted idle time
1832015009162004/02/15 Reducing current variation when switching clocks
1842015009229004/02/15 Non-binary layered low density parity check decoder
1852015009248904/02/15 Flash memory reference voltage detection with tracking of cross-points of cell voltage distributions using histograms
1862015008539203/26/15 System and monitoring preamble signal quality
1872015008558703/26/15 Ping-pong buffer using single-port memory
1882015008559203/26/15 Bit-line discharge assistance in memory devices
1892015008595703/26/15 Method of calibrating a slicer in a receiver or the like
1902015008910203/26/15 Solid state drives that cache boot data
1912015008913203/26/15 Dynamic storage volume configuration based on input/output requests
1922015008933003/26/15 Systems and methods for enhanced data recovery in a solid state memory system
1932015007718803/19/15 Voltage follower amplifier
1942015007727703/19/15 Reduced polar codes
1952015007810303/19/15 Sensing technique for single-ended bit line memory architectures
1962015008162603/19/15 Systems and methods for recovered data stitching
1972015008164903/19/15 In-line deduplication for a network and/or storage platform
1982015008211503/19/15 Systems and methods for fragmented data recovery
1992015008212103/19/15 Method of erase state handling in flash channel tracking
2002015008212403/19/15 Spatially decoupled redundancy schemes for a solid state drive (ssd)
2012015007079603/12/15 Array-reader based magnetic recording systems with mixed synchronization
2022015007432703/12/15 Active recycling for solid state drive
2032015007432803/12/15 Dynamic map pre-fetching for improved sequential reads of a solid-state media
2042015007435503/12/15 Efficient caching of file system journals
2052015007450103/12/15 Cascaded viterbi bitstream generator
2062015006273003/05/15 Array-reader based magnetic recording systems with quadrature amplitude modulation
2072015006273203/05/15 Systems and methods for two stage tone reduction
2082015006273403/05/15 Systems and methods for multi-level encoding and decoding
2092015006273703/05/15 Adaptive pattern detection for pattern-dependent write current control in a magnetic recording system
2102015006273803/05/15 Systems and methods for variable sector count spreading and de-spreading
2112015006321703/05/15 Mapping between variable width samples and a frame
2122015006725303/05/15 Input/output request shipping in a storage system with multiple storage controllers
2132015006734903/05/15 Virtual bands concentration for self encrypting drives
2142015006768503/05/15 Systems and methods for multiple sensor noise predictive filtering
2152015005524902/26/15 Systems and methods for multi-resolution data sensing
2162015005564402/26/15 Precise timestamping of ethernet packets by compensating for start-of-frame delimiter detection delay and delay variations
2172015005577402/26/15 Echo cancellation with quantization compensation
2182015005853302/26/15 Data storage controller and exposing information stored in a data storage controller to a host system
2192015005855702/26/15 Performance improvements in input / output operations between a host system and an adapter-coupled cache
2202015005869302/26/15 Systems and methods for enhanced data encoding and decoding
2212015004831002/19/15 System and providing an electron blocking layer with doping control
2222015004240302/12/15 High-voltage voltage-switched class-s amplifier
2232015004327002/12/15 Memory cell having built-in write assist
2242015004380702/12/15 Depth image compression and decompression utilizing depth and amplitude data
2252015004675602/12/15 Predictive failure analysis to trigger rebuild of a drive in a raid array
2262015003694202/05/15 Object recognition and tracking using a classifier comprising cascaded stages of multiple decision trees
2272015003978702/05/15 Multi-protocol storage controller
2282015003979602/05/15 Acquiring resources from low priority connection requests in sas
2292015003983202/05/15 System and caching hinted data
2302015003983502/05/15 System and hinted cache data removal
2312015003993202/05/15 Arbitration suspension in a sas domain
2322015003997802/05/15 Systems and methods for hybrid priority based data processing
2332015002960801/29/15 Array-reader based magnetic recording systems with frequency division multiplexing
2342015003002701/29/15 Switch device with device-specified bridge domains
2352015003023201/29/15 Image processor configured for efficient estimation and elimination of background information in images
2362015003296301/29/15 Dynamic selection of cache levels
2372015003306501/29/15 Solid state drive emergency pre-boot application providing expanded data recovery function
2382015003307401/29/15 Deadlock detection and recovery in sas
2392015002216901/22/15 Feedback/feed forward switched capacitor voltage regulation
2402015002270401/22/15 Orientation-based camera operation
2412015002360701/22/15 Gesture recognition method and apparatus based on analysis of multiple candidate boundaries
2422015002640301/22/15 Self-adjusting caching system
2432015002641101/22/15 Cache system for managing various cache line conditions
2442015002648801/22/15 Selectively powering a storage device over a data network
2452015002650301/22/15 Appliances powered over sas
2462015002653601/22/15 Data decoder with trapping set flip bit mapper
2472015001532901/15/15 Radio frequency composite class-s power amplifier having discrete power control
2482015001598401/15/15 Storage media inter-track interference cancellation
2492015001598601/15/15 Methods and improved threshold adaptation for a euclidean detector

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Lsi Corporation in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Lsi Corporation with additional patents listed. Browse our Agent directory for other possible listings. Page by