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Lsi Corporation patents


      
Recent patent applications related to Lsi Corporation. Lsi Corporation is listed as an Agent/Assignee. Note: Lsi Corporation may have other listings under different names/spellings. We're not affiliated with Lsi Corporation, we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "L" | Lsi Corporation-related inventors


Interleaved write assist for hierarchical bitline sram architectures

Lsi

Interleaved write assist for hierarchical bitline sram architectures

Global bitline write assist for sram architectures

Lsi

Global bitline write assist for sram architectures

Systems and methods for soft decision generation in a solid state memory system

Lsi

Systems and methods for soft decision generation in a solid state memory system

Search recent Press Releases: Lsi Corporation-related press releases
Count Application # Date Lsi Corporation patents (updated weekly) - BOOKMARK this page
12015013785505/21/15 new patent  Current to voltage converter
22015013886305/21/15 new patent  Interleaved write assist for hierarchical bitline sram architectures
32015013886405/21/15 new patent  Memory architecture with alternating segments and multiple bitlines
42015013887605/21/15 new patent  Global bitline write assist for sram architectures
52015013948705/21/15 new patent  Image processor with static pose recognition module utilizing segmented region of interest
62015014316405/21/15 new patent  I/o request mirroring in a clustered storage system
72015014319605/21/15 new patent  Systems and methods for faid follower decoding
82015014320205/21/15 new patent  Systems and methods for soft decision generation in a solid state memory system
92015013137305/14/15Incremental programming pulse optimization to reduce write errors
102015013461305/14/15Systems and methods for lost synchronization data set reprocessing
112015013485505/14/15Decoupling host and device address maps for a peripheral component interconnect express controller
122015013500605/14/15System and write hole protection for a multiple-node storage cluster
132015013503105/14/15Dynamic per-decoder control of log likelihood ratio and decoding parameters
142015013503205/14/15Detection/erasure of random write errors using converged hard decisions
152015012787105/07/15Updated io memory management unit identity settings for dma remapping
162015012788305/07/15Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory
172015012800605/07/15Device quality metrics using unsatisfied parity checks
182015011709704/30/15Systems and methods for sub-zero threshold characterization in a memory cell
192015011722604/30/15Method and system for session based data monitoring for wireless edge content caching networks
202015012098104/30/15Data interface for point-to-point communications between devices
212015012098904/30/15Tracking and utilizing second level map index for recycling of solid state drive blocks
222015012108804/30/15Method of managing aligned and unaligned data bands in a self encrypting solid state drive
232015012117304/30/15Systems and methods for internal disk drive data compression
242015010905204/23/15Closed-loop adaptive voltage scaling for integrated circuits
252015011016504/23/15Transmitter training using receiver equalizer coefficients
262015011320504/23/15Systems and methods for latency based data recycling in a solid state memory system
272015011331204/23/15System and detecting server removal from a cluster to enable fast failover of storage
282015011331804/23/15Systems and methods for soft data utilization in a solid state memory system
292015011333504/23/15Sending failure information from a solid state drive (ssd) to a host device
302015011335404/23/15Generating soft decoding information for flash memory error correction using hard decision patterns
312015010360404/16/15Memory array architectures having memory cells with shared write assist circuitry
322015010396104/16/15Digital frequency band detector for clock and data recovery
332015010657704/16/15De-interleaving on an as-needed basis
342015010666604/16/15Speculative bit error rate calculator
352015010667504/16/15Systems and methods for multi-algorithm concatenation encoding and decoding
362015009761104/09/15Voltage follower having a feed-forward device
372015010081004/09/15Adaptive power-down of disk drives based on predicted idle time
382015009162004/02/15Reducing current variation when switching clocks
392015009229004/02/15Non-binary layered low density parity check decoder
402015009248904/02/15Flash memory reference voltage detection with tracking of cross-points of cell voltage distributions using histograms
412015008539203/26/15System and monitoring preamble signal quality
422015008558703/26/15Ping-pong buffer using single-port memory
432015008559203/26/15Bit-line discharge assistance in memory devices
442015008595703/26/15Method of calibrating a slicer in a receiver or the like
452015008910203/26/15Solid state drives that cache boot data
462015008913203/26/15Dynamic storage volume configuration based on input/output requests
472015008933003/26/15Systems and methods for enhanced data recovery in a solid state memory system
482015007718803/19/15Voltage follower amplifier
492015007727703/19/15Reduced polar codes
502015007810303/19/15Sensing technique for single-ended bit line memory architectures
512015008162603/19/15Systems and methods for recovered data stitching
522015008164903/19/15In-line deduplication for a network and/or storage platform
532015008211503/19/15Systems and methods for fragmented data recovery
542015008212103/19/15Method of erase state handling in flash channel tracking
552015008212403/19/15Spatially decoupled redundancy schemes for a solid state drive (ssd)
562015007079603/12/15Array-reader based magnetic recording systems with mixed synchronization
572015007432703/12/15Active recycling for solid state drive
582015007432803/12/15Dynamic map pre-fetching for improved sequential reads of a solid-state media
592015007435503/12/15Efficient caching of file system journals
602015007450103/12/15Cascaded viterbi bitstream generator
612015006273003/05/15Array-reader based magnetic recording systems with quadrature amplitude modulation
622015006273203/05/15Systems and methods for two stage tone reduction
632015006273403/05/15Systems and methods for multi-level encoding and decoding
642015006273703/05/15Adaptive pattern detection for pattern-dependent write current control in a magnetic recording system
652015006273803/05/15Systems and methods for variable sector count spreading and de-spreading
662015006321703/05/15Mapping between variable width samples and a frame
672015006725303/05/15Input/output request shipping in a storage system with multiple storage controllers
682015006734903/05/15Virtual bands concentration for self encrypting drives
692015006768503/05/15Systems and methods for multiple sensor noise predictive filtering
702015005524902/26/15Systems and methods for multi-resolution data sensing
712015005564402/26/15Precise timestamping of ethernet packets by compensating for start-of-frame delimiter detection delay and delay variations
722015005577402/26/15Echo cancellation with quantization compensation
732015005853302/26/15Data storage controller and exposing information stored in a data storage controller to a host system
742015005855702/26/15Performance improvements in input / output operations between a host system and an adapter-coupled cache
752015005869302/26/15Systems and methods for enhanced data encoding and decoding
762015004831002/19/15System and providing an electron blocking layer with doping control
772015004240302/12/15High-voltage voltage-switched class-s amplifier
782015004327002/12/15Memory cell having built-in write assist
792015004380702/12/15Depth image compression and decompression utilizing depth and amplitude data
802015004675602/12/15Predictive failure analysis to trigger rebuild of a drive in a raid array
812015003694202/05/15Object recognition and tracking using a classifier comprising cascaded stages of multiple decision trees
822015003978702/05/15Multi-protocol storage controller
832015003979602/05/15Acquiring resources from low priority connection requests in sas
842015003983202/05/15System and caching hinted data
852015003983502/05/15System and hinted cache data removal
862015003993202/05/15Arbitration suspension in a sas domain
872015003997802/05/15Systems and methods for hybrid priority based data processing
882015002960801/29/15Array-reader based magnetic recording systems with frequency division multiplexing
892015003002701/29/15Switch device with device-specified bridge domains
902015003023201/29/15Image processor configured for efficient estimation and elimination of background information in images
912015003296301/29/15Dynamic selection of cache levels
922015003306501/29/15Solid state drive emergency pre-boot application providing expanded data recovery function
932015003307401/29/15Deadlock detection and recovery in sas
942015002216901/22/15Feedback/feed forward switched capacitor voltage regulation
952015002270401/22/15Orientation-based camera operation
962015002360701/22/15Gesture recognition method and apparatus based on analysis of multiple candidate boundaries
972015002640301/22/15Self-adjusting caching system
982015002641101/22/15Cache system for managing various cache line conditions
992015002648801/22/15Selectively powering a storage device over a data network
1002015002650301/22/15Appliances powered over sas
1012015002653601/22/15Data decoder with trapping set flip bit mapper
1022015001532901/15/15Radio frequency composite class-s power amplifier having discrete power control
1032015001598401/15/15Storage media inter-track interference cancellation
1042015001598601/15/15Methods and improved threshold adaptation for a euclidean detector
1052015001598701/15/15Prioritized spin-up of drives
1062015001649701/15/15Clock and data recovery architecture with adaptive digital phase skew
1072015001979501/15/15Memory system for shadowing volatile data
1082015001981801/15/15Maintaining cache size proportional to power pack charge
1092015001982201/15/15System for maintaining dirty cache coherency across reboot of a node
1102015000889401/08/15Dynamic start-up circuit for hysteretic loop switched-capacitor voltage regulator
1112015001269901/08/15System and versioning cache for a clustering topology
1122015001270201/08/15Redundant array of independent disks volume creation
1132015001280001/08/15Systems and methods for correlation based data alignment
1142015000681501/01/15Backup of cached dirty data during power outages
1152014037995912/25/14Map recycling acceleration
1162014038022312/25/14User interface comprising radial layout soft keypad
1172014036771712/18/14Semiconductor optical emitting device with metallized sidewalls
1182014036939512/18/14Error detection based on superheterodyne conversion and direct downconversion
1192014036969612/18/14Color coding and optical sub-band communication utilizing color coding
1202014037263712/18/14Pcie tunneling through sas
1212014037267212/18/14System and providing improved system performance by moving pinned data to open nand flash interface working group modules while the system is in a running state
1222014037278312/18/14System and providing dynamic charge current based on maximum card power
1232014037282812/18/14Systems and methods for hybrid layer data decoding
1242014037283612/18/14Systems and methods for data processing control
1252014036228912/11/14Method and increasing frame rate of an image stream using at least one higher frame rate image stream
1262014036246312/11/14Timing error detector with diversity loop detector decision feedback
1272014035921612/04/14Confirmed divert bitmap to synchronize raid firmware operations with fast-path hardware i/o processing
1282014035926612/04/14Optimizing boot time of a storage system
1292014035939412/04/14Apparatus for processing signals carrying modulation-encoded parity bits
1302014034819711/27/14Semiconductor optical emitting device with lens structure formed in a cavity of a substrate of the device
1312014034947511/27/14Moisture barrier for a wire bond
1322014035148611/27/14Variable redundancy in a solid state drive
1332014035167111/27/14Shift register-based layered low density parity check decoder
1342014034078011/20/14Method and system for sliding-window based phase, gain, frequency and dc offset estimation for servo channel
1352014034123111/20/14Lane-based multiplexing for physical links in serial attached small computer system interface architectures
1362014034449211/20/14Methods and systems for reducing spurious interrupts in a data storage system
1372014034461611/20/14Techniques for providing data redundancy after reducing memory writes
1382014034496011/20/14Selective control of on-chip debug circuitry of embedded processors
1392014033427811/13/14Systems and methods for energy based head contact detection
1402014033428011/13/14Systems and methods for characterizing head contact
1412014033428111/13/14Systems and methods for data processor marginalization based upon bit error rate
1422014033449111/13/14Prediction based methods for fast routing of ip flows using communication/network processors
1432014033754011/13/14Method and system for i/o flow management for pcie devices
1442014033758311/13/14Intelligent cache window management for storage systems
1452014033767611/13/14Systems and methods for processing data with microcontroller based retry features
1462014033100111/06/14Command barrier for a solid state drive controller
1472014033109611/06/14Cross-decoding for non-volatile storage
1482014033110811/06/14Systems and methods for detecting media flaws
1492014032511710/30/14Flash translation layer with lower write amplification
1502014032514410/30/14Protection information initialization
1512014032514510/30/14Cache rebuilds based on tracking data for cache entries
1522014032514610/30/14Creating and managing logical volumes from unused space in raid disk groups
1532014032530310/30/14Systems and methods for protected data encoding
1542014031237210/23/14Semiconductor optical emitting device with grooved substrate providing multiple angled light emission paths
1552014031247510/23/14Die reuse in electrical circuits
1562014031361010/23/14Systems and methods selective complexity data decoding
1572014031394610/23/14Non-linear interference cancellation for wireless transceivers
1582014031417610/23/14Non-linear modeling of a physical system using two-dimensional look-up table with bilinear interpolation
1592014031418110/23/14Non-linear modeling of a physical system using look-up table with polynomial interpolation
1602014031426510/23/14Headphones with rotatable speaker arranged within housing of earpiece assembly
1612014031675210/23/14Non-linear modeling of a physical system using direct optimization of look-up table values
1622014031716310/23/14Vector processor having instruction set with sliding window non-linear convolutional function
1632014031733410/23/14Storage of gate training parameters for devices utilizing random access memory
1642014031734610/23/14Redundant array of independent disks systems that utilize spans with different storage device counts for a logical volume
1652014031737610/23/14Digital processor having instruction set with complex angle function
1662014030734510/16/14Systems and methods for preventing adjacent track erasure
1672014030114310/09/14Techniques for controlling recycling of blocks of memory
1682014030446410/09/14Methods and systems for performing deduplication in a data storage system
1692014030456210/09/14Method for testing paths to pull-up and pull-down of input/output pads
1702014029229810/02/14Operational amplifier-based current-sensing circuit for dc-dc voltage converters and the like
1712014029812310/02/14Scan chain reconfiguration and repair
1722014029812910/02/14Generating partially sparse generator matrix for a quasi-cyclic low-density parity-check encoder
1732014029813110/02/14Priori information based post-processing in low-density parity-check code decoders
1742014029814810/02/14Trend-analysis scheme for reliably reading data values from memory
1752014028591809/25/14Systems and methods for quality based bit error rate prediction
1762014028610209/25/14Method of optimizing solid state drive soft retry voltages
1772014028614909/25/14Automatic on-drive sync-mark search and threshold adjustment
1782014028638509/25/14Systems and methods for multi-dimensional signal equalization
1792014028945009/25/14Dynamic log likelihood ratio quantization for solid state drive controllers
1802014028955009/25/14Integrated clock architecture for improved testing
1812014028958209/25/14Systems and methods for reduced constraint code data processing
1822014026633809/18/14Biased bang-bang phase detector for clock and data recovery
1832014026639509/18/14Ac coupling circuit with hybrid switches
1842014026649709/18/14Ac coupling circuit with hybrid switches and constant load
1852014026681509/18/14Lempel-ziv data compression with shortened hash chains based on repetitive patterns
1862014026682009/18/14Interleaved multipath digital power amplification
1872014026700409/18/14User adjustable gesture space
1882014026838909/18/14Systems and methods for enhanced sync mark mis-detection protection
1892014026839009/18/14Systems and methods for transition based equalization
1902014026839109/18/14Data sequence detection in band-limited channels using cooperative sequence equalization
1912014026839709/18/14Hardware support of servo format with two preamble fields
1922014026840009/18/14Systems and methods for loop feedback
1932014026840109/18/14Systems and methods for p-distance based priority data processing
1942014026904809/18/14Retention detection and/or channel tracking policy in a flash memory based storage system
1952014026905309/18/14Nonvolatile memory data recovery after power failure
1962014026988809/18/14Adaptive continuous time linear equalizer
1972014026997809/18/14Interleaved multipath digital power amplification
1982014028041709/18/14Linear phase fir biorthogonal wavelet filters with complementarity for image noise reduction
1992014028041809/18/14Numerical method: making the infinite, finite. a universal transform and system of force vector
2002014028042909/18/14Efficient hardware structure for sorting/adding multiple inputs assigned to different bins
2012014028105709/18/14Unified message-based communications
2022014028108309/18/14Enhanced queue management
2032014028110609/18/14Direct routing between address spaces through a nontransparent peripheral component interconnect express bridge
2042014028114309/18/14Reducing flash memory write amplification and latency
2052014028117109/18/14Lock-free communication storage request reordering
2062014028128109/18/14Host command based read disturb methodology
2072014028162709/18/14Device sleep partitioning and keys
2082014028168809/18/14Method and system of data recovery in a raid controller
2092014028170309/18/14Local repair signature handling for repairable memories
2102014028176709/18/14Recovery strategy that reduces errors misidentified as reliable
2112014028178709/18/14Min-sum based hybrid non-binary low density parity check decoder
2122014028181809/18/14Method for format savings in coherently written fragmented sectors
2132014028182209/18/14Method and generation of soft decision error correction code information
2142014028184109/18/14Systems and methods for sync mark mis-detection protection
2152014028314609/18/14Tamper sensor
2162014025320309/11/14Programmable clock spreading
2172014025322209/11/14Preventing electronic device counterfeits
2182014025322609/11/14Power integrity control through active current profile management
2192014025404109/11/14Servo marginalization
2202014025404309/11/14Sampling-phase acquisition based on channel-impulse-response estimation
2212014025459309/11/14Network processor having multicasting protocol
2222014025465509/11/14Adaptation of equalizer settings using error signals sampled at several different phases
2232014025473509/11/14Transmit reference signal cleanup within a synchronous network application
2242014025837509/11/14System and large object cache management in a network
2252014025856509/11/14Smart discovery model in a serial attached small computer system topology
2262014025857209/11/14Preemptive connection switching for serial attached small computer system interface systems
2272014025858709/11/14Self recovery in a solid state drive
2282014025859509/11/14System, method and computer-readable medium for dynamic cache sharing in a flash-based caching solution supporting virtual machines
2292014025859809/11/14Scalable storage devices
2302014025861009/11/14Raid cache memory system with volume windows
2312014025861309/11/14Volume change flags for incremental snapshots of stored data
2322014025862809/11/14System, method and computer-readable medium for managing a cache store to achieve improved cache ramp-up across system reboots
2332014025875509/11/14Storage device power failure infrastructure
2342014025875909/11/14System and de-queuing an active queue
2352014025876909/11/14Partial r-block recycling
2362014024751409/04/14Systems and methods for adc sample based inter-track interference compensation
2372014025024609/04/14Intelligent data buffering between interfaces
2382014025026309/04/14Techniques for reducing memory write operations using coalescing memory buffers and difference information
2392014025026909/04/14Declustered raid pool as backup for raid volumes
2402014025031509/04/14Storage system data hardening
2412014025033809/04/14Virtual function timeout for single root input/output virtualization controllers
2422014025035209/04/14Systems and methods for signal reduction based data processor marginalization
2432014024003308/28/14On-die programming of integrated circuit bond pads
2442014024046708/28/14Image processing elimination of depth artifacts
2452014024086408/28/14Storage device having degauss circuitry configured for generating degauss signal with asymmetric decay envelopes
2462014024087008/28/14Analog tunneling current sensors for use with disk drive storage devices
2472014024102808/28/14Two-bit read-only memory cell
2482014024105608/28/14Reduced complexity reliability computations for flash memories
2492014024106108/28/14Fast access with low leakage and low power technique for read only memory devices



ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009



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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Lsi Corporation in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Lsi Corporation with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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