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Lsi Corporation patents


      
Recent patent applications related to Lsi Corporation. Lsi Corporation is listed as an Agent/Assignee. Note: Lsi Corporation may have other listings under different names/spellings. We're not affiliated with Lsi Corporation, we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "L" | Lsi Corporation-related inventors


Two-dimensional magnetic recording reader offset estimation

Lsi

Two-dimensional magnetic recording reader offset estimation

Systems and methods for multi-head balancing in a storage device

Lsi

Systems and methods for multi-head balancing in a storage device

Search recent Press Releases: Lsi Corporation-related press releases
Count Application # Date Lsi Corporation patents (updated weekly) - BOOKMARK this page
12015018631707/02/15 new patent  Method and detecting the initiator/target orientation of a smart bridge
22015018738407/02/15 new patent  Two-dimensional magnetic recording reader offset estimation
32015018738507/02/15 new patent  Systems and methods for multi-head balancing in a storage device
42015018855107/02/15 new patent  Clock recovery using quantized phase error samples using jitter frequency-dependent quantization thresholds and loop gains
52015018857607/02/15 new patent  Systems and methods for efficient targeted symbol flipping
62015017814906/25/15Method to distribute user data and error correction data over different page types by leveraging error rate variations
72015017815206/25/15Preventing programming errors from occurring when programming flash memory cells
82015017820106/25/15System for efficient caching of swap i/o and/or similar i/o pattern(s)
92015017831206/25/15Attribute-based assistance request system for sequentially contacting nearby contacts without having them divulge their presence or location
102015017921306/25/15Servo channel with equalizer adaptation
112015018051206/25/15Systems and methods of converting detector output to multi-level soft information
122015016945806/18/15System and methods for caching a small size i/o to improve caching device endurance
132015017067606/18/15Skew-aware disk format for array reader based magnetic recording
142015017070606/18/15Systems and methods for ati characterization
152015016086906/11/15Systems and methods for multi-dimensional data processor operational marginalization
162015016088606/11/15Method and system for programmable sequencer for processing i/o for various pcie disk drives
172015016104506/11/15Slice formatting and interleaving for interleaved sectors
182015016205706/11/15Multiple retry reads in a read channel of a memory
192015016278106/11/15Illumination-based charging system for portable devices
202015016336306/11/15Low complexity tone/voice discrimination method using a rising edge of a frequency power envelope
212015015411406/04/15System and method to interleave memory
222015015413806/04/15Wide port emulation at serial attached scsi expanders
232015015502106/04/15Area-efficient process-and-temperature-adaptive self-time scheme for performance and power improvement
242015014574005/28/15Integrated frequency multiplier and slot antenna
252015014692005/28/15Gesture recognition method and apparatus utilizing asynchronous multithreaded processing
262015014939505/28/15Incremental updates for ordered multi-field classification rules when represented by a tree of longest prefix matching tables
272015014969805/28/15Eliminating or reducing programming errors when programming flash memory cells
282015014984005/28/15Read retry for non-volatile memories
292015014985505/28/15Bit-line defect detection using unsatisified parity code checks
302015014985605/28/15Decoding with log likelihood ratios stored in a controller
312015014987105/28/15Flash channel with selective decoder likelihood dampening
322015013785505/21/15Current to voltage converter
332015013886305/21/15Interleaved write assist for hierarchical bitline sram architectures
342015013886405/21/15Memory architecture with alternating segments and multiple bitlines
352015013887605/21/15Global bitline write assist for sram architectures
362015013948705/21/15Image processor with static pose recognition module utilizing segmented region of interest
372015014316405/21/15I/o request mirroring in a clustered storage system
382015014319605/21/15Systems and methods for faid follower decoding
392015014320205/21/15Systems and methods for soft decision generation in a solid state memory system
402015013137305/14/15Incremental programming pulse optimization to reduce write errors
412015013461305/14/15Systems and methods for lost synchronization data set reprocessing
422015013485505/14/15Decoupling host and device address maps for a peripheral component interconnect express controller
432015013500605/14/15System and write hole protection for a multiple-node storage cluster
442015013503105/14/15Dynamic per-decoder control of log likelihood ratio and decoding parameters
452015013503205/14/15Detection/erasure of random write errors using converged hard decisions
462015012787105/07/15Updated io memory management unit identity settings for dma remapping
472015012788305/07/15Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory
482015012800605/07/15Device quality metrics using unsatisfied parity checks
492015011709704/30/15Systems and methods for sub-zero threshold characterization in a memory cell
502015011722604/30/15Method and system for session based data monitoring for wireless edge content caching networks
512015012098104/30/15Data interface for point-to-point communications between devices
522015012098904/30/15Tracking and utilizing second level map index for recycling of solid state drive blocks
532015012108804/30/15Method of managing aligned and unaligned data bands in a self encrypting solid state drive
542015012117304/30/15Systems and methods for internal disk drive data compression
552015010905204/23/15Closed-loop adaptive voltage scaling for integrated circuits
562015011016504/23/15Transmitter training using receiver equalizer coefficients
572015011320504/23/15Systems and methods for latency based data recycling in a solid state memory system
582015011331204/23/15System and detecting server removal from a cluster to enable fast failover of storage
592015011331804/23/15Systems and methods for soft data utilization in a solid state memory system
602015011333504/23/15Sending failure information from a solid state drive (ssd) to a host device
612015011335404/23/15Generating soft decoding information for flash memory error correction using hard decision patterns
622015010360404/16/15Memory array architectures having memory cells with shared write assist circuitry
632015010396104/16/15Digital frequency band detector for clock and data recovery
642015010657704/16/15De-interleaving on an as-needed basis
652015010666604/16/15Speculative bit error rate calculator
662015010667504/16/15Systems and methods for multi-algorithm concatenation encoding and decoding
672015009761104/09/15Voltage follower having a feed-forward device
682015010081004/09/15Adaptive power-down of disk drives based on predicted idle time
692015009162004/02/15Reducing current variation when switching clocks
702015009229004/02/15Non-binary layered low density parity check decoder
712015009248904/02/15Flash memory reference voltage detection with tracking of cross-points of cell voltage distributions using histograms
722015008539203/26/15System and monitoring preamble signal quality
732015008558703/26/15Ping-pong buffer using single-port memory
742015008559203/26/15Bit-line discharge assistance in memory devices
752015008595703/26/15Method of calibrating a slicer in a receiver or the like
762015008910203/26/15Solid state drives that cache boot data
772015008913203/26/15Dynamic storage volume configuration based on input/output requests
782015008933003/26/15Systems and methods for enhanced data recovery in a solid state memory system
792015007718803/19/15Voltage follower amplifier
802015007727703/19/15Reduced polar codes
812015007810303/19/15Sensing technique for single-ended bit line memory architectures
822015008162603/19/15Systems and methods for recovered data stitching
832015008164903/19/15In-line deduplication for a network and/or storage platform
842015008211503/19/15Systems and methods for fragmented data recovery
852015008212103/19/15Method of erase state handling in flash channel tracking
862015008212403/19/15Spatially decoupled redundancy schemes for a solid state drive (ssd)
872015007079603/12/15Array-reader based magnetic recording systems with mixed synchronization
882015007432703/12/15Active recycling for solid state drive
892015007432803/12/15Dynamic map pre-fetching for improved sequential reads of a solid-state media
902015007435503/12/15Efficient caching of file system journals
912015007450103/12/15Cascaded viterbi bitstream generator
922015006273003/05/15Array-reader based magnetic recording systems with quadrature amplitude modulation
932015006273203/05/15Systems and methods for two stage tone reduction
942015006273403/05/15Systems and methods for multi-level encoding and decoding
952015006273703/05/15Adaptive pattern detection for pattern-dependent write current control in a magnetic recording system
962015006273803/05/15Systems and methods for variable sector count spreading and de-spreading
972015006321703/05/15Mapping between variable width samples and a frame
982015006725303/05/15Input/output request shipping in a storage system with multiple storage controllers
992015006734903/05/15Virtual bands concentration for self encrypting drives
1002015006768503/05/15Systems and methods for multiple sensor noise predictive filtering
1012015005524902/26/15Systems and methods for multi-resolution data sensing
1022015005564402/26/15Precise timestamping of ethernet packets by compensating for start-of-frame delimiter detection delay and delay variations
1032015005577402/26/15Echo cancellation with quantization compensation
1042015005853302/26/15Data storage controller and exposing information stored in a data storage controller to a host system
1052015005855702/26/15Performance improvements in input / output operations between a host system and an adapter-coupled cache
1062015005869302/26/15Systems and methods for enhanced data encoding and decoding
1072015004831002/19/15System and providing an electron blocking layer with doping control
1082015004240302/12/15High-voltage voltage-switched class-s amplifier
1092015004327002/12/15Memory cell having built-in write assist
1102015004380702/12/15Depth image compression and decompression utilizing depth and amplitude data
1112015004675602/12/15Predictive failure analysis to trigger rebuild of a drive in a raid array
1122015003694202/05/15Object recognition and tracking using a classifier comprising cascaded stages of multiple decision trees
1132015003978702/05/15Multi-protocol storage controller
1142015003979602/05/15Acquiring resources from low priority connection requests in sas
1152015003983202/05/15System and caching hinted data
1162015003983502/05/15System and hinted cache data removal
1172015003993202/05/15Arbitration suspension in a sas domain
1182015003997802/05/15Systems and methods for hybrid priority based data processing
1192015002960801/29/15Array-reader based magnetic recording systems with frequency division multiplexing
1202015003002701/29/15Switch device with device-specified bridge domains
1212015003023201/29/15Image processor configured for efficient estimation and elimination of background information in images
1222015003296301/29/15Dynamic selection of cache levels
1232015003306501/29/15Solid state drive emergency pre-boot application providing expanded data recovery function
1242015003307401/29/15Deadlock detection and recovery in sas
1252015002216901/22/15Feedback/feed forward switched capacitor voltage regulation
1262015002270401/22/15Orientation-based camera operation
1272015002360701/22/15Gesture recognition method and apparatus based on analysis of multiple candidate boundaries
1282015002640301/22/15Self-adjusting caching system
1292015002641101/22/15Cache system for managing various cache line conditions
1302015002648801/22/15Selectively powering a storage device over a data network
1312015002650301/22/15Appliances powered over sas
1322015002653601/22/15Data decoder with trapping set flip bit mapper
1332015001532901/15/15Radio frequency composite class-s power amplifier having discrete power control
1342015001598401/15/15Storage media inter-track interference cancellation
1352015001598601/15/15Methods and improved threshold adaptation for a euclidean detector
1362015001598701/15/15Prioritized spin-up of drives
1372015001649701/15/15Clock and data recovery architecture with adaptive digital phase skew
1382015001979501/15/15Memory system for shadowing volatile data
1392015001981801/15/15Maintaining cache size proportional to power pack charge
1402015001982201/15/15System for maintaining dirty cache coherency across reboot of a node
1412015000889401/08/15Dynamic start-up circuit for hysteretic loop switched-capacitor voltage regulator
1422015001269901/08/15System and versioning cache for a clustering topology
1432015001270201/08/15Redundant array of independent disks volume creation
1442015001280001/08/15Systems and methods for correlation based data alignment
1452015000681501/01/15Backup of cached dirty data during power outages
1462014037995912/25/14Map recycling acceleration
1472014038022312/25/14User interface comprising radial layout soft keypad
1482014036771712/18/14Semiconductor optical emitting device with metallized sidewalls
1492014036939512/18/14Error detection based on superheterodyne conversion and direct downconversion
1502014036969612/18/14Color coding and optical sub-band communication utilizing color coding
1512014037263712/18/14Pcie tunneling through sas
1522014037267212/18/14System and providing improved system performance by moving pinned data to open nand flash interface working group modules while the system is in a running state
1532014037278312/18/14System and providing dynamic charge current based on maximum card power
1542014037282812/18/14Systems and methods for hybrid layer data decoding
1552014037283612/18/14Systems and methods for data processing control
1562014036228912/11/14Method and increasing frame rate of an image stream using at least one higher frame rate image stream
1572014036246312/11/14Timing error detector with diversity loop detector decision feedback
1582014035921612/04/14Confirmed divert bitmap to synchronize raid firmware operations with fast-path hardware i/o processing
1592014035926612/04/14Optimizing boot time of a storage system
1602014035939412/04/14Apparatus for processing signals carrying modulation-encoded parity bits
1612014034819711/27/14Semiconductor optical emitting device with lens structure formed in a cavity of a substrate of the device
1622014034947511/27/14Moisture barrier for a wire bond
1632014035148611/27/14Variable redundancy in a solid state drive
1642014035167111/27/14Shift register-based layered low density parity check decoder
1652014034078011/20/14Method and system for sliding-window based phase, gain, frequency and dc offset estimation for servo channel
1662014034123111/20/14Lane-based multiplexing for physical links in serial attached small computer system interface architectures
1672014034449211/20/14Methods and systems for reducing spurious interrupts in a data storage system
1682014034461611/20/14Techniques for providing data redundancy after reducing memory writes
1692014034496011/20/14Selective control of on-chip debug circuitry of embedded processors
1702014033427811/13/14Systems and methods for energy based head contact detection
1712014033428011/13/14Systems and methods for characterizing head contact
1722014033428111/13/14Systems and methods for data processor marginalization based upon bit error rate
1732014033449111/13/14Prediction based methods for fast routing of ip flows using communication/network processors
1742014033754011/13/14Method and system for i/o flow management for pcie devices
1752014033758311/13/14Intelligent cache window management for storage systems
1762014033767611/13/14Systems and methods for processing data with microcontroller based retry features
1772014033100111/06/14Command barrier for a solid state drive controller
1782014033109611/06/14Cross-decoding for non-volatile storage
1792014033110811/06/14Systems and methods for detecting media flaws
1802014032511710/30/14Flash translation layer with lower write amplification
1812014032514410/30/14Protection information initialization
1822014032514510/30/14Cache rebuilds based on tracking data for cache entries
1832014032514610/30/14Creating and managing logical volumes from unused space in raid disk groups
1842014032530310/30/14Systems and methods for protected data encoding
1852014031237210/23/14Semiconductor optical emitting device with grooved substrate providing multiple angled light emission paths
1862014031247510/23/14Die reuse in electrical circuits
1872014031361010/23/14Systems and methods selective complexity data decoding
1882014031394610/23/14Non-linear interference cancellation for wireless transceivers
1892014031417610/23/14Non-linear modeling of a physical system using two-dimensional look-up table with bilinear interpolation
1902014031418110/23/14Non-linear modeling of a physical system using look-up table with polynomial interpolation
1912014031426510/23/14Headphones with rotatable speaker arranged within housing of earpiece assembly
1922014031675210/23/14Non-linear modeling of a physical system using direct optimization of look-up table values
1932014031716310/23/14Vector processor having instruction set with sliding window non-linear convolutional function
1942014031733410/23/14Storage of gate training parameters for devices utilizing random access memory
1952014031734610/23/14Redundant array of independent disks systems that utilize spans with different storage device counts for a logical volume
1962014031737610/23/14Digital processor having instruction set with complex angle function
1972014030734510/16/14Systems and methods for preventing adjacent track erasure
1982014030114310/09/14Techniques for controlling recycling of blocks of memory
1992014030446410/09/14Methods and systems for performing deduplication in a data storage system
2002014030456210/09/14Method for testing paths to pull-up and pull-down of input/output pads
2012014029229810/02/14Operational amplifier-based current-sensing circuit for dc-dc voltage converters and the like
2022014029812310/02/14Scan chain reconfiguration and repair
2032014029812910/02/14Generating partially sparse generator matrix for a quasi-cyclic low-density parity-check encoder
2042014029813110/02/14Priori information based post-processing in low-density parity-check code decoders
2052014029814810/02/14Trend-analysis scheme for reliably reading data values from memory
2062014028591809/25/14Systems and methods for quality based bit error rate prediction
2072014028610209/25/14Method of optimizing solid state drive soft retry voltages
2082014028614909/25/14Automatic on-drive sync-mark search and threshold adjustment
2092014028638509/25/14Systems and methods for multi-dimensional signal equalization
2102014028945009/25/14Dynamic log likelihood ratio quantization for solid state drive controllers
2112014028955009/25/14Integrated clock architecture for improved testing
2122014028958209/25/14Systems and methods for reduced constraint code data processing
2132014026633809/18/14Biased bang-bang phase detector for clock and data recovery
2142014026639509/18/14Ac coupling circuit with hybrid switches
2152014026649709/18/14Ac coupling circuit with hybrid switches and constant load
2162014026681509/18/14Lempel-ziv data compression with shortened hash chains based on repetitive patterns
2172014026682009/18/14Interleaved multipath digital power amplification
2182014026700409/18/14User adjustable gesture space
2192014026838909/18/14Systems and methods for enhanced sync mark mis-detection protection
2202014026839009/18/14Systems and methods for transition based equalization
2212014026839109/18/14Data sequence detection in band-limited channels using cooperative sequence equalization
2222014026839709/18/14Hardware support of servo format with two preamble fields
2232014026840009/18/14Systems and methods for loop feedback
2242014026840109/18/14Systems and methods for p-distance based priority data processing
2252014026904809/18/14Retention detection and/or channel tracking policy in a flash memory based storage system
2262014026905309/18/14Nonvolatile memory data recovery after power failure
2272014026988809/18/14Adaptive continuous time linear equalizer
2282014026997809/18/14Interleaved multipath digital power amplification
2292014028041709/18/14Linear phase fir biorthogonal wavelet filters with complementarity for image noise reduction
2302014028041809/18/14Numerical method: making the infinite, finite. a universal transform and system of force vector
2312014028042909/18/14Efficient hardware structure for sorting/adding multiple inputs assigned to different bins
2322014028105709/18/14Unified message-based communications
2332014028108309/18/14Enhanced queue management
2342014028110609/18/14Direct routing between address spaces through a nontransparent peripheral component interconnect express bridge
2352014028114309/18/14Reducing flash memory write amplification and latency
2362014028117109/18/14Lock-free communication storage request reordering
2372014028128109/18/14Host command based read disturb methodology
2382014028162709/18/14Device sleep partitioning and keys
2392014028168809/18/14Method and system of data recovery in a raid controller
2402014028170309/18/14Local repair signature handling for repairable memories
2412014028176709/18/14Recovery strategy that reduces errors misidentified as reliable
2422014028178709/18/14Min-sum based hybrid non-binary low density parity check decoder
2432014028181809/18/14Method for format savings in coherently written fragmented sectors
2442014028182209/18/14Method and generation of soft decision error correction code information
2452014028184109/18/14Systems and methods for sync mark mis-detection protection
2462014028314609/18/14Tamper sensor
2472014025320309/11/14Programmable clock spreading
2482014025322209/11/14Preventing electronic device counterfeits
2492014025322609/11/14Power integrity control through active current profile management



ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009



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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Lsi Corporation in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Lsi Corporation with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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