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Lsi Corporation patents


      
Recent patent applications related to Lsi Corporation. Lsi Corporation is listed as an Agent/Assignee. Note: Lsi Corporation may have other listings under different names/spellings. We're not affiliated with Lsi Corporation, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "L" | Lsi Corporation-related inventors




Search recent Press Releases: Lsi Corporation-related press releases
Count Application # Date Lsi Corporation patents (updated weekly) - BOOKMARK this page
12016003418502/04/16 Host-based device driver splitting of input/out for redundant array of independent disks systems
22016003418602/04/16 Host-based device drivers for enhancing operations in redundant array of independent disks systems
32016003439302/04/16 Slice-based random access buffer for data interleaving
42016003538402/04/16 Skew-tolerant multiple-reader array in array-reader based magnetic recording
52016002639901/28/16 Block i/o interface for a host bus adapter that utilizes nvdram
62016002657501/28/16 Selective mirroring in caches for logical volumes
72016002657901/28/16 Storage controller and managing metadata operations in a cache
82016002685701/28/16 Image processor comprising gesture recognition system with static hand pose recognition based on dynamic warping
92016002688901/28/16 Image processor with edge-preserving noise suppression functionality
102016002841901/28/16 Systems and methods for rank independent cyclic data encoding
112016002851401/28/16 Configurable transmitter hardware block and methods
122016001899501/21/16 Raid system for processing i/o requests utilizing xor commands
132016002015801/21/16 Systems and methods for self test circuit security
142016002078301/21/16 Low density parity check decoder with relative indexing
152016001284601/14/16 Serial port communication for storage device using single bidirectional serial data line
162016000446501/07/16 Caching systems and methods with simulated nvdram
172016000464401/07/16 Storage controller and managing modified data flush operations from a cache
182016000465301/07/16 Caching systems and methods with simulated nvdram
192016000491901/07/16 Image processor with evaluation layer implementing software and hardware algorithms of different precision
202016000517901/07/16 Methods and merging depth images generated using distinct depth imaging techniques
212015038004712/31/15 Adaptive filter-based narrowband interference detection, estimation and cancellation
222015038005012/31/15 Multi-level enumerative encoder and decoder
232015038111812/31/15 Eliminating systematic imbalances and reducing circuit parameter variations in high gain amplifiers
242015038114712/31/15 Configurable generic filter hardware block and methods
252015038139312/31/15 Adaptive cancellation of voltage offset in a communication system
262015037073912/24/15 Local reconnection attempts for serial attached small computer system interface expanders
272015037269712/24/15 On-die error detection and correction during multi-step programming
282015036326412/17/15 Cell-to-cell program interference aware data recovery when ecc fails with an optimum read reference voltage
292015036332012/17/15 Write back caching of boot disk in a uefi environment
302015036420512/17/15 Inter-cell interference estimation based on a pattern dependent histogram
312015035670812/10/15 Target image generation utilizing a functional based on functions of information from other images
322015034676212/03/15 Dwell timers for serial attached small computer system interface devices
332015034728912/03/15 Forced map entry flush to prevent return of old data
342015034731012/03/15 Storage controller and managing metadata in a cache store
352015034859412/03/15 Memory banks with shared input/output circuitry
362015034981112/03/15 Scalable mapping with integrated summing of samples for multiple streams in a radio interface frame
372015034998812/03/15 Selecting floating tap positions in a floating tap equalizer
382015035072112/03/15 Pll scan hdtv products
392015033918911/26/15 Fixed point conversion of llr values based on correlation
402015033174811/19/15 Method to dynamically update llrs in an ssd drive and/or controller
412015033176511/19/15 Coordination techniques for redundant array of independent disks storage controllers
422015033177311/19/15 Sideband logic for monitoring pcie headers
432015033275511/19/15 Memory cell having built-in read and write assist
442015033374511/19/15 Voltage comparator
452015032359511/12/15 System for reducing test time using embedded test compression cycle balancing
462015032413611/12/15 Storage system having fifo storage and reserved storage
472015032429511/12/15 Temporal tracking of cache data
482015032430011/12/15 System and methods for efficient i/o processing using multi-level out-of-band hinting
492015032526611/12/15 Multi-dimensional optimization of read channel
502015031709011/05/15 System and life management for low endurance ssd nand devices used as secondary cache
512015031720411/05/15 Systems and methods for efficient data refresh in a storage device
522015031721911/05/15 Logical volume migration in single server high availability environments
532015031801411/05/15 Multiplexed communication in a storage device
542015031803011/05/15 Multiplexed synchronous serial port communication with skew control for storage device
552015031874011/05/15 Electromagnetic energy transfer using tunable inductors
562015031901811/05/15 Slicer trim methodology and device
572015030973210/29/15 Selectively configuring hard-disk drive system
582015030987210/29/15 Data recovery once ecc fails to correct the data
592015031203710/29/15 Data scrambling initialization
602015031206010/29/15 Decision feedback equalization slicer with enhanced latch sensitivity
612015031206810/29/15 Simplified and effective offset calibration circuit for rxlos in serdes
622015030193410/22/15 Flash-based data storage with dual map-based serialization
632015030195610/22/15 Data storage system with caching using application field to carry data block protection information
642015030259310/22/15 Front-end architecture for image processing
652015030288710/22/15 Cross-talk measurement in array reader magnetic recording system
662015030291810/22/15 Word line decoders for dual rail static random access memories
672015030339610/22/15 Method and system for an organic light emitting diode structure
682015030394310/22/15 Systems and methods for puncture based data protection
692015030394710/22/15 Systems and methods for protected portion data processing
702015029380810/15/15 Soft read handling of read noise
712015029473910/15/15 Online histogram and soft information learning
722015028642110/08/15 Read policy for system data of solid state drives
732015028643810/08/15 System, method and computer-readable medium for dynamically configuring an operational mode in a storage controller
742015028652310/08/15 Systems and methods for differential message scaling in a decoding process
752015028652810/08/15 Error correction code (ecc) selection in nand flash controllers with multiple error correction codes
762015028660010/08/15 Arbitration monitoring for serial attached small computer system interface systems during discovery
772015028660410/08/15 Device abstracted zone management of serial attached small computer system interface topologies
782015028747810/08/15 Bad memory unit detection in a solid state drive
792015027939810/01/15 Locking a disk-locked clock using timestamps of successive servo address marks in a spiral servo track
802015027941510/01/15 Systems and methods for skew tolerant multi-head data processing
812015027942110/01/15 Adaptive calibration of noise predictive finite impulse response filter based on decoder convergence
822015026887109/24/15 Read disturb handling in nand flash
832015026902509/24/15 Write redirection in redundant array of independent disks systems
842015026905409/24/15 Multiple core execution trace buffer
852015026909709/24/15 System and elastic despreader memory management
862015026930409/24/15 System and employing signoff-quality timing analysis information concurrently in multiple scenarios to reduce total power within a circuit design
872015026942509/24/15 Dynamic hand gesture recognition with selective enabling based on detected hand velocity
882015026999009/24/15 Memory sense amplifier and column pre-charger
892015026163609/17/15 Data transformations to improve rom yield and programming time
902015026259209/17/15 Systems and methods for distortion characterization
912015026259809/17/15 Systems and methods for head position estimation
922015026266709/17/15 Low power hit bitline driver for content-addressable memory
932015026271009/17/15 Method and system for reducing memory test time utilizing a built-in self-test architecture
942015026294909/17/15 Method for fabricating equal height metal pillars of different diameters
952015026295009/17/15 Method for fabricating equal height metal pillars of different diameters
962015026373209/17/15 Systems and methods for voltage level shifting in a device
972015026384809/17/15 Cdr relock with corrective integral register seeding
982015025510109/10/15 Track misregistration sensitive initialization of joint equalizer
992015025510909/10/15 Non-decision directed magnetoresistive asymetry estimation
1002015025511309/10/15 Online iteration resource allocation for large sector format drive
1012015025514809/10/15 Bit line write assist for static random access memory architectures
1022015025619609/10/15 Soft decoding of polar codes
1032015025636309/10/15 Integrated pam4/nrz n-way parallel digital unrolled decision feedback equalizer (dfe)
1042015025636409/10/15 Group delay based back channel post cursor adaptation
1052015024955509/03/15 Serdes pvt detection and closed loop adaptation
1062015024213308/27/15 Storage workload hinting
1072015024268108/27/15 System and image processing
1082015024331008/27/15 Systems and methods for multi-head separation determination
1092015024331108/27/15 Systems and methods for synchronization hand shaking in a storage device
1102015024332108/27/15 Reading data from hard disks having reduced preambles
1112015024332208/27/15 Systems and methods for multi-head servo data processing
1122015024336308/27/15 Adjusting log likelihood ratio values to compensate misplacement of read voltages
1132015024353408/27/15 Copper wire bonding apparatus using a purge gas to enhance ball bond reliability
1142015024361708/27/15 Method for flip-chip bonding using copper pillars
1152015023442308/20/15 Baud rate phase detector with no error latches
1162015023570508/20/15 System to control a width of a programming threshold voltage distribution width when writing hot-read data
1172015023672608/20/15 Refresh, run, aggregate decoder recovery
1182015023687508/20/15 Method and pre-cursor intersymbol interference correction
1192015022731408/13/15 Systems and methods for last written page handling in a memory device
1202015022740308/13/15 Decoding electronic non-volatile computer storage apparatus
1212015022741808/13/15 Hot-read data aggregation and code selection
1222015022748608/13/15 Method to facilitate fast context switching for partial and extended path extension to remote expanders
1232015022830208/13/15 Zero phase start estimation in readback signals
1242015022830308/13/15 Read channel sampling utilizing two quantization modules for increased sample bit width
1252015022830408/13/15 Systems and methods for end of fragment marker based data alignment
1262015022933108/13/15 Systems and methods for area efficient data encoding
1272015022933308/13/15 Systems and methods for rank deficient encoding
1282015022933708/13/15 Mitigation of write errors in multi-level cell flash memory through adaptive error correction code decoding
1292015022015308/06/15 Gesture recognition system with finite state machine control of cursor detector and dynamic gesture detector
1302015022038808/06/15 Systems and methods for hard error reduction in a solid state memory device
1312015022045208/06/15 System, method and computer-readable medium for dynamically mapping a non-volatile memory store
1322015022074408/06/15 System for execution of security related functions
1332015022080408/06/15 Image processor with edge selection functionality
1342015022133308/06/15 Reader separation dependent linear and track density push for array reader based magnetic recording
1352015021388107/30/15 Integrated read/write tracking in sram
1362015020575207/23/15 High density mapping for multiple converter samples in multiple lane interface
1372015020631807/23/15 Method and image enhancement and edge verificaton using at least one additional image
1382015020657807/23/15 Area-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail sram memories
1392015020764807/23/15 Modular low power serializer-deserializer
1402015020807607/23/15 Multi-core architecture for low latency video decoder
1412015019912907/16/15 System and providing data services in direct attached storage via multiple de-clustered raid pools
1422015019914007/16/15 Interleaving codewords over multiple flash planes
1432015019914907/16/15 Framework for balancing robustness and latency during collection of statistics from soft reads
1442015019922707/16/15 Fault detection and identification in a multi-initiator system
1452015019924407/16/15 Intelligent i/o cache rebuild in a storage controller
1462015019926907/16/15 Enhanced ssd caching
1472015019999107/16/15 Multiple track detection
1482015020068107/16/15 Segmented digital-to-analog converter with overlapping segments
1492015019356407/09/15 System and using clock chain signals of an on-chip clock controller to control cross-domain paths
1502015019421907/09/15 Capacitance coupling parameter estimation in flash memories
1512015019510807/09/15 Receiver with pipelined tap coefficients and shift control
1522015019535707/09/15 Enhancing active link utilization in serial attached scsi topologies
1532015018631707/02/15 Method and detecting the initiator/target orientation of a smart bridge
1542015018738407/02/15 Two-dimensional magnetic recording reader offset estimation
1552015018738507/02/15 Systems and methods for multi-head balancing in a storage device
1562015018855107/02/15 Clock recovery using quantized phase error samples using jitter frequency-dependent quantization thresholds and loop gains
1572015018857607/02/15 Systems and methods for efficient targeted symbol flipping
1582015017814906/25/15 Method to distribute user data and error correction data over different page types by leveraging error rate variations
1592015017815206/25/15 Preventing programming errors from occurring when programming flash memory cells
1602015017820106/25/15 System for efficient caching of swap i/o and/or similar i/o pattern(s)
1612015017831206/25/15 Attribute-based assistance request system for sequentially contacting nearby contacts without having them divulge their presence or location
1622015017921306/25/15 Servo channel with equalizer adaptation
1632015018051206/25/15 Systems and methods of converting detector output to multi-level soft information
1642015016945806/18/15 System and methods for caching a small size i/o to improve caching device endurance
1652015017067606/18/15 Skew-aware disk format for array reader based magnetic recording
1662015017070606/18/15 Systems and methods for ati characterization
1672015016086906/11/15 Systems and methods for multi-dimensional data processor operational marginalization
1682015016088606/11/15 Method and system for programmable sequencer for processing i/o for various pcie disk drives
1692015016104506/11/15 Slice formatting and interleaving for interleaved sectors
1702015016205706/11/15 Multiple retry reads in a read channel of a memory
1712015016278106/11/15 Illumination-based charging system for portable devices
1722015016336306/11/15 Low complexity tone/voice discrimination method using a rising edge of a frequency power envelope
1732015015411406/04/15 System and method to interleave memory
1742015015413806/04/15 Wide port emulation at serial attached scsi expanders
1752015015502106/04/15 Area-efficient process-and-temperature-adaptive self-time scheme for performance and power improvement
1762015014574005/28/15 Integrated frequency multiplier and slot antenna
1772015014692005/28/15 Gesture recognition method and apparatus utilizing asynchronous multithreaded processing
1782015014939505/28/15 Incremental updates for ordered multi-field classification rules when represented by a tree of longest prefix matching tables
1792015014969805/28/15 Eliminating or reducing programming errors when programming flash memory cells
1802015014984005/28/15 Read retry for non-volatile memories
1812015014985505/28/15 Bit-line defect detection using unsatisified parity code checks
1822015014985605/28/15 Decoding with log likelihood ratios stored in a controller
1832015014987105/28/15 Flash channel with selective decoder likelihood dampening
1842015013785505/21/15 Current to voltage converter
1852015013886305/21/15 Interleaved write assist for hierarchical bitline sram architectures
1862015013886405/21/15 Memory architecture with alternating segments and multiple bitlines
1872015013887605/21/15 Global bitline write assist for sram architectures
1882015013948705/21/15 Image processor with static pose recognition module utilizing segmented region of interest
1892015014316405/21/15 I/o request mirroring in a clustered storage system
1902015014319605/21/15 Systems and methods for faid follower decoding
1912015014320205/21/15 Systems and methods for soft decision generation in a solid state memory system
1922015013137305/14/15 Incremental programming pulse optimization to reduce write errors
1932015013461305/14/15 Systems and methods for lost synchronization data set reprocessing
1942015013485505/14/15 Decoupling host and device address maps for a peripheral component interconnect express controller
1952015013500605/14/15 System and write hole protection for a multiple-node storage cluster
1962015013503105/14/15 Dynamic per-decoder control of log likelihood ratio and decoding parameters
1972015013503205/14/15 Detection/erasure of random write errors using converged hard decisions
1982015012787105/07/15 Updated io memory management unit identity settings for dma remapping
1992015012788305/07/15 Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory
2002015012800605/07/15 Device quality metrics using unsatisfied parity checks
2012015011709704/30/15 Systems and methods for sub-zero threshold characterization in a memory cell
2022015011722604/30/15 Method and system for session based data monitoring for wireless edge content caching networks
2032015012098104/30/15 Data interface for point-to-point communications between devices
2042015012098904/30/15 Tracking and utilizing second level map index for recycling of solid state drive blocks
2052015012108804/30/15 Method of managing aligned and unaligned data bands in a self encrypting solid state drive
2062015012117304/30/15 Systems and methods for internal disk drive data compression
2072015010905204/23/15 Closed-loop adaptive voltage scaling for integrated circuits
2082015011016504/23/15 Transmitter training using receiver equalizer coefficients
2092015011320504/23/15 Systems and methods for latency based data recycling in a solid state memory system
2102015011331204/23/15 System and detecting server removal from a cluster to enable fast failover of storage
2112015011331804/23/15 Systems and methods for soft data utilization in a solid state memory system
2122015011333504/23/15 Sending failure information from a solid state drive (ssd) to a host device
2132015011335404/23/15 Generating soft decoding information for flash memory error correction using hard decision patterns
2142015010360404/16/15 Memory array architectures having memory cells with shared write assist circuitry
2152015010396104/16/15 Digital frequency band detector for clock and data recovery
2162015010657704/16/15 De-interleaving on an as-needed basis
2172015010666604/16/15 Speculative bit error rate calculator
2182015010667504/16/15 Systems and methods for multi-algorithm concatenation encoding and decoding
2192015009761104/09/15 Voltage follower having a feed-forward device
2202015010081004/09/15 Adaptive power-down of disk drives based on predicted idle time
2212015009162004/02/15 Reducing current variation when switching clocks
2222015009229004/02/15 Non-binary layered low density parity check decoder
2232015009248904/02/15 Flash memory reference voltage detection with tracking of cross-points of cell voltage distributions using histograms
2242015008539203/26/15 System and monitoring preamble signal quality
2252015008558703/26/15 Ping-pong buffer using single-port memory
2262015008559203/26/15 Bit-line discharge assistance in memory devices
2272015008595703/26/15 Method of calibrating a slicer in a receiver or the like
2282015008910203/26/15 Solid state drives that cache boot data
2292015008913203/26/15 Dynamic storage volume configuration based on input/output requests
2302015008933003/26/15 Systems and methods for enhanced data recovery in a solid state memory system
2312015007718803/19/15 Voltage follower amplifier
2322015007727703/19/15 Reduced polar codes
2332015007810303/19/15 Sensing technique for single-ended bit line memory architectures
2342015008162603/19/15 Systems and methods for recovered data stitching
2352015008164903/19/15 In-line deduplication for a network and/or storage platform
2362015008211503/19/15 Systems and methods for fragmented data recovery
2372015008212103/19/15 Method of erase state handling in flash channel tracking
2382015008212403/19/15 Spatially decoupled redundancy schemes for a solid state drive (ssd)
2392015007079603/12/15 Array-reader based magnetic recording systems with mixed synchronization
2402015007432703/12/15 Active recycling for solid state drive
2412015007432803/12/15 Dynamic map pre-fetching for improved sequential reads of a solid-state media
2422015007435503/12/15 Efficient caching of file system journals
2432015007450103/12/15 Cascaded viterbi bitstream generator
2442015006273003/05/15 Array-reader based magnetic recording systems with quadrature amplitude modulation
2452015006273203/05/15 Systems and methods for two stage tone reduction
2462015006273403/05/15 Systems and methods for multi-level encoding and decoding
2472015006273703/05/15 Adaptive pattern detection for pattern-dependent write current control in a magnetic recording system
2482015006273803/05/15 Systems and methods for variable sector count spreading and de-spreading
2492015006321703/05/15 Mapping between variable width samples and a frame



ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009



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