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Lsi Corporation patents


      
Recent patent applications related to Lsi Corporation. Lsi Corporation is listed as an Agent/Assignee. Note: Lsi Corporation may have other listings under different names/spellings. We're not affiliated with Lsi Corporation, we're just tracking patents.

ARCHIVE: New 2014 2013 2012 2011 2010 2009 | Company Directory "L" | Lsi Corporation-related inventors



Non-linear interference cancellation for wireless transceivers

Lsi

Non-linear interference cancellation for wireless transceivers

Non-linear modeling of a physical system using two-dimensional look-up table with bilinear interpolation

Lsi

Non-linear modeling of a physical system using two-dimensional look-up table with bilinear interpolation

Non-linear modeling of a physical system using two-dimensional look-up table with bilinear interpolation

Lsi

Non-linear modeling of a physical system using look-up table with polynomial interpolation

Search recent Press Releases: Lsi Corporation-related press releases
Count Application # Date Lsi Corporation patents (updated weekly) - BOOKMARK this page
12014031237210/23/14 new patent  Semiconductor optical emitting device with grooved substrate providing multiple angled light emission paths
22014031247510/23/14 new patent  Die reuse in electrical circuits
32014031361010/23/14 new patent  Systems and methods selective complexity data decoding
42014031394610/23/14 new patent  Non-linear interference cancellation for wireless transceivers
52014031417610/23/14 new patent  Non-linear modeling of a physical system using two-dimensional look-up table with bilinear interpolation
62014031418110/23/14 new patent  Non-linear modeling of a physical system using look-up table with polynomial interpolation
72014031426510/23/14 new patent  Headphones with rotatable speaker arranged within housing of earpiece assembly
82014031675210/23/14 new patent  Non-linear modeling of a physical system using direct optimization of look-up table values
92014031716310/23/14 new patent  Vector processor having instruction set with sliding window non-linear convolutional function
102014031733410/23/14 new patent  Storage of gate training parameters for devices utilizing random access memory
112014031734610/23/14 new patent  Redundant array of independent disks systems that utilize spans with different storage device counts for a logical volume
122014031737610/23/14 new patent  Digital processor having instruction set with complex angle function
132014030734510/16/14Systems and methods for preventing adjacent track erasure
142014030114310/09/14Techniques for controlling recycling of blocks of memory
152014030446410/09/14Methods and systems for performing deduplication in a data storage system
162014030456210/09/14Method for testing paths to pull-up and pull-down of input/output pads
172014029229810/02/14Operational amplifier-based current-sensing circuit for dc-dc voltage converters and the like
182014029812310/02/14Scan chain reconfiguration and repair
192014029812910/02/14Generating partially sparse generator matrix for a quasi-cyclic low-density parity-check encoder
202014029813110/02/14Priori information based post-processing in low-density parity-check code decoders
212014029814810/02/14Trend-analysis scheme for reliably reading data values from memory
222014028591809/25/14Systems and methods for quality based bit error rate prediction
232014028610209/25/14Method of optimizing solid state drive soft retry voltages
242014028614909/25/14Automatic on-drive sync-mark search and threshold adjustment
252014028638509/25/14Systems and methods for multi-dimensional signal equalization
262014028945009/25/14Dynamic log likelihood ratio quantization for solid state drive controllers
272014028955009/25/14Integrated clock architecture for improved testing
282014028958209/25/14Systems and methods for reduced constraint code data processing
292014026633809/18/14Biased bang-bang phase detector for clock and data recovery
302014026639509/18/14Ac coupling circuit with hybrid switches
312014026649709/18/14Ac coupling circuit with hybrid switches and constant load
322014026681509/18/14Lempel-ziv data compression with shortened hash chains based on repetitive patterns
332014026682009/18/14Interleaved multipath digital power amplification
342014026700409/18/14User adjustable gesture space
352014026838909/18/14Systems and methods for enhanced sync mark mis-detection protection
362014026839009/18/14Systems and methods for transition based equalization
372014026839109/18/14Data sequence detection in band-limited channels using cooperative sequence equalization
382014026839709/18/14Hardware support of servo format with two preamble fields
392014026840009/18/14Systems and methods for loop feedback
402014026840109/18/14Systems and methods for p-distance based priority data processing
412014026904809/18/14Retention detection and/or channel tracking policy in a flash memory based storage system
422014026905309/18/14Nonvolatile memory data recovery after power failure
432014026988809/18/14Adaptive continuous time linear equalizer
442014026997809/18/14Interleaved multipath digital power amplification
452014028041709/18/14Linear phase fir biorthogonal wavelet filters with complementarity for image noise reduction
462014028041809/18/14Numerical method: making the infinite, finite. a universal transform and system of force vector
472014028042909/18/14Efficient hardware structure for sorting/adding multiple inputs assigned to different bins
482014028105709/18/14Unified message-based communications
492014028108309/18/14Enhanced queue management
502014028110609/18/14Direct routing between address spaces through a nontransparent peripheral component interconnect express bridge
512014028114309/18/14Reducing flash memory write amplification and latency
522014028117109/18/14Lock-free communication storage request reordering
532014028128109/18/14Host command based read disturb methodology
542014028162709/18/14Device sleep partitioning and keys
552014028168809/18/14Method and system of data recovery in a raid controller
562014028170309/18/14Local repair signature handling for repairable memories
572014028176709/18/14Recovery strategy that reduces errors misidentified as reliable
582014028178709/18/14Min-sum based hybrid non-binary low density parity check decoder
592014028181809/18/14Method for format savings in coherently written fragmented sectors
602014028182209/18/14Method and apparatus for generation of soft decision error correction code information
612014028184109/18/14Systems and methods for sync mark mis-detection protection
622014028314609/18/14Tamper sensor
632014025320309/11/14Programmable clock spreading
642014025322209/11/14Preventing electronic device counterfeits
652014025322609/11/14Power integrity control through active current profile management
662014025404109/11/14Servo marginalization
672014025404309/11/14Sampling-phase acquisition based on channel-impulse-response estimation
682014025459309/11/14Network processor having multicasting protocol
692014025465509/11/14Adaptation of equalizer settings using error signals sampled at several different phases
702014025473509/11/14Transmit reference signal cleanup within a synchronous network application
712014025837509/11/14System and method for large object cache management in a network
722014025856509/11/14Smart discovery model in a serial attached small computer system topology
732014025857209/11/14Preemptive connection switching for serial attached small computer system interface systems
742014025858709/11/14Self recovery in a solid state drive
752014025859509/11/14System, method and computer-readable medium for dynamic cache sharing in a flash-based caching solution supporting virtual machines
762014025859809/11/14Scalable storage devices
772014025861009/11/14Raid cache memory system with volume windows
782014025861309/11/14Volume change flags for incremental snapshots of stored data
792014025862809/11/14System, method and computer-readable medium for managing a cache store to achieve improved cache ramp-up across system reboots
802014025875509/11/14Storage device power failure infrastructure
812014025875909/11/14System and method for de-queuing an active queue
822014025876909/11/14Partial r-block recycling
832014024751409/04/14Systems and methods for adc sample based inter-track interference compensation
842014025024609/04/14Intelligent data buffering between interfaces
852014025026309/04/14Techniques for reducing memory write operations using coalescing memory buffers and difference information
862014025026909/04/14Declustered raid pool as backup for raid volumes
872014025031509/04/14Storage system data hardening
882014025033809/04/14Virtual function timeout for single root input/output virtualization controllers
892014025035209/04/14Systems and methods for signal reduction based data processor marginalization
902014024003308/28/14On-die programming of integrated circuit bond pads
912014024046708/28/14Image processing method and apparatus for elimination of depth artifacts
922014024086408/28/14Storage device having degauss circuitry configured for generating degauss signal with asymmetric decay envelopes
932014024087008/28/14Analog tunneling current sensors for use with disk drive storage devices
942014024102808/28/14Two-bit read-only memory cell
952014024105608/28/14Reduced complexity reliability computations for flash memories
962014024106108/28/14Fast access with low leakage and low power technique for read only memory devices
972014024106208/28/14Modular, scalable rigid flex memory module
982014024147808/28/14Timing phase estimation for clock and data recovery
992014024487508/28/14Priority based connection arbitration in a sas topology to facilitate quality of service (qos) in sas transport
1002014024490108/28/14Metadata management for a flash drive
1012014024490208/28/14Fast read in write-back cached memory
1022014024492608/28/14Dedicated memory structure for sector spreading interleaving
1032014024492808/28/14Method and system to provide data protection to raid 0/ or degraded redundant virtual disk
1042014024493608/28/14Maintaining cache coherency between storage controllers
1052014024508608/28/14Test signal generator for low-density parity-check decoder
1062014024509308/28/14Master boot record protection in a solid state drive
1072014024530008/28/14Dynamically balanced credit for virtual functions in single root input/output virtualization
1082014024540808/28/14Biometric approach to track credentials of anonymous user of a mobile device
1092014023312808/21/14Systems and methods for burst demodulation
1102014023312908/21/14Noise predictive filter adaptation for inter-track interference cancellation
1112014023313008/21/14Systems and methods for determining noise components in a signal set
1122014023330208/21/14Write-tracking circuitry for memory devices
1132014023332208/21/14Adaptive architecture in a channel detector for nand flash channels
1142014023356708/21/14High speed network bridging
1152014023361908/21/14Pattern-based loss of signal detector
1162014023366808/21/14Code forwarding and clock generation for transmitter repeaters
1172014023716208/21/14Non-volatile memory channel control using a general purpose programmable processor in combination with a low level programmable sequencer
1182014023716308/21/14Reducing writes to solid state drive cache memories of storage controllers
1192014023716608/21/14Higher-level redundancy information computation
1202014023719308/21/14Cache window management
1212014023731308/21/14Systems and methods for trapping set disruption
1222014023731408/21/14Systems and methods for skip layer data decoding
1232014023732908/21/14Ratio-adjustable sync mark detection system
1242014022566908/14/14Extended variable gain amplification bandwidth with high-frequency boost
1252014022622908/14/14Systems and methods for shared layer data decoding
1262014022623308/14/14Storage device with reflection compensation circuitry
1272014022623408/14/14System and method for providing controllable steady state current waveshaping in a hard disk drive (hdd) preamplifier
1282014022685408/14/14Three-dimensional region of interest tracking based on key frame matching
1292014022689508/14/14Feature point based robust three-dimensional rigid body registration
1302014022796908/14/14Indium tin oxide loop antenna for near field communication
1312014022807308/14/14Automatic presentation of an image from a camera responsive to detection of a particular type of movement of a user device
1322014022965108/14/14Managing arbitration in mixed link rate wide ports
1332014022965208/14/14Methods and structure for fast context switching among a plurality of expanders in a serial attached scsi domain
1342014022965808/14/14Cache load balancing in storage controllers
1352014022967008/14/14Cache coherency and synchronization support in expanders in a raid topology with multiple initiators
1362014022967608/14/14Rebuild of redundant secondary storage cache
1372014022970008/14/14Systems and methods for accommodating end of transfer request in a data storage device
1382014022973308/14/14System and method for key wrapping to allow secure access to media by multiple authorities with modifiable permissions
1392014022975708/14/14Restoring expander operations in a data storage switch
1402014022976908/14/14Methods and structure for single root input/output virtualization enhancement in peripheral component interconnect express systems
1412014022977808/14/14At-speed scan testing of interface functional logic of an embedded memory or other circuit core
1422014022979908/14/14Statistical adaptive error correction for a flash memory
1432014022980608/14/14Systems and methods for distributed low density parity check decoding
1442014022994108/14/14Method and controller device for quality of service (qos) caching in a virtualized environment
1452014022995408/14/14Systems and methods for data quality based variable data process scheduling
1462014021902808/07/14Compensation loop for read voltage adaptation
1472014022076008/07/14Integration of shallow trench isolation and through-substrate vias into integrated circuit designs
1482014022307108/07/14Method and system for reducing write latency in a data storage system by using a command-push model
1492014022307208/07/14Tiered caching using single level cell and multi-level cell flash technology
1502014022307508/07/14Physical-to-logical address map to speed up a recycle operation in a solid state drive
1512014022309408/07/14Selective raid protection for cache memory
1522014022310608/07/14Method to throttle rate of data caching for improved i/o performance
1532014022311408/07/14Buffer for managing data samples in a read channel
1542014022313608/07/14Lookup tables utilizing read only memory and combinational logic
1552014022325908/07/14Memory architecture for layered low-density parity-check decoder
1562014022326708/07/14Radix-4 viterbi forward error correction decoding
1572014022327008/07/14Classifying bit errors in transmitted run length limited data
1582014022329508/07/14Geographic based spell check
1592014021133607/31/14Automatic gain control loop adaptation for enhanced nyquist data pattern detection
1602014021133707/31/14Systems and methods for improved short media defect detection
1612014021183907/31/14Receiver having limiter-enhanced data eye openings
1622014021474807/31/14Incremental dfa compilation with single rule granularity
1632014021474907/31/14System and method for dfa-nfa splitting
1642014021509007/31/14Dfa sub-scans
1652014021512307/31/14Controller-opaque communication with non-volatile memory devices
1662014021514907/31/14File-system aware snapshots of stored data
1672014021519907/31/14Fast-boot list to speed booting an operating system
1682014021528507/31/14Integrated-interleaved low density parity check (ldpc) codes
1692014021534107/31/14Transitioning between pages of content on a display of a user device
1702014020465907/24/14Capacitive coupled sense amplifier biased at maximum gain point
1712014020466007/24/14Memory having sense amplifier for output tracking by controlled feedback latch
1722014020468307/24/14Margin free pvt tolerant fast self-timed sense amplifier reset circuit
1732014020498707/24/14System and method for determining channel loss in a dispersive communication channel at the nyquist frequency
1742014020499507/24/14Efficient region of interest detection
1752014020500507/24/14Method and apparatus for mpeg-2 to h.264 video transcoding
1762014020774307/24/14Method for storage driven de-duplication of server memory
1772014020799607/24/14Hybrid hard disk drive having a flash storage processor
1782014020800307/24/14Variable-size flash translation layer
1792014020800407/24/14Translation layer partitioned between host and controller
1802014020800507/24/14System, method and computer-readable medium for providing selective protection and endurance improvements in flash-based cache
1812014020800707/24/14Management of and region selection for writes to non-volatile memory
1822014020802407/24/14System and methods for performing embedded full-stripe write operations to a data volume with data elements distributed across multiple modules
1832014020804607/24/14Storage device out-of-space handling
1842014020804807/24/14Method and apparatus for efficient remote copy
1852014020806107/24/14Locating data in non-volatile memory
1862014020806207/24/14Storage address space to nvm address, span, and length mapping/converting
1872014020807607/24/14Dfa compression and execution
1882014020817507/24/14At-speed scan testing of clock divider logic in a clock module of an integrated circuit
1892014020818007/24/14Systems and methods for reusing a layered decoder to yield a non-layered result
1902014019840407/17/14Systems and methods for x-sample based noise cancellation
1912014019840507/17/14Systems and methods for loop processing with variance adaptation
1922014019878907/17/14Low latency in-line data compression for packet transmission systems
1932014020084907/17/14Diversity loop detector with component detector switching
1942014020144207/17/14Cache based storage controller
1952014020146207/17/14Subtractive validation of cache lines for virtual machines
1962014020158407/17/14Scan test circuitry comprising at least one scan chain and associated reset multiplexing circuitry
1972014020158507/17/14State-split based endec
1982014019140307/10/14Multi-die semiconductor package and method of manufacturing thereof
1992014019180107/10/14Bicmos gate driver for class-s radio frequency power amplifier
2002014019260307/10/14Differential sense amplifier for solid-state memories
2012014019263307/10/14System and method for providing fast and efficient flushing of a forwarding database in a network processor
2022014019284107/10/14Ultra-wideband loss of signal detector at a receiver in a high speed serializer/deserializer (serdes) application
2032014019293507/10/14Receiver with dual clock recovery circuits
2042014019309207/10/14Superresolution image processing using an invertible sparse matrix
2052014019571407/10/14Methods and structure for buffering host requests in serial attached scsi expanders
2062014019571807/10/14Control logic design to support usb cache offload
2072014019573107/10/14Physical link management
2082014019573207/10/14Method and system to maintain maximum performance levels in all disk groups by using controller vds for background tasks
2092014018432307/03/14Hybrid digital/analog power amplifier
2102014018515807/03/14Fly height control for hard disk drives
2112014018515907/03/14Sync mark detection using branch metrics from data detector
2122014018536607/03/14Pre-charge tracking of global read lines in high speed sram
2132014018565807/03/14Serdes data sampling gear shifter
2142014018896907/03/14Efficient algorithm to bit matrix symmetry
2152014018942107/03/14Non-volatile memory program failure recovery via redundant arrays
2162014018967307/03/14Management of device firmware update effects as seen by a host
2172014017623006/26/14High-voltage tolerant biasing arrangement using low-voltage devices
2182014017623906/26/14Adaptive control mechanisms to control input and output common-mode voltages of differential amplifier circuits
2192014017708206/26/14Over-sampled signal equalizer
2202014017708406/26/14Systems and methods for managed operational marginalization
2212014017708706/26/14Equalization combining outputs of multiple component filters
2222014017732406/26/14Single-port read multiple-port write storage device using single-port memory cells
2232014017737106/26/14Suspend sdram refresh cycles during normal ddr operation
2242014018132706/26/14I/o device and computing host interoperation
2252014018137006/26/14Method to apply fine grain wear leveling and garbage collection
2262014018157006/26/14Signal processing circuitry with frontend and backend circuitry controlled by separate clocks
2272014018161706/26/14Management of non-valid decision patterns of a soft read retry operation
2282014018162406/26/14Majority-tabular post processing of quasi-cyclic low-density parity-check codes
2292014018162506/26/14Read channel data signal detection with reduced-state trellis
2302014018184506/26/14Single serdes transmitter driver design for both ethernet and peripheral component interconnect express applications
2312014016880906/19/14Tag multiplication via a preamplifier interface
2322014016881006/19/14Systems and methods for adaptive threshold pattern detection
2332014016881106/19/14Irregular low density parity check decoder with low syndrome error handling
2342014016921006/19/14Link rate availability based arbitration
2352014016942606/19/14Receiver with distortion compensation circuit
2362014016944006/19/14Adaptive cancellation of voltage offset in a communication system
2372014016945706/19/14Performance control in video encoding
2382014016946806/19/14Picture refresh with constant-bit budget
2392014017279706/19/14Method and apparatus to share a single storage drive across a large number of unique systems when data is highly redundant
2402014017293406/19/14Systems and methods for data retry using averaging process
2412014017313906/19/14System, method, and computer program product for inserting a gap in information sent from a drive to a host device
2422014017315306/19/14Method and system for detecting multiple expanders in an sas topology having the same address
2432014017316506/19/14Expander for loop architectures
2442014017325406/19/14Cache prefetch for deterministic finite automaton instructions
2452014017325606/19/14Processor configured for operation with multiple operation codes per instruction
2462014017333006/19/14Split brain detection and recovery system
2472014017334606/19/14Validating operation of system-on-chip controller for storage device using programmable state machine
2482014017338506/19/14Low density parity check decoder with dynamic scaling
2492014017360306/19/14Multiple step non-deterministic finite automaton matching


ARCHIVE: New 2014 2013 2012 2011 2010 2009



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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Lsi Corporation in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Lsi Corporation with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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