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Lsi Corporation
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Lsi Corporation_20100128
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Lsi Corporation patents

Recent patent applications related to Lsi Corporation. Lsi Corporation is listed as an Agent/Assignee. Note: Lsi Corporation may have other listings under different names/spellings. We're not affiliated with Lsi Corporation, we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "L" | Lsi Corporation-related inventors

Search recent Press Releases: Lsi Corporation-related press releases
Count Application # Date Lsi Corporation patents (updated weekly) - BOOKMARK this page
12015027939810/01/15  new patent  Locking a disk-locked clock using timestamps of successive servo address marks in a spiral servo track
22015027941510/01/15  new patent  Systems and methods for skew tolerant multi-head data processing
32015027942110/01/15  new patent  Adaptive calibration of noise predictive finite impulse response filter based on decoder convergence
42015026887109/24/15 Read disturb handling in nand flash
52015026902509/24/15 Write redirection in redundant array of independent disks systems
62015026905409/24/15 Multiple core execution trace buffer
72015026909709/24/15 System and elastic despreader memory management
82015026930409/24/15 System and employing signoff-quality timing analysis information concurrently in multiple scenarios to reduce total power within a circuit design
92015026942509/24/15 Dynamic hand gesture recognition with selective enabling based on detected hand velocity
102015026999009/24/15 Memory sense amplifier and column pre-charger
112015026163609/17/15 Data transformations to improve rom yield and programming time
122015026259209/17/15 Systems and methods for distortion characterization
132015026259809/17/15 Systems and methods for head position estimation
142015026266709/17/15 Low power hit bitline driver for content-addressable memory
152015026271009/17/15 Method and system for reducing memory test time utilizing a built-in self-test architecture
162015026294909/17/15 Method for fabricating equal height metal pillars of different diameters
172015026295009/17/15 Method for fabricating equal height metal pillars of different diameters
182015026373209/17/15 Systems and methods for voltage level shifting in a device
192015026384809/17/15 Cdr relock with corrective integral register seeding
202015025510109/10/15 Track misregistration sensitive initialization of joint equalizer
212015025510909/10/15 Non-decision directed magnetoresistive asymetry estimation
222015025511309/10/15 Online iteration resource allocation for large sector format drive
232015025514809/10/15 Bit line write assist for static random access memory architectures
242015025619609/10/15 Soft decoding of polar codes
252015025636309/10/15 Integrated pam4/nrz n-way parallel digital unrolled decision feedback equalizer (dfe)
262015025636409/10/15 Group delay based back channel post cursor adaptation
272015024955509/03/15 Serdes pvt detection and closed loop adaptation
282015024213308/27/15 Storage workload hinting
292015024268108/27/15 System and image processing
302015024331008/27/15 Systems and methods for multi-head separation determination
312015024331108/27/15 Systems and methods for synchronization hand shaking in a storage device
322015024332108/27/15 Reading data from hard disks having reduced preambles
332015024332208/27/15 Systems and methods for multi-head servo data processing
342015024336308/27/15 Adjusting log likelihood ratio values to compensate misplacement of read voltages
352015024353408/27/15 Copper wire bonding apparatus using a purge gas to enhance ball bond reliability
362015024361708/27/15 Method for flip-chip bonding using copper pillars
372015023442308/20/15 Baud rate phase detector with no error latches
382015023570508/20/15 System to control a width of a programming threshold voltage distribution width when writing hot-read data
392015023672608/20/15 Refresh, run, aggregate decoder recovery
402015023687508/20/15 Method and pre-cursor intersymbol interference correction
412015022731408/13/15 Systems and methods for last written page handling in a memory device
422015022740308/13/15 Decoding electronic non-volatile computer storage apparatus
432015022741808/13/15 Hot-read data aggregation and code selection
442015022748608/13/15 Method to facilitate fast context switching for partial and extended path extension to remote expanders
452015022830208/13/15 Zero phase start estimation in readback signals
462015022830308/13/15 Read channel sampling utilizing two quantization modules for increased sample bit width
472015022830408/13/15 Systems and methods for end of fragment marker based data alignment
482015022933108/13/15 Systems and methods for area efficient data encoding
492015022933308/13/15 Systems and methods for rank deficient encoding
502015022933708/13/15 Mitigation of write errors in multi-level cell flash memory through adaptive error correction code decoding
512015022015308/06/15 Gesture recognition system with finite state machine control of cursor detector and dynamic gesture detector
522015022038808/06/15 Systems and methods for hard error reduction in a solid state memory device
532015022045208/06/15 System, method and computer-readable medium for dynamically mapping a non-volatile memory store
542015022074408/06/15 System for execution of security related functions
552015022080408/06/15 Image processor with edge selection functionality
562015022133308/06/15 Reader separation dependent linear and track density push for array reader based magnetic recording
572015021388107/30/15 Integrated read/write tracking in sram
582015020575207/23/15 High density mapping for multiple converter samples in multiple lane interface
592015020631807/23/15 Method and image enhancement and edge verificaton using at least one additional image
602015020657807/23/15 Area-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail sram memories
612015020764807/23/15 Modular low power serializer-deserializer
622015020807607/23/15 Multi-core architecture for low latency video decoder
632015019912907/16/15 System and providing data services in direct attached storage via multiple de-clustered raid pools
642015019914007/16/15 Interleaving codewords over multiple flash planes
652015019914907/16/15 Framework for balancing robustness and latency during collection of statistics from soft reads
662015019922707/16/15 Fault detection and identification in a multi-initiator system
672015019924407/16/15 Intelligent i/o cache rebuild in a storage controller
682015019926907/16/15 Enhanced ssd caching
692015019999107/16/15 Multiple track detection
702015020068107/16/15 Segmented digital-to-analog converter with overlapping segments
712015019356407/09/15 System and using clock chain signals of an on-chip clock controller to control cross-domain paths
722015019421907/09/15 Capacitance coupling parameter estimation in flash memories
732015019510807/09/15 Receiver with pipelined tap coefficients and shift control
742015019535707/09/15 Enhancing active link utilization in serial attached scsi topologies
752015018631707/02/15 Method and detecting the initiator/target orientation of a smart bridge
762015018738407/02/15 Two-dimensional magnetic recording reader offset estimation
772015018738507/02/15 Systems and methods for multi-head balancing in a storage device
782015018855107/02/15 Clock recovery using quantized phase error samples using jitter frequency-dependent quantization thresholds and loop gains
792015018857607/02/15 Systems and methods for efficient targeted symbol flipping
802015017814906/25/15 Method to distribute user data and error correction data over different page types by leveraging error rate variations
812015017815206/25/15 Preventing programming errors from occurring when programming flash memory cells
822015017820106/25/15 System for efficient caching of swap i/o and/or similar i/o pattern(s)
832015017831206/25/15 Attribute-based assistance request system for sequentially contacting nearby contacts without having them divulge their presence or location
842015017921306/25/15 Servo channel with equalizer adaptation
852015018051206/25/15 Systems and methods of converting detector output to multi-level soft information
862015016945806/18/15 System and methods for caching a small size i/o to improve caching device endurance
872015017067606/18/15 Skew-aware disk format for array reader based magnetic recording
882015017070606/18/15 Systems and methods for ati characterization
892015016086906/11/15 Systems and methods for multi-dimensional data processor operational marginalization
902015016088606/11/15 Method and system for programmable sequencer for processing i/o for various pcie disk drives
912015016104506/11/15 Slice formatting and interleaving for interleaved sectors
922015016205706/11/15 Multiple retry reads in a read channel of a memory
932015016278106/11/15 Illumination-based charging system for portable devices
942015016336306/11/15 Low complexity tone/voice discrimination method using a rising edge of a frequency power envelope
952015015411406/04/15 System and method to interleave memory
962015015413806/04/15 Wide port emulation at serial attached scsi expanders
972015015502106/04/15 Area-efficient process-and-temperature-adaptive self-time scheme for performance and power improvement
982015014574005/28/15 Integrated frequency multiplier and slot antenna
992015014692005/28/15 Gesture recognition method and apparatus utilizing asynchronous multithreaded processing
1002015014939505/28/15 Incremental updates for ordered multi-field classification rules when represented by a tree of longest prefix matching tables
1012015014969805/28/15 Eliminating or reducing programming errors when programming flash memory cells
1022015014984005/28/15 Read retry for non-volatile memories
1032015014985505/28/15 Bit-line defect detection using unsatisified parity code checks
1042015014985605/28/15 Decoding with log likelihood ratios stored in a controller
1052015014987105/28/15 Flash channel with selective decoder likelihood dampening
1062015013785505/21/15 Current to voltage converter
1072015013886305/21/15 Interleaved write assist for hierarchical bitline sram architectures
1082015013886405/21/15 Memory architecture with alternating segments and multiple bitlines
1092015013887605/21/15 Global bitline write assist for sram architectures
1102015013948705/21/15 Image processor with static pose recognition module utilizing segmented region of interest
1112015014316405/21/15 I/o request mirroring in a clustered storage system
1122015014319605/21/15 Systems and methods for faid follower decoding
1132015014320205/21/15 Systems and methods for soft decision generation in a solid state memory system
1142015013137305/14/15 Incremental programming pulse optimization to reduce write errors
1152015013461305/14/15 Systems and methods for lost synchronization data set reprocessing
1162015013485505/14/15 Decoupling host and device address maps for a peripheral component interconnect express controller
1172015013500605/14/15 System and write hole protection for a multiple-node storage cluster
1182015013503105/14/15 Dynamic per-decoder control of log likelihood ratio and decoding parameters
1192015013503205/14/15 Detection/erasure of random write errors using converged hard decisions
1202015012787105/07/15 Updated io memory management unit identity settings for dma remapping
1212015012788305/07/15 Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory
1222015012800605/07/15 Device quality metrics using unsatisfied parity checks
1232015011709704/30/15 Systems and methods for sub-zero threshold characterization in a memory cell
1242015011722604/30/15 Method and system for session based data monitoring for wireless edge content caching networks
1252015012098104/30/15 Data interface for point-to-point communications between devices
1262015012098904/30/15 Tracking and utilizing second level map index for recycling of solid state drive blocks
1272015012108804/30/15 Method of managing aligned and unaligned data bands in a self encrypting solid state drive
1282015012117304/30/15 Systems and methods for internal disk drive data compression
1292015010905204/23/15 Closed-loop adaptive voltage scaling for integrated circuits
1302015011016504/23/15 Transmitter training using receiver equalizer coefficients
1312015011320504/23/15 Systems and methods for latency based data recycling in a solid state memory system
1322015011331204/23/15 System and detecting server removal from a cluster to enable fast failover of storage
1332015011331804/23/15 Systems and methods for soft data utilization in a solid state memory system
1342015011333504/23/15 Sending failure information from a solid state drive (ssd) to a host device
1352015011335404/23/15 Generating soft decoding information for flash memory error correction using hard decision patterns
1362015010360404/16/15 Memory array architectures having memory cells with shared write assist circuitry
1372015010396104/16/15 Digital frequency band detector for clock and data recovery
1382015010657704/16/15 De-interleaving on an as-needed basis
1392015010666604/16/15 Speculative bit error rate calculator
1402015010667504/16/15 Systems and methods for multi-algorithm concatenation encoding and decoding
1412015009761104/09/15 Voltage follower having a feed-forward device
1422015010081004/09/15 Adaptive power-down of disk drives based on predicted idle time
1432015009162004/02/15 Reducing current variation when switching clocks
1442015009229004/02/15 Non-binary layered low density parity check decoder
1452015009248904/02/15 Flash memory reference voltage detection with tracking of cross-points of cell voltage distributions using histograms
1462015008539203/26/15 System and monitoring preamble signal quality
1472015008558703/26/15 Ping-pong buffer using single-port memory
1482015008559203/26/15 Bit-line discharge assistance in memory devices
1492015008595703/26/15 Method of calibrating a slicer in a receiver or the like
1502015008910203/26/15 Solid state drives that cache boot data
1512015008913203/26/15 Dynamic storage volume configuration based on input/output requests
1522015008933003/26/15 Systems and methods for enhanced data recovery in a solid state memory system
1532015007718803/19/15 Voltage follower amplifier
1542015007727703/19/15 Reduced polar codes
1552015007810303/19/15 Sensing technique for single-ended bit line memory architectures
1562015008162603/19/15 Systems and methods for recovered data stitching
1572015008164903/19/15 In-line deduplication for a network and/or storage platform
1582015008211503/19/15 Systems and methods for fragmented data recovery
1592015008212103/19/15 Method of erase state handling in flash channel tracking
1602015008212403/19/15 Spatially decoupled redundancy schemes for a solid state drive (ssd)
1612015007079603/12/15 Array-reader based magnetic recording systems with mixed synchronization
1622015007432703/12/15 Active recycling for solid state drive
1632015007432803/12/15 Dynamic map pre-fetching for improved sequential reads of a solid-state media
1642015007435503/12/15 Efficient caching of file system journals
1652015007450103/12/15 Cascaded viterbi bitstream generator
1662015006273003/05/15 Array-reader based magnetic recording systems with quadrature amplitude modulation
1672015006273203/05/15 Systems and methods for two stage tone reduction
1682015006273403/05/15 Systems and methods for multi-level encoding and decoding
1692015006273703/05/15 Adaptive pattern detection for pattern-dependent write current control in a magnetic recording system
1702015006273803/05/15 Systems and methods for variable sector count spreading and de-spreading
1712015006321703/05/15 Mapping between variable width samples and a frame
1722015006725303/05/15 Input/output request shipping in a storage system with multiple storage controllers
1732015006734903/05/15 Virtual bands concentration for self encrypting drives
1742015006768503/05/15 Systems and methods for multiple sensor noise predictive filtering
1752015005524902/26/15 Systems and methods for multi-resolution data sensing
1762015005564402/26/15 Precise timestamping of ethernet packets by compensating for start-of-frame delimiter detection delay and delay variations
1772015005577402/26/15 Echo cancellation with quantization compensation
1782015005853302/26/15 Data storage controller and exposing information stored in a data storage controller to a host system
1792015005855702/26/15 Performance improvements in input / output operations between a host system and an adapter-coupled cache
1802015005869302/26/15 Systems and methods for enhanced data encoding and decoding
1812015004831002/19/15 System and providing an electron blocking layer with doping control
1822015004240302/12/15 High-voltage voltage-switched class-s amplifier
1832015004327002/12/15 Memory cell having built-in write assist
1842015004380702/12/15 Depth image compression and decompression utilizing depth and amplitude data
1852015004675602/12/15 Predictive failure analysis to trigger rebuild of a drive in a raid array
1862015003694202/05/15 Object recognition and tracking using a classifier comprising cascaded stages of multiple decision trees
1872015003978702/05/15 Multi-protocol storage controller
1882015003979602/05/15 Acquiring resources from low priority connection requests in sas
1892015003983202/05/15 System and caching hinted data
1902015003983502/05/15 System and hinted cache data removal
1912015003993202/05/15 Arbitration suspension in a sas domain
1922015003997802/05/15 Systems and methods for hybrid priority based data processing
1932015002960801/29/15 Array-reader based magnetic recording systems with frequency division multiplexing
1942015003002701/29/15 Switch device with device-specified bridge domains
1952015003023201/29/15 Image processor configured for efficient estimation and elimination of background information in images
1962015003296301/29/15 Dynamic selection of cache levels
1972015003306501/29/15 Solid state drive emergency pre-boot application providing expanded data recovery function
1982015003307401/29/15 Deadlock detection and recovery in sas
1992015002216901/22/15 Feedback/feed forward switched capacitor voltage regulation
2002015002270401/22/15 Orientation-based camera operation
2012015002360701/22/15 Gesture recognition method and apparatus based on analysis of multiple candidate boundaries
2022015002640301/22/15 Self-adjusting caching system
2032015002641101/22/15 Cache system for managing various cache line conditions
2042015002648801/22/15 Selectively powering a storage device over a data network
2052015002650301/22/15 Appliances powered over sas
2062015002653601/22/15 Data decoder with trapping set flip bit mapper
2072015001532901/15/15 Radio frequency composite class-s power amplifier having discrete power control
2082015001598401/15/15 Storage media inter-track interference cancellation
2092015001598601/15/15 Methods and improved threshold adaptation for a euclidean detector
2102015001598701/15/15 Prioritized spin-up of drives
2112015001649701/15/15 Clock and data recovery architecture with adaptive digital phase skew
2122015001979501/15/15 Memory system for shadowing volatile data
2132015001981801/15/15 Maintaining cache size proportional to power pack charge
2142015001982201/15/15 System for maintaining dirty cache coherency across reboot of a node
2152015000889401/08/15 Dynamic start-up circuit for hysteretic loop switched-capacitor voltage regulator
2162015001269901/08/15 System and versioning cache for a clustering topology
2172015001270201/08/15 Redundant array of independent disks volume creation
2182015001280001/08/15 Systems and methods for correlation based data alignment
2192015000681501/01/15 Backup of cached dirty data during power outages
2202014037995912/25/14 Map recycling acceleration
2212014038022312/25/14 User interface comprising radial layout soft keypad
2222014036771712/18/14 Semiconductor optical emitting device with metallized sidewalls
2232014036939512/18/14 Error detection based on superheterodyne conversion and direct downconversion
2242014036969612/18/14 Color coding and optical sub-band communication utilizing color coding
2252014037263712/18/14 Pcie tunneling through sas
2262014037267212/18/14 System and providing improved system performance by moving pinned data to open nand flash interface working group modules while the system is in a running state
2272014037278312/18/14 System and providing dynamic charge current based on maximum card power
2282014037282812/18/14 Systems and methods for hybrid layer data decoding
2292014037283612/18/14 Systems and methods for data processing control
2302014036228912/11/14 Method and increasing frame rate of an image stream using at least one higher frame rate image stream
2312014036246312/11/14 Timing error detector with diversity loop detector decision feedback
2322014035921612/04/14 Confirmed divert bitmap to synchronize raid firmware operations with fast-path hardware i/o processing
2332014035926612/04/14 Optimizing boot time of a storage system
2342014035939412/04/14 Apparatus for processing signals carrying modulation-encoded parity bits
2352014034819711/27/14 Semiconductor optical emitting device with lens structure formed in a cavity of a substrate of the device
2362014034947511/27/14 Moisture barrier for a wire bond
2372014035148611/27/14 Variable redundancy in a solid state drive
2382014035167111/27/14 Shift register-based layered low density parity check decoder
2392014034078011/20/14 Method and system for sliding-window based phase, gain, frequency and dc offset estimation for servo channel
2402014034123111/20/14 Lane-based multiplexing for physical links in serial attached small computer system interface architectures
2412014034449211/20/14 Methods and systems for reducing spurious interrupts in a data storage system
2422014034461611/20/14 Techniques for providing data redundancy after reducing memory writes
2432014034496011/20/14 Selective control of on-chip debug circuitry of embedded processors
2442014033427811/13/14 Systems and methods for energy based head contact detection
2452014033428011/13/14 Systems and methods for characterizing head contact
2462014033428111/13/14 Systems and methods for data processor marginalization based upon bit error rate
2472014033449111/13/14 Prediction based methods for fast routing of ip flows using communication/network processors
2482014033754011/13/14 Method and system for i/o flow management for pcie devices
2492014033758311/13/14 Intelligent cache window management for storage systems

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Lsi Corporation in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Lsi Corporation with additional patents listed. Browse our Agent directory for other possible listings. Page by