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Lsi Corporation patents


      
Recent patent applications related to Lsi Corporation. Lsi Corporation is listed as an Agent/Assignee. Note: Lsi Corporation may have other listings under different names/spellings. We're not affiliated with Lsi Corporation, we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "L" | Lsi Corporation-related inventors


High density mapping for multiple converter samples in multiple lane interface

Lsi

High density mapping for multiple converter samples in multiple lane interface

Method and  image enhancement and edge verificaton using at least one additional image

Lsi

Method and image enhancement and edge verificaton using at least one additional image

Area-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail sram memories

Lsi

Area-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail sram memories



Search recent Press Releases: Lsi Corporation-related press releases
Count Application # Date Lsi Corporation patents (updated weekly) - BOOKMARK this page
12015021388107/30/15  new patent  Integrated read/write tracking in sram
22015020575207/23/15 High density mapping for multiple converter samples in multiple lane interface
32015020631807/23/15 Method and image enhancement and edge verificaton using at least one additional image
42015020657807/23/15 Area-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail sram memories
52015020764807/23/15 Modular low power serializer-deserializer
62015020807607/23/15 Multi-core architecture for low latency video decoder
72015019912907/16/15 System and providing data services in direct attached storage via multiple de-clustered raid pools
82015019914007/16/15 Interleaving codewords over multiple flash planes
92015019914907/16/15 Framework for balancing robustness and latency during collection of statistics from soft reads
102015019922707/16/15 Fault detection and identification in a multi-initiator system
112015019924407/16/15 Intelligent i/o cache rebuild in a storage controller
122015019926907/16/15 Enhanced ssd caching
132015019999107/16/15 Multiple track detection
142015020068107/16/15 Segmented digital-to-analog converter with overlapping segments
152015019356407/09/15 System and using clock chain signals of an on-chip clock controller to control cross-domain paths
162015019421907/09/15 Capacitance coupling parameter estimation in flash memories
172015019510807/09/15 Receiver with pipelined tap coefficients and shift control
182015019535707/09/15 Enhancing active link utilization in serial attached scsi topologies
192015018631707/02/15 Method and detecting the initiator/target orientation of a smart bridge
202015018738407/02/15 Two-dimensional magnetic recording reader offset estimation
212015018738507/02/15 Systems and methods for multi-head balancing in a storage device
222015018855107/02/15 Clock recovery using quantized phase error samples using jitter frequency-dependent quantization thresholds and loop gains
232015018857607/02/15 Systems and methods for efficient targeted symbol flipping
242015017814906/25/15 Method to distribute user data and error correction data over different page types by leveraging error rate variations
252015017815206/25/15 Preventing programming errors from occurring when programming flash memory cells
262015017820106/25/15 System for efficient caching of swap i/o and/or similar i/o pattern(s)
272015017831206/25/15 Attribute-based assistance request system for sequentially contacting nearby contacts without having them divulge their presence or location
282015017921306/25/15 Servo channel with equalizer adaptation
292015018051206/25/15 Systems and methods of converting detector output to multi-level soft information
302015016945806/18/15 System and methods for caching a small size i/o to improve caching device endurance
312015017067606/18/15 Skew-aware disk format for array reader based magnetic recording
322015017070606/18/15 Systems and methods for ati characterization
332015016086906/11/15 Systems and methods for multi-dimensional data processor operational marginalization
342015016088606/11/15 Method and system for programmable sequencer for processing i/o for various pcie disk drives
352015016104506/11/15 Slice formatting and interleaving for interleaved sectors
362015016205706/11/15 Multiple retry reads in a read channel of a memory
372015016278106/11/15 Illumination-based charging system for portable devices
382015016336306/11/15 Low complexity tone/voice discrimination method using a rising edge of a frequency power envelope
392015015411406/04/15 System and method to interleave memory
402015015413806/04/15 Wide port emulation at serial attached scsi expanders
412015015502106/04/15 Area-efficient process-and-temperature-adaptive self-time scheme for performance and power improvement
422015014574005/28/15 Integrated frequency multiplier and slot antenna
432015014692005/28/15 Gesture recognition method and apparatus utilizing asynchronous multithreaded processing
442015014939505/28/15 Incremental updates for ordered multi-field classification rules when represented by a tree of longest prefix matching tables
452015014969805/28/15 Eliminating or reducing programming errors when programming flash memory cells
462015014984005/28/15 Read retry for non-volatile memories
472015014985505/28/15 Bit-line defect detection using unsatisified parity code checks
482015014985605/28/15 Decoding with log likelihood ratios stored in a controller
492015014987105/28/15 Flash channel with selective decoder likelihood dampening
502015013785505/21/15 Current to voltage converter
512015013886305/21/15 Interleaved write assist for hierarchical bitline sram architectures
522015013886405/21/15 Memory architecture with alternating segments and multiple bitlines
532015013887605/21/15 Global bitline write assist for sram architectures
542015013948705/21/15 Image processor with static pose recognition module utilizing segmented region of interest
552015014316405/21/15 I/o request mirroring in a clustered storage system
562015014319605/21/15 Systems and methods for faid follower decoding
572015014320205/21/15 Systems and methods for soft decision generation in a solid state memory system
582015013137305/14/15 Incremental programming pulse optimization to reduce write errors
592015013461305/14/15 Systems and methods for lost synchronization data set reprocessing
602015013485505/14/15 Decoupling host and device address maps for a peripheral component interconnect express controller
612015013500605/14/15 System and write hole protection for a multiple-node storage cluster
622015013503105/14/15 Dynamic per-decoder control of log likelihood ratio and decoding parameters
632015013503205/14/15 Detection/erasure of random write errors using converged hard decisions
642015012787105/07/15 Updated io memory management unit identity settings for dma remapping
652015012788305/07/15 Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory
662015012800605/07/15 Device quality metrics using unsatisfied parity checks
672015011709704/30/15 Systems and methods for sub-zero threshold characterization in a memory cell
682015011722604/30/15 Method and system for session based data monitoring for wireless edge content caching networks
692015012098104/30/15 Data interface for point-to-point communications between devices
702015012098904/30/15 Tracking and utilizing second level map index for recycling of solid state drive blocks
712015012108804/30/15 Method of managing aligned and unaligned data bands in a self encrypting solid state drive
722015012117304/30/15 Systems and methods for internal disk drive data compression
732015010905204/23/15 Closed-loop adaptive voltage scaling for integrated circuits
742015011016504/23/15 Transmitter training using receiver equalizer coefficients
752015011320504/23/15 Systems and methods for latency based data recycling in a solid state memory system
762015011331204/23/15 System and detecting server removal from a cluster to enable fast failover of storage
772015011331804/23/15 Systems and methods for soft data utilization in a solid state memory system
782015011333504/23/15 Sending failure information from a solid state drive (ssd) to a host device
792015011335404/23/15 Generating soft decoding information for flash memory error correction using hard decision patterns
802015010360404/16/15 Memory array architectures having memory cells with shared write assist circuitry
812015010396104/16/15 Digital frequency band detector for clock and data recovery
822015010657704/16/15 De-interleaving on an as-needed basis
832015010666604/16/15 Speculative bit error rate calculator
842015010667504/16/15 Systems and methods for multi-algorithm concatenation encoding and decoding
852015009761104/09/15 Voltage follower having a feed-forward device
862015010081004/09/15 Adaptive power-down of disk drives based on predicted idle time
872015009162004/02/15 Reducing current variation when switching clocks
882015009229004/02/15 Non-binary layered low density parity check decoder
892015009248904/02/15 Flash memory reference voltage detection with tracking of cross-points of cell voltage distributions using histograms
902015008539203/26/15 System and monitoring preamble signal quality
912015008558703/26/15 Ping-pong buffer using single-port memory
922015008559203/26/15 Bit-line discharge assistance in memory devices
932015008595703/26/15 Method of calibrating a slicer in a receiver or the like
942015008910203/26/15 Solid state drives that cache boot data
952015008913203/26/15 Dynamic storage volume configuration based on input/output requests
962015008933003/26/15 Systems and methods for enhanced data recovery in a solid state memory system
972015007718803/19/15 Voltage follower amplifier
982015007727703/19/15 Reduced polar codes
992015007810303/19/15 Sensing technique for single-ended bit line memory architectures
1002015008162603/19/15 Systems and methods for recovered data stitching
1012015008164903/19/15 In-line deduplication for a network and/or storage platform
1022015008211503/19/15 Systems and methods for fragmented data recovery
1032015008212103/19/15 Method of erase state handling in flash channel tracking
1042015008212403/19/15 Spatially decoupled redundancy schemes for a solid state drive (ssd)
1052015007079603/12/15 Array-reader based magnetic recording systems with mixed synchronization
1062015007432703/12/15 Active recycling for solid state drive
1072015007432803/12/15 Dynamic map pre-fetching for improved sequential reads of a solid-state media
1082015007435503/12/15 Efficient caching of file system journals
1092015007450103/12/15 Cascaded viterbi bitstream generator
1102015006273003/05/15 Array-reader based magnetic recording systems with quadrature amplitude modulation
1112015006273203/05/15 Systems and methods for two stage tone reduction
1122015006273403/05/15 Systems and methods for multi-level encoding and decoding
1132015006273703/05/15 Adaptive pattern detection for pattern-dependent write current control in a magnetic recording system
1142015006273803/05/15 Systems and methods for variable sector count spreading and de-spreading
1152015006321703/05/15 Mapping between variable width samples and a frame
1162015006725303/05/15 Input/output request shipping in a storage system with multiple storage controllers
1172015006734903/05/15 Virtual bands concentration for self encrypting drives
1182015006768503/05/15 Systems and methods for multiple sensor noise predictive filtering
1192015005524902/26/15 Systems and methods for multi-resolution data sensing
1202015005564402/26/15 Precise timestamping of ethernet packets by compensating for start-of-frame delimiter detection delay and delay variations
1212015005577402/26/15 Echo cancellation with quantization compensation
1222015005853302/26/15 Data storage controller and exposing information stored in a data storage controller to a host system
1232015005855702/26/15 Performance improvements in input / output operations between a host system and an adapter-coupled cache
1242015005869302/26/15 Systems and methods for enhanced data encoding and decoding
1252015004831002/19/15 System and providing an electron blocking layer with doping control
1262015004240302/12/15 High-voltage voltage-switched class-s amplifier
1272015004327002/12/15 Memory cell having built-in write assist
1282015004380702/12/15 Depth image compression and decompression utilizing depth and amplitude data
1292015004675602/12/15 Predictive failure analysis to trigger rebuild of a drive in a raid array
1302015003694202/05/15 Object recognition and tracking using a classifier comprising cascaded stages of multiple decision trees
1312015003978702/05/15 Multi-protocol storage controller
1322015003979602/05/15 Acquiring resources from low priority connection requests in sas
1332015003983202/05/15 System and caching hinted data
1342015003983502/05/15 System and hinted cache data removal
1352015003993202/05/15 Arbitration suspension in a sas domain
1362015003997802/05/15 Systems and methods for hybrid priority based data processing
1372015002960801/29/15 Array-reader based magnetic recording systems with frequency division multiplexing
1382015003002701/29/15 Switch device with device-specified bridge domains
1392015003023201/29/15 Image processor configured for efficient estimation and elimination of background information in images
1402015003296301/29/15 Dynamic selection of cache levels
1412015003306501/29/15 Solid state drive emergency pre-boot application providing expanded data recovery function
1422015003307401/29/15 Deadlock detection and recovery in sas
1432015002216901/22/15 Feedback/feed forward switched capacitor voltage regulation
1442015002270401/22/15 Orientation-based camera operation
1452015002360701/22/15 Gesture recognition method and apparatus based on analysis of multiple candidate boundaries
1462015002640301/22/15 Self-adjusting caching system
1472015002641101/22/15 Cache system for managing various cache line conditions
1482015002648801/22/15 Selectively powering a storage device over a data network
1492015002650301/22/15 Appliances powered over sas
1502015002653601/22/15 Data decoder with trapping set flip bit mapper
1512015001532901/15/15 Radio frequency composite class-s power amplifier having discrete power control
1522015001598401/15/15 Storage media inter-track interference cancellation
1532015001598601/15/15 Methods and improved threshold adaptation for a euclidean detector
1542015001598701/15/15 Prioritized spin-up of drives
1552015001649701/15/15 Clock and data recovery architecture with adaptive digital phase skew
1562015001979501/15/15 Memory system for shadowing volatile data
1572015001981801/15/15 Maintaining cache size proportional to power pack charge
1582015001982201/15/15 System for maintaining dirty cache coherency across reboot of a node
1592015000889401/08/15 Dynamic start-up circuit for hysteretic loop switched-capacitor voltage regulator
1602015001269901/08/15 System and versioning cache for a clustering topology
1612015001270201/08/15 Redundant array of independent disks volume creation
1622015001280001/08/15 Systems and methods for correlation based data alignment
1632015000681501/01/15 Backup of cached dirty data during power outages
1642014037995912/25/14 Map recycling acceleration
1652014038022312/25/14 User interface comprising radial layout soft keypad
1662014036771712/18/14 Semiconductor optical emitting device with metallized sidewalls
1672014036939512/18/14 Error detection based on superheterodyne conversion and direct downconversion
1682014036969612/18/14 Color coding and optical sub-band communication utilizing color coding
1692014037263712/18/14 Pcie tunneling through sas
1702014037267212/18/14 System and providing improved system performance by moving pinned data to open nand flash interface working group modules while the system is in a running state
1712014037278312/18/14 System and providing dynamic charge current based on maximum card power
1722014037282812/18/14 Systems and methods for hybrid layer data decoding
1732014037283612/18/14 Systems and methods for data processing control
1742014036228912/11/14 Method and increasing frame rate of an image stream using at least one higher frame rate image stream
1752014036246312/11/14 Timing error detector with diversity loop detector decision feedback
1762014035921612/04/14 Confirmed divert bitmap to synchronize raid firmware operations with fast-path hardware i/o processing
1772014035926612/04/14 Optimizing boot time of a storage system
1782014035939412/04/14 Apparatus for processing signals carrying modulation-encoded parity bits
1792014034819711/27/14 Semiconductor optical emitting device with lens structure formed in a cavity of a substrate of the device
1802014034947511/27/14 Moisture barrier for a wire bond
1812014035148611/27/14 Variable redundancy in a solid state drive
1822014035167111/27/14 Shift register-based layered low density parity check decoder
1832014034078011/20/14 Method and system for sliding-window based phase, gain, frequency and dc offset estimation for servo channel
1842014034123111/20/14 Lane-based multiplexing for physical links in serial attached small computer system interface architectures
1852014034449211/20/14 Methods and systems for reducing spurious interrupts in a data storage system
1862014034461611/20/14 Techniques for providing data redundancy after reducing memory writes
1872014034496011/20/14 Selective control of on-chip debug circuitry of embedded processors
1882014033427811/13/14 Systems and methods for energy based head contact detection
1892014033428011/13/14 Systems and methods for characterizing head contact
1902014033428111/13/14 Systems and methods for data processor marginalization based upon bit error rate
1912014033449111/13/14 Prediction based methods for fast routing of ip flows using communication/network processors
1922014033754011/13/14 Method and system for i/o flow management for pcie devices
1932014033758311/13/14 Intelligent cache window management for storage systems
1942014033767611/13/14 Systems and methods for processing data with microcontroller based retry features
1952014033100111/06/14 Command barrier for a solid state drive controller
1962014033109611/06/14 Cross-decoding for non-volatile storage
1972014033110811/06/14 Systems and methods for detecting media flaws
1982014032511710/30/14 Flash translation layer with lower write amplification
1992014032514410/30/14 Protection information initialization
2002014032514510/30/14 Cache rebuilds based on tracking data for cache entries
2012014032514610/30/14 Creating and managing logical volumes from unused space in raid disk groups
2022014032530310/30/14 Systems and methods for protected data encoding
2032014031237210/23/14 Semiconductor optical emitting device with grooved substrate providing multiple angled light emission paths
2042014031247510/23/14 Die reuse in electrical circuits
2052014031361010/23/14 Systems and methods selective complexity data decoding
2062014031394610/23/14 Non-linear interference cancellation for wireless transceivers
2072014031417610/23/14 Non-linear modeling of a physical system using two-dimensional look-up table with bilinear interpolation
2082014031418110/23/14 Non-linear modeling of a physical system using look-up table with polynomial interpolation
2092014031426510/23/14 Headphones with rotatable speaker arranged within housing of earpiece assembly
2102014031675210/23/14 Non-linear modeling of a physical system using direct optimization of look-up table values
2112014031716310/23/14 Vector processor having instruction set with sliding window non-linear convolutional function
2122014031733410/23/14 Storage of gate training parameters for devices utilizing random access memory
2132014031734610/23/14 Redundant array of independent disks systems that utilize spans with different storage device counts for a logical volume
2142014031737610/23/14 Digital processor having instruction set with complex angle function
2152014030734510/16/14 Systems and methods for preventing adjacent track erasure
2162014030114310/09/14 Techniques for controlling recycling of blocks of memory
2172014030446410/09/14 Methods and systems for performing deduplication in a data storage system
2182014030456210/09/14 Method for testing paths to pull-up and pull-down of input/output pads
2192014029229810/02/14 Operational amplifier-based current-sensing circuit for dc-dc voltage converters and the like
2202014029812310/02/14 Scan chain reconfiguration and repair
2212014029812910/02/14 Generating partially sparse generator matrix for a quasi-cyclic low-density parity-check encoder
2222014029813110/02/14 Priori information based post-processing in low-density parity-check code decoders
2232014029814810/02/14 Trend-analysis scheme for reliably reading data values from memory
2242014028591809/25/14 Systems and methods for quality based bit error rate prediction
2252014028610209/25/14 Method of optimizing solid state drive soft retry voltages
2262014028614909/25/14 Automatic on-drive sync-mark search and threshold adjustment
2272014028638509/25/14 Systems and methods for multi-dimensional signal equalization
2282014028945009/25/14 Dynamic log likelihood ratio quantization for solid state drive controllers
2292014028955009/25/14 Integrated clock architecture for improved testing
2302014028958209/25/14 Systems and methods for reduced constraint code data processing
2312014026633809/18/14 Biased bang-bang phase detector for clock and data recovery
2322014026639509/18/14 Ac coupling circuit with hybrid switches
2332014026649709/18/14 Ac coupling circuit with hybrid switches and constant load
2342014026681509/18/14 Lempel-ziv data compression with shortened hash chains based on repetitive patterns
2352014026682009/18/14 Interleaved multipath digital power amplification
2362014026700409/18/14 User adjustable gesture space
2372014026838909/18/14 Systems and methods for enhanced sync mark mis-detection protection
2382014026839009/18/14 Systems and methods for transition based equalization
2392014026839109/18/14 Data sequence detection in band-limited channels using cooperative sequence equalization
2402014026839709/18/14 Hardware support of servo format with two preamble fields
2412014026840009/18/14 Systems and methods for loop feedback
2422014026840109/18/14 Systems and methods for p-distance based priority data processing
2432014026904809/18/14 Retention detection and/or channel tracking policy in a flash memory based storage system
2442014026905309/18/14 Nonvolatile memory data recovery after power failure
2452014026988809/18/14 Adaptive continuous time linear equalizer
2462014026997809/18/14 Interleaved multipath digital power amplification
2472014028041709/18/14 Linear phase fir biorthogonal wavelet filters with complementarity for image noise reduction
2482014028041809/18/14 Numerical method: making the infinite, finite. a universal transform and system of force vector
2492014028042909/18/14 Efficient hardware structure for sorting/adding multiple inputs assigned to different bins



ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009



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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Lsi Corporation in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Lsi Corporation with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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