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Lsi Corporation patents


      
Recent patent applications related to Lsi Corporation. Lsi Corporation is listed as an Agent/Assignee. Note: Lsi Corporation may have other listings under different names/spellings. We're not affiliated with Lsi Corporation, we're just tracking patents.

ARCHIVE: New 2014 2013 2012 2011 2010 2009 | Company Directory "L" | Lsi Corporation-related inventors



Lsi

Numerical method: making the infinite, finite. a universal transform and system of force vector

Lsi

Direct routing between address spaces through a nontransparent peripheral component interconnect express bridge

Search recent Press Releases: Lsi Corporation-related press releases
Count Application # Date Lsi Corporation patents (updated weekly) - BOOKMARK this page
12014026633809/18/14 new patent  Biased bang-bang phase detector for clock and data recovery
22014026639509/18/14 new patent  Ac coupling circuit with hybrid switches
32014026649709/18/14 new patent  Ac coupling circuit with hybrid switches and constant load
42014026681509/18/14 new patent  Lempel-ziv data compression with shortened hash chains based on repetitive patterns
52014026682009/18/14 new patent  Interleaved multipath digital power amplification
62014026700409/18/14 new patent  User adjustable gesture space
72014026838909/18/14 new patent  Systems and methods for enhanced sync mark mis-detection protection
82014026839009/18/14 new patent  Systems and methods for transition based equalization
92014026839109/18/14 new patent  Data sequence detection in band-limited channels using cooperative sequence equalization
102014026839709/18/14 new patent  Hardware support of servo format with two preamble fields
112014026840009/18/14 new patent  Systems and methods for loop feedback
122014026840109/18/14 new patent  Systems and methods for p-distance based priority data processing
132014026904809/18/14 new patent  Retention detection and/or channel tracking policy in a flash memory based storage system
142014026905309/18/14 new patent  Nonvolatile memory data recovery after power failure
152014026988809/18/14 new patent  Adaptive continuous time linear equalizer
162014026997809/18/14 new patent  Interleaved multipath digital power amplification
172014028041709/18/14 new patent  Linear phase fir biorthogonal wavelet filters with complementarity for image noise reduction
182014028041809/18/14 new patent  Numerical method: making the infinite, finite. a universal transform and system of force vector
192014028042909/18/14 new patent  Efficient hardware structure for sorting/adding multiple inputs assigned to different bins
202014028105709/18/14 new patent  Unified message-based communications
212014028108309/18/14 new patent  Enhanced queue management
222014028110609/18/14 new patent  Direct routing between address spaces through a nontransparent peripheral component interconnect express bridge
232014028114309/18/14 new patent  Reducing flash memory write amplification and latency
242014028117109/18/14 new patent  Lock-free communication storage request reordering
252014028128109/18/14 new patent  Host command based read disturb methodology
262014028162709/18/14 new patent  Device sleep partitioning and keys
272014028168809/18/14 new patent  Method and system of data recovery in a raid controller
282014028170309/18/14 new patent  Local repair signature handling for repairable memories
292014028176709/18/14 new patent  Recovery strategy that reduces errors misidentified as reliable
302014028178709/18/14 new patent  Min-sum based hybrid non-binary low density parity check decoder
312014028181809/18/14 new patent  Method for format savings in coherently written fragmented sectors
322014028182209/18/14 new patent  Method and apparatus for generation of soft decision error correction code information
332014028184109/18/14 new patent  Systems and methods for sync mark mis-detection protection
342014028314609/18/14 new patent  Tamper sensor
352014025320309/11/14Programmable clock spreading
362014025322209/11/14Preventing electronic device counterfeits
372014025322609/11/14Power integrity control through active current profile management
382014025404109/11/14Servo marginalization
392014025404309/11/14Sampling-phase acquisition based on channel-impulse-response estimation
402014025459309/11/14Network processor having multicasting protocol
412014025465509/11/14Adaptation of equalizer settings using error signals sampled at several different phases
422014025473509/11/14Transmit reference signal cleanup within a synchronous network application
432014025837509/11/14System and method for large object cache management in a network
442014025856509/11/14Smart discovery model in a serial attached small computer system topology
452014025857209/11/14Preemptive connection switching for serial attached small computer system interface systems
462014025858709/11/14Self recovery in a solid state drive
472014025859509/11/14System, method and computer-readable medium for dynamic cache sharing in a flash-based caching solution supporting virtual machines
482014025859809/11/14Scalable storage devices
492014025861009/11/14Raid cache memory system with volume windows
502014025861309/11/14Volume change flags for incremental snapshots of stored data
512014025862809/11/14System, method and computer-readable medium for managing a cache store to achieve improved cache ramp-up across system reboots
522014025875509/11/14Storage device power failure infrastructure
532014025875909/11/14System and method for de-queuing an active queue
542014025876909/11/14Partial r-block recycling
552014024751409/04/14Systems and methods for adc sample based inter-track interference compensation
562014025024609/04/14Intelligent data buffering between interfaces
572014025026309/04/14Techniques for reducing memory write operations using coalescing memory buffers and difference information
582014025026909/04/14Declustered raid pool as backup for raid volumes
592014025031509/04/14Storage system data hardening
602014025033809/04/14Virtual function timeout for single root input/output virtualization controllers
612014025035209/04/14Systems and methods for signal reduction based data processor marginalization
622014024003308/28/14On-die programming of integrated circuit bond pads
632014024046708/28/14Image processing method and apparatus for elimination of depth artifacts
642014024086408/28/14Storage device having degauss circuitry configured for generating degauss signal with asymmetric decay envelopes
652014024087008/28/14Analog tunneling current sensors for use with disk drive storage devices
662014024102808/28/14Two-bit read-only memory cell
672014024105608/28/14Reduced complexity reliability computations for flash memories
682014024106108/28/14Fast access with low leakage and low power technique for read only memory devices
692014024106208/28/14Modular, scalable rigid flex memory module
702014024147808/28/14Timing phase estimation for clock and data recovery
712014024487508/28/14Priority based connection arbitration in a sas topology to facilitate quality of service (qos) in sas transport
722014024490108/28/14Metadata management for a flash drive
732014024490208/28/14Fast read in write-back cached memory
742014024492608/28/14Dedicated memory structure for sector spreading interleaving
752014024492808/28/14Method and system to provide data protection to raid 0/ or degraded redundant virtual disk
762014024493608/28/14Maintaining cache coherency between storage controllers
772014024508608/28/14Test signal generator for low-density parity-check decoder
782014024509308/28/14Master boot record protection in a solid state drive
792014024530008/28/14Dynamically balanced credit for virtual functions in single root input/output virtualization
802014024540808/28/14Biometric approach to track credentials of anonymous user of a mobile device
812014023312808/21/14Systems and methods for burst demodulation
822014023312908/21/14Noise predictive filter adaptation for inter-track interference cancellation
832014023313008/21/14Systems and methods for determining noise components in a signal set
842014023330208/21/14Write-tracking circuitry for memory devices
852014023332208/21/14Adaptive architecture in a channel detector for nand flash channels
862014023356708/21/14High speed network bridging
872014023361908/21/14Pattern-based loss of signal detector
882014023366808/21/14Code forwarding and clock generation for transmitter repeaters
892014023716208/21/14Non-volatile memory channel control using a general purpose programmable processor in combination with a low level programmable sequencer
902014023716308/21/14Reducing writes to solid state drive cache memories of storage controllers
912014023716608/21/14Higher-level redundancy information computation
922014023719308/21/14Cache window management
932014023731308/21/14Systems and methods for trapping set disruption
942014023731408/21/14Systems and methods for skip layer data decoding
952014023732908/21/14Ratio-adjustable sync mark detection system
962014022566908/14/14Extended variable gain amplification bandwidth with high-frequency boost
972014022622908/14/14Systems and methods for shared layer data decoding
982014022623308/14/14Storage device with reflection compensation circuitry
992014022623408/14/14System and method for providing controllable steady state current waveshaping in a hard disk drive (hdd) preamplifier
1002014022685408/14/14Three-dimensional region of interest tracking based on key frame matching
1012014022689508/14/14Feature point based robust three-dimensional rigid body registration
1022014022796908/14/14Indium tin oxide loop antenna for near field communication
1032014022807308/14/14Automatic presentation of an image from a camera responsive to detection of a particular type of movement of a user device
1042014022965108/14/14Managing arbitration in mixed link rate wide ports
1052014022965208/14/14Methods and structure for fast context switching among a plurality of expanders in a serial attached scsi domain
1062014022965808/14/14Cache load balancing in storage controllers
1072014022967008/14/14Cache coherency and synchronization support in expanders in a raid topology with multiple initiators
1082014022967608/14/14Rebuild of redundant secondary storage cache
1092014022970008/14/14Systems and methods for accommodating end of transfer request in a data storage device
1102014022973308/14/14System and method for key wrapping to allow secure access to media by multiple authorities with modifiable permissions
1112014022975708/14/14Restoring expander operations in a data storage switch
1122014022976908/14/14Methods and structure for single root input/output virtualization enhancement in peripheral component interconnect express systems
1132014022977808/14/14At-speed scan testing of interface functional logic of an embedded memory or other circuit core
1142014022979908/14/14Statistical adaptive error correction for a flash memory
1152014022980608/14/14Systems and methods for distributed low density parity check decoding
1162014022994108/14/14Method and controller device for quality of service (qos) caching in a virtualized environment
1172014022995408/14/14Systems and methods for data quality based variable data process scheduling
1182014021902808/07/14Compensation loop for read voltage adaptation
1192014022076008/07/14Integration of shallow trench isolation and through-substrate vias into integrated circuit designs
1202014022307108/07/14Method and system for reducing write latency in a data storage system by using a command-push model
1212014022307208/07/14Tiered caching using single level cell and multi-level cell flash technology
1222014022307508/07/14Physical-to-logical address map to speed up a recycle operation in a solid state drive
1232014022309408/07/14Selective raid protection for cache memory
1242014022310608/07/14Method to throttle rate of data caching for improved i/o performance
1252014022311408/07/14Buffer for managing data samples in a read channel
1262014022313608/07/14Lookup tables utilizing read only memory and combinational logic
1272014022325908/07/14Memory architecture for layered low-density parity-check decoder
1282014022326708/07/14Radix-4 viterbi forward error correction decoding
1292014022327008/07/14Classifying bit errors in transmitted run length limited data
1302014022329508/07/14Geographic based spell check
1312014021133607/31/14Automatic gain control loop adaptation for enhanced nyquist data pattern detection
1322014021133707/31/14Systems and methods for improved short media defect detection
1332014021183907/31/14Receiver having limiter-enhanced data eye openings
1342014021474807/31/14Incremental dfa compilation with single rule granularity
1352014021474907/31/14System and method for dfa-nfa splitting
1362014021509007/31/14Dfa sub-scans
1372014021512307/31/14Controller-opaque communication with non-volatile memory devices
1382014021514907/31/14File-system aware snapshots of stored data
1392014021519907/31/14Fast-boot list to speed booting an operating system
1402014021528507/31/14Integrated-interleaved low density parity check (ldpc) codes
1412014021534107/31/14Transitioning between pages of content on a display of a user device
1422014020465907/24/14Capacitive coupled sense amplifier biased at maximum gain point
1432014020466007/24/14Memory having sense amplifier for output tracking by controlled feedback latch
1442014020468307/24/14Margin free pvt tolerant fast self-timed sense amplifier reset circuit
1452014020498707/24/14System and method for determining channel loss in a dispersive communication channel at the nyquist frequency
1462014020499507/24/14Efficient region of interest detection
1472014020500507/24/14Method and apparatus for mpeg-2 to h.264 video transcoding
1482014020774307/24/14Method for storage driven de-duplication of server memory
1492014020799607/24/14Hybrid hard disk drive having a flash storage processor
1502014020800307/24/14Variable-size flash translation layer
1512014020800407/24/14Translation layer partitioned between host and controller
1522014020800507/24/14System, method and computer-readable medium for providing selective protection and endurance improvements in flash-based cache
1532014020800707/24/14Management of and region selection for writes to non-volatile memory
1542014020802407/24/14System and methods for performing embedded full-stripe write operations to a data volume with data elements distributed across multiple modules
1552014020804607/24/14Storage device out-of-space handling
1562014020804807/24/14Method and apparatus for efficient remote copy
1572014020806107/24/14Locating data in non-volatile memory
1582014020806207/24/14Storage address space to nvm address, span, and length mapping/converting
1592014020807607/24/14Dfa compression and execution
1602014020817507/24/14At-speed scan testing of clock divider logic in a clock module of an integrated circuit
1612014020818007/24/14Systems and methods for reusing a layered decoder to yield a non-layered result
1622014019840407/17/14Systems and methods for x-sample based noise cancellation
1632014019840507/17/14Systems and methods for loop processing with variance adaptation
1642014019878907/17/14Low latency in-line data compression for packet transmission systems
1652014020084907/17/14Diversity loop detector with component detector switching
1662014020144207/17/14Cache based storage controller
1672014020146207/17/14Subtractive validation of cache lines for virtual machines
1682014020158407/17/14Scan test circuitry comprising at least one scan chain and associated reset multiplexing circuitry
1692014020158507/17/14State-split based endec
1702014019140307/10/14Multi-die semiconductor package and method of manufacturing thereof
1712014019180107/10/14Bicmos gate driver for class-s radio frequency power amplifier
1722014019260307/10/14Differential sense amplifier for solid-state memories
1732014019263307/10/14System and method for providing fast and efficient flushing of a forwarding database in a network processor
1742014019284107/10/14Ultra-wideband loss of signal detector at a receiver in a high speed serializer/deserializer (serdes) application
1752014019293507/10/14Receiver with dual clock recovery circuits
1762014019309207/10/14Superresolution image processing using an invertible sparse matrix
1772014019571407/10/14Methods and structure for buffering host requests in serial attached scsi expanders
1782014019571807/10/14Control logic design to support usb cache offload
1792014019573107/10/14Physical link management
1802014019573207/10/14Method and system to maintain maximum performance levels in all disk groups by using controller vds for background tasks
1812014018432307/03/14Hybrid digital/analog power amplifier
1822014018515807/03/14Fly height control for hard disk drives
1832014018515907/03/14Sync mark detection using branch metrics from data detector
1842014018536607/03/14Pre-charge tracking of global read lines in high speed sram
1852014018565807/03/14Serdes data sampling gear shifter
1862014018896907/03/14Efficient algorithm to bit matrix symmetry
1872014018942107/03/14Non-volatile memory program failure recovery via redundant arrays
1882014018967307/03/14Management of device firmware update effects as seen by a host
1892014017623006/26/14High-voltage tolerant biasing arrangement using low-voltage devices
1902014017623906/26/14Adaptive control mechanisms to control input and output common-mode voltages of differential amplifier circuits
1912014017708206/26/14Over-sampled signal equalizer
1922014017708406/26/14Systems and methods for managed operational marginalization
1932014017708706/26/14Equalization combining outputs of multiple component filters
1942014017732406/26/14Single-port read multiple-port write storage device using single-port memory cells
1952014017737106/26/14Suspend sdram refresh cycles during normal ddr operation
1962014018132706/26/14I/o device and computing host interoperation
1972014018137006/26/14Method to apply fine grain wear leveling and garbage collection
1982014018157006/26/14Signal processing circuitry with frontend and backend circuitry controlled by separate clocks
1992014018161706/26/14Management of non-valid decision patterns of a soft read retry operation
2002014018162406/26/14Majority-tabular post processing of quasi-cyclic low-density parity-check codes
2012014018162506/26/14Read channel data signal detection with reduced-state trellis
2022014018184506/26/14Single serdes transmitter driver design for both ethernet and peripheral component interconnect express applications
2032014016880906/19/14Tag multiplication via a preamplifier interface
2042014016881006/19/14Systems and methods for adaptive threshold pattern detection
2052014016881106/19/14Irregular low density parity check decoder with low syndrome error handling
2062014016921006/19/14Link rate availability based arbitration
2072014016942606/19/14Receiver with distortion compensation circuit
2082014016944006/19/14Adaptive cancellation of voltage offset in a communication system
2092014016945706/19/14Performance control in video encoding
2102014016946806/19/14Picture refresh with constant-bit budget
2112014017279706/19/14Method and apparatus to share a single storage drive across a large number of unique systems when data is highly redundant
2122014017293406/19/14Systems and methods for data retry using averaging process
2132014017313906/19/14System, method, and computer program product for inserting a gap in information sent from a drive to a host device
2142014017315306/19/14Method and system for detecting multiple expanders in an sas topology having the same address
2152014017316506/19/14Expander for loop architectures
2162014017325406/19/14Cache prefetch for deterministic finite automaton instructions
2172014017325606/19/14Processor configured for operation with multiple operation codes per instruction
2182014017333006/19/14Split brain detection and recovery system
2192014017334606/19/14Validating operation of system-on-chip controller for storage device using programmable state machine
2202014017338506/19/14Low density parity check decoder with dynamic scaling
2212014017360306/19/14Multiple step non-deterministic finite automaton matching
2222014015980706/12/14Multiple-clock, noise-immune slicer with offset cancellation and equalization inputs
2232014015999106/12/14Switching power amplifier system for multi-path signal interleaving
2242014016059206/12/14Systems and methods for x-sample based data processor marginalization
2252014016119806/12/14Multi-layer approach for frame-missing concealment in a video decoder
2262014016430906/12/14Non-deterministic finite automaton overflow recovery
2272014016465306/12/14Load balancing with scsi i/o referrals
2282014016467006/12/14Structure for non-blocking serial attached scsi infrastructure utilizing virtual pathways
2292014016471506/12/14Methods and structure for using region locks to divert i/o requests in a storage controller having multiple processing stacks
2302014016484606/12/14Master-slave expander logging
2312014016486606/12/14Low density parity check decoder with miscorrection handling
2322014016486806/12/14Flash memory read error recovery with soft-decision decode
2332014016488006/12/14Error correction code rate management for nonvolatile memory
2342014016488106/12/14Policy for read operations addressing on-the-fly decoding failure in non-volatile memory
2352014015234106/05/14External component-less pvt compensation scheme for io buffers
2362014015234506/05/14Sense-amplifier latch having single data input
2372014015236606/05/14Concurrent true and complement signal generation
2382014015312606/05/14Systems and methods for old data inter-track interference compensation
2392014015334606/05/14Read assist scheme for reducing read access time in a memory
2402014015357506/05/14Packet data processor in a communications processor architecture
2412014015364406/05/14Dynamic slice resizing while encoding video
2422014015707406/05/14Systems and methods for selective retry data retention processing
2432014014577505/29/14Overshoot suppression for input/output buffers
2442014014641305/29/14Systems and methods for enhanced servo data processing
2452014014686005/29/14Transceiver with short-circuit detection and protection
2462014014686705/29/14Receiver with parallel decision feedback equalizers
2472014014943905/29/14Dfa-nfa hybrid
2482014014961405/29/14Sata data appliance for providing sata hosts with access to a configurable number of sata drives residing in a sas topology
2492014014962405/29/14Method for determining a serial attached small computer system interface topology


ARCHIVE: New 2014 2013 2012 2011 2010 2009



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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Lsi Corporation in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Lsi Corporation with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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