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Lsi Corporation patents


      
Recent patent applications related to Lsi Corporation. Lsi Corporation is listed as an Agent/Assignee. Note: Lsi Corporation may have other listings under different names/spellings. We're not affiliated with Lsi Corporation, we're just tracking patents.

ARCHIVE: New 2014 2013 2012 2011 2010 2009 | Company Directory "L" | Lsi Corporation-related inventors



Providing dynamic charge current based on maximum card power

Lsi

Providing dynamic charge current based on maximum card power

Data processing control

Lsi

Data processing control

Data processing control

Lsi

Error detection based on superheterodyne conversion and direct downconversion

Search recent Press Releases: Lsi Corporation-related press releases
Count Application # Date Lsi Corporation patents (updated weekly) - BOOKMARK this page
12014036771712/18/14 new patent  Semiconductor optical emitting device with metallized sidewalls
22014036939512/18/14 new patent  Error detection based on superheterodyne conversion and direct downconversion
32014036969612/18/14 new patent  Color coding and optical sub-band communication utilizing color coding
42014037263712/18/14 new patent  Pcie tunneling through sas
52014037267212/18/14 new patent  Providing improved system performance by moving pinned data to open nand flash interface working group modules while the system is in a running state
62014037278312/18/14 new patent  Providing dynamic charge current based on maximum card power
72014037282812/18/14 new patent  Hybrid layer data decoding
82014037283612/18/14 new patent  Data processing control
92014036228912/11/14Increasing frame rate of an image stream using at least one higher frame rate image stream
102014036246312/11/14Timing error detector with diversity loop detector decision feedback
112014035921612/04/14Confirmed divert bitmap to synchronize raid firmware operations with fast-path hardware i/o processing
122014035926612/04/14Optimizing boot time of a storage system
132014035939412/04/14Apparatus for processing signals carrying modulation-encoded parity bits
142014034819711/27/14Semiconductor optical emitting device with lens structure formed in a cavity of a substrate of the device
152014034947511/27/14Moisture barrier for a wire bond
162014035148611/27/14Variable redundancy in a solid state drive
172014035167111/27/14Shift register-based layered low density parity check decoder
182014034078011/20/14Sliding-window based phase, gain, frequency and dc offset estimation for servo channel
192014034123111/20/14Lane-based multiplexing for physical links in serial attached small computer system interface architectures
202014034449211/20/14Reducing spurious interrupts in a data storage system
212014034461611/20/14Techniques for providing data redundancy after reducing memory writes
222014034496011/20/14Selective control of on-chip debug circuitry of embedded processors
232014033427811/13/14Energy based head contact detection
242014033428011/13/14Characterizing head contact
252014033428111/13/14Data processor marginalization based upon bit error rate
262014033449111/13/14Prediction based methods for fast routing of ip flows using communication/network processors
272014033754011/13/14I/o flow management for pcie devices
282014033758311/13/14Intelligent cache window management for storage systems
292014033767611/13/14Processing data with microcontroller based retry features
302014033100111/06/14Command barrier for a solid state drive controller
312014033109611/06/14Cross-decoding for non-volatile storage
322014033110811/06/14Detecting media flaws
332014032511710/30/14Flash translation layer with lower write amplification
342014032514410/30/14Protection information initialization
352014032514510/30/14Cache rebuilds based on tracking data for cache entries
362014032514610/30/14Creating and managing logical volumes from unused space in raid disk groups
372014032530310/30/14Protected data encoding
382014031237210/23/14Semiconductor optical emitting device with grooved substrate providing multiple angled light emission paths
392014031247510/23/14Die reuse in electrical circuits
402014031361010/23/14Systems and methods selective complexity data decoding
412014031394610/23/14Non-linear interference cancellation for wireless transceivers
422014031417610/23/14Non-linear modeling of a physical system using two-dimensional look-up table with bilinear interpolation
432014031418110/23/14Non-linear modeling of a physical system using look-up table with polynomial interpolation
442014031426510/23/14Headphones with rotatable speaker arranged within housing of earpiece assembly
452014031675210/23/14Non-linear modeling of a physical system using direct optimization of look-up table values
462014031716310/23/14Vector processor having instruction set with sliding window non-linear convolutional function
472014031733410/23/14Storage of gate training parameters for devices utilizing random access memory
482014031734610/23/14Redundant array of independent disks systems that utilize spans with different storage device counts for a logical volume
492014031737610/23/14Digital processor having instruction set with complex angle function
502014030734510/16/14Preventing adjacent track erasure
512014030114310/09/14Techniques for controlling recycling of blocks of memory
522014030446410/09/14Performing deduplication in a data storage system
532014030456210/09/14Method for testing paths to pull-up and pull-down of input/output pads
542014029229810/02/14Operational amplifier-based current-sensing circuit for dc-dc voltage converters and the like
552014029812310/02/14Scan chain reconfiguration and repair
562014029812910/02/14Generating partially sparse generator matrix for a quasi-cyclic low-density parity-check encoder
572014029813110/02/14Priori information based post-processing in low-density parity-check code decoders
582014029814810/02/14Trend-analysis scheme for reliably reading data values from memory
592014028591809/25/14Quality based bit error rate prediction
602014028610209/25/14Method of optimizing solid state drive soft retry voltages
612014028614909/25/14Automatic on-drive sync-mark search and threshold adjustment
622014028638509/25/14Multi-dimensional signal equalization
632014028945009/25/14Dynamic log likelihood ratio quantization for solid state drive controllers
642014028955009/25/14Integrated clock architecture for improved testing
652014028958209/25/14Reduced constraint code data processing
662014026633809/18/14Biased bang-bang phase detector for clock and data recovery
672014026639509/18/14Ac coupling circuit with hybrid switches
682014026649709/18/14Ac coupling circuit with hybrid switches and constant load
692014026681509/18/14Lempel-ziv data compression with shortened hash chains based on repetitive patterns
702014026682009/18/14Interleaved multipath digital power amplification
712014026700409/18/14User adjustable gesture space
722014026838909/18/14Enhanced sync mark mis-detection protection
732014026839009/18/14Transition based equalization
742014026839109/18/14Data sequence detection in band-limited channels using cooperative sequence equalization
752014026839709/18/14Hardware support of servo format with two preamble fields
762014026840009/18/14Loop feedback
772014026840109/18/14P-distance based priority data processing
782014026904809/18/14Retention detection and/or channel tracking policy in a flash memory based storage system
792014026905309/18/14Nonvolatile memory data recovery after power failure
802014026988809/18/14Adaptive continuous time linear equalizer
812014026997809/18/14Interleaved multipath digital power amplification
822014028041709/18/14Linear phase fir biorthogonal wavelet filters with complementarity for image noise reduction
832014028041809/18/14Numerical method: making the infinite, finite. a universal transform and system of force vector
842014028042909/18/14Efficient hardware structure for sorting/adding multiple inputs assigned to different bins
852014028105709/18/14Unified message-based communications
862014028108309/18/14Enhanced queue management
872014028110609/18/14Direct routing between address spaces through a nontransparent peripheral component interconnect express bridge
882014028114309/18/14Reducing flash memory write amplification and latency
892014028117109/18/14Lock-free communication storage request reordering
902014028128109/18/14Host command based read disturb methodology
912014028162709/18/14Device sleep partitioning and keys
922014028168809/18/14Method and system of data recovery in a raid controller
932014028170309/18/14Local repair signature handling for repairable memories
942014028176709/18/14Recovery strategy that reduces errors misidentified as reliable
952014028178709/18/14Min-sum based hybrid non-binary low density parity check decoder
962014028181809/18/14Method for format savings in coherently written fragmented sectors
972014028182209/18/14Generation of soft decision error correction code information
982014028184109/18/14Sync mark mis-detection protection
992014028314609/18/14Tamper sensor
1002014025320309/11/14Programmable clock spreading
1012014025322209/11/14Preventing electronic device counterfeits
1022014025322609/11/14Power integrity control through active current profile management
1032014025404109/11/14Servo marginalization
1042014025404309/11/14Sampling-phase acquisition based on channel-impulse-response estimation
1052014025459309/11/14Network processor having multicasting protocol
1062014025465509/11/14Adaptation of equalizer settings using error signals sampled at several different phases
1072014025473509/11/14Transmit reference signal cleanup within a synchronous network application
1082014025837509/11/14Large object cache management in a network
1092014025856509/11/14Smart discovery model in a serial attached small computer system topology
1102014025857209/11/14Preemptive connection switching for serial attached small computer system interface systems
1112014025858709/11/14Self recovery in a solid state drive
1122014025859509/11/14System, method and computer-readable medium for dynamic cache sharing in a flash-based caching solution supporting virtual machines
1132014025859809/11/14Scalable storage devices
1142014025861009/11/14Raid cache memory system with volume windows
1152014025861309/11/14Volume change flags for incremental snapshots of stored data
1162014025862809/11/14System, method and computer-readable medium for managing a cache store to achieve improved cache ramp-up across system reboots
1172014025875509/11/14Storage device power failure infrastructure
1182014025875909/11/14De-queuing an active queue
1192014025876909/11/14Partial r-block recycling
1202014024751409/04/14Adc sample based inter-track interference compensation
1212014025024609/04/14Intelligent data buffering between interfaces
1222014025026309/04/14Techniques for reducing memory write operations using coalescing memory buffers and difference information
1232014025026909/04/14Declustered raid pool as backup for raid volumes
1242014025031509/04/14Storage system data hardening
1252014025033809/04/14Virtual function timeout for single root input/output virtualization controllers
1262014025035209/04/14Signal reduction based data processor marginalization
1272014024003308/28/14On-die programming of integrated circuit bond pads
1282014024046708/28/14Image processing method and apparatus for elimination of depth artifacts
1292014024086408/28/14Storage device having degauss circuitry configured for generating degauss signal with asymmetric decay envelopes
1302014024087008/28/14Analog tunneling current sensors for use with disk drive storage devices
1312014024102808/28/14Two-bit read-only memory cell
1322014024105608/28/14Reduced complexity reliability computations for flash memories
1332014024106108/28/14Fast access with low leakage and low power technique for read only memory devices
1342014024106208/28/14Modular, scalable rigid flex memory module
1352014024147808/28/14Timing phase estimation for clock and data recovery
1362014024487508/28/14Priority based connection arbitration in a sas topology to facilitate quality of service (qos) in sas transport
1372014024490108/28/14Metadata management for a flash drive
1382014024490208/28/14Fast read in write-back cached memory
1392014024492608/28/14Dedicated memory structure for sector spreading interleaving
1402014024492808/28/14Method and system to provide data protection to raid 0/ or degraded redundant virtual disk
1412014024493608/28/14Maintaining cache coherency between storage controllers
1422014024508608/28/14Test signal generator for low-density parity-check decoder
1432014024509308/28/14Master boot record protection in a solid state drive
1442014024530008/28/14Dynamically balanced credit for virtual functions in single root input/output virtualization
1452014024540808/28/14Biometric approach to track credentials of anonymous user of a mobile device
1462014023312808/21/14Burst demodulation
1472014023312908/21/14Noise predictive filter adaptation for inter-track interference cancellation
1482014023313008/21/14Determining noise components in a signal set
1492014023330208/21/14Write-tracking circuitry for memory devices
1502014023332208/21/14Adaptive architecture in a channel detector for nand flash channels
1512014023356708/21/14High speed network bridging
1522014023361908/21/14Pattern-based loss of signal detector
1532014023366808/21/14Code forwarding and clock generation for transmitter repeaters
1542014023716208/21/14Non-volatile memory channel control using a general purpose programmable processor in combination with a low level programmable sequencer
1552014023716308/21/14Reducing writes to solid state drive cache memories of storage controllers
1562014023716608/21/14Higher-level redundancy information computation
1572014023719308/21/14Cache window management
1582014023731308/21/14Trapping set disruption
1592014023731408/21/14Skip layer data decoding
1602014023732908/21/14Ratio-adjustable sync mark detection system
1612014022566908/14/14Extended variable gain amplification bandwidth with high-frequency boost
1622014022622908/14/14Shared layer data decoding
1632014022623308/14/14Storage device with reflection compensation circuitry
1642014022623408/14/14Providing controllable steady state current waveshaping in a hard disk drive (hdd) preamplifier
1652014022685408/14/14Three-dimensional region of interest tracking based on key frame matching
1662014022689508/14/14Feature point based robust three-dimensional rigid body registration
1672014022796908/14/14Indium tin oxide loop antenna for near field communication
1682014022807308/14/14Automatic presentation of an image from a camera responsive to detection of a particular type of movement of a user device
1692014022965108/14/14Managing arbitration in mixed link rate wide ports
1702014022965208/14/14Methods and structure for fast context switching among a plurality of expanders in a serial attached scsi domain
1712014022965808/14/14Cache load balancing in storage controllers
1722014022967008/14/14Cache coherency and synchronization support in expanders in a raid topology with multiple initiators
1732014022967608/14/14Rebuild of redundant secondary storage cache
1742014022970008/14/14Accommodating end of transfer request in a data storage device
1752014022973308/14/14Key wrapping to allow secure access to media by multiple authorities with modifiable permissions
1762014022975708/14/14Restoring expander operations in a data storage switch
1772014022976908/14/14Methods and structure for single root input/output virtualization enhancement in peripheral component interconnect express systems
1782014022977808/14/14At-speed scan testing of interface functional logic of an embedded memory or other circuit core
1792014022979908/14/14Statistical adaptive error correction for a flash memory
1802014022980608/14/14Distributed low density parity check decoding
1812014022994108/14/14Method and controller device for quality of service (qos) caching in a virtualized environment
1822014022995408/14/14Data quality based variable data process scheduling
1832014021902808/07/14Compensation loop for read voltage adaptation
1842014022076008/07/14Integration of shallow trench isolation and through-substrate vias into integrated circuit designs
1852014022307108/07/14Reducing write latency in a data storage system by using a command-push model
1862014022307208/07/14Tiered caching using single level cell and multi-level cell flash technology
1872014022307508/07/14Physical-to-logical address map to speed up a recycle operation in a solid state drive
1882014022309408/07/14Selective raid protection for cache memory
1892014022310608/07/14Method to throttle rate of data caching for improved i/o performance
1902014022311408/07/14Buffer for managing data samples in a read channel
1912014022313608/07/14Lookup tables utilizing read only memory and combinational logic
1922014022325908/07/14Memory architecture for layered low-density parity-check decoder
1932014022326708/07/14Radix-4 viterbi forward error correction decoding
1942014022327008/07/14Classifying bit errors in transmitted run length limited data
1952014022329508/07/14Geographic based spell check
1962014021133607/31/14Automatic gain control loop adaptation for enhanced nyquist data pattern detection
1972014021133707/31/14Improved short media defect detection
1982014021183907/31/14Receiver having limiter-enhanced data eye openings
1992014021474807/31/14Incremental dfa compilation with single rule granularity
2002014021474907/31/14Dfa-nfa splitting
2012014021509007/31/14Dfa sub-scans
2022014021512307/31/14Controller-opaque communication with non-volatile memory devices
2032014021514907/31/14File-system aware snapshots of stored data
2042014021519907/31/14Fast-boot list to speed booting an operating system
2052014021528507/31/14Integrated-interleaved low density parity check (ldpc) codes
2062014021534107/31/14Transitioning between pages of content on a display of a user device
2072014020465907/24/14Capacitive coupled sense amplifier biased at maximum gain point
2082014020466007/24/14Memory having sense amplifier for output tracking by controlled feedback latch
2092014020468307/24/14Margin free pvt tolerant fast self-timed sense amplifier reset circuit
2102014020498707/24/14Determining channel loss in a dispersive communication channel at the nyquist frequency
2112014020499507/24/14Efficient region of interest detection
2122014020500507/24/14Mpeg-2 to h.264 video transcoding
2132014020774307/24/14Method for storage driven de-duplication of server memory
2142014020799607/24/14Hybrid hard disk drive having a flash storage processor
2152014020800307/24/14Variable-size flash translation layer
2162014020800407/24/14Translation layer partitioned between host and controller
2172014020800507/24/14System, method and computer-readable medium for providing selective protection and endurance improvements in flash-based cache
2182014020800707/24/14Management of and region selection for writes to non-volatile memory
2192014020802407/24/14System and methods for performing embedded full-stripe write operations to a data volume with data elements distributed across multiple modules
2202014020804607/24/14Storage device out-of-space handling
2212014020804807/24/14Efficient remote copy
2222014020806107/24/14Locating data in non-volatile memory
2232014020806207/24/14Storage address space to nvm address, span, and length mapping/converting
2242014020807607/24/14Dfa compression and execution
2252014020817507/24/14At-speed scan testing of clock divider logic in a clock module of an integrated circuit
2262014020818007/24/14Reusing a layered decoder to yield a non-layered result
2272014019840407/17/14X-sample based noise cancellation
2282014019840507/17/14Loop processing with variance adaptation
2292014019878907/17/14Low latency in-line data compression for packet transmission systems
2302014020084907/17/14Diversity loop detector with component detector switching
2312014020144207/17/14Cache based storage controller
2322014020146207/17/14Subtractive validation of cache lines for virtual machines
2332014020158407/17/14Scan test circuitry comprising at least one scan chain and associated reset multiplexing circuitry
2342014020158507/17/14State-split based endec
2352014019140307/10/14Multi-die semiconductor package and method of manufacturing thereof
2362014019180107/10/14Bicmos gate driver for class-s radio frequency power amplifier
2372014019260307/10/14Differential sense amplifier for solid-state memories
2382014019263307/10/14Providing fast and efficient flushing of a forwarding database in a network processor
2392014019284107/10/14Ultra-wideband loss of signal detector at a receiver in a high speed serializer/deserializer (serdes) application
2402014019293507/10/14Receiver with dual clock recovery circuits
2412014019309207/10/14Superresolution image processing using an invertible sparse matrix
2422014019571407/10/14Methods and structure for buffering host requests in serial attached scsi expanders
2432014019571807/10/14Control logic design to support usb cache offload
2442014019573107/10/14Physical link management
2452014019573207/10/14Method and system to maintain maximum performance levels in all disk groups by using controller vds for background tasks
2462014018432307/03/14Hybrid digital/analog power amplifier
2472014018515807/03/14Fly height control for hard disk drives
2482014018515907/03/14Sync mark detection using branch metrics from data detector
2492014018536607/03/14Pre-charge tracking of global read lines in high speed sram


ARCHIVE: New 2014 2013 2012 2011 2010 2009



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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Lsi Corporation in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Lsi Corporation with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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