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Lsi Corporation
Lsi Corporation_20100107
Lsi Corporation_20100114
Lsi Corporation_20100128
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Lsi Corporation patents

Recent patent applications related to Lsi Corporation. Lsi Corporation is listed as an Agent/Assignee. Note: Lsi Corporation may have other listings under different names/spellings. We're not affiliated with Lsi Corporation, we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "L" | Lsi Corporation-related inventors

Search recent Press Releases: Lsi Corporation-related press releases
Count Application # Date Lsi Corporation patents (updated weekly) - BOOKMARK this page
12015024213308/27/15  new patent  Storage workload hinting
22015024268108/27/15  new patent  System and image processing
32015024331008/27/15  new patent  Systems and methods for multi-head separation determination
42015024331108/27/15  new patent  Systems and methods for synchronization hand shaking in a storage device
52015024332108/27/15  new patent  Reading data from hard disks having reduced preambles
62015024332208/27/15  new patent  Systems and methods for multi-head servo data processing
72015024336308/27/15  new patent  Adjusting log likelihood ratio values to compensate misplacement of read voltages
82015024353408/27/15  new patent  Copper wire bonding apparatus using a purge gas to enhance ball bond reliability
92015024361708/27/15  new patent  Method for flip-chip bonding using copper pillars
102015023442308/20/15 Baud rate phase detector with no error latches
112015023570508/20/15 System to control a width of a programming threshold voltage distribution width when writing hot-read data
122015023672608/20/15 Refresh, run, aggregate decoder recovery
132015023687508/20/15 Method and pre-cursor intersymbol interference correction
142015022731408/13/15 Systems and methods for last written page handling in a memory device
152015022740308/13/15 Decoding electronic non-volatile computer storage apparatus
162015022741808/13/15 Hot-read data aggregation and code selection
172015022748608/13/15 Method to facilitate fast context switching for partial and extended path extension to remote expanders
182015022830208/13/15 Zero phase start estimation in readback signals
192015022830308/13/15 Read channel sampling utilizing two quantization modules for increased sample bit width
202015022830408/13/15 Systems and methods for end of fragment marker based data alignment
212015022933108/13/15 Systems and methods for area efficient data encoding
222015022933308/13/15 Systems and methods for rank deficient encoding
232015022933708/13/15 Mitigation of write errors in multi-level cell flash memory through adaptive error correction code decoding
242015022015308/06/15 Gesture recognition system with finite state machine control of cursor detector and dynamic gesture detector
252015022038808/06/15 Systems and methods for hard error reduction in a solid state memory device
262015022045208/06/15 System, method and computer-readable medium for dynamically mapping a non-volatile memory store
272015022074408/06/15 System for execution of security related functions
282015022080408/06/15 Image processor with edge selection functionality
292015022133308/06/15 Reader separation dependent linear and track density push for array reader based magnetic recording
302015021388107/30/15 Integrated read/write tracking in sram
312015020575207/23/15 High density mapping for multiple converter samples in multiple lane interface
322015020631807/23/15 Method and image enhancement and edge verificaton using at least one additional image
332015020657807/23/15 Area-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail sram memories
342015020764807/23/15 Modular low power serializer-deserializer
352015020807607/23/15 Multi-core architecture for low latency video decoder
362015019912907/16/15 System and providing data services in direct attached storage via multiple de-clustered raid pools
372015019914007/16/15 Interleaving codewords over multiple flash planes
382015019914907/16/15 Framework for balancing robustness and latency during collection of statistics from soft reads
392015019922707/16/15 Fault detection and identification in a multi-initiator system
402015019924407/16/15 Intelligent i/o cache rebuild in a storage controller
412015019926907/16/15 Enhanced ssd caching
422015019999107/16/15 Multiple track detection
432015020068107/16/15 Segmented digital-to-analog converter with overlapping segments
442015019356407/09/15 System and using clock chain signals of an on-chip clock controller to control cross-domain paths
452015019421907/09/15 Capacitance coupling parameter estimation in flash memories
462015019510807/09/15 Receiver with pipelined tap coefficients and shift control
472015019535707/09/15 Enhancing active link utilization in serial attached scsi topologies
482015018631707/02/15 Method and detecting the initiator/target orientation of a smart bridge
492015018738407/02/15 Two-dimensional magnetic recording reader offset estimation
502015018738507/02/15 Systems and methods for multi-head balancing in a storage device
512015018855107/02/15 Clock recovery using quantized phase error samples using jitter frequency-dependent quantization thresholds and loop gains
522015018857607/02/15 Systems and methods for efficient targeted symbol flipping
532015017814906/25/15 Method to distribute user data and error correction data over different page types by leveraging error rate variations
542015017815206/25/15 Preventing programming errors from occurring when programming flash memory cells
552015017820106/25/15 System for efficient caching of swap i/o and/or similar i/o pattern(s)
562015017831206/25/15 Attribute-based assistance request system for sequentially contacting nearby contacts without having them divulge their presence or location
572015017921306/25/15 Servo channel with equalizer adaptation
582015018051206/25/15 Systems and methods of converting detector output to multi-level soft information
592015016945806/18/15 System and methods for caching a small size i/o to improve caching device endurance
602015017067606/18/15 Skew-aware disk format for array reader based magnetic recording
612015017070606/18/15 Systems and methods for ati characterization
622015016086906/11/15 Systems and methods for multi-dimensional data processor operational marginalization
632015016088606/11/15 Method and system for programmable sequencer for processing i/o for various pcie disk drives
642015016104506/11/15 Slice formatting and interleaving for interleaved sectors
652015016205706/11/15 Multiple retry reads in a read channel of a memory
662015016278106/11/15 Illumination-based charging system for portable devices
672015016336306/11/15 Low complexity tone/voice discrimination method using a rising edge of a frequency power envelope
682015015411406/04/15 System and method to interleave memory
692015015413806/04/15 Wide port emulation at serial attached scsi expanders
702015015502106/04/15 Area-efficient process-and-temperature-adaptive self-time scheme for performance and power improvement
712015014574005/28/15 Integrated frequency multiplier and slot antenna
722015014692005/28/15 Gesture recognition method and apparatus utilizing asynchronous multithreaded processing
732015014939505/28/15 Incremental updates for ordered multi-field classification rules when represented by a tree of longest prefix matching tables
742015014969805/28/15 Eliminating or reducing programming errors when programming flash memory cells
752015014984005/28/15 Read retry for non-volatile memories
762015014985505/28/15 Bit-line defect detection using unsatisified parity code checks
772015014985605/28/15 Decoding with log likelihood ratios stored in a controller
782015014987105/28/15 Flash channel with selective decoder likelihood dampening
792015013785505/21/15 Current to voltage converter
802015013886305/21/15 Interleaved write assist for hierarchical bitline sram architectures
812015013886405/21/15 Memory architecture with alternating segments and multiple bitlines
822015013887605/21/15 Global bitline write assist for sram architectures
832015013948705/21/15 Image processor with static pose recognition module utilizing segmented region of interest
842015014316405/21/15 I/o request mirroring in a clustered storage system
852015014319605/21/15 Systems and methods for faid follower decoding
862015014320205/21/15 Systems and methods for soft decision generation in a solid state memory system
872015013137305/14/15 Incremental programming pulse optimization to reduce write errors
882015013461305/14/15 Systems and methods for lost synchronization data set reprocessing
892015013485505/14/15 Decoupling host and device address maps for a peripheral component interconnect express controller
902015013500605/14/15 System and write hole protection for a multiple-node storage cluster
912015013503105/14/15 Dynamic per-decoder control of log likelihood ratio and decoding parameters
922015013503205/14/15 Detection/erasure of random write errors using converged hard decisions
932015012787105/07/15 Updated io memory management unit identity settings for dma remapping
942015012788305/07/15 Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory
952015012800605/07/15 Device quality metrics using unsatisfied parity checks
962015011709704/30/15 Systems and methods for sub-zero threshold characterization in a memory cell
972015011722604/30/15 Method and system for session based data monitoring for wireless edge content caching networks
982015012098104/30/15 Data interface for point-to-point communications between devices
992015012098904/30/15 Tracking and utilizing second level map index for recycling of solid state drive blocks
1002015012108804/30/15 Method of managing aligned and unaligned data bands in a self encrypting solid state drive
1012015012117304/30/15 Systems and methods for internal disk drive data compression
1022015010905204/23/15 Closed-loop adaptive voltage scaling for integrated circuits
1032015011016504/23/15 Transmitter training using receiver equalizer coefficients
1042015011320504/23/15 Systems and methods for latency based data recycling in a solid state memory system
1052015011331204/23/15 System and detecting server removal from a cluster to enable fast failover of storage
1062015011331804/23/15 Systems and methods for soft data utilization in a solid state memory system
1072015011333504/23/15 Sending failure information from a solid state drive (ssd) to a host device
1082015011335404/23/15 Generating soft decoding information for flash memory error correction using hard decision patterns
1092015010360404/16/15 Memory array architectures having memory cells with shared write assist circuitry
1102015010396104/16/15 Digital frequency band detector for clock and data recovery
1112015010657704/16/15 De-interleaving on an as-needed basis
1122015010666604/16/15 Speculative bit error rate calculator
1132015010667504/16/15 Systems and methods for multi-algorithm concatenation encoding and decoding
1142015009761104/09/15 Voltage follower having a feed-forward device
1152015010081004/09/15 Adaptive power-down of disk drives based on predicted idle time
1162015009162004/02/15 Reducing current variation when switching clocks
1172015009229004/02/15 Non-binary layered low density parity check decoder
1182015009248904/02/15 Flash memory reference voltage detection with tracking of cross-points of cell voltage distributions using histograms
1192015008539203/26/15 System and monitoring preamble signal quality
1202015008558703/26/15 Ping-pong buffer using single-port memory
1212015008559203/26/15 Bit-line discharge assistance in memory devices
1222015008595703/26/15 Method of calibrating a slicer in a receiver or the like
1232015008910203/26/15 Solid state drives that cache boot data
1242015008913203/26/15 Dynamic storage volume configuration based on input/output requests
1252015008933003/26/15 Systems and methods for enhanced data recovery in a solid state memory system
1262015007718803/19/15 Voltage follower amplifier
1272015007727703/19/15 Reduced polar codes
1282015007810303/19/15 Sensing technique for single-ended bit line memory architectures
1292015008162603/19/15 Systems and methods for recovered data stitching
1302015008164903/19/15 In-line deduplication for a network and/or storage platform
1312015008211503/19/15 Systems and methods for fragmented data recovery
1322015008212103/19/15 Method of erase state handling in flash channel tracking
1332015008212403/19/15 Spatially decoupled redundancy schemes for a solid state drive (ssd)
1342015007079603/12/15 Array-reader based magnetic recording systems with mixed synchronization
1352015007432703/12/15 Active recycling for solid state drive
1362015007432803/12/15 Dynamic map pre-fetching for improved sequential reads of a solid-state media
1372015007435503/12/15 Efficient caching of file system journals
1382015007450103/12/15 Cascaded viterbi bitstream generator
1392015006273003/05/15 Array-reader based magnetic recording systems with quadrature amplitude modulation
1402015006273203/05/15 Systems and methods for two stage tone reduction
1412015006273403/05/15 Systems and methods for multi-level encoding and decoding
1422015006273703/05/15 Adaptive pattern detection for pattern-dependent write current control in a magnetic recording system
1432015006273803/05/15 Systems and methods for variable sector count spreading and de-spreading
1442015006321703/05/15 Mapping between variable width samples and a frame
1452015006725303/05/15 Input/output request shipping in a storage system with multiple storage controllers
1462015006734903/05/15 Virtual bands concentration for self encrypting drives
1472015006768503/05/15 Systems and methods for multiple sensor noise predictive filtering
1482015005524902/26/15 Systems and methods for multi-resolution data sensing
1492015005564402/26/15 Precise timestamping of ethernet packets by compensating for start-of-frame delimiter detection delay and delay variations
1502015005577402/26/15 Echo cancellation with quantization compensation
1512015005853302/26/15 Data storage controller and exposing information stored in a data storage controller to a host system
1522015005855702/26/15 Performance improvements in input / output operations between a host system and an adapter-coupled cache
1532015005869302/26/15 Systems and methods for enhanced data encoding and decoding
1542015004831002/19/15 System and providing an electron blocking layer with doping control
1552015004240302/12/15 High-voltage voltage-switched class-s amplifier
1562015004327002/12/15 Memory cell having built-in write assist
1572015004380702/12/15 Depth image compression and decompression utilizing depth and amplitude data
1582015004675602/12/15 Predictive failure analysis to trigger rebuild of a drive in a raid array
1592015003694202/05/15 Object recognition and tracking using a classifier comprising cascaded stages of multiple decision trees
1602015003978702/05/15 Multi-protocol storage controller
1612015003979602/05/15 Acquiring resources from low priority connection requests in sas
1622015003983202/05/15 System and caching hinted data
1632015003983502/05/15 System and hinted cache data removal
1642015003993202/05/15 Arbitration suspension in a sas domain
1652015003997802/05/15 Systems and methods for hybrid priority based data processing
1662015002960801/29/15 Array-reader based magnetic recording systems with frequency division multiplexing
1672015003002701/29/15 Switch device with device-specified bridge domains
1682015003023201/29/15 Image processor configured for efficient estimation and elimination of background information in images
1692015003296301/29/15 Dynamic selection of cache levels
1702015003306501/29/15 Solid state drive emergency pre-boot application providing expanded data recovery function
1712015003307401/29/15 Deadlock detection and recovery in sas
1722015002216901/22/15 Feedback/feed forward switched capacitor voltage regulation
1732015002270401/22/15 Orientation-based camera operation
1742015002360701/22/15 Gesture recognition method and apparatus based on analysis of multiple candidate boundaries
1752015002640301/22/15 Self-adjusting caching system
1762015002641101/22/15 Cache system for managing various cache line conditions
1772015002648801/22/15 Selectively powering a storage device over a data network
1782015002650301/22/15 Appliances powered over sas
1792015002653601/22/15 Data decoder with trapping set flip bit mapper
1802015001532901/15/15 Radio frequency composite class-s power amplifier having discrete power control
1812015001598401/15/15 Storage media inter-track interference cancellation
1822015001598601/15/15 Methods and improved threshold adaptation for a euclidean detector
1832015001598701/15/15 Prioritized spin-up of drives
1842015001649701/15/15 Clock and data recovery architecture with adaptive digital phase skew
1852015001979501/15/15 Memory system for shadowing volatile data
1862015001981801/15/15 Maintaining cache size proportional to power pack charge
1872015001982201/15/15 System for maintaining dirty cache coherency across reboot of a node
1882015000889401/08/15 Dynamic start-up circuit for hysteretic loop switched-capacitor voltage regulator
1892015001269901/08/15 System and versioning cache for a clustering topology
1902015001270201/08/15 Redundant array of independent disks volume creation
1912015001280001/08/15 Systems and methods for correlation based data alignment
1922015000681501/01/15 Backup of cached dirty data during power outages
1932014037995912/25/14 Map recycling acceleration
1942014038022312/25/14 User interface comprising radial layout soft keypad
1952014036771712/18/14 Semiconductor optical emitting device with metallized sidewalls
1962014036939512/18/14 Error detection based on superheterodyne conversion and direct downconversion
1972014036969612/18/14 Color coding and optical sub-band communication utilizing color coding
1982014037263712/18/14 Pcie tunneling through sas
1992014037267212/18/14 System and providing improved system performance by moving pinned data to open nand flash interface working group modules while the system is in a running state
2002014037278312/18/14 System and providing dynamic charge current based on maximum card power
2012014037282812/18/14 Systems and methods for hybrid layer data decoding
2022014037283612/18/14 Systems and methods for data processing control
2032014036228912/11/14 Method and increasing frame rate of an image stream using at least one higher frame rate image stream
2042014036246312/11/14 Timing error detector with diversity loop detector decision feedback
2052014035921612/04/14 Confirmed divert bitmap to synchronize raid firmware operations with fast-path hardware i/o processing
2062014035926612/04/14 Optimizing boot time of a storage system
2072014035939412/04/14 Apparatus for processing signals carrying modulation-encoded parity bits
2082014034819711/27/14 Semiconductor optical emitting device with lens structure formed in a cavity of a substrate of the device
2092014034947511/27/14 Moisture barrier for a wire bond
2102014035148611/27/14 Variable redundancy in a solid state drive
2112014035167111/27/14 Shift register-based layered low density parity check decoder
2122014034078011/20/14 Method and system for sliding-window based phase, gain, frequency and dc offset estimation for servo channel
2132014034123111/20/14 Lane-based multiplexing for physical links in serial attached small computer system interface architectures
2142014034449211/20/14 Methods and systems for reducing spurious interrupts in a data storage system
2152014034461611/20/14 Techniques for providing data redundancy after reducing memory writes
2162014034496011/20/14 Selective control of on-chip debug circuitry of embedded processors
2172014033427811/13/14 Systems and methods for energy based head contact detection
2182014033428011/13/14 Systems and methods for characterizing head contact
2192014033428111/13/14 Systems and methods for data processor marginalization based upon bit error rate
2202014033449111/13/14 Prediction based methods for fast routing of ip flows using communication/network processors
2212014033754011/13/14 Method and system for i/o flow management for pcie devices
2222014033758311/13/14 Intelligent cache window management for storage systems
2232014033767611/13/14 Systems and methods for processing data with microcontroller based retry features
2242014033100111/06/14 Command barrier for a solid state drive controller
2252014033109611/06/14 Cross-decoding for non-volatile storage
2262014033110811/06/14 Systems and methods for detecting media flaws
2272014032511710/30/14 Flash translation layer with lower write amplification
2282014032514410/30/14 Protection information initialization
2292014032514510/30/14 Cache rebuilds based on tracking data for cache entries
2302014032514610/30/14 Creating and managing logical volumes from unused space in raid disk groups
2312014032530310/30/14 Systems and methods for protected data encoding
2322014031237210/23/14 Semiconductor optical emitting device with grooved substrate providing multiple angled light emission paths
2332014031247510/23/14 Die reuse in electrical circuits
2342014031361010/23/14 Systems and methods selective complexity data decoding
2352014031394610/23/14 Non-linear interference cancellation for wireless transceivers
2362014031417610/23/14 Non-linear modeling of a physical system using two-dimensional look-up table with bilinear interpolation
2372014031418110/23/14 Non-linear modeling of a physical system using look-up table with polynomial interpolation
2382014031426510/23/14 Headphones with rotatable speaker arranged within housing of earpiece assembly
2392014031675210/23/14 Non-linear modeling of a physical system using direct optimization of look-up table values
2402014031716310/23/14 Vector processor having instruction set with sliding window non-linear convolutional function
2412014031733410/23/14 Storage of gate training parameters for devices utilizing random access memory
2422014031734610/23/14 Redundant array of independent disks systems that utilize spans with different storage device counts for a logical volume
2432014031737610/23/14 Digital processor having instruction set with complex angle function
2442014030734510/16/14 Systems and methods for preventing adjacent track erasure
2452014030114310/09/14 Techniques for controlling recycling of blocks of memory
2462014030446410/09/14 Methods and systems for performing deduplication in a data storage system
2472014030456210/09/14 Method for testing paths to pull-up and pull-down of input/output pads
2482014029229810/02/14 Operational amplifier-based current-sensing circuit for dc-dc voltage converters and the like
2492014029812310/02/14 Scan chain reconfiguration and repair

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Lsi Corporation in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Lsi Corporation with additional patents listed. Browse our Agent directory for other possible listings. Page by