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Lsi Corporation patents


      
Recent patent applications related to Lsi Corporation. Lsi Corporation is listed as an Agent/Assignee. Note: Lsi Corporation may have other listings under different names/spellings. We're not affiliated with Lsi Corporation, we're just tracking patents.

ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009 | Company Directory "L" | Lsi Corporation-related inventors


Echo cancellation with quantization compensation

Lsi

Echo cancellation with quantization compensation

Data storage controller and  exposing information stored in a data storage controller to a host system

Lsi

Data storage controller and exposing information stored in a data storage controller to a host system

Search recent Press Releases: Lsi Corporation-related press releases
Count Application # Date Lsi Corporation patents (updated weekly) - BOOKMARK this page
12015005524902/26/15 new patent  Systems and methods for multi-resolution data sensing
22015005564402/26/15 new patent  Precise timestamping of ethernet packets by compensating for start-of-frame delimiter detection delay and delay variations
32015005577402/26/15 new patent  Echo cancellation with quantization compensation
42015005853302/26/15 new patent  Data storage controller and exposing information stored in a data storage controller to a host system
52015005855702/26/15 new patent  Performance improvements in input / output operations between a host system and an adapter-coupled cache
62015005869302/26/15 new patent  Systems and methods for enhanced data encoding and decoding
72015004831002/19/15System and providing an electron blocking layer with doping control
82015004240302/12/15High-voltage voltage-switched class-s amplifier
92015004327002/12/15Memory cell having built-in write assist
102015004380702/12/15Depth image compression and decompression utilizing depth and amplitude data
112015004675602/12/15Predictive failure analysis to trigger rebuild of a drive in a raid array
122015003694202/05/15Object recognition and tracking using a classifier comprising cascaded stages of multiple decision trees
132015003978702/05/15Multi-protocol storage controller
142015003979602/05/15Acquiring resources from low priority connection requests in sas
152015003983202/05/15System and caching hinted data
162015003983502/05/15System and hinted cache data removal
172015003993202/05/15Arbitration suspension in a sas domain
182015003997802/05/15Systems and methods for hybrid priority based data processing
192015002960801/29/15Array-reader based magnetic recording systems with frequency division multiplexing
202015003002701/29/15Switch device with device-specified bridge domains
212015003023201/29/15Image processor configured for efficient estimation and elimination of background information in images
222015003296301/29/15Dynamic selection of cache levels
232015003306501/29/15Solid state drive emergency pre-boot application providing expanded data recovery function
242015003307401/29/15Deadlock detection and recovery in sas
252015002216901/22/15Feedback/feed forward switched capacitor voltage regulation
262015002270401/22/15Orientation-based camera operation
272015002360701/22/15Gesture recognition method and apparatus based on analysis of multiple candidate boundaries
282015002640301/22/15Self-adjusting caching system
292015002641101/22/15Cache system for managing various cache line conditions
302015002648801/22/15Selectively powering a storage device over a data network
312015002650301/22/15Appliances powered over sas
322015002653601/22/15Data decoder with trapping set flip bit mapper
332015001532901/15/15Radio frequency composite class-s power amplifier having discrete power control
342015001598401/15/15Storage media inter-track interference cancellation
352015001598601/15/15Methods and improved threshold adaptation for a euclidean detector
362015001598701/15/15Prioritized spin-up of drives
372015001649701/15/15Clock and data recovery architecture with adaptive digital phase skew
382015001979501/15/15Memory system for shadowing volatile data
392015001981801/15/15Maintaining cache size proportional to power pack charge
402015001982201/15/15System for maintaining dirty cache coherency across reboot of a node
412015000889401/08/15Dynamic start-up circuit for hysteretic loop switched-capacitor voltage regulator
422015001269901/08/15System and versioning cache for a clustering topology
432015001270201/08/15Redundant array of independent disks volume creation
442015001280001/08/15Systems and methods for correlation based data alignment
452015000681501/01/15Backup of cached dirty data during power outages
462014037995912/25/14Map recycling acceleration
472014038022312/25/14User interface comprising radial layout soft keypad
482014036771712/18/14Semiconductor optical emitting device with metallized sidewalls
492014036939512/18/14Error detection based on superheterodyne conversion and direct downconversion
502014036969612/18/14Color coding and optical sub-band communication utilizing color coding
512014037263712/18/14Pcie tunneling through sas
522014037267212/18/14System and providing improved system performance by moving pinned data to open nand flash interface working group modules while the system is in a running state
532014037278312/18/14System and providing dynamic charge current based on maximum card power
542014037282812/18/14Systems and methods for hybrid layer data decoding
552014037283612/18/14Systems and methods for data processing control
562014036228912/11/14Method and increasing frame rate of an image stream using at least one higher frame rate image stream
572014036246312/11/14Timing error detector with diversity loop detector decision feedback
582014035921612/04/14Confirmed divert bitmap to synchronize raid firmware operations with fast-path hardware i/o processing
592014035926612/04/14Optimizing boot time of a storage system
602014035939412/04/14Apparatus for processing signals carrying modulation-encoded parity bits
612014034819711/27/14Semiconductor optical emitting device with lens structure formed in a cavity of a substrate of the device
622014034947511/27/14Moisture barrier for a wire bond
632014035148611/27/14Variable redundancy in a solid state drive
642014035167111/27/14Shift register-based layered low density parity check decoder
652014034078011/20/14Method and system for sliding-window based phase, gain, frequency and dc offset estimation for servo channel
662014034123111/20/14Lane-based multiplexing for physical links in serial attached small computer system interface architectures
672014034449211/20/14Methods and systems for reducing spurious interrupts in a data storage system
682014034461611/20/14Techniques for providing data redundancy after reducing memory writes
692014034496011/20/14Selective control of on-chip debug circuitry of embedded processors
702014033427811/13/14Systems and methods for energy based head contact detection
712014033428011/13/14Systems and methods for characterizing head contact
722014033428111/13/14Systems and methods for data processor marginalization based upon bit error rate
732014033449111/13/14Prediction based methods for fast routing of ip flows using communication/network processors
742014033754011/13/14Method and system for i/o flow management for pcie devices
752014033758311/13/14Intelligent cache window management for storage systems
762014033767611/13/14Systems and methods for processing data with microcontroller based retry features
772014033100111/06/14Command barrier for a solid state drive controller
782014033109611/06/14Cross-decoding for non-volatile storage
792014033110811/06/14Systems and methods for detecting media flaws
802014032511710/30/14Flash translation layer with lower write amplification
812014032514410/30/14Protection information initialization
822014032514510/30/14Cache rebuilds based on tracking data for cache entries
832014032514610/30/14Creating and managing logical volumes from unused space in raid disk groups
842014032530310/30/14Systems and methods for protected data encoding
852014031237210/23/14Semiconductor optical emitting device with grooved substrate providing multiple angled light emission paths
862014031247510/23/14Die reuse in electrical circuits
872014031361010/23/14Systems and methods selective complexity data decoding
882014031394610/23/14Non-linear interference cancellation for wireless transceivers
892014031417610/23/14Non-linear modeling of a physical system using two-dimensional look-up table with bilinear interpolation
902014031418110/23/14Non-linear modeling of a physical system using look-up table with polynomial interpolation
912014031426510/23/14Headphones with rotatable speaker arranged within housing of earpiece assembly
922014031675210/23/14Non-linear modeling of a physical system using direct optimization of look-up table values
932014031716310/23/14Vector processor having instruction set with sliding window non-linear convolutional function
942014031733410/23/14Storage of gate training parameters for devices utilizing random access memory
952014031734610/23/14Redundant array of independent disks systems that utilize spans with different storage device counts for a logical volume
962014031737610/23/14Digital processor having instruction set with complex angle function
972014030734510/16/14Systems and methods for preventing adjacent track erasure
982014030114310/09/14Techniques for controlling recycling of blocks of memory
992014030446410/09/14Methods and systems for performing deduplication in a data storage system
1002014030456210/09/14Method for testing paths to pull-up and pull-down of input/output pads
1012014029229810/02/14Operational amplifier-based current-sensing circuit for dc-dc voltage converters and the like
1022014029812310/02/14Scan chain reconfiguration and repair
1032014029812910/02/14Generating partially sparse generator matrix for a quasi-cyclic low-density parity-check encoder
1042014029813110/02/14Priori information based post-processing in low-density parity-check code decoders
1052014029814810/02/14Trend-analysis scheme for reliably reading data values from memory
1062014028591809/25/14Systems and methods for quality based bit error rate prediction
1072014028610209/25/14Method of optimizing solid state drive soft retry voltages
1082014028614909/25/14Automatic on-drive sync-mark search and threshold adjustment
1092014028638509/25/14Systems and methods for multi-dimensional signal equalization
1102014028945009/25/14Dynamic log likelihood ratio quantization for solid state drive controllers
1112014028955009/25/14Integrated clock architecture for improved testing
1122014028958209/25/14Systems and methods for reduced constraint code data processing
1132014026633809/18/14Biased bang-bang phase detector for clock and data recovery
1142014026639509/18/14Ac coupling circuit with hybrid switches
1152014026649709/18/14Ac coupling circuit with hybrid switches and constant load
1162014026681509/18/14Lempel-ziv data compression with shortened hash chains based on repetitive patterns
1172014026682009/18/14Interleaved multipath digital power amplification
1182014026700409/18/14User adjustable gesture space
1192014026838909/18/14Systems and methods for enhanced sync mark mis-detection protection
1202014026839009/18/14Systems and methods for transition based equalization
1212014026839109/18/14Data sequence detection in band-limited channels using cooperative sequence equalization
1222014026839709/18/14Hardware support of servo format with two preamble fields
1232014026840009/18/14Systems and methods for loop feedback
1242014026840109/18/14Systems and methods for p-distance based priority data processing
1252014026904809/18/14Retention detection and/or channel tracking policy in a flash memory based storage system
1262014026905309/18/14Nonvolatile memory data recovery after power failure
1272014026988809/18/14Adaptive continuous time linear equalizer
1282014026997809/18/14Interleaved multipath digital power amplification
1292014028041709/18/14Linear phase fir biorthogonal wavelet filters with complementarity for image noise reduction
1302014028041809/18/14Numerical method: making the infinite, finite. a universal transform and system of force vector
1312014028042909/18/14Efficient hardware structure for sorting/adding multiple inputs assigned to different bins
1322014028105709/18/14Unified message-based communications
1332014028108309/18/14Enhanced queue management
1342014028110609/18/14Direct routing between address spaces through a nontransparent peripheral component interconnect express bridge
1352014028114309/18/14Reducing flash memory write amplification and latency
1362014028117109/18/14Lock-free communication storage request reordering
1372014028128109/18/14Host command based read disturb methodology
1382014028162709/18/14Device sleep partitioning and keys
1392014028168809/18/14Method and system of data recovery in a raid controller
1402014028170309/18/14Local repair signature handling for repairable memories
1412014028176709/18/14Recovery strategy that reduces errors misidentified as reliable
1422014028178709/18/14Min-sum based hybrid non-binary low density parity check decoder
1432014028181809/18/14Method for format savings in coherently written fragmented sectors
1442014028182209/18/14Method and generation of soft decision error correction code information
1452014028184109/18/14Systems and methods for sync mark mis-detection protection
1462014028314609/18/14Tamper sensor
1472014025320309/11/14Programmable clock spreading
1482014025322209/11/14Preventing electronic device counterfeits
1492014025322609/11/14Power integrity control through active current profile management
1502014025404109/11/14Servo marginalization
1512014025404309/11/14Sampling-phase acquisition based on channel-impulse-response estimation
1522014025459309/11/14Network processor having multicasting protocol
1532014025465509/11/14Adaptation of equalizer settings using error signals sampled at several different phases
1542014025473509/11/14Transmit reference signal cleanup within a synchronous network application
1552014025837509/11/14System and large object cache management in a network
1562014025856509/11/14Smart discovery model in a serial attached small computer system topology
1572014025857209/11/14Preemptive connection switching for serial attached small computer system interface systems
1582014025858709/11/14Self recovery in a solid state drive
1592014025859509/11/14System, method and computer-readable medium for dynamic cache sharing in a flash-based caching solution supporting virtual machines
1602014025859809/11/14Scalable storage devices
1612014025861009/11/14Raid cache memory system with volume windows
1622014025861309/11/14Volume change flags for incremental snapshots of stored data
1632014025862809/11/14System, method and computer-readable medium for managing a cache store to achieve improved cache ramp-up across system reboots
1642014025875509/11/14Storage device power failure infrastructure
1652014025875909/11/14System and de-queuing an active queue
1662014025876909/11/14Partial r-block recycling
1672014024751409/04/14Systems and methods for adc sample based inter-track interference compensation
1682014025024609/04/14Intelligent data buffering between interfaces
1692014025026309/04/14Techniques for reducing memory write operations using coalescing memory buffers and difference information
1702014025026909/04/14Declustered raid pool as backup for raid volumes
1712014025031509/04/14Storage system data hardening
1722014025033809/04/14Virtual function timeout for single root input/output virtualization controllers
1732014025035209/04/14Systems and methods for signal reduction based data processor marginalization
1742014024003308/28/14On-die programming of integrated circuit bond pads
1752014024046708/28/14Image processing elimination of depth artifacts
1762014024086408/28/14Storage device having degauss circuitry configured for generating degauss signal with asymmetric decay envelopes
1772014024087008/28/14Analog tunneling current sensors for use with disk drive storage devices
1782014024102808/28/14Two-bit read-only memory cell
1792014024105608/28/14Reduced complexity reliability computations for flash memories
1802014024106108/28/14Fast access with low leakage and low power technique for read only memory devices
1812014024106208/28/14Modular, scalable rigid flex memory module
1822014024147808/28/14Timing phase estimation for clock and data recovery
1832014024487508/28/14Priority based connection arbitration in a sas topology to facilitate quality of service (qos) in sas transport
1842014024490108/28/14Metadata management for a flash drive
1852014024490208/28/14Fast read in write-back cached memory
1862014024492608/28/14Dedicated memory structure for sector spreading interleaving
1872014024492808/28/14Method and system to provide data protection to raid 0/ or degraded redundant virtual disk
1882014024493608/28/14Maintaining cache coherency between storage controllers
1892014024508608/28/14Test signal generator for low-density parity-check decoder
1902014024509308/28/14Master boot record protection in a solid state drive
1912014024530008/28/14Dynamically balanced credit for virtual functions in single root input/output virtualization
1922014024540808/28/14Biometric approach to track credentials of anonymous user of a mobile device
1932014023312808/21/14Systems and methods for burst demodulation
1942014023312908/21/14Noise predictive filter adaptation for inter-track interference cancellation
1952014023313008/21/14Systems and methods for determining noise components in a signal set
1962014023330208/21/14Write-tracking circuitry for memory devices
1972014023332208/21/14Adaptive architecture in a channel detector for nand flash channels
1982014023356708/21/14High speed network bridging
1992014023361908/21/14Pattern-based loss of signal detector
2002014023366808/21/14Code forwarding and clock generation for transmitter repeaters
2012014023716208/21/14Non-volatile memory channel control using a general purpose programmable processor in combination with a low level programmable sequencer
2022014023716308/21/14Reducing writes to solid state drive cache memories of storage controllers
2032014023716608/21/14Higher-level redundancy information computation
2042014023719308/21/14Cache window management
2052014023731308/21/14Systems and methods for trapping set disruption
2062014023731408/21/14Systems and methods for skip layer data decoding
2072014023732908/21/14Ratio-adjustable sync mark detection system
2082014022566908/14/14Extended variable gain amplification bandwidth with high-frequency boost
2092014022622908/14/14Systems and methods for shared layer data decoding
2102014022623308/14/14Storage device with reflection compensation circuitry
2112014022623408/14/14System and providing controllable steady state current waveshaping in a hard disk drive (hdd) preamplifier
2122014022685408/14/14Three-dimensional region of interest tracking based on key frame matching
2132014022689508/14/14Feature point based robust three-dimensional rigid body registration
2142014022796908/14/14Indium tin oxide loop antenna for near field communication
2152014022807308/14/14Automatic presentation of an image from a camera responsive to detection of a particular type of movement of a user device
2162014022965108/14/14Managing arbitration in mixed link rate wide ports
2172014022965208/14/14Methods and structure for fast context switching among a plurality of expanders in a serial attached scsi domain
2182014022965808/14/14Cache load balancing in storage controllers
2192014022967008/14/14Cache coherency and synchronization support in expanders in a raid topology with multiple initiators
2202014022967608/14/14Rebuild of redundant secondary storage cache
2212014022970008/14/14Systems and methods for accommodating end of transfer request in a data storage device
2222014022973308/14/14System and key wrapping to allow secure access to media by multiple authorities with modifiable permissions
2232014022975708/14/14Restoring expander operations in a data storage switch
2242014022976908/14/14Methods and structure for single root input/output virtualization enhancement in peripheral component interconnect express systems
2252014022977808/14/14At-speed scan testing of interface functional logic of an embedded memory or other circuit core
2262014022979908/14/14Statistical adaptive error correction for a flash memory
2272014022980608/14/14Systems and methods for distributed low density parity check decoding
2282014022994108/14/14Method and controller device for quality of service (qos) caching in a virtualized environment
2292014022995408/14/14Systems and methods for data quality based variable data process scheduling
2302014021902808/07/14Compensation loop for read voltage adaptation
2312014022076008/07/14Integration of shallow trench isolation and through-substrate vias into integrated circuit designs
2322014022307108/07/14Method and system for reducing write latency in a data storage system by using a command-push model
2332014022307208/07/14Tiered caching using single level cell and multi-level cell flash technology
2342014022307508/07/14Physical-to-logical address map to speed up a recycle operation in a solid state drive
2352014022309408/07/14Selective raid protection for cache memory
2362014022310608/07/14Method to throttle rate of data caching for improved i/o performance
2372014022311408/07/14Buffer for managing data samples in a read channel
2382014022313608/07/14Lookup tables utilizing read only memory and combinational logic
2392014022325908/07/14Memory architecture for layered low-density parity-check decoder
2402014022326708/07/14Radix-4 viterbi forward error correction decoding
2412014022327008/07/14Classifying bit errors in transmitted run length limited data
2422014022329508/07/14Geographic based spell check
2432014021133607/31/14Automatic gain control loop adaptation for enhanced nyquist data pattern detection
2442014021133707/31/14Systems and methods for improved short media defect detection
2452014021183907/31/14Receiver having limiter-enhanced data eye openings
2462014021474807/31/14Incremental dfa compilation with single rule granularity
2472014021474907/31/14System and dfa-nfa splitting
2482014021509007/31/14Dfa sub-scans
2492014021512307/31/14Controller-opaque communication with non-volatile memory devices



ARCHIVE: New 2015 2014 2013 2012 2011 2010 2009



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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Lsi Corporation in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Lsi Corporation with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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