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Macronix International Co Ltd
Macronix International Co Ltd a Taiwanese Corporation
Macronix International Co Ltd_20100107
Macronix International Co Ltd_20100121
Macronix International Co Ltd_20131212
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Macronix International Co Ltd patents

Recent patent applications related to Macronix International Co Ltd. Macronix International Co Ltd is listed as an Agent/Assignee. Note: Macronix International Co Ltd may have other listings under different names/spellings. We're not affiliated with Macronix International Co Ltd, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Macronix International Co Ltd-related inventors




Date Macronix International Co Ltd patents (updated weekly) - BOOKMARK this page
11/09/17Memory device including risky mapping table and controlling method thereof
11/09/17Memory structure and manufacturing the same
10/26/17Nested wrap-around memory access
10/12/17Phase change storage device with multiple serially connected storage regions
10/12/17Semiconductor structure having etching stop layer and manufacturing the same
10/12/17Self-aligned multiple patterning semiconductor device fabrication
10/12/17Semiconductor structure having gate replacement and manufacturing the same
10/05/17Electrostatic discharge protection apparatus and applications thereof
10/05/17Electrostatic discharge protection apparatus and applications thereof
10/05/17Method of improving localized wafer shape changes
09/14/17Reading memory cells
09/14/17Phase change memory having a composite memory element
08/17/17Electrostatic discharge device
08/03/17Extended polar codes
07/27/17Generating a transition signal for controlling memory data output
07/20/17Semiconductor memory device and temperature compensation using temperature-resistance-voltage functions
07/20/17Memory device and operating resistive memory cell
07/20/17Integrated circuit device and delay circuit device having varied delay time structure
07/13/17Method and device for reading a memory
07/06/17Sgvc 3d architecture with floating gate device in lateral recesses on sides of conductive strips and insulating strips
06/29/17Semiconductor structure and manufacturing the same
06/22/17Memory structure having material layer made from a transition metal on interlayer dielectric
06/08/17Semiconductor device having output compensation
05/25/17Data allocating method and electric system using the same
05/25/17Erasing method and memory device using the same
05/25/17Reprogramming single bit memory cells
05/04/17Methods of manufacturing semiconductor devices with improved metal gate fill-in for vertical memory cell and devices thereof
04/27/17Three dimensional memory device and fabricating the same
04/20/17I/o bus shared memory system
04/20/17Semiconductor device and zener diode having branch impurity regions
04/20/17Method and device for performing polar codes channel-aware procedure
04/13/17Method and determining status element total with sequentially coupled counting status circuits
04/06/17Method and improving yield for non-volatile memory
03/30/17Memory structure
03/23/17Memory device with flexible data transfer rate interface and method thereof
03/23/17Memory structure
03/23/17Patterned material layer and patterning method
03/16/17Adjustable writing circuit
03/16/17Phase change memory array architecture achieving high write/read speed
03/16/17Isolation structure and fabricating the same
03/16/17Structure and operation for improved gate capacity for 3d nor flash memory
03/16/17Semiconductor device having gate structures and manufacturing method thereof
03/09/17Memory circuit including pre-charging unit, sensing unit, and sink unit and operating same
03/09/17Memory structure
03/09/17Memory device and fabricating the same
03/02/17Electronic device and data exchange method including protocol indicative of modes of operation
03/02/17Cooperative overlay
03/02/17Photo pattern method to increase via etching rate
02/23/17Buffer cache device managing the same and applying system thereof
02/23/17Memory device and manufacturing the same
02/23/17U-shaped vertical thin-channel memory
02/16/17Connector structure and fabricating the same
02/16/17Memory device comprising memory strings penetrating through a stacking structure and electrically contacting with a metal layer and fabricating the same
02/16/17Memory device and manufacturing the same
02/16/17Method for manufacturing a resistive random access memory device
02/09/17Memory with sub-block erase architecture
02/02/17Memory system with uniform decoder and operating same
01/26/17Non-volatile memory device for reducing bit line recovery time
01/26/17Memory device and fabricating the same
01/26/17Memory device and manufacturing the same
01/19/17Structure with conductive plug and metod of forming the same
01/19/17Capacitor with 3d nand memory
01/12/17Latch-up test device and method
01/12/17Method and system for providing an improved wafer transport system
01/12/17Conductive plug and forming the same
Patent Packs
01/12/17Memory device and forming the same
01/05/17High voltage junction field effect transistor
12/22/16Phase change memory with inter-granular switching
12/22/16Resistance random access memory, operating method thereof and operating system thereof
12/22/16Memory device having only the top poly cut
12/22/16Non-volatile memory device having multiple string select lines
12/22/16Photo pattern method to increase via etching rate
12/22/16Memory device and fabricating the same
12/22/16Gasbge phase change memory materials
12/15/16System and chemical mechanical planarization process prediction and optimization
12/15/16Stacked bit line dual word line nonvolatile memory
12/15/16Capacitor with 3d nand memory
12/15/16Semiconductor device having buried layer
12/08/16Semiconductor device and fabricating the same
12/08/16Gate-all-around vertical gate memory structures and semiconductor devices, and methods of fabricating gate-all-around vertical gate memory structures and semiconductor devices thereof
Patent Packs
12/08/16Semiconductor device and fabricating the same
12/01/16Test pattern structure for monitoring semiconductor fabrication process
12/01/16Semiconductor device and manufacturing the same
12/01/16Semiconductor device
12/01/16Biased plasma oxidation rounding structure
11/24/16Contact structure for thin film semiconductor
11/17/16Verify scheme for reram
11/17/16Memory device and fabricating the same
11/17/16Device and determining electrical characteristics for ellipse gate-all-around flash memory
11/10/16Method, apparatus, and storage medium for writing data
11/10/16Memory device and operation method
11/10/16Semiconductor device and fabricating the same
11/10/16Memory structure having array-under-periphery structure
11/10/163d voltage switching transistors for 3d vertical gate memory array
11/03/16Current mirror with tunable mirror ratio
10/27/16Method and system for detecting defects of wafer by wafer sort
10/27/16Memory device and reading method thereof
10/27/16Semiconductor device with a p-n junction for reduced charge leakage and manufacturing the same
10/20/16Method for programming memory device and associated memory device
10/20/16Method and improving data retention and read-performance of a non-volatile memory device
10/20/16Semiconductor memory device bit line transistor with discrete gate
10/20/16Semiconductor structure and manufacturing the same
10/20/16Boost circuit
10/13/16Memory device and operating same
10/13/16Method, electronic device and controller for recovering array of memory cells
10/13/16Memory device and associated erase method
10/13/16Semiconductor device and fabricating the same
10/13/16Semiconductor device and fabricating the same
10/13/16Semiconductor device having buried region and fabricating same
10/06/16Memory device and erasing method thereof
Social Network Patent Pack
10/06/16Determining contact edge roughness of a contact hole etched in a wafer
10/06/16Length-compatible extended polar codes
09/29/16Page erase in flash memory
09/29/16Semiconductor package structure and manufacturing the same
09/29/16Memory device and manufacturing the same
09/29/16Method of fabricating three-dimensional gate-all-around vertical gate structures and semiconductor devices, and three-dimensional gate-all-around vertical gate structures and semiconductor devices thereof
09/29/16Memory device and manufacturing the same
09/15/163d memory structure and manufacturing the same
09/15/16Electronic device, non-volatile memorty device, and programming method
09/15/16Forced-bias method in sub-block erase
Patent Packs
09/15/16Twisted array design for high speed vertical channel 3d nand memory
09/15/16Semiconductor device having metal layer and fabricating same
09/08/16Memory repairing method and memory device applying the same
09/08/16Separated lower select line in 3d nand architecture
09/08/16Vertical thin-channel memory
09/08/16U-shaped vertical thin-channel memory
09/08/16Damascene process of rram top electrodes
08/25/16And-type sgvc architecture for 3d nand flash
08/25/16Semiconductor devices and fabrication methods with improved word line resistance and reduced salicide bridge formation
08/25/16Semiconductor device and manufacturing method thereof
08/25/16Semiconductor device and manufacturing method thereof
08/18/16Semiconductor structure and manufacturing the same
08/18/163d nand memory with decoder and local word line drivers
08/18/16Memory device and fabricating the same
08/18/16Semiconductor device having buried layer
08/18/16Memory device and fabricating the same
08/18/16Electrostatic discharge protection device
08/11/16Memory device and operating same
08/04/16Writing method and reading phase change memory
08/04/16Stress trim and modified ispp procedures for pcm
08/04/16Method and healing phase change memory devices
08/04/16Method of fabricating memory structure
08/04/16Resistive memory device with ring-shaped metal oxide on top surfaces of ring-shaped metal layer and barrier layer
07/28/16Memory operating method and associated memory device
07/28/16Memory device and fabricating the same
07/28/16Rram process with roughness tuning technology
07/28/16Memory structure and manufacturing the same
07/28/16Capped contact structure with variable adhesion layer thickness
07/21/16Contact process and contact structure for semiconductor device
07/14/16Circuit driving
Patent Packs
07/14/16Power source for memory circuitry
07/14/16Power source for memory circuitry
07/14/16Memory device and operating method thereof for reducing interference between memory cells
07/14/16Three-dimensional semiconductor device and manufacturing the same
07/14/16Method of fabricating three-dimensional semiconductor devices, and three-dimensional semiconductor devices thereof
07/14/16Charge pump circuit and controlling same
07/14/16Decode switch and controlling decode switch
07/14/16Power drop detector circuit and operating same
07/07/16Patterning method
07/07/16Memory device and fabricating the same
07/07/16Vertical memory devices and related methods of manufacture
07/07/16Memory device and manufacturing the same
06/30/16Layout pattern and photomask including the same
06/30/16Patterning method and semiconductor structure
06/30/16Semiconductor device and manufacturing the same
06/30/16Semiconductor device and manufacturing the same
06/30/16Photomask and semiconductor structure
06/30/163d memory process and structures
06/30/16Semiconductor device and fabricating the same
06/30/16Active device and high voltage-semiconductor device with the same
Social Network Patent Pack
06/30/16Memory device and manufacturing the same
06/23/16Memory operation latency control
06/23/16Three dimensional stacked semiconductor structure and manufacturing the same
06/23/16Memory architecture of array with single gate memory devices
06/16/16Memory repair redundancy
06/16/16Memory device and data erasing method thereof
06/16/16High aspect ratio structure
06/16/16Forming memory using doped oxide
06/09/16Protection circuit and input circuit suitable for integrated circuit
06/09/16Clock integrated circuit
06/02/16Reduced size semiconductor device and manufacture thereof
06/02/16Memory system and a data managing method thereof
06/02/16Data processing method and system with application-level information awareness
06/02/16Word line driver circuitry and compact memory using same
06/02/16Memory device and operating the same
06/02/16Read leveling method and memory device using the same
06/02/16Semiconductor wafer holder and wafer carrying tool using the same
05/26/16Memory orprating method and memory device using the same
05/26/16Page buffer circuit and operating same
05/26/16Variant operation sequences for multibit memory
Social Network Patent Pack
05/26/16Semiconductor structure having field plates over resurf regions in semiconductor substrate
05/19/16Device and detecting controller signal errors in flash memory
05/19/16Electrostatic discharge protection circuit, structure and making the same
05/19/16Vertical and 3d memory devices and methods of manufacturing the same
05/19/16Three-dimensional memory and manufacturing the same
05/19/16Active device and semiconductor device with the same
05/12/16Contact structure for nand based non-volatile memory device and a manufacture
05/12/16Semiconductor device and fabricating the same
05/05/16Inspection of inconsistencies in and on semiconductor devices and structures
05/05/16Threshold voltage grouping of memory cells in same threshold voltage range
05/05/16Semiconductor device
04/28/16Monitoring data error status in a memory
04/21/16Inspection contact by die to database
04/21/16Semiconductor structure and manufacturing the same
04/21/16Lc module layout arrangement for contact opening etch windows
04/14/16Memory page buffer
04/07/16Integrated circuit with independent programmability
04/07/16Program verify with multiple sensing
04/07/16Line layout and spacer self-aligned quadruple patterning for the same
04/07/16Three dimensional stacked semiconductor structure and manufacturing the same
03/24/16Multi-layer memory array and manufacturing the same
03/24/16Health management of non-volatile memory
03/24/16Method and device for command processing
03/24/16Memory device and operating method thereof
03/24/16Memory architecture of thin film 3d array
03/24/16Method for disconnecting polysilicon stringers during plasma etching
03/24/16Patterning method and semiconductor structure
03/24/16Method for fabricating memory device
03/24/16Semiconductor memory array with air gaps between adjacent gate structures and manufacturing the same
03/24/16Semiconductor device
Social Network Patent Pack
03/24/16Semiconductor device and fabricating same
03/17/16Memory utilizing bundle-level status values and bundle status circuits
03/17/16Word line repair for 3d vertical channel memory
03/17/16Semiconductor structure
03/10/16Semiconductor device and fabricating the same
03/10/16High voltage device and manufacturing the same
03/10/16Sense amplifier with improved margin
03/03/16Mask monitor mark and marking the mark
03/03/16Circuit and adjusting select gate voltage of non-volatile memory
03/03/16Test memory
03/03/16Method of forming semiconductor device
03/03/16Semiconductor structure and manufacturing the same
03/03/16Semiconductor device and manufacturing the same
03/03/16High voltage semiconductor device
03/03/16Memory device and fabricating the same
03/03/16Semiconductor structure
03/03/16Circuit for voltage detection and protection and operating method thereof
02/25/163d nand nonvolatile memory with staggered vertical gates
02/18/16Scanner and performing exposure process on wafer
02/18/16Method and adjusting drain bias of a memory cell with addressed and neighbor bits
02/18/16Sub-block erase
02/18/16Stabilization of output timing delay
02/11/16Die structure, contact test structure, and contact testing method utilizing the contact test structure
02/11/16Method and device for monitoring data error status in a memory
02/11/16Level shifter and decoder for memory
02/11/16Low latency memory erase suspend operation
02/11/16Semiconductor device including high-voltage diode
02/04/16Transistor and circuit using same
02/04/16Systems and methods for trimming control transistors for 3d nand flash







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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