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Macronix International Co Ltd
Macronix International Co Ltd a Taiwanese Corporation
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Macronix International Co Ltd patents


Recent patent applications related to Macronix International Co Ltd. Macronix International Co Ltd is listed as an Agent/Assignee. Note: Macronix International Co Ltd may have other listings under different names/spellings. We're not affiliated with Macronix International Co Ltd, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Macronix International Co Ltd-related inventors


 new patent  3d phase change memory with high endurance

A plurality of memory cells in a 3D cross-point array with improved endurance is disclosed. Each memory cell, disposed between first and second conductors, includes a switch in series with a pillar of phase change material. The pillar has a Te-rich material at one end proximal to the second conductor,... Macronix International Co Ltd

Circuit and adjusting select gate voltage of non-volatile memory during erasure of memory cells based on a well voltage

A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, and an adjustment unit. There is a capacitive coupling between the well and the select gate. The adjustment unit generates a driving voltage for the select gate based... Macronix International Co Ltd

Memory device and operating method thereof

A memory device and an operating method thereof are provided. The memory device includes a first memory array, a first row decoder, a first column decoder, a second memory array, a second row decoder and a second column decoder. The first memory array and the second memory array are different... Macronix International Co Ltd

Memory and operating a memory with interruptible command sequence

A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and then to proceed directly to receive and decode a second command sequence, such as a read sequence, without latency associated, completing the first command sequence.... Macronix International Co Ltd

Three-dimensional semiconductor device

A 3D semiconductor device is provided, including several memory layers vertically stacked on a substrate, an upper selection layer formed on the memory layers, a lower selection layer formed above the substrate, several strings formed vertically to the memory layers and the substrate, several bit lines parallel to each other... Macronix International Co Ltd

Memory system and memory management method thereof

A memory management method includes: providing a hybrid memory comprising a first type memory and a second type memory; providing an inactive list and a read active list for recording in-used pages on the first type memory; providing a write active list for recording in-used pages on the second type... Macronix International Co Ltd

Resistive memory fabricating the same and applications thereof

A resistive memory includes a semiconductor substrate, a dielectric layer, an insulating layer and a metal electrode layer. The semiconductor substrate has a top surface and a recess extending downwards into the semiconductor substrate from the top surface. The dielectric layer is disposed on the semiconductor substrate and has a... Macronix International Co Ltd

Memory device including risky mapping table and controlling method thereof

A memory device includes a first storage unit storing an address mapping table, and a control unit coupled to the first storage unit and including a second storage unit storing a risky mapping table and a cached mapping table. The control unit is configured to: write data into the first... Macronix International Co Ltd

Memory structure and manufacturing the same

A memory structure and a manufacturing method for the same are disclosed. The memory structure comprises memory segments. Each of the memory segments comprises a memory array region, a memory selecting region adjacent to the memory array region, a semiconductor gate electrode, a semiconductor channel connecting to the semiconductor gate... Macronix International Co Ltd

Nested wrap-around memory access

A nested wrap-around technology includes an address counter and associated logic for generating addresses to perform a nested wrap-around access operation. The nested wrap-around access operation may be a read or a write operation. A wrap-around section length and a wrap-around count define a wrap-around block. A wrap starting address,... Macronix International Co Ltd

Phase change storage device with multiple serially connected storage regions

A phase change storage device, Integrated Circuit (IC) chip including the devices and method of manufacturing IC chips with the devices. The device includes a phase change storage region with multiple phase change regions, e.g., two (2), of different phase change material serially-connected between said program/read line and a select... Macronix International Co Ltd

Semiconductor structure having etching stop layer and manufacturing the same

A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a stack structure, an etching stop layer, and a conductive structure. The stack structure includes a plurality of conductive layers and a plurality of insulating layers stacked interlacedly. The etching stop layer is formed... Macronix International Co Ltd

Self-aligned multiple patterning semiconductor device fabrication

Various embodiments provide a self-merged profile (SMP) method for fabricating a semiconductor device and a device fabricated using an SMP method. In an example embodiment, a semiconductor device is provided. The example semiconductor device comprises (a) a plurality of conductive lines; (b) a plurality of conductive pads; (c) a plurality... Macronix International Co Ltd

Semiconductor structure having gate replacement and manufacturing the same

A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first stacked structures and two second stacked structures disposed on the substrate. Each of the first stacked structures includes alternately stacked metal layers and oxide layers. Each of the second stacked structures includes alternately stacked silicon... Macronix International Co Ltd

Electrostatic discharge protection apparatus and applications thereof

An ESD protection apparatus includes a semiconductor substrate, a first well, a second well, a first doping region, a second doping region, a third doping region and a fourth doping region. The first well and the second well respectively having a first conductivity and a second conductivity are disposed in... Macronix International Co Ltd

Electrostatic discharge protection apparatus and applications thereof

An ESD protection apparatus includes a semiconductor substrate, a first gate structure, a first doping region, a second doping region and a third doping region. The semiconductor substrate has a doping well with a first conductivity one end of which is grounded. The first gate structure is disposed on the... Macronix International Co Ltd

Method of improving localized wafer shape changes

A method of manufacturing an integrated circuit including forming trenches into the surface of a crystalline wafer and the trenches extending along a <100> lattice direction is disclosed. Such wafer can experience less deformation due to less stress induced when the trenches are filled using a spin-on dielectric material. Thus,... Macronix International Co Ltd

Reading memory cells

A first read operation is performed using a first voltage level to read data from a memory array. An instant bit count corresponding to a number of bits in the data read from the memory array is determined. A recorded bit count corresponding to a number of bits in the... Macronix International Co Ltd

Phase change memory having a composite memory element

A phase change memory device with a composite memory element includes first and second layers of memory materials, and the composite memory element has a basis phase change material, such as a chalcogenide, and one or more additives, where the first layer of memory material is formed using oxygen-free atmosphere... Macronix International Co Ltd

Electrostatic discharge device

An electrostatic discharge device includes a power clamping circuit and an isolation circuit. The power clamping circuit includes a first Zener diode and a second Zener diode. A cathode of the first Zener diode is coupled to a first power supply line. An anode of the first Zener diode is... Macronix International Co Ltd

Extended polar codes

A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N−K frozen bit-channels. The additional frozen part has q additional... Macronix International Co Ltd

Generating a transition signal for controlling memory data output

A memory device comprises an output buffer and a control circuit. The control circuit is configured to receive a system clock signal at an input of the control circuit. The control circuit is configured to generate a data transition signal based on the system clock signal. The control circuit is... Macronix International Co Ltd

Semiconductor memory device and temperature compensation using temperature-resistance-voltage functions

A semiconductor device includes: a physical parameter sensing circuit configured to sense a variation of a physical parameter; an applying parameter generating circuit coupled to the physical parameter sensing circuit, configured to adjust an applying parameter from the variation of the physical parameter based on a transfer function which defines... Macronix International Co Ltd

Memory device and operating resistive memory cell

A memory device and an operating method for a resistive memory cell are provided. The memory device includes the resistive memory cell. The resistive memory cell includes a first electrode, a second electrode and a memory film between the first electrode and the second electrode. The first electrode includes a... Macronix International Co Ltd

Integrated circuit device and delay circuit device having varied delay time structure

An electronic circuit includes a forward delay circuit having a plurality of first stages. Each of the first stages is configured to introduce a delay time, the delay times of the first stages being varied. The electronic circuit further includes a control circuit coupled to the forward delay circuit, and... Macronix International Co Ltd

Method and device for reading a memory

A method for reading data from memory cells of a target word line in a semiconductor memory includes determining a disturbance status of the target word line. The disturbance status reflects a disturbance of a neighboring word line on the memory cells of the target word line. The method further... Macronix International Co Ltd

Sgvc 3d architecture with floating gate device in lateral recesses on sides of conductive strips and insulating strips

A memory device is provided that includes a plurality of memory cells. The memory device includes a plurality of stacks of conductive strips separated by insulating strips. Data storage structures including floating gates are disposed along the conductive strips in the stacks. Vertical channel films are disposed on sidewalls of... Macronix International Co Ltd

Semiconductor structure and manufacturing the same

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a stack including first conductive layers and first dielectric layers, a second conductive layer formed on the stack, openings through the second conductive layer and the stack, and through structures formed in the openings,... Macronix International Co Ltd

Memory structure having material layer made from a transition metal on interlayer dielectric

A memory structure and a manufacturing method for the same are disclosed. The memory structure comprises a lower electrode, an upper insulating layer, a material layer, a dielectric film, and an upper electrode. The upper insulating layer is on the lower electrode. The material layer is on the upper insulating... Macronix International Co Ltd

Semiconductor device having output compensation

A semiconductor device includes an amplifier, a pass transistor, a compensation circuit, and a bias voltage generator. The amplifier has an output terminal. The pass transistor has a gate and an output terminal. The gate is coupled to the output terminal of the amplifier, and the output terminal of the... Macronix International Co Ltd

Data allocating method and electric system using the same

A data allocating method includes steps of: determining whether data to be written into a physical memory block is hot data or cold data; when the data is hot data, according to a hot data allocating order, searching at least one first empty sub-block from the physical memory block to... Macronix International Co Ltd

Erasing method and memory device using the same

An erasing method and a memory device are provided. The memory device includes a plurality of memory blocks. Each of the memory blocks has n sub-blocks. The erasing method includes the following steps. A first erase region is selected from a first memory block of the memory blocks, and the... Macronix International Co Ltd

Reprogramming single bit memory cells

A method to operate a single bit per cell memory comprises erasing a group of memory cells establishing a first logical value by setting threshold voltages in a first range of threshold voltages. First writing, after said erasing, includes programming first selected memory cells to establish a second logical value... Macronix International Co Ltd

Methods of manufacturing semiconductor devices with improved metal gate fill-in for vertical memory cell and devices thereof

Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. The methods may include two or more nitride removal steps during formation of gate layers in vertical memory cells. The two or more nitride removal steps may allow for wider gate layers increasing the gate fill-in,... Macronix International Co Ltd

Three dimensional memory device and fabricating the same

A 3D semiconductor memory device includes a semiconductor substrate, a source line, a gate line and a plurality of memory cells connected in series. The semiconductor substrate has a protruding portion. The source line is disposed in the semiconductor substrate and partially extending below the protruding portion. The gate line... Macronix International Co Ltd

04/20/17 / #20170109297

I/o bus shared memory system

A memory system has a plurality of memory devices coupled with a hub in discrete and shared port arrangements. A plurality of bus lines connect the plurality of memory devices to the hub, including a first subset of bus lines connected in a point-to-point configuration between the hub and a... Macronix International Co Ltd

04/20/17 / #20170110597

Semiconductor device and zener diode having branch impurity regions

A semiconductor device includes a substrate, a well region of a first-conductivity type disposed in the substrate, a first impurity region of a second-conductivity type and having a plurality of branches disposed in the well region, a second impurity region of the first-conductivity type and having a plurality of branches,... Macronix International Co Ltd

04/20/17 / #20170111060

Method and device for performing polar codes channel-aware procedure

A method and a device for performing a polar codes channel-aware procedure are provided. A plurality of bit-channels have a polar code construction which is dynamic. The method includes the following steps. A plurality of reliability indices of some of the bit-channels are ranked. Whether an updating condition is satisfied... Macronix International Co Ltd

04/13/17 / #20170102977

Method and determining status element total with sequentially coupled counting status circuits

Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in... Macronix International Co Ltd

04/06/17 / #20170098478

Method and improving yield for non-volatile memory

A method, apparatus and computer program product are provided in order to test word line failure of a non-volatile memory device. An example of the method includes performing a failure screening of the non-volatile memory device, wherein the non-volatile memory device comprises one or more word lines; identifying a point... Macronix International Co Ltd

03/30/17 / #20170092632

Memory structure

A memory structure is provided. The memory structure includes a first chip. The first chip has an array region and a periphery region. The first chip includes a first stack and a plurality of through structures. The first stack is disposed in the periphery region. The first stack includes alternately... Macronix International Co Ltd

03/23/17 / #20170083439

Memory device with flexible data transfer rate interface and method thereof

A memory device includes an input/output interface configured to receive and output signals. The input/output interface is configured to receive a memory address to be accessed and data sequence information within a clock cycle or at a rising or falling edge of a clock cycle. The data sequence information specifies... Macronix International Co Ltd

03/23/17 / #20170084310

Memory structure

A memory structure includes N array regions and N page buffers coupled to the N array regions, respectively. N is an integer≧2. Each of the N array regions includes a 3D array of a plurality of memory cells. The memory cells have a lateral distance d between two adjacent memory... Macronix International Co Ltd

03/23/17 / #20170084597

Patterned material layer and patterning method

A structure of a patterned material layer including separate patterns arranged in rows and columns is described. The separate patterns in at least one row including the outmost row each have a larger dimension in the column direction than the separate patterns in the other rows. The separate patterns in... Macronix International Co Ltd

03/16/17 / #20170076795

Adjustable writing circuit

A write pulse driver is provided. The write pulse driver includes a parameter storage, storing a set of parameters specifying characteristics of a write pulse, and driver circuitry configured to generate the write pulse on an output node, the write pulse having a leading edge, a trailing edge and an... Macronix International Co Ltd

03/16/17 / #20170076797

Phase change memory array architecture achieving high write/read speed

A memory configured to have data read therefrom is provided. The memory includes a data port including B transmitters disposed in parallel and for transferring data on both rising and falling edges of a clock, a first memory including a first data bus including N lines on which N bits... Macronix International Co Ltd

03/16/17 / #20170076976

Isolation structure and fabricating the same

An isolation structure and a method of fabricating the same are provided. The isolation structure includes a buffer layer and an encapsulation layer. The buffer layer is located in a trench of a substrate. The encapsulation layer is located in the trench and encapsulates around the buffer layer, wherein the... Macronix International Co Ltd

03/16/17 / #20170077118

Structure and operation for improved gate capacity for 3d nor flash memory

Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive... Macronix International Co Ltd

03/16/17 / #20170077293

Semiconductor device having gate structures and manufacturing method thereof

A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a high-voltage doped region having the first conductivity type and disposed in the high-voltage well, a drain region disposed in the high-voltage well and spaced apart... Macronix International Co Ltd

03/09/17 / #20170069360

Memory circuit including pre-charging unit, sensing unit, and sink unit and operating same

A memory circuit includes a pre-charging unit configured to charge a metal bit line during a pre-charging period, a sensing unit configured to sense a status of a memory cell coupled to the metal bit line during the pre-charging period, and a sink circuit configured to provide a sink current... Macronix International Co Ltd

03/09/17 / #20170069567

Memory structure

A memory structure is provided. The memory structure comprises M array regions and N contact regions. M is an integer ≧2. N is an integer ≧M. Each array region is coupled to at least one contact region. Each contact region comprises a stair structure and a plurality of contacts. The... Macronix International Co Ltd

03/09/17 / #20170069762

Memory device and fabricating the same

A memory device and a method for fabricating the same are provided. A memory device includes a tunneling dielectric layer located on a substrate. The floating gate includes a first doped portion on the tunneling dielectric layer and a second doped portion located on the first doped portion. The first... Macronix International Co Ltd

03/02/17 / #20170060785

Electronic device and data exchange method including protocol indicative of modes of operation

An electronic device includes a processor coupled to a memory device, through a data bus to receive and transmit bits on the data bus. The processor is configured to transmit a message including a first bit indicative of controlling the data bus, address bits indicative of an address identifying the... Macronix International Co Ltd

03/02/17 / #20170060793

Cooperative overlay

An embedded system includes a program to be executed. The program is divided into overlays. The embedded system includes a processor configured to request one of the overlays. The requested overlay includes a segment of the program to be executed by the processor. The embedded system also includes a first... Macronix International Co Ltd

03/02/17 / #20170062270

Photo pattern method to increase via etching rate

Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between... Macronix International Co Ltd

02/23/17 / #20170052899

Buffer cache device managing the same and applying system thereof

A buffer cache device used to get at least one data from at least one application is provided, wherein the buffer cache device includes a first-level cache memory, a second-level cache memory and a controller. The first-level cache memory is used to receive and store the data. The second-level cache... Macronix International Co Ltd

02/23/17 / #20170053867

Memory device and manufacturing the same

Provided is a memory device including a plurality of first conductive line layers, a plurality of support structures, and a charge storage layer. Each of the first conductive line layers extends along a plane defined by a first direction and a second direction. Each of the first conductive line layers... Macronix International Co Ltd

02/23/17 / #20170053934

U-shaped vertical thin-channel memory

A memory device, which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips, including even stacks and odd stacks having sidewalls. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls... Macronix International Co Ltd

02/16/17 / #20170047245

Connector structure and fabricating the same

A connector structure for electrically contacting with a conductive layer disposed on a substrate is provided. The connector structure comprises a conductive connecting element disposed on the substrate. The conductive connecting element comprises a connecting part and an extending part. The connecting part has a bottom portion electrically contacting with... Macronix International Co Ltd

02/16/17 / #20170047289

Memory device comprising memory strings penetrating through a stacking structure and electrically contacting with a metal layer and fabricating the same

A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a ground layer disposed on the substrate, a stacking structure having a plurality of conductive layers and a plurality of insulating layers alternatively stacked on the ground layer and a plurality of... Macronix International Co Ltd

02/16/17 / #20170047377

Memory device and manufacturing the same

A memory device is provided. The memory device includes a substrate, a plurality of alternately stacked semiconductor layers and oxide layers disposed on the substrate, at least one through hole penetrating the stacked semiconductor layers and oxide layers, and an electrode layer disposed in the through hole. Each of the... Macronix International Co Ltd

02/16/17 / #20170047514

Method for manufacturing a resistive random access memory device

A method for manufacturing a resistive memory device is disclosed and comprises following steps. Firstly, a bottom electrode is formed over a substrate. Next, an oxidation process is performed to the bottom electrode to form a metal oxide layer, wherein a hydrogen plasma and an oxygen plasma are provided during... Macronix International Co Ltd

02/09/17 / #20170040061

Memory with sub-block erase architecture

A memory device has a divided reference line structure which supports sub-block erase in NAND memory including a plurality of blocks. Each block in the plurality of blocks is coupled to a set of Y reference lines, where Y is two or more. Each block in the plurality of blocks... Macronix International Co Ltd

02/02/17 / #20170032826

Memory system with uniform decoder and operating same

A memory system includes a memory array including a plurality of memory cells, and an encoder operatively coupled to the memory array, for encoding an original data element to be programmed into the memory cells into a uniform data element in which the number of “0”s approximately equals the number... Macronix International Co Ltd

01/26/17 / #20170025179

Non-volatile memory device for reducing bit line recovery time

Methods and apparatuses are contemplated herein for reducing bit-line recovery time of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of non-volatile memory cells, including a plurality of blocks, each block comprising a plurality of NAND strings, each of the NAND strings coupled... Macronix International Co Ltd

Patent Packs
01/26/17 / #20170025428

Memory device and fabricating the same

A memory device includes a semiconductor substrate, an isolation layer disposed on the semiconductor substrate, a first conductive layer disposed on the isolation layer, at least one contact plug passing through the isolation layer and electrically contacting the semiconductor substrate with the first conductive layer, a plurality of insulating layers... Macronix International Co Ltd

01/26/17 / #20170025473

Memory device and manufacturing the same

A memory device having an array area and a periphery area is provided. The memory device includes a substrate, an isolation layer formed in the substrate, a first doped region formed on the isolation layer in the array area, a second doped region formed on the first doped region, a... Macronix International Co Ltd

01/19/17 / #20170018500

Structure with conductive plug and metod of forming the same

Provided is a structure with a conductive plug including a substrate, a first dielectric layer, an etch stop layer, a second dielectric layer, a conductive plug and a liner. The substrate has a conductive region therein. The first dielectric layer, the etch stop layer and the second dielectric layer are... Macronix International Co Ltd

01/19/17 / #20170018570

Capacitor with 3d nand memory

An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality... Macronix International Co Ltd

01/12/17 / #20170010321

Latch-up test device and method

Latch-up test device and method are provided, and the method includes following steps. A set operation is performed for setting a basic test value according to a test range and setting a trigger pulse and a predetermined error value by the basic test value. A test on a test chip... Macronix International Co Ltd

01/12/17 / #20170010605

Method and system for providing an improved wafer transport system

A method of controlling a delivery to a working station comprises processing first carrier of wafers at a working station for a processing step, checking location of a second carrier at a predetermined checking time to obtain a checking result. The predetermined checking time is a predetermined period of time... Macronix International Co Ltd

01/12/17 / #20170011960

Conductive plug and forming the same

A method of forming a conductive plug is disclosed. A material layer having at least one opening is provided on a substrate. A first conductive layer is deposited in the opening, wherein the first conductive layer does not completely fill up the opening. A second conductive layer is deposited on... Macronix International Co Ltd

01/12/17 / #20170011995

Memory device and forming the same

Provided is a memory device including a plurality of bit line layers and a plurality of supporting structures. Each bit line layer extends in a plane defined by a first direction and a second direction and has a plurality of bit lines extending along the first direction. Each bit line... Macronix International Co Ltd

01/05/17 / #20170005205

High voltage junction field effect transistor

Provided is a semiconductor device, including: a substrate, a well region of a first conductivity type, a field region of a second conductivity type, a first doped region of the first conductivity type, and a second doped region of the second conductivity type. The well region is located in the... Macronix International Co Ltd








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