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Mentor Graphics Corporation patents

Recent patent applications related to Mentor Graphics Corporation. Mentor Graphics Corporation is listed as an Agent/Assignee. Note: Mentor Graphics Corporation may have other listings under different names/spellings. We're not affiliated with Mentor Graphics Corporation, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Mentor Graphics Corporation-related inventors




Date Mentor Graphics Corporation patents (updated weekly) - BOOKMARK this page
04/20/17Simultaneous retargeting of layout features based on process window simulation
04/13/17Hybrid compilation for fpga prototyping
04/13/17Generating root cause candidates for yield analysis
03/30/17Subtractive design for heat sink improvement
03/02/17Secure protocol for chip authentication
02/23/17Selective per-cycle masking of scan chains for system level test
02/23/17Multi-fpga prototyping of an asic circuit
01/12/17Physically-aware circuit design partitioning
01/05/17Integrated circuit layout design methodology with process variation bands
12/22/16Layout synthesis of a three-dimensional mechanical system design
12/22/16Statistical channel analysis with correlated multiple-level input modulation
12/15/16Pattern optical similarity determination
12/08/16Coverage data interchange
11/24/16Visualization of analysis process parameters for layout-based checks
11/17/16Memory corruption protection by tracing memory
11/10/16Selectively loading design data for logical equivalency check
11/03/16Multi-stage test response compactors
10/06/16Guiding patterns optimization for directed self-assembly
10/06/16Leakage reduction using stress-enhancing filler cells
10/06/16Signal integrity delay utilizing a window bump-based aggressor alignment scheme
10/06/16Directed self-assembly-aware layout decomposition for multiple patterning
10/06/16Optical proximity correction for directed-self-assembly guiding patterns
09/29/16Fragmentation point and simulation site adjustment for resolution enhancement techniques
09/15/16Modelling and simulation method
09/01/16Test-per-clock based on dynamically-partitioned reconfigurable scan chains
08/25/16Deterministic built-in self-test
08/25/16Dynamic design partitioning for diagnosis
08/25/16Code coverage reconstruction
08/18/16Source optimization for image fidelity and throughput
08/18/16Automatic calibration of thermal models
08/11/16Class object handle tracking
08/04/16Harness sub-assembly rationalization
08/04/16Hiding compilation latency
08/04/16Harness design change record and replay
08/04/16Additive design of heat sinks
08/04/16Loop handling in a word-level netlist
08/04/16Protocol probes
08/04/16Logical equivalency check with dynamic mode change
08/04/16System-level analysis with transactions from protocol probes
07/28/16Domain bounding for symmetric multiprocessing systems
07/21/16Identification of high impedance nodes in a circuit design
07/14/16Multi-mode multi-corner clocktree synthesis
07/14/16Mask creation with hierarchy management using cover cells
07/07/16Power management with hardware virtualization
07/07/16Device for monitoring the proper functioning of a transmission path, particularly of a camera
06/23/16Take rate determination
06/16/16Constrained flattening of design data
06/16/16Circuit design layout in multiple synchronous representations
06/16/16Three-dimensional composite solid component modeling
06/09/16Automated analyzing a board having a plurality of fpga components
06/02/16Resource mapping in a hardware emulation environment
05/26/16Execution of complex recursive algorithms
05/26/16Handling blind statements in mixed language environments
05/19/16Manufacture of non-rectilinear features
05/19/16Modeling photoresist shrinkage effects in lithography
05/12/16Generalization of shot definitions for mask and wafer writing tools
05/05/16Chip-scale electrothermal analysis
05/05/16Measure of analysis performed in property checking
04/28/16Electrostatic damage protection circuitry verification
04/21/16Test point insertion for low test pattern counts
04/07/16Hierarchical fill in a design layout
03/03/16Reset verification
03/03/16Connectivity-aware layout data reduction for design verification
02/25/16Design and analysis of silicon photonics array wave guides
02/25/16Verification of photonic integrated circuits
Patent Packs
01/21/16Clock tree synthesis graphical user interface
01/07/16Continuous application and decompression of test patterns and selective compaction of test responses
01/07/16Statistical channel analysis with correlated input patterns
12/03/15Prelinked embedding
12/03/15System design management
12/03/15System design management
12/03/15System design management
11/26/15Non-intrusive software verification
11/12/15Low power testing based on dynamic grouping of scan
11/12/15Timing-aware test generation and fault simulation
10/22/15Expanded canonical forms of layout patterns
10/15/15Pattern optical similarity determination
09/24/15Switching activity reduction through retiming
09/10/15Isometric test compression with low toggling activity
09/03/15Scan cell selection for partial scan designs
Patent Packs
08/20/15Cell internal defect diagnosis
08/13/15Generating test sets for diagnosing scan chain failures
08/13/15Generating guiding patterns for directed self-assembly
08/06/15Streaming, at-speed debug and validation architecture
08/06/15Selective power state table composition
07/30/15Tag based system for leveraging design data
07/30/15Logic equivalency check using vector stream event simulation
07/30/15Regression nearest neighbor analysis for statistical functional coverage
07/30/15Distributed state and data functional coverage
07/30/15Distributed state and data functional coverage
07/30/15Regression signature for statistical functional coverage
07/30/15Tag based system for leveraging design data
07/30/15Timing driven clock tree synthesis
07/30/15Social electronic design automation
07/30/15Metastability glitch detection
07/30/15Optical physical uncloneable function
07/09/15Trace routing according to freeform sketches
07/02/15Selective parasitic extraction
06/25/15Hardware simulation controller, functional verification
06/18/15Compiler for closed-loop 1xn vlsi design
06/18/15Coherent state among multiple simulation models in an eda simulation environment
06/11/15On-chip comparison and response collection tools and techniques
06/11/15High-frequency vlsi interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate
06/11/15Nor-or decoder
06/04/15Dynamic shift for test pattern compression
05/28/15Tag based system for leveraging design data
05/28/15Channel sharing for testing circuits having non-identical cores
05/28/15Third party component debugging for integrated circuit design
05/21/15Grouping layout features for directed self assembly
05/21/15Determination of electromigration features
Social Network Patent Pack
05/21/15Determination of electromigration susceptibility based on hydrostatic stress analysis
05/21/15Generating guiding patterns for directed self-assembly
05/14/15Speeding up defect diagnosis techniques
05/14/15Canonical forms of layout patterns
04/09/15Adaptive clock management in emulation
03/05/15Controller area network (can) worst-case message latency with priority inversion
03/05/15Bandwidth control in a controller area network (can)
03/05/15Integrated circuit layout design methodology with process variation bands
03/05/15Logic-driven layout pattern analysis
03/05/15Rapid expression coverage
Patent Packs
03/05/15Layout content analysis for source mask optimization acceleration
02/26/15Programmable pattern aware voltage analysis
02/12/15Dynamic control of design clock generation in emulation
02/05/15Identification of power sensitive scan cells
01/29/15Clustering for processing of circuit design data
01/29/15Clustering for processing of circuit design data
01/22/15Hierarchical verification of clock domain crossings
12/18/14Test-per-clock based on dynamically-partitioned reconfigurable scan chains
12/18/14Scan chain configuration for test-per-clock based on circuit topology
12/18/14Fault-driven scan chain configuration for test-per-clock
12/18/14Scan chain stitching for test-per-clock
12/18/14Test generation for test-per-clock
11/27/14Method and circuit of pulse-vanishing test
11/13/14Modular platform for integrated circuit design analysis and verification
11/06/14Identification of fluid flow bottlenecks
10/30/14Cloud services platform
10/23/14Cloud services platform
10/23/14Managing and controlling the use of hardware resources on integrated circuits
09/25/14Single event upset mitigation for electronic design synthesis
09/18/14Modeling content-addressable memory for emulation
09/04/14Programmable leakage test for interconnects in stacked designs
08/21/14Resource mapping in a hardware emulation environment
08/21/14Test architecture for characterizing interconnects in stacked designs
08/21/14Layout decomposition for triple patterning lithography
08/14/14Selective per-cycle masking of scan chains for system level test
08/14/14Optical proximity correction for topographically non-uniform substrates
08/07/14Scan-based test architecture for interconnects in stacked designs
08/07/14High-frequency vlsi interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate
07/31/14Multiresolution mask writing
07/31/14Mask rule checking based on curvature
Patent Packs
07/31/14Integration of optical proximity correction and mask data preparation
07/24/14Circuit and measuring delays between edges of signals of a circuit
07/17/14User interfaces
07/17/14Wrap based fill in layout designs
07/03/14Voltage-related analysis of layout design data
06/19/14Resolution enhancing technology using phase assignment bridges
06/12/14Dynamic design partitioning for scan chain diagnosis
05/22/14Fragmentation point and simulation site adjustment for resolution enhancement techniques
05/01/14Coexistence of multiple verification component types in a hardware verification framework
05/01/14Dynamic printed circuit board design reuse
04/24/14Random access memory for use in an emulation environment
04/24/14Fault dictionary based scan chain failure diagnosis
04/17/14Fault support in an emulation environment
04/10/14Test access mechanism for diagnosis based on partitioning scan chains
03/27/14Electrical hotspot detection, analysis and correction
02/27/14Defect injection for transistor-level fault simulation
02/27/14Generating root cause candidates for yield analysis
02/20/14Partitionless multi user support for hardware assisted verification
02/20/14Density-based integrated circuit design adjustment
02/13/14Trace routing network
Social Network Patent Pack
02/13/14Timing-aware test generation and fault simulation
02/06/14Controllable turn-around time for post tape-out flow
02/06/14Manufacturability
01/30/14Partitionless multi user support for hardware assisted verification
01/30/14Mutual inductance extraction using dipole approximations
01/16/14Test bench hierarchy and connectivity in a debugging environment
01/16/14Biometric markers in a debugging environment
01/09/14Input space reduction for verification test set generation
01/02/14Test bench transaction synchronization in a debugging environment
01/02/14Continuous application and decompression of test patterns and selective compaction of test responses
12/05/13Nor-or decoder
12/05/13Reliability evaluation and system fail warning methods using on chip parametric monitors
11/28/13Third party component debugging for integrated circuit design
11/28/13Programmable circuit characteristics analysis
11/28/13Domain bounding for symmetric multiprocessing systems
11/21/13Virtual use of electronic design automation tools
11/14/13On-chip comparison and response collection tools and techniques
11/14/13Circuit and simultaneously measuring multiple changes in delay
11/14/13Analysis optimizer
11/14/13Hierarchical feature extraction for electrical interaction calculations
Social Network Patent Pack
11/07/13Input space reduction for verification test set generation
10/31/13System and predicting problematic areas for lithography in a circuit design
10/31/13Test scheduling with pattern-independent test access mechanism
10/17/13Delta retiming in logic simulation
10/03/13Analog rule check waiver
09/26/13Power profiling for embedded system design
09/19/13Enhanced diagnosis with limited failure cycles
09/19/13Metastability effects simulation for a circuit description
09/19/13Coexistence of multiple verification component types in a hardware verification framework
09/12/13Methods and system for analysis and management of parametric yield
09/12/13Measure of analysis performed in property checking
09/12/13Event queue management for embedded systems
09/05/13Execution time profiling for interpreted programming languages
08/29/13Designing wiring harnesses
08/29/13Calculation system for inverse masks
08/22/13Hybrid memory failure bitmap classification
08/01/13Edge fragment correlation determination for optical proximity correction
08/01/13Pattern matching optical proximity correction
08/01/13Layout design defect repair based on inverse lithography and traditional optical proximity correction
08/01/13Estimation of power and thermal profiles
08/01/13Placement and area adjustment for hierarchical groups in printed circuit board design
08/01/13Verification test set and test bench map maintenance
07/25/13Sub-resolution assist feature repair
07/25/13Layout design defect repair using inverse lithography
07/25/13Simulation of circuits with repetitive elements
06/27/13Diagnosis-aware scan chain stitching
06/06/13Dynamic design partitioning for diagnosis
05/30/13Model-based fill
05/23/13Pattern matching hints
04/25/13Tolerable flare difference determination
Social Network Patent Pack
03/28/13Test pattern generation for diagnosing scan chain failures
03/28/13Simulation and correction of mask shadowing effect
02/28/13Cell-aware fault model generation for delay faults
02/14/13Data flow branching in mask data preparation
02/07/13Layout content analysis for source mask optimization acceleration
01/17/13Prediction of circuit performance variations due to device mismatch
12/20/12Random access memory for use in an emulation environment
12/13/12Multi-targeting boolean satisfiability-based test pattern generation
11/22/12Root cause distribution determination based on layout aware scan diagnosis results
11/08/12Resource remapping in a hardware emulation environment
10/18/12Logic injection
10/11/12Modeling and simulation method
10/04/12High-frequency vlsi interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate
09/13/12Two-dimensional scan architecture
09/06/12Monitoring physical parameters in an emulation environment
08/30/12Memory-based trigger generation scheme in an emulation environment
08/23/12Generating test sets for diagnosing scan chain failures
08/16/12Low power scan-based testing
08/16/12Selective per-cycle masking of scan chains for system level test
08/09/12Determining mutual inductance between intentional inductors
07/05/12Timing-aware test generation and fault simulation
06/28/12Modelling and simulation method
06/14/12Conversion of circuit description to an abstract model of the circuit
06/14/12Conversion of circuit description to an abstract model of the circuit
06/07/12Gate modeling for semiconductor fabrication process effects
06/07/12Analysis optimzer
05/31/12Managing communication bandwidth in co-verification of circuit designs
02/23/12Layout decomposition based on partial intensity distribution
02/23/12Incremental layout analysis







ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009



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