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Mentor Graphics Corporation patents


Recent patent applications related to Mentor Graphics Corporation. Mentor Graphics Corporation is listed as an Agent/Assignee. Note: Mentor Graphics Corporation may have other listings under different names/spellings. We're not affiliated with Mentor Graphics Corporation, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Mentor Graphics Corporation-related inventors


Worst case eye for multi-level pulse amplitude modulated links

This application discloses a computing system to perform a fast evaluation of a worst case eye diagram for a channel capable of communicating signals encoding data in more than two value levels. The computing system can identify multiple step responses of the channel, each corresponding to a transition between a... Mentor Graphics Corporation

Cloud services platform

Embodiments of the disclosed technology comprise a cloud-hosted central service platform that interfaces and enables access to both central and distributed resources and peripherals for connected mobile applications. For example, this platform allows service providers and application developers to create a large number of new classes of applications, leveraging web... Mentor Graphics Corporation

Back-pressure in virtual machine interface

This application discloses a computing system having a virtual machine and a host program that communicate via a virtual interface. The virtual machine can generate a data packet for transmission to the host program via the virtual interface. The virtual machine can receive a saturation signal generated by a virtual... Mentor Graphics Corporation

Bandwidth test in networking system-on-chip verification

Aspects of the disclosed technology relate to techniques of bandwidth test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates dispatch time information with messages when the messages are dispatched by a hardware model of a circuit design implemented in... Mentor Graphics Corporation

Latency test in networking system-on-chip verification

Aspects of the disclosed technology relate to techniques of latency test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates arrival time information with messages when the messages are delivered to a hardware model of a circuit design implemented in... Mentor Graphics Corporation

Removal of artificial resonances using boundary element method

This application discloses a computing system configured to crop a layout design for an electronic device implemented with a layered interconnect, place a termination structure corresponding to a resistive sheet or a set of resistive components on an artificial boundary corresponding to an edge in the cropped portion of the... Mentor Graphics Corporation

Traffic shaping in networking system-on-chip verification

Traffic-shaping information is associated with ingress transaction-level messages by a traffic generation device. The ingress transaction-level messages and the traffic-shaping information are then sent to a reconfigurable hardware modeling device. The ingress transaction-level messages are converted to ingress signal-level messages by a hardware model of interface circuitry implemented in the... Mentor Graphics Corporation

Flow control in networking system-on-chip verification

A system for verifying networking system-on-chip designs comprises a reconfigurable hardware modeling device programmed to implement circuitry hardware models and a traffic generation device communicating with the reconfigurable hardware modeling device. The circuitry hardware models comprise a hardware model of a circuit design and a hardware model of interface circuitry.... Mentor Graphics Corporation

Vehicle localization with map-matched sensor measurements

This application discloses a computing system to implement vehicle localization in an assisted or automated driving system. The computing system can receive an environmental model populated with measurement data captured by sensors mounted in a vehicle. The computing system can detect a location of the vehicle relative to the map... Mentor Graphics Corporation

Sensor event detection and fusion

This application discloses a computing system to implement sensor event detection and fusion system in an assisted or automated driving system of a vehicle. The computing system can monitor an environmental model to identify spatial locations in the environmental model populated with temporally-aligned measurement data. The computing system can analyze,... Mentor Graphics Corporation

Situational awareness determination based on an annotated environmental model

Determining a situational annotation of a vehicle based on an annotated environmental model is disclosed. A computing system receives an annotated environmental model for a vehicle. The annotated environmental model can include data from a plurality of modalities. The computing system uses a classifier to determine an annotation of the... Mentor Graphics Corporation

Low-level sensor fusion

This application discloses a computing system to implement low-level sensor fusion in an assisted or automated driving system of a vehicle. The low-level sensor fusion can include receiving raw measurement data from sensors in the vehicle and temporally aligning the raw measurement data based on a time of capture. The... Mentor Graphics Corporation

Pre-tracking sensor event detection and fusion

This application discloses a computing system to implement pre-tracking sensor event detection and fusion in an assisted or automated driving system of a vehicle. The computing system can receive an environmental model including sensor measurement data from different types of sensors in the vehicle. The computing system can identify, on... Mentor Graphics Corporation

Event classification and object tracking

This application discloses a computing system to implement object tracking in an assisted or automated driving system of a vehicle. The computing system can assign a pre-classification to a detection event in an environmental model, update the environmental model with new sensor measurements and corresponding detection events over time, and... Mentor Graphics Corporation

Multi-level sensor fusion

This application discloses a computing system to implement multi-level sensor fusion in an assisted or automated driving system of a vehicle. The computing system can populate an environment model with raw measurement data captured by sensors mounted in a vehicle and with data corresponding to a possible object in an... Mentor Graphics Corporation

Event-driven region of interest management

This application discloses a computing system to implement event-driven region of interest management in an assisted or automated driving system of a vehicle. The computing system can identify a portion of an environmental model for a vehicle that corresponds to a region of interest for a driving functionality system. The... Mentor Graphics Corporation

Map building with sensor measurements

This application discloses a computing system to implement map building in an assisted or automated driving system. The computing system can track movement of a vehicle based on sensor measurement data populated in an environmental model and vehicle movement measurements. The computing system can correlate the tracked movement of the... Mentor Graphics Corporation

Object recognition and classification using multiple sensor modalities

Object recognition and classification based on data from multiple sensor modalities is disclosed. A computing system can detect an event in a monitored portion of an environment coordinate field associated with a vehicle. The computing system can retrieve data associated with the detected event from a plurality of modalities. At... Mentor Graphics Corporation

Acceleration of voltage propagation based on local iteration

Aspects of the disclosed technology relate to techniques of voltage propagation-based reliability verification. Voltage values are propagated across components of a circuit design through global iterations until voltage values on nets of the circuit design are not changed from one global iteration to a next global iteration or one preset... Mentor Graphics Corporation

Acceleration of voltage propagation based on device chain reduction

Aspects of the disclosed technology relate to techniques of voltage propagation-based reliability verification. A circuit design is analyzed to identify circuit component chains. Voltage values are propagated across components of the circuit design based, at least in part, on treating the circuit component chains as virtual single components. The propagated... Mentor Graphics Corporation

Timing-aware test generation and fault simulation

Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from... Mentor Graphics Corporation

Debug environment for a multi user hardware assisted verification system

Technologies for debugging hardware errors discovered during hardware assisted software verification processes are provided. For example, in one embodiment, a concurrent emulation debug environment including a concurrent emulation system, an emulation trace module and a model state module is provided. The concurrent emulation system includes an emulator and an emulation... Mentor Graphics Corporation

Continuous application and decompression of test patterns and selective compaction of test responses

A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan... Mentor Graphics Corporation

Data injection in emulation without rebooting

An emulator is configured with a circuit design model for a circuit design comprising a processor and is running with an operating system. Data are transferred from a computer to a memory in the emulator through a design-independent interface or a transaction-level interface. A software program is then activated in... Mentor Graphics Corporation

Homotopy optimized parasitic extraction

Aspects of the disclosed technology relate to techniques of parasitic extraction. A signature for a set of geometric elements of a layout design is computed based on contour-related information. The set of geometric elements corresponds to a net of connected equipotential interconnects of a circuit design. Based on comparing the... Mentor Graphics Corporation

Pattern matching using edge-driven dissected rectangles

Aspects of the disclosed technology relate to techniques of pattern matching. Matching rectangles in a layout design that match rectangle members of a search pattern are identified based on edge operations. The rectangle members comprise an origin rectangle member and one or more reference rectangle members. Grid element identification values... Mentor Graphics Corporation

Virtual ethernet mutable port group transactor

Disclosed herein are example embodiments of methods, apparatus, and systems for transactors configured for use in a hardware emulation environment and designed to adapt to speed changes dynamically at runtime in addition to providing dynamic port mapping. Among the embodiments disclosed herein is an emulation system comprising one or more... Mentor Graphics Corporation

Logic-driven layout pattern analysis

A user or other source may specify one or more components in logical design data, such as schematic netlist design data. Based upon the provided logical component, portions of the physical design data that correspond to the logical component are selected. The selected physical design data corresponding to the specified... Mentor Graphics Corporation

Target capture and replay in emulation

An emulation process is performed with an emulator coupled to one or more targets. During a part or a whole of the emulation process, input signals to the emulator from the one or more targets are being captured, streamed out of the emulator and stored in one or more processor-readable... Mentor Graphics Corporation

Wide-range clock signal generation for speed grading of logic cores

An integrated circuit for on-chip speed grading comprises test circuitry comprising scan chains and a test controller; and wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry. The wide-range clock signal generation circuitry is configured to generate a wide-range test clock signal for the test circuitry... Mentor Graphics Corporation

Secure mechanism for finite provisioning of an integrated circuit

This application discloses an electronic system including active circuitry configured to be selectively enabled for authorized number of times. The electronic system also includes security circuitry to detect an enablement event associated with the electronic system. The enablement event can correspond to reception of a reset signal associated with the... Mentor Graphics Corporation

Power profiling for embedded system design

Tools and methods for profiling power consumption of an embedded system are provided. Power event and control modules, executable by the embedded system are provided. Additionally, a power measurement and control unit is provided that can measure the power consumption and limit the supply current to the embedded system. Furthermore,... Mentor Graphics Corporation

Graphical analysis of complex clock trees

This application discloses a computing system to implement a place and route tool to synthesize a clock tree in a layout design of an integrated circuit based on timing constraints for the integrated circuit. The computing system can select a portion of the clock tree to present in a schematic... Mentor Graphics Corporation

Correcting euv crosstalk effects for lithography simulation

Disclosed are techniques for correcting the EUV crosstalk effects. Isolated mask feature component diffraction signals associated with individual layout feature components are determined based on a component-based mask diffraction modeling method such as a domain decomposition method. Mask feature component diffraction signals are then determined based on the isolated mask... Mentor Graphics Corporation

Full-chip assessment of time-dependent dielectric breakdown

Aspects of the disclosed technology relate to techniques of full-chip assessment of time-dependent dielectric breakdown. A layout design is analyzed to identify matching patterns that match a pre-calculated pattern in a pattern database. Each of pre-calculated patterns in the pattern database has a time-to-failure characteristic value pre-computed based on a... Mentor Graphics Corporation

10/05/17 / #20170286592

Automatic axial thrust analysis of turbomachinery designs

Various aspects of the disclosed technology relate to axial thrust analysis of turbomachinery designs. A cavity of a turbomachinery design is divided into sub-cavities. Magnitudes of horizontal components of forces exerted on rotational faces in each of the sub-cavities are computed based on computational fluid dynamics, areas of the rotational... Mentor Graphics Corporation

09/28/17 / #20170277822

Printed circuit board design for manufacturing across multiple suppliers

This application discloses a computing system to parse a product model definition that includes a layout design of a printed circuit board assembly, which identifies physical design characteristics of the layout design of the printed circuit board assembly. The computing system can identify one or more manufacturing processes capable of... Mentor Graphics Corporation

09/21/17 / #20170270235

Fragmentation point and simulation site adjustment for resolution enhancement techniques

A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image... Mentor Graphics Corporation

09/14/17 / #20170262324

Event queue management for embedded systems

An event management structure for an embedded system, which supports multiple waiters waiting on the same event without replicating the events for each waiter, is provided. Notifications of events are received from entities within an embedded system. The event management architecture then posts the events to a central queue and... Mentor Graphics Corporation

09/14/17 / #20170262570

Layout design repair using pattern classification

Geometric elements within regions needing lithographic repair are examined to identify characteristics of the patterns formed by those geometric elements. Repair regions with common pattern characteristics then are categorized into classes. When a repair solution is determined for a selected repair region, that repair solution is applied to the other... Mentor Graphics Corporation

09/14/17 / #20170264718

Communication circuitry in an electronic control unit

This application discloses an electronic control unit coupled to a bus in a vehicle communication network. The electronic control unit includes a processing system configured to generate an instruction including an identifier of a type of signal exchanged through a vehicle communication network and including a command associated with exchange... Mentor Graphics Corporation

08/24/17 / #20170242953

Preserving hierarchy and coloring uniformity in multi-patterning layout design

Layout design data is seeded with sampling markers. The sampling markers are used to determine patterning scores for patterning clusters in the layout design data, such that a patterning score corresponds to a particular coloring arrangement, and the value of a patterning score corresponds to how many of the sampling... Mentor Graphics Corporation

08/03/17 / #20170220455

Test case generation using a constraint graph solver

The application discloses a computing system to analyze a program to generate a control flow graph representing paths capable of being traversed through the program during execution. The computing system can translate the control flow graph into a constraint graph representation of the program. The computing system can utilize a... Mentor Graphics Corporation

08/03/17 / #20170220729

Directed self-assembly-aware layout decomposition for multiple patterning

Aspects of the disclosed technology relate to techniques of combining directed self-assembly lithography and multiple patterning lithography. A coloring/grouping graph is first generated from layout data of a layout design. In the coloring/grouping graph, each coloring edge connects two nodes representing layout features that must be assigned to different masks,... Mentor Graphics Corporation

08/03/17 / #20170221197

Video inspection system with augmented display content

This application discloses a video inspection system for a rework station, which includes multiple image capture devices to capture multiple images or videos of a printed circuit board assembly, a presentation tool to merge the captured images or video into a image or video, and a display device to present... Mentor Graphics Corporation

07/27/17 / #20170213043

Security hardened controller area network transceiver

This application discloses a controller area network node including a controller and a transceiver. The transceiver includes security circuitry to perform various security checks on messages the controller area network node intends to have transmitted over a shared bus in a controller area network. The security circuitry can determine whether... Mentor Graphics Corporation

07/20/17 / #20170205462

Power-on self-test and in-system test

An integrated circuit comprises a plurality of built-in self-test circuits, a plurality of SIBs (segment insertion bits) coupled to a plurality of registers that are associated with the plurality of built-in self-test circuits, one or more storage devices, and a controller coupled to a part or a whole of an... Mentor Graphics Corporation

07/20/17 / #20170205702

Pattern correction in multiple patterning steps

This application discloses a computing system to simulate a wafer image based on a mandrel mask and a block mask to be utilized to print a final wafer image on a substrate. To simulate the wafer image the computing system can estimate dummy sidewalls based on the mandrel mask, estimate... Mentor Graphics Corporation

07/06/17 / #20170193155

Transition test generation for detecting cell internal defects

Aspects of the disclosed technology relate to techniques of test pattern generation based on the cell transition fault model. An assignment for two consecutive clock cycles at inputs of a complex cell in a circuit design is determined based on a gate-level representation of the circuit design. The assignment includes... Mentor Graphics Corporation

06/29/17 / #20170185708

Controlling real time during embedded system development

Disclosed herein are representative embodiments of methods, systems, and apparatus that can used to control real-time events (e.g., the real-time clock) during the design, simulation, or verification of an embedded system. In one exemplary embodiment disclosed herein, for example, a real-time clock signal is generated and tasks defined by an... Mentor Graphics Corporation

06/29/17 / #20170185710

Testbench restoration based on capture and replay

Messages transmitted from an emulator to a testbench of a part of the testbench are recorded from a starting point of an emulation operation to a checkpoint of the emulation operation. State information of the emulator at the checkpoint is captured and stored. The emulator is then configured to a... Mentor Graphics Corporation

06/08/17 / #20170161403

Assertion statement check and debug

This application discloses a computing system to check and generate an assertion statement. The assertion statement, when executed during a simulation of a circuit design, can verify a simulated behavior of the circuit design. The computing system can extract sequence items from the assertion statement, and generate a state representation... Mentor Graphics Corporation

06/08/17 / #20170161408

Topology recognition

This application discloses tools to build a topology library including one or more topologies, each of which includes a description of multiple transistors, their parameters, and associated connectivity, and also includes rules or criteria to be utilized in downstream design flow processes. The tools can analyze a circuit design describing... Mentor Graphics Corporation

05/25/17 / #20170147732

Simultaneous multi-layer fill generation

Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After... Mentor Graphics Corporation

05/18/17 / #20170140082

Target capture and replay in emulation

An emulation process is performed with an emulator coupled to one or more targets. During a part or a whole of the emulation process, input signals to the emulator from the one or more targets are being captured, streamed out of the emulator and stored in one or more processor-readable... Mentor Graphics Corporation

05/18/17 / #20170140083

Modeling memory in emulation based on cache

Aspects of the disclosed technology relate to techniques for modeling memories in emulation. An emulator is configured to implement an emulation model for a circuit design and a cache memory model for a memory accessible by the circuit design. A workstation coupled to the emulator is configured to implement a... Mentor Graphics Corporation

05/18/17 / #20170140084

Low power corruption of memory in emulation

Aspects of the disclosed technology relate to techniques for corrupting memories in emulation. After a power domain in a circuit design being emulated in an emulator is powered down, a main memory model for a memory in the power domain is corrupted and a cache memory model for the memory... Mentor Graphics Corporation

05/18/17 / #20170141764

Metastability glitch detection

... Mentor Graphics Corporation

05/18/17 / #20170141930

Test point-enhanced hardware security

Various aspects of the disclosed technology relate to techniques of using control test points to enhance hardware security. The design-for-security circuitry reuses control test points, a part of design-for-test circuitry. The design-for-security circuitry comprises: identity verification circuitry; scrambler circuitry coupled; and test point circuitry. The test point circuitry comprises scan... Mentor Graphics Corporation

05/11/17 / #20170132434

Measure variation tolerant physical unclonable function device

This application discloses a physical unclonable function device including physical unclonable function units, each capable of generating an output. The physical unclonable function device can extract bits from the outputs at various inspection locations and utilize the extracted bits to generate an identifier for the physical unclonable function device. An... Mentor Graphics Corporation

05/11/17 / #20170134175

Tolerant of absolute offsets physical unclonable function device

This application discloses a physical unclonable function device including physical unclonable function units, each capable of generating an output. The physical unclonable function device can utilize transforms to derive bits from the outputs and utilize the derived bits to generate an identifier for the physical unclonable function device. An inspection... Mentor Graphics Corporation

04/20/17 / #20170109459

Simultaneous retargeting of layout features based on process window simulation

Various aspects of the disclosed technology relate to techniques of retargeting layout features. A process window simulation on a layout design is performed to generate process window information that comprises predicted print positions of layout features computed under various process conditions. Retargeted print positions for a plurality of edge fragments... Mentor Graphics Corporation

04/13/17 / #20170103156

Hybrid compilation for fpga prototyping

Aspects of the disclosed technology relate to techniques of design implementation for FPGA prototyping. An initial FPGA-mapped netlist and a generic RTL design associated with the initial FPGA-mapped netlist are generated based on an original RTL (register-transfer level) design for a circuit design and optionally on verification-related features. Based on... Mentor Graphics Corporation

04/13/17 / #20170103158

Generating root cause candidates for yield analysis

Aspects of the invention relate to yield analysis techniques for generating root cause candidates for yield analysis. With various implementations of the invention, points of interest are first identified in a layout design. Next, regions of interest are determined for the identified points of interest. Next, one or more properties... Mentor Graphics Corporation

03/30/17 / #20170091356

Subtractive design for heat sink improvement

Aspects of the disclosed technology relate to techniques of improving heat sink designs based on systematic mass removal. A thermal simulation is performed to determine thermal property values for a heat sink design. The thermal property value of a portion of the heat sink design relates to the portion's contribution... Mentor Graphics Corporation

Patent Packs
03/02/17 / #20170063821

Secure protocol for chip authentication

This application discloses a supply chain security technique that enrolls an integrated circuit with a security server and subsequently utilizes the enrollment to authenticate the integrated circuit. The integrated circuit can include security circuitry to enroll the integrated circuit with the security server by generating an enrollment message—including a fingerprint... Mentor Graphics Corporation

02/23/17 / #20170052227

Selective per-cycle masking of scan chains for system level test

Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector... Mentor Graphics Corporation

02/23/17 / #20170053052

Multi-fpga prototyping of an asic circuit

The invention concerns a method of designing a prototype comprising a plurality of programmable chips, such as FPGA chips, for modelling an ASIC circuit, said ASIC circuit being intended to implement a logic design comprising a hierarchy of logic modules communicating together. The method according to the invention comprises the... Mentor Graphics Corporation

01/12/17 / #20170011139

Physically-aware circuit design partitioning

This application discloses a computing system implementing a synthesis tool to synthesize a circuit design of an electronic system into a gate-level netlist having a logical hierarchy, utilize the gate-level netlist to generate a physical representation of the circuit design, and partition the circuit design into sub-designs based on the... Mentor Graphics Corporation

01/05/17 / #20170004250

Integrated circuit layout design methodology with process variation bands

A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations.... Mentor Graphics Corporation








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