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Micron Technology Inc
Micron Technology Inc_20100114
Micron Technology Inc_20100107
Micron Technology Inc_20100121
Micron Technology Inc_20100128
Micron Technology Inc_20131212
Micron Technology Incorporated

Micron Technology Inc patents

Recent patent applications related to Micron Technology Inc. Micron Technology Inc is listed as an Agent/Assignee. Note: Micron Technology Inc may have other listings under different names/spellings. We're not affiliated with Micron Technology Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Micron Technology Inc-related inventors

Date Micron Technology Inc patents (updated weekly) - BOOKMARK this page
10/01/09Phase change memory
07/20/17 new patent  Non-volatile memory module architecture to support memory error correction
07/20/17 new patent  Development developing photoresist layer on wafer using the same
07/20/17 new patent  Non-volatile memory including selective error correction
07/20/17 new patent  Recovery for non-volatile memory after power loss
07/20/17 new patent  Apparatuses, circuits, and methods for biasing signal lines
07/20/17 new patent  Integrated circuitry and 3d memory
07/20/17 new patent  Functional data programming in a non-volatile memory
07/20/17 new patent  Memory devices that apply a programming potential to a memory cell in a string coupled to a source and data line concurrently with biasing the data line to a greater potential than the source
07/20/17 new patent  Methods for forming interconnect assemblies with probed bond pads
07/20/17 new patent  Semiconductor device
07/20/17 new patent  Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture
07/20/17 new patent  Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
07/20/17 new patent  Memory cell with independently-sized elements
07/20/17 new patent  Diode/superionic conductor/polymer memory structure
07/20/17 new patent  Ultrathin solid state dies and methods of manufacturing the same
07/13/17Chained bus method
07/13/17Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory
07/13/17Solid state memory formatting
07/13/17Apparatuses and methods for configuring i/os of memory for hybrid memory modules
07/13/17Estimation of error correcting performance of low-density parity-check (ldpc) codes
07/13/17Apparatuses and methods for current limitation in threshold switching memories
07/13/17Forming array contacts in semiconductor memories
07/13/17Waters having a die region and a scribe-line region adjacent to the die region
07/13/17Memory device and fabricating the same
07/13/17Memory device and fabricating method thereof
07/13/17Integrated structures and methods of forming vertically-stacked memory cells
07/13/17Devices and methods including an etch stop protection material
07/13/17Semiconductor devices with magnetic regions and attracter material and methods of fabrication
07/06/17Error code calculation on sensing circuitry
07/06/17Memory tile access and selection patterns
07/06/17Methods and systems for vector length management
07/06/17Overhead traveling vehicle, transportation system with the same, and operating the same
07/06/17Semiconductor constructions, methods of forming vertical memory strings, and methods of forming vertically-stacked structures
07/06/17Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures
07/06/17Packaged leds with phosphor films, and associated systems and methods
06/29/17Apparatuses and methods for exiting low power states in memory devices
06/29/17Data shift by elements of a vector in memory
06/29/17Memory device command receiving and decoding methods
06/29/17Semiconductor memory device including output buffer
06/29/17Apparatuses and methods of reading memory cells
06/29/17Test mode circuit for memory apparatus
06/29/17Stacked semiconductor dies with selective capillary under fill
06/29/17Methods of forming a ferroelectric memory cell
06/29/17Cross-point memory and methods for fabrication of same
06/29/17Computerized apparatus with a high speed data bus
06/22/17Apparatuses and methods for providing reference voltages
06/22/17Asymmetric chip-to-chip interconnect
06/22/17Phase change memory in a dual inline memory module
06/22/17Methods and apparatuses for compensating for source voltage
06/22/17Control lines to sensing components
06/22/17Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second select transistor
06/22/17Apparatuses and methods for charging a global access line prior to accessing a memory
06/22/17Programming memory cells to be programmed to different levels to an intermediate level from a lowest level
06/22/17Reducing programming disturbance in memory devices
06/22/17Electronic component of integrated circuitry and a forming a conductive via to a region of semiconductor material
06/22/17Methods of processing wafer-level assemblies to reduce warpage, and related assemblies
06/22/17Memory having a continuous channel
06/22/17Method and apparatus providing multi-planed array memory device
06/15/17Systems and methods for reordering packet transmissions in a scalable memory system protocol
06/15/17Conditional operation in an internal processor of a memory device
06/15/17Apparatus for impedance adjustment and methods of their operation
06/15/17Apparatuses and methods for dynamic voltage and frequency switching for dynamic random access memory
06/15/17Threshold voltage distribution determination
Patent Packs
06/15/17Memory devices with controllers under memory packages and associated systems and methods
06/15/17Apparatuses and methods for forming die stacks
06/08/17Controller to manage nand memories
06/08/17Solid state drive controller
06/08/17Apparatuses and methods for pre-fetching and write-back for a segmented cache memory
06/08/17Systems, circuits, and methods for charge sharing
06/08/17Apparatuses including multiple read modes and methods for same
06/08/17Apparatuses and methods for performing logical operations using sensing circuitry
06/08/17Systems, methods, and apparatuses for performing refresh operations
06/08/17Providing power availability information to memory
06/08/17Apparatuses and methods including memory access in cross point memory
06/08/17Programming a memory device in response to its program history
06/08/17Apparatuses and methods for reducing read disturb
06/08/17Low capacitance interconnect structures and associated systems and methods
06/08/17Ferroelectric capacitor, ferroelectric field effect transistor, and method used in forming an electronic component comprising conductive material and ferroelectric material
Patent Packs
06/08/17Transistors, semiconductor constructions, and methods of forming semiconductor constructions
06/08/17Methods and generation of voltages
06/08/17Phase interpolators and push-pull buffers
06/08/17Error correction methods and apparatuses using first and second decoders
06/01/17Storage devices configured to generate linked lists
06/01/17Apparatus having dice to perorm refresh operations
06/01/17Apparatuses and methods for providing set and reset voltages at the same time
06/01/17Capacitor, array of capacitors, and device comprising an electrode
06/01/17Recessed transistors containing ferroelectric material
05/25/17Input receiver circuit
05/25/17Semiconductor device with single ended main i/o line
05/25/17Multi-bit ferroelectric memory device and methods of forming the same
05/25/17Through substrate via liner densification
05/25/17Methods and systems for imaging and cutting semiconductor wafers and other semiconductor workpieces
05/25/17Methods of forming a semiconductor device comprising first and second nitride layers
05/25/17Interconnect structures with intermetallic palladium joints and associated systems and methods
05/25/17Integrated assemblies and methods of forming integrated assemblies
05/25/17Memory arrays and methods of forming memory arrays
05/25/17Vertical solid-state transducers having backside terminals and associated systems and methods
05/25/17Memory cell structures
05/25/17Apparatuses and methods for providing a signal with a differential phase mixer
05/18/17Apparatus providing simplified alignment of optical fiber in photonic integrated circuits
05/18/17Method for controlling user access to an electronic device
05/18/17Stt-mram cell structures
05/18/17Apparatuses and methods for transistor protection by charge sharing
05/18/17Erasing memory segments in a memory block of memory cells using select gate control line voltages
05/18/17Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
05/18/17Proximity coupling of interconnect packaging systems and methods
05/18/17Integrated structures and methods of forming integrated structures
05/18/17Vertical memory blocks and related devices and methods
Social Network Patent Pack
05/11/17Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation
05/11/17Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device
05/11/17Memory devices having differently configured blocks of memory cells
05/11/17Setting a default read signal based on error correction
05/11/17Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding
05/11/17Comparison operations in memory
05/11/17Unidirectional spin torque transfer magnetic memory cell structure
05/11/17Fixed voltage sensing in a memory device
05/11/17Frequency synthesis for memory input-output operations
05/11/17Autorecovery after manufacturing/system integration
Patent Packs
05/11/17Semiconductor device with modified current distribution
05/11/17Enhanced charge storage materials, related semiconductor memory cells and semiconductor devices, and related systems and methods
05/11/17Wiring with external terminal
05/11/17Memory including blocking dielectric in etch stop tier
05/11/17Self-aligned cross-point phase change memory-switch array
05/11/17Transistors, memory cells and semiconductor constructions
05/11/17Methods of forming resistive memory elements
05/11/17Method, apparatus and system providing a storage gate pixel with high dynamic range
05/04/17Memory cells configured in multiple configuration modes
05/04/17Data transfer techniques for multiple devices on a shared bus
05/04/17System and controlling user access to an electronic device
05/04/17Methods of operating storage systems including encrypting a key salt
05/04/17Self-measuring nonvolatile memory device systems and methods
05/04/17Methods and systems for power management in a pattern recognition processing system
05/04/17Memory bank signal coupling buffer and method
05/04/17Apparatuses and methods including memory and operation of same
05/04/17Apparatuses and methods for adjusting write parameters based on a write count
05/04/17Semiconductor memory column decoder device and method
05/04/17Semiconductor constructions
05/04/17Solid state transducers with state detection, and associated systems and methods
05/04/17Integrated assemblies and methods of forming assemblies
05/04/17Three-dimensional memory apparatuses and methods of use
04/27/17Interface device accessing a stack of memory dice and a solid state disk
04/27/17Efficient operations of components in a wireless communications device
04/27/17Command packets for the direct control of non-volatile memory channels within a solid state drive
04/27/17Apparatuses and methods for storing a data value in multiple columns
04/27/17Semiconductor device and error correction method
04/27/17Semiconductor device packages with improved thermal management and related methods
04/27/17Apparatuses and methods for heat transfer from packaged semiconductor die
04/27/17Solid state lighting device with different illumination parameters at different regions of an emitter array
Patent Packs
04/27/17Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells
04/27/17Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical ferroelectric field effect transistors, vertical strings of ferroelectric field effect transistors, and vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors
04/27/17Pixel with strained silicon layer for improving carrier mobility and blue response in imagers
04/27/17Ohmic contacts for semiconductor structures
04/20/17Logical address history management in memory device
04/20/17Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination
04/20/17Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination
04/20/17Persistent content in nonvolatile memory
04/20/17Method and decoding commands
04/20/17Device having multiple switching buffers for data paths controlled based on io configuration modes
04/20/17Apparatuses and methods to control body potential in memory operations
04/20/17External gettering
04/20/17Conductive structures, systems and devices including conductive structures and related methods
04/13/17Sequence power control
04/13/17Apparatuses and methods for setting a signal in variable resistance memory
04/13/17Semiconductor device including subword driver circuit
04/13/17Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
04/13/17Memory including a selector switch on a variable resistance memory cell
04/13/17Memory arrays
04/13/17Light emitting devices with built-in chromaticity conversion and methods of manufacturing
Social Network Patent Pack
04/13/17Transistors and methods of forming transistors
04/13/17Methods of forming memory devices having electrodes comprising nanowires
04/06/17Solid state storage device with variable logical capacity based on memory lifecycle
04/06/17Methods and systems for representing processing resources
04/06/17Estimating an error rate associated with memory
04/06/17Block or page lock features in serial interface memory
04/06/17Secure subsystem
04/06/17Methods and systems for creating networks
04/06/17Methods and systems for event reporting
04/06/17Soft post package repair of memory devices
04/06/17Apparatuses having a ferroelectric field-effect transistor memory array and related method
03/30/17Systems and methods for reducing temperature sensor reading variation due to device mismatch
03/30/17Apparatuses and methods for power regulation based on input power
03/30/17Arrays of memory cells and methods of forming an array of memory cells
03/30/17Phase change memory device with voltage control elements
03/30/17Methods of forming conductive elements of semiconductor devices and of forming memory cells
03/30/17System and duty cycle correction
03/23/17Systems and methods for providing file information in a memory system protocol
03/23/17Apparatuses and methods for providing data from a buffer
03/23/17Memory management for a hierarchical memory system
Social Network Patent Pack
03/23/17Stacked microfeature devices and associated methods
03/16/17Sense operation flags in a memory device
03/16/17Timing control circuit shared by a plurality of banks
03/16/17Access line management in a memory device
03/16/17Methods and apparatuses having strings of memory cells and select gates with double gates
03/16/17Stair step formation using at least two masks
03/16/17Collars for under-bump metal structures and associated systems and methods
03/16/17Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
03/16/17Magnetic tunnel junctions, methods used while forming magnetic tunnel junctions, and methods of forming magnetic tunnel junctions
03/16/17Boolean logic in a state machine lattice
03/16/17Multi channel memory with flexible code-length ecc
03/09/17Searching data in parallel using processor-in-memory devices
03/09/17Line termination methods
03/09/17Methods and apparatuses for reducing power consumption in a pattern recognition processor
03/09/17Methods and apparatuses for searching data stored in a memory array using a replicated data pattern
03/09/17Apparatuses including multiple read modes and methods for same
03/09/17Quantizing circuits having improved sensing
03/09/17Via formation for cross-point memory
03/09/17Systems, methods and devices for programming a multilevel resistive memory cell
03/09/17Apparatuses and methods for charging a global access line prior to accessing a memory
03/09/17Fuse element assemblies
03/09/17Integrated circuitry and methods of forming transistors
03/09/17Semiconductor devices and packages and methods of forming semiconductor device packages
03/09/17Methods of forming diodes
03/09/17Adjustable delay circuit for optimizing timing margin
03/02/17Programmable device, heirarchical parallel machines, and methods for providing state information
03/02/17Apparatuses and methods for transferring data from memory on a data path
03/02/17Methods of operating ferroelectric memory cells, and related ferroelectric memory cells and capacitors
03/02/17Storing information and updating management data in non-volatile memory
03/02/17Semiconductor devices including conductive lines and methods of forming the semiconductor devices
Social Network Patent Pack
03/02/17Methods of forming semiconductor device structures including stair step structures, and related semiconductor device structures and semiconductor devices
03/02/17Integrated circuit structures comprising conductive vias and methods of forming conductive vias
03/02/17Semiconductor device assemblies including intermetallic compound interconnect structures
03/02/17Apparatus including gettering agents in memory charge storage structures
03/02/17Clamp elements for phase change memory arrays
02/23/17Encryption of executables in computational memory
02/23/17Comparison operations in memory
02/23/17Program and read trim setting
02/23/17Apparatuses and/or methods for operating a memory cell as an anti-fuse
02/23/17Multi-channel testing
02/23/17Read voltage offset
02/23/17Bonding pads with thermal pathways
02/23/17Integrated structures containing vertically-stacked memory cells
02/23/17Integrated structures
02/23/17Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding
02/16/17Memory device with reduced neighbor memory cell disturbance
02/16/17Memory devices having source lines directly coupled to body regions and methods
02/16/17Fuses, and methods of forming and using fuses
02/16/17Method for packaging circuits
02/16/17Light-emitting metal-oxide-semiconductor devices and associated systems, devices, and methods
02/09/17Sense circuits, memory devices, and related methods for resistance variable memory
02/09/17Output buffer circuit with low sub-threshold leakage current
02/09/17Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods
02/09/17Method of forming conductive material of a buried transistor gate line and forming a buried transistor gate line
02/09/17Semiconductor devices including back-side integrated circuitry
02/09/17Memory cells including a metal chalcogenide material and related methods
02/09/17Memory cells and methods of forming memory cells
02/09/17Solid state optoelectronic device with plated support substrate
02/09/17Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Micron Technology Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Micron Technology Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by