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Micron Technology Inc
Micron Technology Inc_20100114
Micron Technology Inc_20100107
Micron Technology Inc_20100121
Micron Technology Inc_20100128
Micron Technology Inc_20131212
Micron Technology Incorporated

Micron Technology Inc patents

Recent patent applications related to Micron Technology Inc. Micron Technology Inc is listed as an Agent/Assignee. Note: Micron Technology Inc may have other listings under different names/spellings. We're not affiliated with Micron Technology Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Micron Technology Inc-related inventors

Date Micron Technology Inc patents (updated weekly) - BOOKMARK this page
10/01/09Phase change memory
09/21/17 new patent  Apparatuses and methods for photonic communication and photonic addressing
09/21/17 new patent  Apparatuses and methods for power regulation based on input power
09/21/17 new patent  Apparatuses and methods for operations using compressed and decompressed data
09/21/17 new patent  Signed division in memory
09/21/17 new patent  Semiconductor device having error correction code (ecc) circuit
09/21/17 new patent  Methods and apparatuses for providing a program voltage responsive to a voltage determination
09/21/17 new patent  Apparatuses and methods for concurrently accessing different memory planes of a memory
09/21/17 new patent  Apparatuses and methods for setting a signal in variable resistance memory
09/21/17 new patent  Cell-specific reference generation and sensing
09/21/17 new patent  Ferroelectric memory cell sensing
09/21/17 new patent  Ferroelectric memory cell apparatuses and methods of operating ferroelectric memory cells
09/21/17 new patent  Memory cells having a plurality of resistance variable materials
09/21/17 new patent  Feram-dram hybrid memory
09/21/17 new patent  3d flash memory device having different dummy word lines and data storage devices including same
09/21/17 new patent  Carrierless chip package for integrated circuit devices, and methods of making same
09/21/17 new patent  Semiconductor constructions, electronic systems, and methods of forming cross-point memory arrays
09/21/17 new patent  Structures incorporating and methods of forming metal lines including carbon
09/14/17Method, apparatus and system providing holographic layer as micro-lens and color filter array in an imager
09/14/17Counter operation in a state machine lattice
09/14/17Memory system data management
09/14/17Apparatuses and methods for cache invalidate
09/14/17Memory having a static cache and a dynamic cache
09/14/17Systems and methods to determine kinematical parameters using rfid tags
09/14/17Apparatus for power management
09/14/17Offset compensation for ferroelectric memory cell sensing
09/14/17Parallel access techniques within memory sections through section independence
09/14/17Memory cell sensing with storage component isolation
09/14/17Apparatuses and methods for logic/memory devices
09/14/17Methods of forming nanostructures having low defect density
09/14/17Methods of forming a portion of a memory array having a conductor having a variable concentration of germanium
09/14/17Semiconductor package with sidewall-protected rdl interposer
09/14/17Semiconductor device structures
09/14/17Conductive structures, systems and devices including conductive structures and related methods
09/14/17Semiconductor constructions
09/14/17Three dimensional memory array with select device
09/14/17Replacement materials processes for forming cross point memory
09/14/17Constructions comprising stacked memory arrays
09/14/17Conductive hard mask for memory device formation
09/14/17Buried low-resistance metal word lines for cross-point variable-resistance material memories
09/14/17Apparatuses and methods for voltage buffering
09/14/17Apparatuses and methods for adjusting timing of signals
09/14/17Read threshold calibration for ldpc
09/14/17Folding device stand for portable devices
09/07/17Apparatuses and methods of entering unselected memories into a different power mode during multi-memory operation
09/07/17Space efficient random forests implementation utilizing automata processors
09/07/17Ground reference scheme for a memory cell
09/07/17Apparatuses and methods for performing multiple memory operations
09/07/17Method of forming patterns
09/07/17Methods of forming through substrate interconnects
09/07/17Low capacitance through substrate via structures
09/07/17Methods of forming semiconductor devices including determining misregistration between semiconductor levels and related apparatuses
09/07/17Semiconductor memory device including output buffer
09/07/17Methods of making semiconductor device packages and related semiconductor device packages
09/07/17Apparatuses and methods for semiconductor circuit layout
09/07/17Semiconductor device structures including staircase structures, and related methods and electronic systems
09/07/17Methods for forming narrow vertical pillars and integrated circuit devices having the same
08/31/17Redundant array of independent nand for a three-dimensional memory array
08/31/17Microprocessor architecture having alternative memory access paths
08/31/17High speed, parallel configuration of multiple field programmable gate arrays
08/31/17Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes
08/31/17Current sense amplifiers, memory devices and methods
08/31/17Methods for isolating portions of a loop of pitch-multiplied material and related structures
08/31/17Memory array having connections going through control gates
08/31/17Solid-state radiation transducer devices having at least partially transparent buried-contact elements, and associated systems and methods
Patent Packs
08/31/17Memory arrays and methods of forming memory arrays
08/31/17Apparatuses and methods for level shifting
08/31/17Multi channel memory with flexible code-length ecc
08/24/17Apparatuses and methods for photonic communication and photonic addressing
08/24/17Apparatuses and methods for multiple address registers for a solid state device
08/24/17Error rate reduction
08/24/17Data transfer with a bit vector operation device
08/24/17Modified decode for corner turn
08/24/17Method and controlling access to a common bus by multiple components
08/24/17Refresh architecture and algorithm for non-volatile memories
08/24/17Removing polysilicon
08/24/17Methods of forming vertical field-effect transistor with selfaligned contacts for memory devices with planar periphery/array and intermediate structures formed thereby
08/17/17Apparatuses and methods for data movement
08/17/17Distributed input/output virtualization
08/17/17High performance memory controller
Patent Packs
08/17/17Semiconductor device with single ended main i/o line
08/17/17Read threshold voltage selection
08/17/17Data gathering in memory
08/17/17Loop structure for operations in memory
08/17/17Memory cell architecture for multilevel cell programming
08/17/17Memory devices with a connecting region having a band gap lower than a band gap of a body region
08/17/17Selectors on interface die for memory device
08/17/17Array of gated devices and methods of forming an array of gated devices
08/17/17Apparatuses and methods for internal heat spreading for packaged semiconductor die
08/17/17Memory cells
08/17/17Solid state lighting devices with improved contacts and associated methods of manufacturing
08/17/17Apparatuses and methods for voltage level control
08/10/17Apparatuses and methods for providing constant current
08/10/17Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination
08/10/17Apparatuses and methods for partitioned parallel data movement
08/10/17Command line output redirection
08/10/17Methods of operating memory including receipt of ecc data
08/10/17Semiconductor device
08/10/17Memory systems and memory programming methods
08/10/17Memory devices with a transistor that selectively connects a data line to another data line and methods for programming and sensing
08/10/17Fast programming memory device
08/10/17Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
08/10/17Integrated structures and methods of forming vertically-stacked memory cells
08/10/17Methods of forming metal on inhomogeneous surfaces and structures incorporating metal on inhomogeneous surfaces
08/10/17Methods, apparatuses, and circuits for programming a memory device
08/10/17Systems and methods to selectively connect antennas to receive and backscatter radio frequency signals
08/03/17Three-way valve and using the same
08/03/17Memory device having address and command selectable capabilities
08/03/17Memory device for a hierarchical memory architecture
08/03/17System and command based and current limit controlled memory device power up
Social Network Patent Pack
08/03/17Device having multiple channels with calibration circuit shared by multiple channels
08/03/17Methods and apparatuses for modulating threshold voltages of memory cells
08/03/17Cell-based reference voltage generation
08/03/17Memories having a shared resistance variable material
08/03/17Erasable block segmentation for memory
08/03/17Semiconductor device including a roll call circuit for outputting addresses of defective memory cells
08/03/17Apparatuses and methods for forming die stacks
08/03/17Methods of forming phase change memory apparatuses
08/03/17Solid-state radiation transducer devices having flip-chip mounted solid-state radiation transducers and associated systems and methods
08/03/17Progressive effort decoder architecture
Patent Packs
07/27/17Memory systems and methods including training, data organizing, and/or shadowing
07/27/17Memory systems and methods including training, data organizing, and/or shadowing
07/27/17Apparatuses and methods for encoding and decoding of signal lines for multi-level communication architectures
07/27/17Apparatuses and methods for accessing memory cells in semiconductor memories
07/27/17Apparatuses, multi-chip modules and capacitive chips
07/27/17Method of forming patterns
07/27/17Method for fabricating semiconductor package
07/27/17Semiconductor with through-substrate interconnect
07/27/17Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices
07/27/17Method for fabricating a semiconductor device
07/27/17Method for manufacturing a package-on-package assembly
07/27/17Semiconductor memory device having enlarged cell contact area and fabricating the same
07/27/17Method of fabricating semiconductor memory device having enlarged cell contact area
07/27/17Semiconductor structure and fabricating method thereof
07/27/17Apparatus and standby current control of signal path
07/20/17Non-volatile memory module architecture to support memory error correction
07/20/17Development developing photoresist layer on wafer using the same
07/20/17Non-volatile memory including selective error correction
07/20/17Recovery for non-volatile memory after power loss
07/20/17Apparatuses, circuits, and methods for biasing signal lines
07/20/17Integrated circuitry and 3d memory
07/20/17Functional data programming in a non-volatile memory
07/20/17Memory devices that apply a programming potential to a memory cell in a string coupled to a source and data line concurrently with biasing the data line to a greater potential than the source
07/20/17Methods for forming interconnect assemblies with probed bond pads
07/20/17Semiconductor device
07/20/17Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture
07/20/17Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods
07/20/17Memory cell with independently-sized elements
07/20/17Diode/superionic conductor/polymer memory structure
07/20/17Ultrathin solid state dies and methods of manufacturing the same
Patent Packs
07/13/17Chained bus method
07/13/17Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory
07/13/17Solid state memory formatting
07/13/17Apparatuses and methods for configuring i/os of memory for hybrid memory modules
07/13/17Estimation of error correcting performance of low-density parity-check (ldpc) codes
07/13/17Apparatuses and methods for current limitation in threshold switching memories
07/13/17Forming array contacts in semiconductor memories
07/13/17Waters having a die region and a scribe-line region adjacent to the die region
07/13/17Memory device and fabricating the same
07/13/17Memory device and fabricating method thereof
07/13/17Integrated structures and methods of forming vertically-stacked memory cells
07/13/17Devices and methods including an etch stop protection material
07/13/17Semiconductor devices with magnetic regions and attracter material and methods of fabrication
07/06/17Error code calculation on sensing circuitry
07/06/17Memory tile access and selection patterns
07/06/17Methods and systems for vector length management
07/06/17Overhead traveling vehicle, transportation system with the same, and operating the same
07/06/17Semiconductor constructions, methods of forming vertical memory strings, and methods of forming vertically-stacked structures
07/06/17Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures
Social Network Patent Pack
07/06/17Packaged leds with phosphor films, and associated systems and methods
06/29/17Apparatuses and methods for exiting low power states in memory devices
06/29/17Data shift by elements of a vector in memory
06/29/17Memory device command receiving and decoding methods
06/29/17Semiconductor memory device including output buffer
06/29/17Apparatuses and methods of reading memory cells
06/29/17Test mode circuit for memory apparatus
06/29/17Stacked semiconductor dies with selective capillary under fill
06/29/17Methods of forming a ferroelectric memory cell
06/29/17Cross-point memory and methods for fabrication of same
06/29/17Computerized apparatus with a high speed data bus
06/22/17Apparatuses and methods for providing reference voltages
06/22/17Asymmetric chip-to-chip interconnect
06/22/17Phase change memory in a dual inline memory module
06/22/17Methods and apparatuses for compensating for source voltage
06/22/17Control lines to sensing components
06/22/17Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second select transistor
06/22/17Apparatuses and methods for charging a global access line prior to accessing a memory
06/22/17Programming memory cells to be programmed to different levels to an intermediate level from a lowest level
06/22/17Reducing programming disturbance in memory devices
Social Network Patent Pack
06/22/17Electronic component of integrated circuitry and a forming a conductive via to a region of semiconductor material
06/22/17Methods of processing wafer-level assemblies to reduce warpage, and related assemblies
06/22/17Memory having a continuous channel
06/22/17Method and apparatus providing multi-planed array memory device
06/15/17Systems and methods for reordering packet transmissions in a scalable memory system protocol
06/15/17Conditional operation in an internal processor of a memory device
06/15/17Apparatus for impedance adjustment and methods of their operation
06/15/17Apparatuses and methods for dynamic voltage and frequency switching for dynamic random access memory
06/15/17Threshold voltage distribution determination
06/15/17Memory devices with controllers under memory packages and associated systems and methods
06/15/17Apparatuses and methods for forming die stacks
06/08/17Controller to manage nand memories
06/08/17Solid state drive controller
06/08/17Apparatuses and methods for pre-fetching and write-back for a segmented cache memory
06/08/17Systems, circuits, and methods for charge sharing
06/08/17Apparatuses including multiple read modes and methods for same
06/08/17Apparatuses and methods for performing logical operations using sensing circuitry
06/08/17Systems, methods, and apparatuses for performing refresh operations
06/08/17Providing power availability information to memory
06/08/17Apparatuses and methods including memory access in cross point memory
06/08/17Programming a memory device in response to its program history
06/08/17Apparatuses and methods for reducing read disturb
06/08/17Low capacitance interconnect structures and associated systems and methods
06/08/17Ferroelectric capacitor, ferroelectric field effect transistor, and method used in forming an electronic component comprising conductive material and ferroelectric material
06/08/17Transistors, semiconductor constructions, and methods of forming semiconductor constructions
06/08/17Methods and generation of voltages
06/08/17Phase interpolators and push-pull buffers
06/08/17Error correction methods and apparatuses using first and second decoders
06/01/17Storage devices configured to generate linked lists
06/01/17Apparatus having dice to perorm refresh operations
Social Network Patent Pack
06/01/17Apparatuses and methods for providing set and reset voltages at the same time
06/01/17Capacitor, array of capacitors, and device comprising an electrode
06/01/17Recessed transistors containing ferroelectric material
05/25/17Input receiver circuit
05/25/17Semiconductor device with single ended main i/o line
05/25/17Multi-bit ferroelectric memory device and methods of forming the same
05/25/17Through substrate via liner densification
05/25/17Methods and systems for imaging and cutting semiconductor wafers and other semiconductor workpieces
05/25/17Methods of forming a semiconductor device comprising first and second nitride layers
05/25/17Interconnect structures with intermetallic palladium joints and associated systems and methods
05/25/17Integrated assemblies and methods of forming integrated assemblies
05/25/17Memory arrays and methods of forming memory arrays
05/25/17Vertical solid-state transducers having backside terminals and associated systems and methods
05/25/17Memory cell structures
05/25/17Apparatuses and methods for providing a signal with a differential phase mixer
05/18/17Apparatus providing simplified alignment of optical fiber in photonic integrated circuits
05/18/17Method for controlling user access to an electronic device
05/18/17Stt-mram cell structures
05/18/17Apparatuses and methods for transistor protection by charge sharing
05/18/17Erasing memory segments in a memory block of memory cells using select gate control line voltages
05/18/17Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
05/18/17Proximity coupling of interconnect packaging systems and methods
05/18/17Integrated structures and methods of forming integrated structures
05/18/17Vertical memory blocks and related devices and methods
05/11/17Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation
05/11/17Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device
05/11/17Memory devices having differently configured blocks of memory cells
05/11/17Setting a default read signal based on error correction
05/11/17Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Micron Technology Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Micron Technology Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by