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Micron Technology Inc
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Micron Technology Incorporated
  

Micron Technology Inc patents

Recent patent applications related to Micron Technology Inc. Micron Technology Inc is listed as an Agent/Assignee. Note: Micron Technology Inc may have other listings under different names/spellings. We're not affiliated with Micron Technology Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Micron Technology Inc-related inventors




Date Micron Technology Inc patents (updated weekly) - BOOKMARK this page
10/01/09Phase change memory
11/16/17 new patent  Serial peripheral interface and methods of operating same
11/16/17 new patent  Apparatuses and methods for variable latency memory operations
11/16/17 new patent  Systems and methods for packing data in a scalable memory system protocol
11/16/17 new patent  Signed division in memory
11/16/17 new patent  Data storage error protection
11/16/17 new patent  3d nand memory z-decoder
11/16/17 new patent  Memory cell programming
11/16/17 new patent  Semiconductor structures comprising polymeric materials
11/16/17 new patent  Array of cross point memory cells and methods of forming an array of cross point memory cells
11/16/17 new patent  Semiconductor memory device having coplanar digit line contacts and storage node contacts in memory array and fabricating the same
11/16/17 new patent  Magnetic tunnel junctions
11/16/17 new patent  Thermally optimized phase change memory cells and methods of fabricating the same
11/16/17 new patent  Semiconductor structures including liners and related methods
11/16/17 new patent  Pixel array with shared pixels in a single column and associated devices, systems, and methods
11/09/17Microfeature workpieces having alloyed conductive structures, and associated methods
11/09/17Non-deterministic memory protocol
11/09/17Memory access techniques in memory devices with multiple partitions
11/09/17Dynamic arrays and overlays with bounds policies
11/09/17Memories having select devices between access lines and in memory cells formed of a same type of circuit element
11/09/17Apparatuses and methods for targeted refreshing of memory
11/09/17Semiconductor die assemblies with heat sink and associated systems and methods
11/09/17Microfeature workpieces and methods for forming interconnects in microfeature workpieces
11/09/17Semiconductor package with multiple coplanar interposers
11/09/17Magnetic devices with magnetic and getter regions and methods of formation
11/09/17Integrated structures having gallium-containing regions
11/09/17Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated systems and methods
11/09/17Method, system, and device for l-shaped memory component
11/09/17Resistive memory having confined filament formation
11/02/17Semiconductor device including amplifier
11/02/17Method and structure providing optical isolation of a waveguide on a silicon-on-insulator substrate
11/02/17Device having internal voltage generating circuit
11/02/17Memory devices for detecting known initial states and related methods and electronic systems
11/02/17Data caching
11/02/17Charge sharing between memory cell plates using a conductive path
11/02/17Performing logical operations using sensing circuitry
11/02/17Performing logical operations using sensing circuitry
11/02/17Apparatus and methods including a bipolar junction transistor coupled to a string of memory cells
11/02/17Electronic memory device having two portions that can be decoupled
11/02/17Semiconductor device including fuse circuit
11/02/17Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods
11/02/17Semiconductor devices and methods of manufacturing semiconductor devices
11/02/17Method of forming conductive material of a buried transistor gate line and forming a buried transistor gate line
11/02/17Integrated structures
11/02/17Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material, and methods of forming integrated structures
11/02/17Semiconductor devices and methods for forming patterned radiation blocking on a semiconductor device
11/02/17Light emitting diodes with enhanced thermal sinking and associated methods of operation
11/02/17Apparatuses and methods for mixed charge pumps with voltage regulator circuits
10/26/17Apparatuses and methods for memory operations having variable latencies
10/26/17Apparatuses and methods for memory operations having variable latencies
10/26/17Overflow detection and correction in state machine engines
10/26/17Apparatuses and methods for performing corner turn operations using sensing circuitry
10/26/17Simulating access lines
10/26/17Apparatuses and methods for performing corner turn operations using sensing circuitry
10/26/17Apparatuses and methods for detecting frequency ranges corresponding to signal delays of conductive vias
10/26/17Methods and apparatuses including command delay adjustment circuit
10/26/17Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays
10/26/17Methods and apparatuses including command delay adjustment circuit
10/26/17Apparatuses and methods of reading memory cells based on response to a test pulse
10/26/17Operational signals generated from capacitive stored charge
10/26/17Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line
10/26/17Interfaces and die packages, and appartuses including the same
10/26/17Method for embedding silicon die into a stacked package
10/26/17Semiconductor apparatus with multiple tiers, and methods
10/26/17Magnetic memory cells and semiconductor devices comprising the magnetic memory cells
Patent Packs
10/26/17Memory cells including dielectric materials, memory devices including the memory cells, and methods of forming same
10/26/17Memory cell materials and semiconductor device structures
10/26/17Circuits, apparatuses, and methods for frequency division
10/19/17Monitoring error correction operations performed in memory
10/19/17Systems and methods for improving efficiencies of a memory system
10/19/17Apparatuses and methods for providing data to a configurable storage area
10/19/17Memory device with direct read access
10/19/17Apparatuses and methods for parity determination using sensing circuitry
10/19/17Invert operations using sensing circuitry
10/19/17Apparatuses and methods for controlling wordlines and sense amplifiers
10/19/17Semiconductor device suppressing bti deterioration
10/19/17Resistance variable memory sensing using programming signals
10/19/17Threshold voltage margin analysis
10/19/17Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
10/19/17Microelectronic devices and methods for filling vias in microelectronic devices
Patent Packs
10/19/17Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus
10/19/17Memory arrays
10/19/17Memory devices including capacitor structures having improved area efficiency
10/19/17Memory cells having a number of conductive diffusion barrier materials and manufacturing methods
10/19/17System and duty cycle correction
10/12/17Span mask generation
10/12/17Methods of operating ferroelectric memory cells, and related ferroelectric memory cells and capacitors
10/12/17Dynamic adjustment of memory cell digit line capacitance
10/12/17Boosted channel programming of memory
10/12/17Memory programming methods and memory systems
10/12/17Patterns forming method
10/12/17Semiconductor device structures including staircase structures, and related methods and electronic systems
10/12/17Computer modules with small thicknesses and associated methods of manufacturing
10/12/17Three-dimensional structured memory devices
10/12/17Methods, devices, and systems related to forming semiconductor power devices with a handle substrate
10/12/17Self-identifying solid-state transducer modules and associated systems and methods
10/05/17Methods of forming interconnects and semiconductor structures
10/05/17Latching data for output at an edge of a clock signal generated in response to an edge of another clock signal
10/05/17Memory power coordination
10/05/17Error correction code (ecc) operations in memory
10/05/17Memory devices including dynamic superblocks, and related methods and electronic systems
10/05/17Apparatuses and methods for compensating for process, voltage, and temperature variation in a memory
10/05/17Vertical bit vector shift in memory
10/05/17Apparatuses and methods for controlling data timing in a multi-memory system
10/05/17Charge extraction from ferroelectric memory cell
10/05/17Refresh circuitry
10/05/17Semiconductor device
10/05/17Apparatuses and methods for refresh control
10/05/17Apparatuses and methods using dummy cells programmed to different states
10/05/17Methods of forming memory cells with air gaps and other low dielectric constant materials
Social Network Patent Pack
10/05/17Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods
10/05/17Bond pad with micro-protrusions for direct metallic bonding
10/05/17Thermal insulation for three-dimensional memory arrays
10/05/17Light emitting diodes with n-polarity and associated methods of manufacturing
10/05/17High-voltage solid-state transducers and associated systems and methods
10/05/17Pre-encapsulated lead frames for microelectronic device packages, and associated methods
10/05/17Apparatuses and methods for a load current control circuit for a source follower voltage regulator
10/05/17Clock signal and supply voltage variation tracking
09/28/17Mask patterns generated in memory from seed vectors
09/28/17Apparatuses and methods to determine timing of operations
Patent Packs
09/28/17Read cache memory
09/28/17Apparatus and methods for debugging on a memory device
09/28/17Apparatuses and methods for cache operations
09/28/17Adaptive content inspection
09/28/17Apparatuses and methods for data movement
09/28/17Cross-point memory compensation
09/28/17Devices including memory arrays, row decoder circuitries and column decoder circuitries
09/28/17Apparatus and methods for debugging on a host and memory device
09/28/17Semiconductor dies with recesses, associated leadframes, and associated systems and methods
09/28/17Semiconductor device having a memory cell and forming the same
09/21/17Apparatuses and methods for photonic communication and photonic addressing
09/21/17Apparatuses and methods for power regulation based on input power
09/21/17Apparatuses and methods for operations using compressed and decompressed data
09/21/17Signed division in memory
09/21/17Semiconductor device having error correction code (ecc) circuit
09/21/17Methods and apparatuses for providing a program voltage responsive to a voltage determination
09/21/17Apparatuses and methods for concurrently accessing different memory planes of a memory
09/21/17Apparatuses and methods for setting a signal in variable resistance memory
09/21/17Cell-specific reference generation and sensing
09/21/17Ferroelectric memory cell sensing
09/21/17Ferroelectric memory cell apparatuses and methods of operating ferroelectric memory cells
09/21/17Memory cells having a plurality of resistance variable materials
09/21/17Feram-dram hybrid memory
09/21/173d flash memory device having different dummy word lines and data storage devices including same
09/21/17Carrierless chip package for integrated circuit devices, and methods of making same
09/21/17Semiconductor constructions, electronic systems, and methods of forming cross-point memory arrays
09/21/17Structures incorporating and methods of forming metal lines including carbon
09/14/17Method, apparatus and system providing holographic layer as micro-lens and color filter array in an imager
09/14/17Counter operation in a state machine lattice
09/14/17Memory system data management
Patent Packs
09/14/17Apparatuses and methods for cache invalidate
09/14/17Memory having a static cache and a dynamic cache
09/14/17Systems and methods to determine kinematical parameters using rfid tags
09/14/17Apparatus for power management
09/14/17Offset compensation for ferroelectric memory cell sensing
09/14/17Parallel access techniques within memory sections through section independence
09/14/17Memory cell sensing with storage component isolation
09/14/17Apparatuses and methods for logic/memory devices
09/14/17Methods of forming nanostructures having low defect density
09/14/17Methods of forming a portion of a memory array having a conductor having a variable concentration of germanium
09/14/17Semiconductor package with sidewall-protected rdl interposer
09/14/17Semiconductor device structures
09/14/17Conductive structures, systems and devices including conductive structures and related methods
09/14/17Semiconductor constructions
09/14/17Three dimensional memory array with select device
09/14/17Replacement materials processes for forming cross point memory
09/14/17Constructions comprising stacked memory arrays
09/14/17Conductive hard mask for memory device formation
09/14/17Buried low-resistance metal word lines for cross-point variable-resistance material memories
09/14/17Apparatuses and methods for voltage buffering
Social Network Patent Pack
09/14/17Apparatuses and methods for adjusting timing of signals
09/14/17Read threshold calibration for ldpc
09/14/17Folding device stand for portable devices
09/07/17Apparatuses and methods of entering unselected memories into a different power mode during multi-memory operation
09/07/17Space efficient random forests implementation utilizing automata processors
09/07/17Ground reference scheme for a memory cell
09/07/17Apparatuses and methods for performing multiple memory operations
09/07/17Method of forming patterns
09/07/17Methods of forming through substrate interconnects
09/07/17Low capacitance through substrate via structures
09/07/17Methods of forming semiconductor devices including determining misregistration between semiconductor levels and related apparatuses
09/07/17Semiconductor memory device including output buffer
09/07/17Methods of making semiconductor device packages and related semiconductor device packages
09/07/17Apparatuses and methods for semiconductor circuit layout
09/07/17Semiconductor device structures including staircase structures, and related methods and electronic systems
09/07/17Methods for forming narrow vertical pillars and integrated circuit devices having the same
08/31/17Redundant array of independent nand for a three-dimensional memory array
08/31/17Microprocessor architecture having alternative memory access paths
08/31/17High speed, parallel configuration of multiple field programmable gate arrays
08/31/17Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes
Social Network Patent Pack
08/31/17Current sense amplifiers, memory devices and methods
08/31/17Methods for isolating portions of a loop of pitch-multiplied material and related structures
08/31/17Memory array having connections going through control gates
08/31/17Solid-state radiation transducer devices having at least partially transparent buried-contact elements, and associated systems and methods
08/31/17Memory arrays and methods of forming memory arrays
08/31/17Apparatuses and methods for level shifting
08/31/17Multi channel memory with flexible code-length ecc
08/24/17Apparatuses and methods for photonic communication and photonic addressing
08/24/17Apparatuses and methods for multiple address registers for a solid state device
08/24/17Error rate reduction
08/24/17Data transfer with a bit vector operation device
08/24/17Modified decode for corner turn
08/24/17Method and controlling access to a common bus by multiple components
08/24/17Refresh architecture and algorithm for non-volatile memories
08/24/17Removing polysilicon
08/24/17Methods of forming vertical field-effect transistor with selfaligned contacts for memory devices with planar periphery/array and intermediate structures formed thereby
08/17/17Apparatuses and methods for data movement
08/17/17Distributed input/output virtualization
08/17/17High performance memory controller
08/17/17Semiconductor device with single ended main i/o line
08/17/17Read threshold voltage selection
08/17/17Data gathering in memory
08/17/17Loop structure for operations in memory
08/17/17Memory cell architecture for multilevel cell programming
08/17/17Memory devices with a connecting region having a band gap lower than a band gap of a body region
08/17/17Selectors on interface die for memory device
08/17/17Array of gated devices and methods of forming an array of gated devices
08/17/17Apparatuses and methods for internal heat spreading for packaged semiconductor die
08/17/17Memory cells
08/17/17Solid state lighting devices with improved contacts and associated methods of manufacturing
Social Network Patent Pack
08/17/17Apparatuses and methods for voltage level control
08/10/17Apparatuses and methods for providing constant current
08/10/17Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination
08/10/17Apparatuses and methods for partitioned parallel data movement
08/10/17Command line output redirection
08/10/17Methods of operating memory including receipt of ecc data
08/10/17Semiconductor device
08/10/17Memory systems and memory programming methods
08/10/17Memory devices with a transistor that selectively connects a data line to another data line and methods for programming and sensing
08/10/17Fast programming memory device
08/10/17Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
08/10/17Integrated structures and methods of forming vertically-stacked memory cells
08/10/17Methods of forming metal on inhomogeneous surfaces and structures incorporating metal on inhomogeneous surfaces
08/10/17Methods, apparatuses, and circuits for programming a memory device
08/10/17Systems and methods to selectively connect antennas to receive and backscatter radio frequency signals
08/03/17Three-way valve and using the same
08/03/17Memory device having address and command selectable capabilities
08/03/17Memory device for a hierarchical memory architecture
08/03/17System and command based and current limit controlled memory device power up
08/03/17Device having multiple channels with calibration circuit shared by multiple channels
08/03/17Methods and apparatuses for modulating threshold voltages of memory cells
08/03/17Cell-based reference voltage generation
08/03/17Memories having a shared resistance variable material
08/03/17Erasable block segmentation for memory
08/03/17Semiconductor device including a roll call circuit for outputting addresses of defective memory cells
08/03/17Apparatuses and methods for forming die stacks
08/03/17Methods of forming phase change memory apparatuses
08/03/17Solid-state radiation transducer devices having flip-chip mounted solid-state radiation transducers and associated systems and methods
08/03/17Progressive effort decoder architecture







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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