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Filing Names

Micron Technology Inc
Micron Technology Inc_20100114
Micron Technology Inc_20100107
Micron Technology Inc_20100121
Micron Technology Inc_20100128
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Micron Technology Incorporated

Micron Technology Inc patents

Recent patent applications related to Micron Technology Inc. Micron Technology Inc is listed as an Agent/Assignee. Note: Micron Technology Inc may have other listings under different names/spellings. We're not affiliated with Micron Technology Inc, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Micron Technology Inc-related inventors

Date Micron Technology Inc patents (updated weekly) - BOOKMARK this page
10/01/09Phase change memory
04/20/17 new patent  Logical address history management in memory device
04/20/17 new patent  Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination
04/20/17 new patent  Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination
04/20/17 new patent  Persistent content in nonvolatile memory
04/20/17 new patent  Method and decoding commands
04/20/17 new patent  Device having multiple switching buffers for data paths controlled based on io configuration modes
04/20/17 new patent  Apparatuses and methods to control body potential in memory operations
04/20/17 new patent  External gettering
04/20/17 new patent  Conductive structures, systems and devices including conductive structures and related methods
04/13/17Sequence power control
04/13/17Apparatuses and methods for setting a signal in variable resistance memory
04/13/17Semiconductor device including subword driver circuit
04/13/17Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
04/13/17Memory including a selector switch on a variable resistance memory cell
04/13/17Memory arrays
04/13/17Light emitting devices with built-in chromaticity conversion and methods of manufacturing
04/13/17Transistors and methods of forming transistors
04/13/17Methods of forming memory devices having electrodes comprising nanowires
04/06/17Solid state storage device with variable logical capacity based on memory lifecycle
04/06/17Methods and systems for representing processing resources
04/06/17Estimating an error rate associated with memory
04/06/17Block or page lock features in serial interface memory
04/06/17Secure subsystem
04/06/17Methods and systems for creating networks
04/06/17Methods and systems for event reporting
04/06/17Soft post package repair of memory devices
04/06/17Apparatuses having a ferroelectric field-effect transistor memory array and related method
03/30/17Systems and methods for reducing temperature sensor reading variation due to device mismatch
03/30/17Apparatuses and methods for power regulation based on input power
03/30/17Arrays of memory cells and methods of forming an array of memory cells
03/30/17Phase change memory device with voltage control elements
03/30/17Methods of forming conductive elements of semiconductor devices and of forming memory cells
03/30/17System and duty cycle correction
03/23/17Systems and methods for providing file information in a memory system protocol
03/23/17Apparatuses and methods for providing data from a buffer
03/23/17Memory management for a hierarchical memory system
03/23/17Stacked microfeature devices and associated methods
03/16/17Sense operation flags in a memory device
03/16/17Timing control circuit shared by a plurality of banks
03/16/17Access line management in a memory device
03/16/17Methods and apparatuses having strings of memory cells and select gates with double gates
03/16/17Stair step formation using at least two masks
03/16/17Collars for under-bump metal structures and associated systems and methods
03/16/17Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
03/16/17Magnetic tunnel junctions, methods used while forming magnetic tunnel junctions, and methods of forming magnetic tunnel junctions
03/16/17Boolean logic in a state machine lattice
03/16/17Multi channel memory with flexible code-length ecc
03/09/17Searching data in parallel using processor-in-memory devices
03/09/17Line termination methods
03/09/17Methods and apparatuses for reducing power consumption in a pattern recognition processor
03/09/17Methods and apparatuses for searching data stored in a memory array using a replicated data pattern
03/09/17Apparatuses including multiple read modes and methods for same
03/09/17Quantizing circuits having improved sensing
03/09/17Via formation for cross-point memory
03/09/17Systems, methods and devices for programming a multilevel resistive memory cell
03/09/17Apparatuses and methods for charging a global access line prior to accessing a memory
03/09/17Fuse element assemblies
03/09/17Integrated circuitry and methods of forming transistors
03/09/17Semiconductor devices and packages and methods of forming semiconductor device packages
03/09/17Methods of forming diodes
03/09/17Adjustable delay circuit for optimizing timing margin
03/02/17Programmable device, heirarchical parallel machines, and methods for providing state information
03/02/17Apparatuses and methods for transferring data from memory on a data path
03/02/17Methods of operating ferroelectric memory cells, and related ferroelectric memory cells and capacitors
Patent Packs
03/02/17Storing information and updating management data in non-volatile memory
03/02/17Semiconductor devices including conductive lines and methods of forming the semiconductor devices
03/02/17Methods of forming semiconductor device structures including stair step structures, and related semiconductor device structures and semiconductor devices
03/02/17Integrated circuit structures comprising conductive vias and methods of forming conductive vias
03/02/17Semiconductor device assemblies including intermetallic compound interconnect structures
03/02/17Apparatus including gettering agents in memory charge storage structures
03/02/17Clamp elements for phase change memory arrays
02/23/17Encryption of executables in computational memory
02/23/17Comparison operations in memory
02/23/17Program and read trim setting
02/23/17Apparatuses and/or methods for operating a memory cell as an anti-fuse
02/23/17Multi-channel testing
02/23/17Read voltage offset
02/23/17Bonding pads with thermal pathways
02/23/17Integrated structures containing vertically-stacked memory cells
Patent Packs
02/23/17Integrated structures
02/23/17Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding
02/16/17Memory device with reduced neighbor memory cell disturbance
02/16/17Memory devices having source lines directly coupled to body regions and methods
02/16/17Fuses, and methods of forming and using fuses
02/16/17Method for packaging circuits
02/16/17Light-emitting metal-oxide-semiconductor devices and associated systems, devices, and methods
02/09/17Sense circuits, memory devices, and related methods for resistance variable memory
02/09/17Output buffer circuit with low sub-threshold leakage current
02/09/17Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods
02/09/17Method of forming conductive material of a buried transistor gate line and forming a buried transistor gate line
02/09/17Semiconductor devices including back-side integrated circuitry
02/09/17Memory cells including a metal chalcogenide material and related methods
02/09/17Memory cells and methods of forming memory cells
02/09/17Solid state optoelectronic device with plated support substrate
02/09/17Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals
02/02/17Interrupted write memory operation in a serial interface memory with a portion of a memory
02/02/17Systems and methods to determine motion parameters using rfid tags
02/02/17Connections for memory electrode lines
02/02/17Memory cell and an array of memory cells
02/02/17Semiconductor devices comprising magnetic memory cells and methods of fabrication
02/02/17Generation of voltages
01/26/17Method and a volume management system in a non-volatile memory device
01/26/17Memory having internal processors and data communication methods in memory
01/26/17Apparatuses and methods for performing compare operations using sensing circuitry
01/26/17Interfaces and die packages, and appartuses including the same
01/26/17Two-part programming methods
01/26/17Concurrently reading first and second pages of memory cells having different page addresses
01/26/17Apparatuses including stair-step structures and methods of forming the same
01/26/17Array of cross point memory cells
Social Network Patent Pack
01/26/17Memory arrays and methods of forming memory arrays
01/26/17Thyristor random access memory device and method
01/26/17Array of cross point memory cells and methods of forming an array of cross point memory cells
01/26/17Semiconductor constructions and memory arrays
01/26/17Solid state storage device with command and control access
01/19/17Apparatuses and methods for providing reference voltages
01/19/17Apparatuses and methods for segmented sgs lines
01/19/17Solder bond site including an opening with discontinous profile
01/19/17Memory devices and memory device forming methods
01/19/17Magnetic tunnel junctions
Patent Packs
01/19/17Memory cells, memory arrays, and methods of forming memory cells and arrays
01/19/17Secure shared key sharing systems and methods
01/12/17Systems and methods for forming apertures in microfeature workpieces
01/12/17Devices, systems, and methods to synchronize simultaneous dma parallel processing of a single data stream by multiple devices
01/12/17Apparatuses and methods for performing logical operations using sensing circuitry
01/12/17Semiconductor structures including carrier wafers and methods of using such semiconductor structures
01/12/17Methods of making semiconductor device packages and related semiconductor device packages
01/12/17Integrated structures and methods of forming vertically-stacked memory cells
01/12/17Apparatuses and methods for charge pump regulation
01/05/17System and decoding commands based on command signals and operating state
01/05/17Determining soft data
01/05/17Solid state transducer dies having reflective features over contacts and associated systems and methods
12/29/16Methods and systems for data analysis in a state machine
12/29/16Performing logical operations using sensing circuitry
12/29/16Solid state lighting devices with accessible electrodes and methods of manufacturing
12/22/16Apparatuses and methods for data transfer from sensing circuitry to a controller
12/22/16Multiple data channel memory module architecture
12/22/16Methods and apparatuses for providing data received by a state machine engine
12/22/16Memory devices for pattern matching
12/22/16Systems and methods using single antenna for multiple resonant frequency ranges
12/22/16Data shifting
12/22/16Apparatuses and methods for chip identification in a memory package
12/22/16Apparatuses and methods for performing an exclusive or operation using sensing circuitry
12/22/16Boosting channels of memory cells
12/22/16Back-to-back solid state lighting devices and associated methods
12/22/16Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods
12/22/16Methods and apparatuses having strings of memory cells including a metal source
12/22/16Elevated pocket pixels, imaging devices and systems including the same and forming the same
12/22/16Solid state transducer devices, including devices having integrated electrostatic discharge protection, and associated systems and methods
12/22/16Vertical memory cell string with dielectric in a portion of the body
Patent Packs
12/22/16Vertical light emitting devices with nickel silicide bonding and methods of manufacturing
12/15/16Systems and methods to use radar in rfid systems
12/15/16Command queuing
12/15/16Stripe mapping in memory
12/15/16Apparatuses and methods for encoding using error protection codes
12/15/16Data storage error protection
12/15/16Memory having a static cache and a dynamic cache
12/15/16Apparatuses and methods for compensating for process, voltage, and temperature variation in a memory
12/15/16Simulating access lines
12/15/16Apparatuses, devices and methods for sensing a snapback event in a circuit
12/15/16Memory cells having a plurality of resistance variable materials
12/15/16Programming methods and memories
12/15/16Methods of forming memory arrays
12/15/16Semiconductor structures including liners comprising alucone and related methods
12/15/16Clock signal and supply voltage variation tracking
12/08/16Sequential memory access operations
12/08/16Methods and devices for reducing array size and complexity in automata processors
12/08/16Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, methods of writing to and reading from a memory cell, and computer systems
12/08/16Threshold voltage analysis
12/08/16Multi-function resistance change memory cells and apparatuses including the same
Social Network Patent Pack
12/08/16Methods of operating memory
12/08/16Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
12/08/16Methods of manufacturing multi die semiconductor device packages and related assemblies
12/08/16Methods of forming magnetic memory cells and semiconductor devices
12/08/16Apparatus and methods for leakage current reduction in integrated circuits
12/08/16Method, apparatus, and system providing an imager with pixels having extended dynamic range
12/01/16Methods and apparatuses for error correction
12/01/16Apparatuses and methods for compute enabled cache
12/01/16Histogram creation process for memory devices
12/01/16Interconnection for memory electrodes
12/01/16Semiconductor device suppressing bti deterioration
12/01/16Programming memory cells to be programmed to different levels to an intermediate level from a lowest level
12/01/16Apparatuses and methods for performing multiple memory operations
12/01/16Functional data programming and reading in a memory
12/01/16Leakage current detection
12/01/16Determining soft data from a hard read
12/01/16Semiconductor devices and packages including conductive underfill material and related methods
12/01/16Semiconductor device with modified current distribution
12/01/16Devices and methods including an etch stop protection material
12/01/16Magnetic memory cells, semiconductor devices, and methods of operation
Social Network Patent Pack
11/24/16Power management
11/24/16Power management
11/24/16Translation lookaside buffer in memory
11/24/16Multi-function, modular system for network security, secure communication, and malware protection
11/24/16Virtual ground sensing circuitry and related devices, systems, and methods
11/24/16Apparatus having dice to perorm refresh operations
11/24/16Apparatus and methods including source gates
11/24/16Apparatuses and methods using dummy cells programmed to different states
11/24/16Seminconductor device assembly with vapor chamber
11/24/16Semiconductor device including semiconductor chips mounted over both surfaces of substrate
11/24/16Semiconductor device assembly with heat transfer structure formed from semiconductor material
11/24/16Interconnect structure with improved conductive properties and associated systems and methods
11/24/16Package-on-package semiconductor assemblies and methods of manufacturing the same
11/24/16Stacked semiconductor die assemblies with support members and associated systems and methods
11/24/16Solid-state radiation transducer devices having at least partially transparent buried-contact elements, and associated systems and methods
11/24/16Solid state optoelectronic device with preformed metal support substrate
11/17/16Apparatuses and methods for asymmetric input/output interface for a memory
11/17/16Memory arrays
11/17/16Electromagnetic shield and associated methods
11/17/16Stacked semiconductor die assemblies with die support members and associated systems and methods
11/17/16Discontinuous patterned bonds for semiconductor devices and associated systems and methods
11/17/16Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias
11/17/16Methods and apparatuses having memory cells including a monolithic semiconductor channel
11/17/16Semiconductor constructions and nand unit cells
11/17/16Interconnection systems
11/10/16Multiple virtually over-provisioned, virtual storage devices created from a single physical storage device
11/10/16Devices, systems, and methods of reducing chip select
11/10/16Frequency synthesis for memory input-output operations
11/10/16Reduced voltage nonvolatile flash memory
11/10/16Semiconductor device packages including a controller element and related methods
Social Network Patent Pack
11/10/16Select device for memory cell applications
11/10/16Magnetic tunnel junctions
11/10/16Magnetic tunnel junctions
11/03/16Method and device to reduce power consumption managment of a pattern-recognition processor
11/03/16Methods and systems for using state vector data in a state machine engine
11/03/16Semiconductor die assembly and methods of forming the same
11/03/16Memory cells having a folded digit line architecture
11/03/16Memory structures and arrays, and methods of forming memory structures and arrays
11/03/16Methods of forming transistor gates
11/03/16Resistive memory having confined filament formation
11/03/16Methods and apparatuses including command latency control circuit
10/27/16Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory
10/27/16Methods and apparatuses for command shifter reduction
10/27/16Apparatuses and methods for providing active and inactive clock signals to a command path circuit
10/27/16Reference voltage generation apparatuses and methods
10/27/16Epitaxial devices
10/27/16Resistive ram devices and methods
10/27/16Apparatuses and methods for pipelining memory operations with error correction coding
10/27/16Multi-junction solid state transducer devices for direct ac power and associated systems and methods
10/20/16Apparatuses and methods to reverse data stored in memory
10/20/16Division operations for memory
10/20/16Target architecture determination
10/20/16Memory tile access and selection patterns
10/20/16Programming memories with multi-level pass signal
10/20/16Apparatuses, memories, and methods for address decoding and selecting an access line
10/20/16Repair of memory devices using volatile and non-volatile memory
10/20/16Semiconductor device structures
10/20/16Array of memory cells, methods associated with forming memory cells that comprise programmable material, and methods associated with forming memory cells that comprise selector device material
10/20/16Resistive memory cell structures and methods

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Micron Technology Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Micron Technology Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by