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Micron Technology Inc
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Micron Technology Inc patents


Recent patent applications related to Micron Technology Inc. Micron Technology Inc is listed as an Agent/Assignee. Note: Micron Technology Inc may have other listings under different names/spellings. We're not affiliated with Micron Technology Inc, we're just tracking patents.

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 new patent  Fault isolation detecting faults in a circuit

The present invention provides a method and a fault isolation system for detecting errors in an integrated circuit. One feature of the present invention is using a movable second probe to scan and acquire an output signal through the vias or metal line structure of a diagnostic area along a... Micron Technology Inc

 new patent  Data storage with data randomizer in multiple operating modes

Methods of operating a memory include programming a particular portion of a data state to a memory cell with a data randomizer in a first operating mode, and programming a remaining portion of the data state to the memory cell with the data randomizer in a second operating mode different... Micron Technology Inc

 new patent  Methods of forming one or more covered voids in a semiconductor substrate

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures... Micron Technology Inc

 new patent  Methods of forming an elevationally extending conductor laterally between a pair of conductive lines

A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines... Micron Technology Inc

 new patent  Elevationally-extending string of memory cells individually comprising a programmable charge storage transistor and forming an elevationally-extending string of memory cells individually comprising a programmable charge storage transistor

An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the... Micron Technology Inc

Active alignment of optical fiber to chip using liquid crystals

Devices and systems to perform optical alignment by using one or more liquid crystal layers to actively steer a light beam from an optical fiber to an optical waveguide integrated on a chip. An on-chip feedback mechanism can steer the beam between the fiber and a grating based waveguide to... Micron Technology Inc

Memory device including current generator plate

Some embodiments include an apparatus and methods using a first conductive material located in a first level of an apparatus (e.g., a memory device); a second conductive material located in a second level of the apparatus; pillars extending between the first and second levels and contacting the first and second... Micron Technology Inc

Scan chain operation in sensing circuitry

Examples include apparatuses and methods related to scan chain operation in sensing circuitry. A number of embodiments include an apparatus comprising an array of memory cells coupled to sensing circuitry having a sense amplifier and a compute component, the sensing circuitry to receive a scan vector and perform a scan... Micron Technology Inc

Memory device including multiple select gates and different bias conditions

Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the... Micron Technology Inc

Thermal transfer structures for semiconductor die assemblies

Several embodiments of the present technology are described with reference to a semiconductor die assembly and processes for manufacturing the assembly. In some embodiments of the present technology, a semiconductor die assembly includes a stack of semiconductor dies attached to a thermal transfer structure (also known as a “heat spreader,”... Micron Technology Inc

Solid state optoelectronic device with preformed metal support substrate

A wafer-level process for manufacturing solid state lighting (“SSL”) devices using large-diameter preformed metal substrates is disclosed. A light emitting structure is formed on a growth substrate, and a preformed metal substrate is bonded to the light emitting structure opposite the growth substrate. The preformed metal substrate can be bonded... Micron Technology Inc

Apparatuses and methods for layer-by-layer error correction

One example of layer-by-layer error correction can include iteratively error correcting the codeword on a layer-by-layer basis with the first error correction circuit in a first mode and determining on the layer-by-layer basis whether a number of parity errors in a particular layer is less than a threshold number of... Micron Technology Inc

Apparatus providing simplified alignment of optical fiber in photonic integrated circuits

A structure for optically aligning an optical fiber to a protonic device and method of fabrication of same. The structure optically aligns an optical fiber to the protonic device using a lens between the two which is moveable by actuator heads. The lens is moveable by respective motive sources associated... Micron Technology Inc

Error correction code event detection

Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable... Micron Technology Inc

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry can include a sense amplifier coupled to a pair of complementary sense lines and a compute... Micron Technology Inc

Apparatuses and methods for performing intra-module databus inversion operations

Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module comprising a data bus inversion (DBI) and buffer circuit and a plurality of memories. The DBI and buffer circuit configured to encode a block of data received by the... Micron Technology Inc

Dynamic adjustment of memory cell digit line capacitance

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state. The capacitance of a digit line of the ferroelectric memory cell may be dynamically increased prior to, and during a portion of, a read... Micron Technology Inc

Cell performance recovery using cycling techniques

Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of memory cell. For example, a ferroelectric memory cell may enter a fatigue state after a number of access operations are performed at an access... Micron Technology Inc

Writing to cross-point non-volatile memory

Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component.... Micron Technology Inc

Ferroelectric memory cell apparatuses and methods of operating ferroelectric memory cells

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may... Micron Technology Inc

Oscillator controlled random sampling method and circuit

Various embodiments comprise methods and apparatuses for selecting a randomly-chosen seed row from among a stream of available data in a memory system. A refresh operation is then performed on at least one selected row of memory in the memory system based on the randomly-chosen seed row. Additional apparatuses and... Micron Technology Inc

Soft post package repair of memory devices

Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a... Micron Technology Inc

Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices

Microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a packaged microelectronic device can include an interposer substrate with a plurality of interposer contacts. A microelectronic die is attached and electrically coupled to the interposer substrate. The device further includes a casing covering the die... Micron Technology Inc

Package-on-package semiconductor device assemblies including one or more windows and related methods and packages

Semiconductor device packages for incorporation into semiconductor device assemblies may include a substrate including an array of electrically conductive elements located on a lower surface of the substrate. A window may extend through the substrate from the lower surface to an upper surface of the substrate. The array of electrically... Micron Technology Inc

Layout of transmission vias for memory device

Apparatuses and methods for supplying power to a plurality of dies are described. An example apparatus includes: a substrate; first, second and third memory cell arrays arranged in line in a first direction in the substrate; a first set of through electrodes arranged between the first and second memory cell... Micron Technology Inc

Ferroelectric memory and methods of forming the same

Ferroelectric memory and methods of forming the same are provided. An example memory cell can include a buried recessed access device (BRAD) formed in a substrate and a ferroelectric capacitor formed on the BRAD.... Micron Technology Inc

Solid state transducer devices with separately controlled regions, and associated systems and methods

Solid state transducer devices with independently controlled regions, and associated systems and methods are disclosed. A solid state transducer device in accordance with a particular embodiment includes a transducer structure having a first semiconductor material, a second semiconductor material and an active region between the first and second semiconductor materials,... Micron Technology Inc

Method for base contact layout, such as for memory

Embodiments disclosed herein may relate to forming a base contact layout in a memory device.... Micron Technology Inc

Cross-point memory and methods for fabrication of same

The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions... Micron Technology Inc

Memory cell structures

The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode,... Micron Technology Inc

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a clock generator circuit configured to provide first and second clock signals responsive to an input clock signal. A duty phase interpolator circuit may be coupled to the... Micron Technology Inc

Bank to bank data transfer

The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal... Micron Technology Inc

Managing host communication with a regulator in a low power mode

A solid-state drive (SSD) includes a connector communicatively coupling the SSD to a host device, a controller coupled to the connector, and a memory device. The SSD also include a regulator configured to receive an instruction to enter a low power mode of the SSD, enter the low power mode... Micron Technology Inc

Systems and devices for accessing a state machine

A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion... Micron Technology Inc

Multi-level storage in ferroelectric memory

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. In some examples, multi-level accessing, sensing, and other operations for ferroelectric memory may be based on sensing multiple charges, including a first charge associated with a dielectric of the memory cell and a second charge associated... Micron Technology Inc

12/28/17 / #20170372784

Connecting memory cells to a data line sequentially while applying a program voltage to the memory cells

Programming methods include applying a voltage to a selected access line commonly connected to a plurality of memory cells, and, while the voltage applied to the selected access line remains at a program voltage without being discharged, electrically connecting a subset of the plurality of memory cells to one data... Micron Technology Inc

12/28/17 / #20170372795

Systems and methods for testing a semiconductor memory device having a reference memory array

Semiconductor memory testing devices and methods are disclosed. In one respect, a device is disclosed that includes a first memory cell array having a first bit-line and a plurality of first memory cells coupled to the first bit-line; a second memory cell array having a second bit-line and a plurality... Micron Technology Inc

12/28/17 / #20170372861

Fuse element assemblies

Some embodiments include a fuse element assembly having a first portion configured to rupture as materials of the first portion flow to a second portion through electromigration. The assembly has a second portion configured to accumulate the materials that have flowed from the first portion. The assembly also has a... Micron Technology Inc

12/28/17 / #20170372913

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched.... Micron Technology Inc

12/28/17 / #20170372940

Methods of forming one or more covered voids in a semiconductor substrate

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures... Micron Technology Inc

12/28/17 / #20170372941

Methods of forming one or more covered voids in a semiconductor substrate

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures... Micron Technology Inc

12/28/17 / #20170372942

Methods of forming one or more covered voids in a semiconductor substrate, methods of forming field effect transistors, methods of forming semiconductor-on-insulator substrates, methods of forming a span comprising silicon dioxide, methods of cooling semiconductor devices, methods of forming electromagnetic radiation emitters and conduits, methods of forming imager systems, methods of forming nanofluidic channels, fluorimetry methods, and integrated circuitry

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures... Micron Technology Inc

12/28/17 / #20170372943

Methods of forming one or more covered voids in a semiconductor substrate, methods of forming field effect transistors, methods of forming semiconductor-on-insulator substrates, methods of forming a span comprising silicon dioxide, methods of cooling semiconductor devices, methods of forming electromagnetic radiation emitters and conduits, methods of forming imager systems, methods of forming nanofluidic channels, fluorimetry methods, and integrated circuitry

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures... Micron Technology Inc

12/28/17 / #20170372961

Vias and conductive routing layers in semiconductor substrates

Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a method for processing a semiconductor substrate includes forming an aperture in a semiconductor substrate and through a dielectric on the semiconductor substrate. The aperture has a first end open... Micron Technology Inc

12/28/17 / #20170373021

Semiconductor device including semiconductor chips mounted over both surfaces of substrate

A semiconductor chip 10 flip-chip mounted on a first surface 32 of a wiring substrate 30, a semiconductor chip 20 flip-chip mounted on a second surface 33 of the wiring substrate 30, a sealing resin 71 covering the semiconductor chip 10, a sealing resin 72 covering the semiconductor chip 20,... Micron Technology Inc

12/28/17 / #20170373069

Semiconductor device comprising gate structure sidewalls having different angles

The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first active region and the second active region are disposed in the substrate. The gate structure includes a bottom, a first sidewall attached to the first active... Micron Technology Inc

12/28/17 / #20170373075

Memory cell pillar including source junction plug

Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of... Micron Technology Inc

12/28/17 / #20170373076

Integrated structures and methods of forming integrated structures

Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any... Micron Technology Inc

12/28/17 / #20170373081

Integrated structures containing vertically-stacked memory cells

Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains... Micron Technology Inc

12/28/17 / #20170373198

Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors

A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain region is at opposite ends of the channel. A gate construction of the transistor comprises inner dielectric extending along the channel top and laterally along the channel sidewalls. Inner conductive material... Micron Technology Inc

12/28/17 / #20170373247

Transistors and methods of forming transistors

Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second... Micron Technology Inc

12/28/17 / #20170373703

Error correction code (ecc) operations in memory

Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include generating a codeword based on a number of low density parity check (LDPC) codewords failing a LDPC decoding operation and performing a BCH decoding operation on the codeword.... Micron Technology Inc

12/28/17 / #20170373705

Apparatuses and methods for erasure-assisted ecc decoding

One example of erasure-assisted error correction code (ECC) decoding can include reading a codeword with a first trim level, reading the codeword with a second trim level, and reading the codeword with a third trim level. A first result from reading the codeword with the first trim level, a second... Micron Technology Inc

12/21/17 / #20170364135

Apparatuses and methods for exiting low power states in memory devices

According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification. The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device... Micron Technology Inc

12/21/17 / #20170364268

Memory devices having distributed controller systems

Apparatus including a memory array further include an analog voltage generation circuit, an analog controller, a data cache, a data cache controller, and a master controller. The master controller is configured to generate an indication in response to an interpreted command. The analog controller is configured to determine, in response... Micron Technology Inc

12/21/17 / #20170364301

Data deduplication

The present disclosure includes devices and methods for data deduplication. One such method includes receiving a write command, transforming data associated with the write command, determining if a transformation value of the data exists in a transformation table, and responsive to a determination that the transformation value does not exist... Micron Technology Inc

12/21/17 / #20170364337

Method and compiling regular expressions

Apparatus, systems, and methods for a compiler are described. One such compiler converts source code into an automaton comprising states and transitions between the states, wherein the states in the automaton include a special purpose state that corresponds to a special purpose hardware element. The compiler converts the automaton into... Micron Technology Inc

12/21/17 / #20170364438

Methods of operating a storage device

Methods of operating a storage device include reading first data from a first storage location of a first memory of the storage device, storing the first data to a first storage location of a second memory of the storage device, compressing the first data and storing the compressed first data... Micron Technology Inc

12/21/17 / #20170364439

Data storage layout

Examples of the present disclosure provide apparatuses and methods for determining a data storage layout. An example apparatus comprising a first address space of a memory array comprising a first number of memory cells coupled to a plurality of sense lines and to a first select line. The first address... Micron Technology Inc

12/21/17 / #20170364444

Cache architecture for comparing data

The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache... Micron Technology Inc

12/21/17 / #20170364474

Devices for time division multiplexing of state machine engine signals

A device includes a plurality of blocks. Each block of the plurality of blocks includes a plurality of rows. Each row of the plurality of rows includes a plurality of configurable elements and a routing line, whereby each configurable element of the plurality of configurable elements includes a data analysis... Micron Technology Inc

12/21/17 / #20170365298

Interconnections for 3d memory

Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at... Micron Technology Inc

12/21/17 / #20170365299

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier coupled to a pair of complementary sense lines, and a compute component... Micron Technology Inc

12/21/17 / #20170365301

Apparatuses and methods for performing compare operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value.... Micron Technology Inc

12/21/17 / #20170365304

Data gathering in memory

Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of... Micron Technology Inc

Patent Packs
12/21/17 / #20170365310

Comparison operations in memory

The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a... Micron Technology Inc

12/21/17 / #20170365318

Array data bit inversion

Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of... Micron Technology Inc

12/21/17 / #20170365319

Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory

Virtual ground sensing circuits, electrical systems, computing devices, and related methods are disclosed. A virtual ground sensing circuit includes a sense circuit configured to compare a reference voltage potential to a sense node voltage potential, and virtual ground circuitry operably coupled to the sense circuit. The virtual ground circuitry is... Micron Technology Inc

12/21/17 / #20170365321

Ferroelectric memory cell sensing

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground reference for a duration associated with biasing a ferroelectric capacitor of a memory cell. For example, a digit line that is in electronic communication... Micron Technology Inc

12/21/17 / #20170365322

Cell-specific reference generation and sensing

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for example, stored using a capacitor or intrinsic capacitance of the memory array that includes the memory cell. The memory cell may be recharged... Micron Technology Inc

12/21/17 / #20170365323

Memory cell imprint avoidance

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with... Micron Technology Inc

12/21/17 / #20170365339

Memory programming methods and memory systems

Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the... Micron Technology Inc

12/21/17 / #20170365342

Memory as a programmable logic device

Methods for operating a memory, and memory configured to perform similar methods, include programming a first series string of memory cells of a first group of memory cells such that pairs of complementary memory cells have complementary states to provide a first minterm, the first minterm comprising a plurality of... Micron Technology Inc

12/21/17 / #20170365343

Boosting channels of memory cells

A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected memory string of the memory device, discharging the boosted channels of the memory cells in the selected memory string, and programming a selected memory cell in the... Micron Technology Inc

12/21/17 / #20170365344

Methods of operating a memory during a programming operation

Methods of operating a memory include increasing a voltage applied to a first access line from a first voltage to a second voltage higher than the first voltage while applying the first voltage to a second access line, the first access line coupled to a target memory cell of the... Micron Technology Inc

12/21/17 / #20170365345

Fast programming memory device

In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line,... Micron Technology Inc

12/21/17 / #20170365353

Apparatuses and/or methods for operating a memory cell as an anti-fuse

Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.... Micron Technology Inc

12/21/17 / #20170365356

Shared error detection and correction memory

Apparatuses and methods of sharing error correction memory on an interface chip are described. An example apparatus includes: at least one memory chip having a plurality of first memory cells and an interface chip coupled to the at least one memory chip and having a control circuit and a storage... Micron Technology Inc

12/21/17 / #20170365358

Methods of operating a memory device

Methods of operating a memory device include comparing an input address to one or more addresses stored in the memory device and indicative of problematic memory cells of the memory device, determining a status value of an indicator corresponding to a matched address if the input address matches a stored... Micron Technology Inc

12/21/17 / #20170365360

Plate defect mitigation techniques

Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells. Cells may be selected in pairs in order to accommodate an electric... Micron Technology Inc

Patent Packs
12/21/17 / #20170365481

Semiconductor structures

Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion... Micron Technology Inc

12/21/17 / #20170365580

Semiconductor package and fabrication method thereof

A semiconductor package may include a first logic die and a second logic die located laterally adjacent to the first logic die. A bridge memory die may be coupled to both the first logic die and the second logic die on a first active face of the first logic die... Micron Technology Inc

12/21/17 / #20170365584

Semiconductor device assembly with heat transfer structure formed from semiconductor material

Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a... Micron Technology Inc

12/21/17 / #20170365614

Charge storage apparatus and methods

Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so... Micron Technology Inc

12/21/17 / #20170365615

Floating gate memory cells in vertical memory

Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes... Micron Technology Inc

12/21/17 / #20170365617

Integrated structures and methods of forming integrated structures

Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more... Micron Technology Inc

12/21/17 / #20170365618

Systems including memory cells on opposing sides of a pillar

Systems including a processor and a memory device in communication with the processor include an array of non-volatile memory cells configured in a NAND architecture. The array includes a plurality of series-coupled first non-volatile memory cells, each first non-volatile memory cell curving around a first curved side of a substantially... Micron Technology Inc

12/21/17 / #20170365619

Memory having memory cell string and coupling components

Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses... Micron Technology Inc

12/21/17 / #20170365642

Cross-point memory and methods for fabrication of same

The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material... Micron Technology Inc

12/21/17 / #20170365726

Method and optoelectronic structure providing polysilicon photonic devices with different optical properties in different regions

Method and structural embodiments are described which provide an integrated structure using polysilicon material having different optical properties in different regions of the structure.... Micron Technology Inc

12/21/17 / #20170366184

Apparatus and standby current control of signal path

Apparatuses and methods for standby current control of a signal path in a semiconductor device are described. An example apparatus includes: first and second logic gates coupled in series; a first circuit coupled between the first logic gate and a power supply line that activates the first logic gate responsive... Micron Technology Inc

12/21/17 / #20170366188

Apparatuses with an embedded combination logic circuit for high speed operations

Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage,... Micron Technology Inc

12/14/17 / #20170356946

Apparatus and methods for testing devices

The present disclosure includes apparatuses and methods related to test devices, for example testing devices by measuring signals emitted by a device. One example apparatus can include a first portion including a number of sidewalls positioned to at least partially surround a device under test; and a second portion electrically... Micron Technology Inc

12/14/17 / #20170357057

Photonics grating coupler and manufacture

A structure for coupling an optical signal between an integrated circuit photonic structure and an external optical fiber is disclosed as in a method of formation. The coupling structure is sloped relative to a horizontal surface of the photonic structure such that light entering or leaving the photonic structure is... Micron Technology Inc

12/14/17 / #20170357467

Stripe mapping in memory

Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of... Micron Technology Inc

12/14/17 / #20170357482

Apparatuses and methods for timing domain crossing

Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event in based in... Micron Technology Inc

12/14/17 / #20170357605

System and independent, direct and parallel communication among multiple field programmable gate arrays

Representative embodiments are disclosed for data transfer between field programmable gate arrays (FPGAs). A representative system includes: a PCIe communication network comprising a PCIe switch and a plurality of PCIe communication lines; a host computing system coupled to the PCIe communication network; a nonblocking crossbar switch; a plurality of memory... Micron Technology Inc

12/14/17 / #20170357870

Descriptor guided fast marching analyzing images and systems using the same

Methods and systems for descriptor guided fast marching method based image analysis and associated systems are disclosed. A representative image processing method includes processing an image of a microelectronic device using a fast marching algorithm to obtain arrival time information for the image. The arrival time information is analyzed using... Micron Technology Inc

12/14/17 / #20170358328

Apparatus and methods to perform read-while write (rww) operations

Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of... Micron Technology Inc

12/14/17 / #20170358331

Apparatuses and methods for converting a mask to an index

The present disclosure includes apparatuses and methods related to converting a mask to an index. An example apparatus comprises an array of memory cells and periphery logic configured to: generate an indicator mask by resetting, in response to a first control signal, a second digit of a mask different from... Micron Technology Inc

12/14/17 / #20170358332

Apparatuses and methods for performing logical operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory... Micron Technology Inc

12/14/17 / #20170358333

Division operations in memory

Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a dividend element. An example apparatus might include a second group of memory... Micron Technology Inc

12/14/17 / #20170358336

Stack access control for memory device

Apparatuses and methods including an interface die that interfaces with dice through memory channels are described. An example apparatus includes a first die. The first die receives a first command including first command information and second command information provided after the first command information. The first die changes an order... Micron Technology Inc

12/14/17 / #20170358338

Half density ferroelectric memory and operation

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory... Micron Technology Inc

12/14/17 / #20170358339

Cell-based reference voltage generation

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. Each state may have a corresponding digit line voltage. The digit... Micron Technology Inc

12/14/17 / #20170358340

Boosting a digit line voltage for a write operation

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. The magnitude of a voltage applied across a ferroelectric capacitor may be dynamically increased during a write operation. For example, a memory cell may be selected for a write operation, and a voltage may be applied... Micron Technology Inc

12/14/17 / #20170358347

Apparatuses, devices and methods for sensing a snapback event in a circuit

Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a... Micron Technology Inc

12/14/17 / #20170358348

Memory device architecture

Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.... Micron Technology Inc

12/14/17 / #20170358359

Methods of programming memory

Methods of programming a memory include applying a programming voltage on an access line selected for a programming operation of a single page of the memory, applying a second voltage on an access line unselected for the programming operation, increasing the programming voltage for a first plurality of steps of... Micron Technology Inc

12/14/17 / #20170358366

Inferring threshold voltage distributions associated with memory cells via interpolation

The present disclosure includes apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation. A number of embodiments include determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of... Micron Technology Inc

Social Network Patent Pack
12/14/17 / #20170358370

Ferroelectric memory cell recovery

Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell that is fatigued due to repeated access (read or write) operations. The recovery voltage may have a greater amplitude than the access voltage and may include multiple voltage... Micron Technology Inc

12/14/17 / #20170358532

Electronic component of integrated circuitry and a forming a conductive via to a region of semiconductor material

An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface. A conductive via extends elevationally into the material of the one terminal. The conductive via extends laterally into the material of the one terminal under the... Micron Technology Inc

12/14/17 / #20170358547

Semiconductor devices including conductive pillars

A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and... Micron Technology Inc

12/14/17 / #20170358556

Semiconductor device assembly with through-mold cooling channel formed in encapsulant

Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached... Micron Technology Inc

12/14/17 / #20170358559

Methods of manufacturing a semiconductor device package including a controller element

Semiconductor device packages include a stack of semiconductor memory devices positioned over an interposer substrate, a controller element, and a redistribution substrate positioned laterally adjacent to the controller element. At least a portion of the controller element is positioned directly between the stack and the interposer substrate. The controller element... Micron Technology Inc

12/14/17 / #20170358580

Three-dimensional devices having reduced contact length

Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent... Micron Technology Inc

12/14/17 / #20170358583

Memory device and fabricating method thereof

A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a first active region, a second active region, a gate structure, and a capping layer. The first active region and the second active region are alternately disposed in the substrate. The gate... Micron Technology Inc

12/14/17 / #20170358595

Vertical memory blocks and related devices and methods

Vertical memory blocks for semiconductor devices include a memory cell region including an array of memory cell pillars and at least one via region including a dielectric stack of alternating dielectric materials and at least one conductive via extending through the dielectric stack. Semiconductor devices including a vertical memory block... Micron Technology Inc

12/14/17 / #20170358598

Memory cells comprising a programmable field effect transistor having a reversibly programmable gate insulator

A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different Vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is... Micron Technology Inc

12/14/17 / #20170358599

Apparatuses having a ferroelectric field-effect transistor memory array and related method

An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the... Micron Technology Inc

Patent Packs
12/14/17 / #20170358627

Select device for memory cell applications

The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material,... Micron Technology Inc

12/14/17 / #20170358628

Cross-point memory and methods for fabrication of same

A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void.... Micron Technology Inc

12/14/17 / #20170358629

Phase change memory stack with treated sidewalls

Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase... Micron Technology Inc

12/14/17 / #20170358737

Magnetic cell structures, and methods of fabrication

A magnetic cell structure comprises a seed material including tantalum, platinum, and ruthenium. The seed material comprises a platinum portion overlying a tantalum portion, and a ruthenium portion overlying the platinum portion. The magnetic cell structure comprises a magnetic region overlying the seed material, an insulating material overlying the magnetic... Micron Technology Inc

12/14/17 / #20170358741

Semiconductor devices with magnetic and attracter materials and methods of fabrication

A magnetic cell includes an attracter material proximate to a magnetic region (e.g., a free region). The attracter material is formulated to have a higher chemical affinity for a diffusible species of a magnetic material, from which the magnetic region is formed, compared to a chemical affinity between the diffusible... Micron Technology Inc








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