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Micron Technology Inc
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Micron Technology Inc patents


Recent patent applications related to Micron Technology Inc. Micron Technology Inc is listed as an Agent/Assignee. Note: Micron Technology Inc may have other listings under different names/spellings. We're not affiliated with Micron Technology Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Micron Technology Inc-related inventors


Temperature update for a memory device

Methods, systems, and devices for operating a ferroelectric memory cell or cells and, more particularly, a temperature update for a memory device are described. A memory array may be operated according to a timing cycle that includes a first interval for performing a first type of operation and a second... Micron Technology Inc

Power interrupt management

The present disclosure includes methods for operating a memory system, and memory systems. One such method includes updating transaction log information in a transaction log using write look ahead information; and updating a logical address (LA) table using the transaction log.... Micron Technology Inc

Apparatuses and methods for comparing a current representative of a number of failing memory cells

Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and... Micron Technology Inc

Read threshold voltage selection

Apparatuses and methods for read threshold voltage selection are provided. One example method can include setting a first soft read threshold voltage and a second soft read threshold voltage based on a difference between a first number of memory cells that are read as being programmed to a first state... Micron Technology Inc

Shifting data in sensing circuitry

The present disclosure is related to shifting data using sensing circuitry. An example apparatus can include a first sensing component and a second sensing component. The first sensing component can include a first sense amplifier coupled to a first pair of complementary sense lines and a first compute component comprising... Micron Technology Inc

Semiconductor device including a clock adjustment circuit

Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time... Micron Technology Inc

Compensating for variations in selector threshold voltages

Methods, systems, and devices are described for operating a memory array. A first voltage may be applied to a memory cell to activate a selection component of the memory cell prior to applying a second voltage to the memory cell. The second voltage may be applied to facilitate a sensing... Micron Technology Inc

Reprogrammable non-volatile ferroelectric latch for use with a memory controller

Methods, systems, and apparatuses related to a reprogrammable non-volatile latch are described. A latch may include ferroelectric cells, ferroelectric capacitors, a sense component, and other circuitry and components related to ferroelectric memory technology. The ferroelectric latch may be independent from (or exclusive of) a main ferroelectric memory array. The ferroelectric... Micron Technology Inc

Semiconductor device release during pick and place operations, and associated systems and methods

Systems and methods for releasing semiconductor devices during pick and place operations are disclosed. A representative system for handling semiconductor dies comprises a support member positioned to carry at least one semiconductor die releasably attached to a support substrate. The system further includes a picking device having a pick head... Micron Technology Inc

Semiconductor package utilizing embedded bridge through-silicon-via interconnect component

A semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a front-side RDL structure, and a back-side RDL structure. A bridge TSV interconnect component is embedded in the resin molded core. The bridge TSV interconnect component... Micron Technology Inc

Wafer level package utilizing molded interposer

A molded interposer includes a layer of first molding compound having a first side and a second side opposite to the first side; a first redistribution layer (RDL) structure disposed on the first side; a second redistribution layer (RDL) structure disposed on the second side; a plurality of metal vias... Micron Technology Inc

Semiconductor memory device having coplanar digit line contacts and storage node contacts in memory array and fabricating the same

A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of... Micron Technology Inc

Ferroelectric capacitor, ferroelectric field effect transistor, and method used in forming an electronic component comprising conductive material and ferroelectric material

A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of... Micron Technology Inc

Apparatuses and methods for removing defective energy storage cells from an energy storage array

Apparatuses and methods for removing a defective energy storage cell from an energy storage array is described. An apparatus includes an energy storage array including a plurality of energy storage cells, and a cell removal circuit coupled to the energy storage array. The cell removal circuit is configured to prevent... Micron Technology Inc

Electronic device structures and methods of making

Electronic device structures may include a sleeve member including a cavity extending from a first end of a body toward a second, opposite end, and an opening in communication with the cavity at the first end of the sleeve member. A frame configured to engage an electronic device member, such... Micron Technology Inc

Systems and apparatuses for a configurable temperature dependent reference voltage generator

Systems and apparatuses for a configurable, temperature dependent reference voltage generator are provided. An example apparatus includes control logic configured receive temperature data, and produce a signal, based on the temperature data, indicative of the temperature data, a temperature dependence and a temperature slope. The apparatus may also include a... Micron Technology Inc

Methods and related devices for operating a memory array

Methods of operating memory arrays, as well as the memory arrays, are described. In various embodiments, a method includes determining a pattern to be written to a memory array, the pattern comprising both data bits having sensitive information to be stored and data bits having a state that is unimportant... Micron Technology Inc

Analyzing data using a hierarchical structure

Apparatus, systems, and methods for analyzing data are described. The data can be analyzed using a hierarchical structure. One such hierarchical structure can comprise a plurality of layers, where each layer performs an analysis on input data and provides an output based on the analysis. The output from lower layers... Micron Technology Inc

Two-part programming methods

Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed... Micron Technology Inc

Selectors on interface die for memory device

Apparatuses including an interface chip that interfaces with dice through memory channels are described. An example apparatus includes: an interface chip that interfaces with a plurality of dice through a plurality of memory channels, each of the dice comprising a plurality of memory cells, and the interface chip comprising a... Micron Technology Inc

Apparatuses and methods to change data category values

The present disclosure includes apparatuses and methods to change data category values. An example is a memory device that includes an array having a plurality of sequences of memory cells, where each of the respective sequences of memory cells includes a plurality of designated subsets of memory cells, and the... Micron Technology Inc

Validation of a symbol response memory

Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows... Micron Technology Inc

System and individual addressing

In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to... Micron Technology Inc

Secure subsystem

An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers,... Micron Technology Inc

Apparatuses and methods for current limitation in threshold switching memories

Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells... Micron Technology Inc

Memory systems and memory programming methods

Memory systems and memory programming methods are described. In one arrangement, a memory system includes a memory cell configured to have a plurality of different memory states, an access circuit coupled with the memory cell and configured to provide a first signal to a memory element of the memory cell... Micron Technology Inc

3d vertical nand memory device including multiple select lines and control lines having different vertical spacing

Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a pillar including a length, a memory cell string and control lines located along a first segment of the pillar, and select lines located along a second segment of the pillar. The control... Micron Technology Inc

Reclaimable semiconductor device package and associated systems and methods

Several embodiments of reclaimable semiconductor device packages and assemblies are disclosed herein. A semiconductor device assembly (100) includes a package (101) having a housing (102) and a package contact (104) arranged to receive a signal indicative of a reclamation state. A plurality of modules of semiconductor dies (106) are located... Micron Technology Inc

Apparatuses and methods for semiconductor circuit layout

Apparatuses including compensation capacitors are described. An example apparatus includes: first, second and third capacitors arranged such that the second capacitor is sandwiched between the first and third capacitors, each of the first, second and third capacitors including first and second electrodes. The first electrodes of the first, second and... Micron Technology Inc

Vertical light emitting devices with nickel silicide bonding and methods of manufacturing

Various embodiments of light emitting devices, assemblies, and methods of manufacturing are described herein. In one embodiment, a method for manufacturing a lighting emitting device includes forming a light emitting structure, and depositing a barrier material, a mirror material, and a bonding material on the light emitting structure in series.... Micron Technology Inc

Methods of forming an array of cross point memory cells

A method of forming an array of cross point memory cells comprises forming spaced conductive lower electrode pillars for individual of the memory cells being formed along and elevationally over spaced lower first lines. Walls cross elevationally over the first lines and between the electrode pillars that are along the... Micron Technology Inc

Memory devices and electronic systems having a hybrid cache with static and dynamic cells, and related methods

A memory device having a memory controller is configured to operate a hybrid cache including a dynamic cache including XLC blocks and a static cache including the SLC blocks. The memory controller is configured to disable at least one of the static cache or the dynamic cache. A method of... Micron Technology Inc

Apparatuses and methods for generating probabilistic information with current integration sensing

Methods and apparatuses for generating probabilistic information for error correction using current integration are disclosed. An example method comprises sensing a first plurality of memory cells based on a first sense threshold, responsive to sensing the first plurality of cells, associating a first set of probabilistic information with the first... Micron Technology Inc

Storing memory array operational information in nonvolatile subarrays

Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array... Micron Technology Inc

Data shifting

The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located... Micron Technology Inc

03/22/18 / #20180082721

Apparatus of offset voltage adjustment in input buffer

Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes an input pad, an input buffer including a first input node and a second input node, a switch that couples the first input node and the second input node in an active state and further... Micron Technology Inc

03/22/18 / #20180082728

Compensation for threshold voltage variation of memory cell components

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Before reading a memory cell, the voltage on an access line of the memory cell may be initialized to a value associated with the threshold voltage of a switching component in electronic communication with the memory... Micron Technology Inc

03/22/18 / #20180082730

Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, methods of writing to and reading from a memory cell, and computer systems

Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line... Micron Technology Inc

03/22/18 / #20180082756

Comparison operations in memory

Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group... Micron Technology Inc

03/22/18 / #20180082940

Methods of forming a semiconductor device structure including a stair step structure, and related semiconductor devices

A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. A... Micron Technology Inc

03/22/18 / #20180082983

Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture

Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads,... Micron Technology Inc

03/22/18 / #20180083010

Method of forming semiconductor device including tungsten layer

A method of forming a semiconductor device includes forming a tungsten layer over a semiconductor substrate in a first chamber, transferring the substrate over which the tungsten layer is formed from the first chamber to a second chamber without exposing into an atmosphere including oxygen, and forming a silicon nitride... Micron Technology Inc

03/22/18 / #20180083011

Semiconductor devices, memory dies and related methods

A semiconductor substrate is provided. Active areas and trench isolation regions are formed. The active areas extend along a first direction. Buried word lines extending along a second direction are formed in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each... Micron Technology Inc

03/22/18 / #20180083653

Apparatuses and methods for staircase code encoding and decoding for storage devices

An apparatus is provided. The apparatus comprises a first syndrome computation circuit configured to receive a codeword having a plurality of rows and a plurality of columns and further configured to compute a first syndrome for at least a portion of a first component codeword of the codeword. The apparatus... Micron Technology Inc

03/15/18 / #20180075165

Methods and devices for saving and/or restoring a state of a pattern-recognition processor

Systems and methods are disclosed for saving and restoring the search state of a pattern-recognition processor. Embodiments include a pattern-recognition processor having a state variable array and a state variable storage array stored in on-chip memory (on-silicon memory with the processor). State variable storage control logic of the pattern-recognition processor... Micron Technology Inc

03/15/18 / #20180074740

Memory device configuration commands

Apparatuses and methods for configuring a memory device using configuration commands are provided. A method can include executing a first command while the memory device is in a ready state to configure the memory device to a particular mode and executing a second command to perform a first operation while... Micron Technology Inc

03/15/18 / #20180074754

Updating a register in memory

The present disclosure includes apparatuses and methods updating a register in memory. An example includes an array of memory cells; and a controller coupled to the array of memory cells configured to perform logical operations on data stored in the array of memory cells using a register that is updated... Micron Technology Inc

03/15/18 / #20180075899

Apparatuses and methods for shift decisions

The present disclosure includes apparatuses and methods for shift decisions. An example apparatus includes a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes a sense amplifier and a compute component... Micron Technology Inc

03/15/18 / #20180075913

Memory devices for reading memory cells of different memory planes

Memory devices may include digital-to-analog converters configured to convert digital values to analog read voltages and to apply the analog read voltages to memory cells in different memory planes, and multiplexers to selectively couple a corresponding table to a page buffer for output of a code from an identified code-containing... Micron Technology Inc

03/15/18 / #20180075920

Apparatuses and methods for flexible fuse transmission

Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input... Micron Technology Inc

03/15/18 / #20180075922

Semiconductor device including fuse circuit

Disclosed here is a semiconductor device that comprises plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input nodes, the decoder configured to decode the input signals and output decoded sepals, and a plurality of fuse circuits provided correspondingly with the decoded signals... Micron Technology Inc

03/15/18 / #20180076173

Semiconductor device including two or more chips mounted over wiring substrate

A semiconductor device includes a composite chip mounted over the a wiring substrate, the composite chip including a first area, a second area that is provided independently from the first area, and a third area including a first material between the first and second areas. the first area including a... Micron Technology Inc

03/15/18 / #20180076209

Integrated assemblies and methods of forming integrated assemblies

Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region are majority doped with a same dopant type. The integrated assembly includes a gating structure adjacent the semiconductor channel... Micron Technology Inc

03/15/18 / #20180076710

Apparatuses and methods for mixed charge pumps with voltage regulator circuits

Apparatuses and methods for mixed charge pumps with voltage regulator circuits is disclosed. An example apparatus comprises a first charge pump circuit configured to provide a first voltage, a second charge pump circuit configured to provide a second voltage, a plurality of coupling circuits configured to voltage couple and current... Micron Technology Inc

03/08/18 / #20180067656

Computing reduction and prefix sum operations in memory

The present disclosure includes apparatuses and methods for computing reduction and prefix sum operations in memory. A number of embodiments include processing circuitry configured to compute a reduction operation on data stored in a group of memory cells by splitting the data into a plurality of elements, copying each of... Micron Technology Inc

03/08/18 / #20180067661

Memory wear leveling

Systems and methods for intra-sector re-ordered wear leveling include: detecting, in a memory device, a high wear sub-sector having a high wear level, the sub-sector residing in a first sector; determining a second sector of the memory device having a low wear level; swapping the first sector with the second... Micron Technology Inc

03/08/18 / #20180068694

Invert operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a plurality of sensing components coupled to a controller. The controller is configured to selectively... Micron Technology Inc

03/08/18 / #20180068696

Tracking and correction of timing signals

Various embodiments include apparatus and methods to track and/or correct timing signals. Timing signals generated from an interface can be compared to the timing signals returned to the interface. A timing delta from the comparison can be applied to calculate a correction value make adjustments that can include adjustment to... Micron Technology Inc

03/08/18 / #20180068705

Redundancy array column decoder for memory

Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other memory cells of the array. Such redundant memory cells may be used if a another memory cell is discovered to be defective in some way;... Micron Technology Inc

03/08/18 / #20180068723

Oxide based memory

Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory cell includes forming a first electrode, forming a tunnel barrier, wherein a first portion of the tunnel barrier includes a first material and a second... Micron Technology Inc

03/08/18 / #20180068724

Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices

Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively... Micron Technology Inc

03/08/18 / #20180068737

Erasing memory segments in a memory block of memory cells using select gate control line voltages

A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device during an erase operation. The memory block of memory cells includes a plurality of memory segments and a corresponding plurality of first select gate... Micron Technology Inc

03/08/18 / #20180069015

Drain select gate formation methods and apparatus

Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed... Micron Technology Inc

03/01/18 / #20180061477

Apparatuses and methods including two transistor-one capacitor memory and for accessing same

Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the... Micron Technology Inc

03/01/18 / #20180059764

Apparatuses for reducing clock path power consumption in low power dynamic random access memory

Apparatus and methods of reducing clock path power consumption are described herein. According to one embodiment, an example apparatus includes a clock control circuit. The clock control circuit includes a command/address domain configured to selectively provide a command/address clock signal based, at least in part, on a chip select signal.... Micron Technology Inc

Patent Packs
03/01/18 / #20180059958

Hybrid memory device

Methods, systems, and devices for a hybrid memory device are described. The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their... Micron Technology Inc

03/01/18 / #20180060069

Apparatus and methods related to microcode instructions

The present disclosure includes apparatuses and methods related to microcode instructions. One example apparatus comprises a memory storing a set of microcode instructions. Each microcode instruction of the set can comprise a first field comprising a number of control data units, and a second field comprising a number of type... Micron Technology Inc

03/01/18 / #20180060234

Multiple data channel memory module architecture

According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of... Micron Technology Inc

03/01/18 / #20180060268

Systems, devices, and methods for selective communication through an electrical connector

Electrical systems and related methods are disclosed. An electrical system comprises an electronic device configured to communicate through an electrical connector using one of a plurality of different communication protocols responsive to receiving an indication of the one of the plurality of different communication protocols through the electrical connector from... Micron Technology Inc

03/01/18 / #20180061460

Sense amplifier constructions

A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are... Micron Technology Inc

03/01/18 / #20180061468

Ferroelectric memory cells

Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.... Micron Technology Inc

03/01/18 / #20180061469

Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory

Apparatuses and methods are disclosed that in ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first... Micron Technology Inc

03/01/18 / #20180061470

Full bias sensing in a memory array

Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. Access operations may also... Micron Technology Inc

03/01/18 / #20180061471

Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory

Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node.... Micron Technology Inc

03/01/18 / #20180061475

Device having multiple switching buffers for data paths controlled based on io configuration modes

A device includes a first data terminal, a second data terminal, a first switching buffer coupled between a data node and the first data terminal and a second switching buffer coupled between the data node and the second data terminal. The first switching buffer and the second switching buffer are... Micron Technology Inc

03/01/18 / #20180061477

Apparatuses and methods including two transistor-one capacitor memory and for accessing same

Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the... Micron Technology Inc

03/01/18 / #20180061480

Semiconductor device

A semiconductor device includes an equalizing circuit and a control circuit. The equalizing circuit executes an operation of pre-charging the signal input/output line pair used for data inputting/outputting and an operation of equalizing it independently of each other. In case a plurality of data write operations occur in succession, the... Micron Technology Inc

03/01/18 / #20180061481

Memory arrays

Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the... Micron Technology Inc

03/01/18 / #20180061483

A temperature-dependent refresh circuit configured to increase or decrease a count value of a refresh timer according to a self-refresh signal

Systems and apparatuses for memory devices utilizing a continuous self-refresh timer are provided. An example apparatus includes a self-refresh timer configured to generate a signal periodically, wherein a period of the signal is based on a self-refresh refresh time interval, wherein the self-refresh refresh time interval is dependent on temperature... Micron Technology Inc

03/01/18 / #20180061497

Temperature compensation in memory sensing

Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level... Micron Technology Inc

Patent Packs
03/01/18 / #20180061635

Methods of forming nanostructures using self-assembled nucleic acids, and nanostructures thereof

A method of forming a nanostructure comprises forming a directed self-assembly of nucleic acid structures on a patterned substrate. The patterned substrate comprises multiple regions. Each of the regions on the patterned substrate is specifically tailored for adsorption of specific nucleic acid structure in the directed self-assembly.... Micron Technology Inc

03/01/18 / #20180061665

Methods of forming semiconductor device structures including two-dimensional material structures

A method of forming a semiconductor device structure comprises forming at least one 2D material over a substrate. The at least one 2D material is treated with at least one laser beam having a frequency of electromagnetic radiation corresponding to a resonant frequency of crystalline defects within the at least... Micron Technology Inc

03/01/18 / #20180061834

Memory cells and memory arrays

Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative to the first transistor. The first capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with... Micron Technology Inc

03/01/18 / #20180061835

Memory cells and memory arrays

Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the... Micron Technology Inc

03/01/18 / #20180061836

Memory cells and memory arrays

Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of... Micron Technology Inc

03/01/18 / #20180061837

Memory cells and memory arrays

Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the... Micron Technology Inc

03/01/18 / #20180061840

Memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry

A memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a container-shape conductive first capacitor node electrically coupled with a first current node of the first transistor, a conductive second capacitor node electrically coupled with... Micron Technology Inc

03/01/18 / #20180061886

Methods of forming magnetic memory cells, and methods of forming arrays of magnetic memory cells

Methods of forming a magnetic memory cell are disclosed. The method comprises forming a magnetic cell core material over a substrate, wherein forming the magnetic cell core comprises forming a first magnetic region over the substrate, forming a tunnel barrier material over the first magnetic region, and forming a second... Micron Technology Inc

03/01/18 / #20180062629

Apparatus and instant-on quadra-phase signal generator

Apparatuses are provided for a quadra-phase clock signal generator. An example apparatus includes a first delay circuit configured to receive a first input clock signal generating a first delayed clock signal. A first phase mixer is provided communicatively coupled to the first delay circuit and configured to receive the first... Micron Technology Inc

03/01/18 / #20180062640

Systems, methods, and apparatuses for temperature and process corner sensitive control of power gated domains

Apparatuses and methods for temperature and process corner sensitive control of power gated domains are described. An example apparatus includes an internal circuit; a power supply line; and a power gating control circuit which responds, at least in part, to a first change from a first state to a second... Micron Technology Inc

03/01/18 / #20180063452

Anti-eclipse circuitry with tracking of floating diffusion reset level

Imagers and associated devices and systems are disclosed herein. In one embodiment, an imager includes a pixel array and control circuitry operably coupled to the pixel array. The pixel array includes an imaging pixel configured to produce a reset signal and a non-imaging pixel configured to produce a nominal reset... Micron Technology Inc

02/22/18 / #20180053538

Apparatuses and methods for adjusting delay of command signal path

Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a... Micron Technology Inc

02/22/18 / #20180053552

Segmented memory and operation

Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of the plurality of strings is selectively connected to a common data line through a corresponding respective select gate. A first set of access lines are each coupled to a respective memory... Micron Technology Inc

02/22/18 / #20180053708

Semiconductor package and fabrication method thereof

A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first RDL structure. A second RDL structure is disposed on the interconnect component. A plurality of first connecting elements is disposed on the second RDL structure. A polish stop layer covers a surface... Micron Technology Inc

02/15/18 / #20180043450

Connection verification technique

Some embodiments of the present invention are generally directed to testing connections of a memory device to a circuit board or other device. In one embodiment, a memory device that is configured to facilitate continuity testing between the device and a printed circuit board or other device is disclosed. The... Micron Technology Inc

02/15/18 / #20180046375

Sequential memory access operations

Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used... Micron Technology Inc

02/15/18 / #20180046405

Apparatuses and methods for data movement

The present disclosure includes apparatuses and methods for data movement. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes a sense amplifier and a compute component... Micron Technology Inc

02/15/18 / #20180046461

Smallest or largest value element determination

Examples of the present disclosure provide apparatuses and methods for smallest value element or largest value element determination in memory. An example method comprises: storing an elements vector comprising a plurality of elements in a group of memory cells coupled to an access line of an array; performing, using sensing... Micron Technology Inc

02/15/18 / #20180047432

Semiconductor layered device with data bus

Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first... Micron Technology Inc

02/15/18 / #20180047434

Apparatuses including multiple read modes and methods for same

Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first read mode and a second read mode. The memory has a read operation for the first read mode including a first pre-access phase, an access phase,... Micron Technology Inc

02/15/18 / #20180047438

Semiconductor memory device including output buffer

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to... Micron Technology Inc

02/15/18 / #20180047446

Memory sense amplifiers and memory verification methods

Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a... Micron Technology Inc

02/15/18 / #20180047460

Methods and providing redundancy in memory

Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective memory cell to an address of a redundant area of the memory array, and writing second data to the memory array, wherein a portion... Micron Technology Inc

02/15/18 / #20180047739

Methods of forming an array of elevationally-extending strings of memory cells comprising a programmable charge storage transistor and arrays of elevationally-extending strings of memory cells comprising a programmable charge storage transistor

An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative... Micron Technology Inc

02/15/18 / #20180047747

Three dimensional memory and methods of forming the same

Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the... Micron Technology Inc

02/15/18 / #20180047783

Memory devices and memory device forming methods

Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied... Micron Technology Inc

02/15/18 / #20180047896

Memory cell with independently-sized electrode

Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element... Micron Technology Inc

02/15/18 / #20180048234

Analog assisted digital switch regulator

A device includes a digital switch regulator to supply an output voltage and a first current to a load based on a reference voltage. The device also includes an analog circuit to supply a second current to the load in addition to the first current based on a duty cycle... Micron Technology Inc








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