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Mie Fujitsu Semiconductor Limited patents


Recent patent applications related to Mie Fujitsu Semiconductor Limited. Mie Fujitsu Semiconductor Limited is listed as an Agent/Assignee. Note: Mie Fujitsu Semiconductor Limited may have other listings under different names/spellings. We're not affiliated with Mie Fujitsu Semiconductor Limited, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Mie Fujitsu Semiconductor Limited-related inventors


Semiconductor device manufacturing method

A method of manufacturing a semiconductor device includes the following processes. A metal film forming process in which a metal film including cobalt is formed on a surface of silicon. ... Mie Fujitsu Semiconductor Limited

Digital circuits having improved transistors, and methods therefor

Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. ... Mie Fujitsu Semiconductor Limited

Buried channel deeply depleted channel transistor

Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. ... Mie Fujitsu Semiconductor Limited

Semiconductor device

There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. ... Mie Fujitsu Semiconductor Limited

Semiconductor integrated circuit and design method thereof

A semiconductor integrated circuit includes a bus signal line and a test signal line arranged adjacent to the bus signal line. The semiconductor integrated circuit has a system mode, which is an operation mode that uses the bus signal line, and a scan mode, which is an operation mode that uses the test signal line. ... Mie Fujitsu Semiconductor Limited

Semiconductor intergrated curcuit apparatus and manufacturing method for same

A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.. ... Mie Fujitsu Semiconductor Limited

Semiconductor device and semiconductor device fabrication method

A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration cx. ... Mie Fujitsu Semiconductor Limited

Method of manufacturing semiconductor device and method of forming mask

A first mask with a first pattern is formed above a substrate, a first portion is formed in or above the substrate using the first mask, a second mask with a second pattern is formed above the substrate, a first positional deviation between the first portion and the second pattern is measured, a second portion is formed in or above the substrate using the second mask, a third mask with a third pattern is formed above the substrate, and a third portion is formed in or above the substrate using the third mask. In the forming the third mask, the third pattern is formed in a material film for the third mask with alignment in consideration of the first positional deviation.. ... Mie Fujitsu Semiconductor Limited

Digital circuits having improved transistors, and methods therefor

Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. ... Mie Fujitsu Semiconductor Limited

Method for manufacturing a semiconductor device having moisture-resistant rings being formed in a peripheral region

A semiconductor device includes a first moisture-resistant ring disposed in a peripheral region surrounding a circuit region on a semiconductor substrate in such a way as to surround the circuit region and a second moisture-resistant ring disposed in the peripheral region in such a way as to surround the first moisture-resistant ring.. . ... Mie Fujitsu Semiconductor Limited

Semiconductor structure with multiple transistors having various threshold voltages

A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. ... Mie Fujitsu Semiconductor Limited

Electronic devices and systems, and methods for making and using the same

Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk cmos process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a deeply depleted channel (ddc) design, allowing cmos based devices to have a reduced σvt compared to conventional bulk cmos and can allow the threshold voltage vt of fets having dopants in the channel region to be set much more precisely. ... Mie Fujitsu Semiconductor Limited

Tipless transistors, short-tip transistors, and methods and circuits therefor

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.. ... Mie Fujitsu Semiconductor Limited

Integrated circuit device body boas circuits and methods

A system having an integrated circuit (ic) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.. . ... Mie Fujitsu Semiconductor Limited

02/09/17 / #20170040419

Advanced transistors with punch through suppression

An advanced transistor with punch through suppression includes a gate with length lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. ... Mie Fujitsu Semiconductor Limited

02/09/17 / #20170040225

Reducing or eliminating pre-amorphization in transistor manufacture

A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. ... Mie Fujitsu Semiconductor Limited

02/09/17 / #20170040064

Semiconductor storage device and data read method

A semiconductor storage device including plural bit lines, plural select gate lines that intersect with the plural bit lines, and plural memory cells that each include a p-channel memory transistor. The semiconductor storage device includes plural p-channel charging transistors that are respectively connected to the plural bit lines, and a charging line that is connected to each of the plurality of charging transistors. ... Mie Fujitsu Semiconductor Limited

01/26/17 / #20170025501

Method for fabricating a transistor device with a tuned dopant profile

A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. ... Mie Fujitsu Semiconductor Limited

01/26/17 / #20170025457

Buried channel deeply depleted channel transistor

Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. ... Mie Fujitsu Semiconductor Limited

01/12/17 / #20170012044

Low power semiconductor transistor structure and method of fabrication thereof

A structure and method of fabrication thereof relate to a deeply depleted channel (ddc) design, allowing cmos based devices to have a reduced σvt compared to conventional bulk cmos and can allow the threshold voltage vt of fets having dopants in the channel region to be set much more precisely. The ddc design also can have a strong body effect compared to conventional bulk cmos transistors, which can allow for significant dynamic control of power consumption in ddc transistors. ... Mie Fujitsu Semiconductor Limited








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