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Mips Technologies Inc
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Mips Technologies Inc patents

Recent patent applications related to Mips Technologies Inc. Mips Technologies Inc is listed as an Agent/Assignee. Note: Mips Technologies Inc may have other listings under different names/spellings. We're not affiliated with Mips Technologies Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Mips Technologies Inc-related inventors




Date Mips Technologies Inc patents (updated weekly) - BOOKMARK this page
12/24/15Resource sharing using process delay
09/18/14Superforwarding processor
09/11/14Apparatus and operating a processor with an operation cache
09/11/14Apparatus and memory operation bonding
09/11/14Apparatus and branch instruction bonding
09/11/14Apparatus and transitive instruction scheduling
09/04/14Branch target buffer with efficient return prediction capability
08/28/14Way lookahead
08/28/14Deferred saving of registers in a shared register pool for a multithreaded microprocessor
08/28/14Precision exception signaling for multiple data architecture
08/28/14Resource sharing using process delay
03/06/14Embedded processor with virtualized security controls using guest identifications, a common kernel address space and operational permissions
01/02/14Carry look-ahead adder with generate bits and propagate bits used for column sums
12/12/13Shared register pool for a multithreaded microprocessor
10/03/13Apparatus and guest and root register sharing in a virtual machine
07/25/13Merged floating point operation using a modebit
06/20/13System and automatic hardware interrupt handling
06/20/13Vector size agnostic single instruction multiple data (simd) processor architecture
06/20/13System for compression of fixed width values in a processor hardware trace
05/23/13Processor with kernel mode access to user space virtual addresses
05/23/13Apparatus and achieving glitch-free clock domain crossing signals
03/14/13Apparatus and low overhead correlation of multi-processor trace information
03/07/13Systems and methods for controlling the use of processing algorithms, and applications thereof
01/31/13Support for multiple coherence domains
12/27/12Apparatus and accelerated hardware page table walk
12/20/12Apparatus and hardware initiation of emulated instructions
12/20/12Programmable memory address
11/15/12Multithreaded operation of a microprocessor cache
08/30/12Software programmable hardware state machines
04/05/12Method and predicting characteristics of incoming data packets to enable speculative processing to reduce processor latency
02/09/12Clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof
02/02/12System and automatic hardware interrupt handling
06/23/11Apparatus and controlling the exclusivity mode of a level-two cache
06/09/11Automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof
04/28/11System and extracting fields from packets having fields spread over more than one register
03/03/11Horizontally-shared cache victims in multiple core processors
03/03/11Alignment and ordering of vector elements for single instruction multiple data processing
03/03/11Method and de-duplication after mirror operation
02/17/11Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
12/09/10Microprocessor with compact instruction set architecture
12/02/10Apparatus and forming a mixed signal circuit with fully customizable analog cells and programmable interconnect
12/02/10Processor core and managing program counter redirection in an out-of-order processor pipeline
11/11/10Variable register and immediate field encoding in an instruction set architecture
08/05/10System and improving memory transfer
05/06/10Apparatus, method and instruction for initiation of concurrent instruction streams in a multithreading microprocessor
05/06/10Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency
04/29/10Context sharing between a streaming processing unit (spu) and a packet management unit (pmu) in a packet processing environment
03/18/10Methods, systems, and computer program products for evaluating electrical circuits from information stored in simulation dump files
02/25/10Data cache way prediction
02/25/10Data cache receive flop bypass
02/04/10Instruction encoding for system register bit set and clear
01/14/10Data cache virtual hint way prediction, and applications thereof
01/07/10Method and global ordering to insure latency independent coherence
12/31/09Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor
12/17/09System and extracting fields from packets having fields spread over more than one register
11/12/09Microprocessor with compact instruction set architecture
10/29/09Apparatus for storing instructions in a multithreading microprocessor
10/01/09Mechanism for maintaining consistency of data written by io devices
10/01/09Providing extended precision in simd vector arithmetic operations
10/01/09Apparatus and condensing trace information in a multi-processor system
10/01/09Apparatus and low overhead correlation of multi-processor trace information
10/01/09Round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor
09/17/09Efficient, scalable and high performance mechanism for handling io requests
08/06/09Configurable instruction sequence generation
07/30/09Virtual processor based security for on-chip memory, and applications thereof
Patent Packs
06/25/09Apparatus and controlling the exclusivity mode of a level-two cache
06/18/09Coherent instruction cache utilizing cache-op execution resources
06/18/09Clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof
05/21/09Processor accessing a scratch pad on-demand to reduce power consumption
05/14/09Interrupt and exception handling for multi-streaming digital processors
05/07/09Hyperjtag system including debug probe, on-chip instrumentation, and protocol
04/30/09Fetch director employing barrel-incrementer-based round-robin use in multithreading microprocessor
04/30/09Automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof
04/02/09Speculative read in a cache coherent microprocessor
03/26/09Semiconductor with hardware locked intellectual property and related methods
03/26/09Support for multiple coherence domains
03/19/09Method and predicting characteristics of incoming data packets to enable speculative processing to reduce processor latency
03/19/09Microprocessor with improved data stream prefetching
03/05/09Low-overhead/power-saving processor synchronization mechanism, and applications thereof
02/19/09Power management for system having one or more integrated circuits
Patent Packs
02/05/09Trace control from hardware and software
02/05/09Apparatus and evaluating a free-running trace stream
12/12/13Shared register pool for a multithreaded microprocessor
01/14/10Data cache virtual hint way prediction, and applications thereof
01/07/10Method and global ordering to insure latency independent coherence







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