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Mosaid Technologies Incorporated
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Mosaid Technologies Incorporated patents

Recent patent applications related to Mosaid Technologies Incorporated. Mosaid Technologies Incorporated is listed as an Agent/Assignee. Note: Mosaid Technologies Incorporated may have other listings under different names/spellings. We're not affiliated with Mosaid Technologies Incorporated, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Mosaid Technologies Incorporated-related inventors




Date Mosaid Technologies Incorporated patents (updated weekly) - BOOKMARK this page
04/02/15Vertical gate stacked nand and row decoder for erase operation
10/16/14U-shaped common-body type cell string
09/18/14Lithography-friendly local read circuit for nand flash memory devices and manufacturing method thereof
08/07/14Dispersion tolerant optical system and method
07/10/14Flash multi-level threshold distribution scheme
07/10/14Nonvolatile memory with split substrate select gates and heirarchical bitline configuration
07/10/14Scalable memory system
07/03/14Hybrid solid-state memory system having volatile and non-volatile memory
06/26/14Package-level integrated circuit connection without top metal pads or bonding wire
06/19/14Modular outlet
06/19/14Packet data id generation for serially interconnected devices
06/05/14Nand flash memory with vertical cell stack structure and manufacturing same
06/05/14Method and providing a packet buffer random access memory
05/22/14Multi-chip package with pillar connection
05/15/14Pll locking control in daisy chained memory system
05/15/14Non-volatile memory device having configurable page size
05/15/14Hierarchical common source line structure in nand flash memory
05/15/14Method and system for programming non-volatile memory with junctionless cells
05/15/14Memory with output control
05/15/14Clock mode determination in a memory system
05/15/14Frequency division multiplexing system with selectable rate
05/01/14Method, apparatus, signals and media, for selecting operating conditions of a genset
05/01/14Method and system for packet processing
05/01/14Flash memory controller having multi mode pin-out
04/24/14Integrated erase voltage path for multiple cell substrates in nonvolatile memory devices
04/24/14Ring-of-clusters network topologies
04/17/14Split block decoder for a nonvolatile memory device
04/17/14Non-volatile semiconductor memory having multiple external power supplies
04/17/14Delay locked loop implementation in a synchronous dynamic random access memory
04/17/14Network architecture for data communication
04/03/14Method and reducing pool starvation in a shared memory switch
04/03/14System and method providing interoperability between cellular and other wireless systems
04/03/14Outlet add-on module
03/27/14Wide frequency range delay locked loop
03/27/14Semiconductor memory asynchronous pipeline
03/20/14Flash memory controller having dual mode pin-out
03/13/14Stacked semiconductor devices including a master device
03/13/14Voltage down converter for high speed memory
02/20/14Local area network for distributing data communication, sensing and control signals
02/06/14System for transmission line termination by signal cancellation
02/06/14Storage system having a heatsink
01/30/14Memory system having a plurality of serially connected devices
01/23/14Nand flash memory having multiple cell substrates
01/16/14Dram memory cells reconfigured to provide bulk capacitance
01/16/14Dynamic traffic rearrangement and restoration for mpls networks with differentiated services capabilities
01/16/14Bridging device having a configurable virtual page size
01/09/14Frequency-doubling delay locked loop
01/09/14Non-volatile memory with dynamic multi-mode operation
01/09/14Dual function compatible non-volatile memory device
01/09/14Simultaneous read and write data transfer
12/26/13Apparatus and methods for carrying out operations in a non-volatile memory cell having multiple memory states
12/26/13Dynamic random access memory and boosted voltage producer therefor
12/19/13Phase change memory word line driver
12/19/13Non-volatile semiconductor memory with page erase
12/12/13High bandwidth memory interface
12/05/13Configurable module and memory subsystem
12/05/13Ring topology status indication
11/28/13Telephone communication system and method over local area network wiring
11/28/13Bridging device having a frequency configurable clock domain
11/21/13Multi-chip package with offset die stacking and making same
09/26/13Termination circuit for on-die termination
09/26/13Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage
09/19/13Flash multi-level threshold distribution scheme
09/19/13Memory controller with flexible data alignment to clock
09/12/13Clock mode determination in a memory system
Patent Packs
09/12/13Multi-hazard alarm system using selectable power-level transmission and localization
09/05/13Memory with output control
09/05/13Error detection and correction codes for channels and memories with incomplete error characteristics
08/22/13Phase-change memory with multiple polarity bits having enhanced endurance and error tolerance
08/22/13Local area network of serial intelligent cells
08/15/13Congestion management in a network
08/15/13Modular outlet
08/15/13Asynchronous id generation
08/08/13Single-strobe operation of memory devices
08/01/13Method and connecting memory dies to form a memory system
08/01/13Semiconductor device having metal lines with slits
07/25/13Method and system for accessing a flash memory device
07/11/13Device, estimating the termination to a wired transmission-line based on determination of characteristic impedance
07/11/13Delay locked loop circuit and method
07/11/13Device selection schemes in multi chip package nand flash memory system
Patent Packs
07/04/13Using interrupted through-silicon-vias in integrated circuits adapted for stacking
07/04/13Multiple-bit per cell (mbc) non-volatile memory apparatus and system having polarity control and programming same
07/04/13Scalable memory system
06/27/13Solid state drive memory system
06/06/13Cpu with stacked memory
06/06/13Non-volatile memory with dynamic multi-mode operation
05/30/13Interposer for stacked semiconductor devices
05/30/13Process, voltage, temperature independent switched delay compensation scheme
05/30/13Memory system and method using stacked memory device dice
05/30/13A telephone outlet for implementing a local area network over telephone lines and a local area network using such outlets
05/23/13Non-volatile memory device having configurable page size
05/23/13Memory module including a plurality of synchronous memory devices
05/16/13Package having stacked memory dies with serially connected buffer dies
05/16/13Delay locked loop implementation in a synchronous dynamic random access memory
05/09/13Distributed network management hierarchy in a multi-station communication network
05/02/13Flash memory module and memory subsystem
04/25/13Stacked semiconductor devices including a master device
04/18/13Connection of multiple semiconductor memory devices with chip enable function
04/04/13Reduced noise dram sensing
04/04/13Serially connected memory having subdivided data interface
03/28/13Flash memory system
03/21/13Method and connecting inlaid chip into printed circuit board
03/21/13Dynamic random access memory with fully independent partial array refresh function
03/21/13Voltage regulation for 3d packages and manufacturing same
03/21/13Memory system with a layer comprising a dedicated redundancy area
03/21/13Apparatus and establishing device identifiers for serially interconnected devices
03/14/13Apparatus and producing device identifiers for serially interconnected devices of mixed type
02/21/13Non-volatile memory bank and page buffer therefor
02/21/13Method of configuring non-volatile memory for a hybrid disk drive
02/14/13Flash memory program inhibit scheme
Social Network Patent Pack
02/14/13Apparatus and producing ids for interconnected devices of mixed type
02/07/13Write scheme in a phase change memory
02/07/13Non-volatile semiconductor memory having multiple external power supplies
01/24/13Phase change memory with double write drivers
01/24/13Double data rate output circuit and method
01/17/13Frequency-doubling delay locked loop
01/17/13Semiconductor memory device having a three-dimensional structure
01/10/13Memory device and repairing a semiconductor memory
01/10/13Dynamic random access memory device and self-refreshing memory cells with temperature compensated self-refresh
01/10/13Network combining wired and non-wired segments
Patent Packs
01/03/13Independent link and bank selection
01/03/13Wide frequency range delay locked loop
01/03/13Flow-fill spacer structures for flat panel display device
12/20/12Multi-level cell access buffer with dual function
12/20/12Dual function compatible non-volatile memory device
12/20/12Pre-charge voltage generation and power saving modes
12/06/12Initialization circuit for delay locked loop
12/06/12Telephone communication system over a single telephone line
10/18/12Source side asymmetrical precharge programming scheme
10/04/12Non-volatile semiconductor memory with page erase
09/27/12Trunking in a matrix
09/20/12Barrier-metal-free copper damascene technology using enhanced reflow
09/13/12Word line driver in flash memory
08/30/12Nand flash architecture with multi-level row decoding
08/30/12Port packet queuing
08/23/12Vertical transistor having a gate structure formed on a buried drain region and a source region overlying the upper most layer of the gate structure
08/23/12Circuit for clamping current in a charge pump
08/23/12Non-volatile memory devices and control and operation thereof
08/23/12Memory with output control
08/09/12Dynamic traffic rearrangement and restoration for mpls networks with differentiated services capabilities
07/26/12Intermediate cache and system with client interface routine connecting server to clients
07/26/12Universal remote control protocol transcoder
07/19/12Local area network for distributing data communication, sensing and control signals
07/12/12Voltage down converter for high speed memory
07/05/12Data flow control in multiple independent port
06/28/12Frequency division multiplexing system with selectable rate
06/07/12Semiconductor memory asynchronous pipeline
05/31/12Bridge device architecture for connecting discrete memory devices to a system
05/31/12Method and providing a packet buffer random access memory
05/24/12Method and sharing internal power supplies in integrated circuit devices
Patent Packs
05/17/12Wiring
05/17/12Mixed composition interface layer and forming
05/10/12Flexible memory operations in nand flash devices
05/03/12Method and device for tunable optical filtering
04/26/12Charge pump for pll/dll
04/19/12Method, system and multi-level processing
04/12/12Phase-change memory with multiple polarity bits having enhanced endurance and error tolerance
04/12/12Flash multi-level threshold distribution scheme
03/22/12Dynamic random access memory and boosted voltage producer therefor
03/15/12System and page buffer operation for memory devices
03/08/12Multi-chip package with offset die stacking
03/08/12System for transmission line terminatino by signal cancellation
02/09/12Non-volatile memory device having configurable page size
02/02/12Modular outlet
01/26/12Dynamic impedance control for input/output buffers
01/26/12Multipage program scheme for flash memory
01/26/12Power supplies in flash memory devices and systems
01/26/12Non-volatile memory with dynamic multi-mode operation
01/26/12Apparatus and page program operation for memory devices with mirror back-up of data
01/12/12High speed dram architecture with uniform access latency
Social Network Patent Pack
01/05/12Multi-chip package with thermal frame and assembling
01/05/12Systems and methods for minimizing static leakage of an integrated circuit
12/29/11Apparatus and modeling coarse stepsize delay element and delay locked loop using same
12/29/11Method and optical phase modulation
12/29/11Phase change memory word line driver
12/29/11Multiple-bit per cell (mbc) non-volatile memory apparatus and system having polarity control and programming same
12/22/11Apparatus and using a page buffer of a memory device as a temporary cache
12/08/11Multi-chip package with pillar connection
12/08/11Flash memory program inhibit scheme
12/08/11Modular outlet
12/01/11Wide frequency range delay locked loop
12/01/11High-speed interface for daisy-chained devices
11/24/11Method and reducing pool starvation in a shared memory switch
11/10/11Method and concurrently reading a plurality of memory devices using a single buffer
11/03/11Non-volatile semiconductor memory with page erase
10/27/11Low leakage and data retention circuitry
10/27/11Phase change memory array blocks with alternate selection
10/27/11Write scheme in phase change memory
10/27/11System of interconnected nonvolatile memories having automatic status packet
10/20/11Method and system for accessing a flash memory device
Social Network Patent Pack
10/20/11Status indication in a system having a plurality of memory devices
10/20/11Apparatus and identifying device types of series-connected devices of mixed type
10/13/11Memory programming using variable data width
10/06/11Three-dimensional phase change memory
10/06/11Dual function compatible non-volatile memory device
09/29/11Bias generator providing for low power, self-biased delay element and delay line
09/29/11Hierarchical common source line structure in nand flash memory
09/29/11Flash memory system having a plurality of serially connected devices
09/29/11Non-volatile memory devices and control and operation thereof
09/15/11Multi-level cell access buffer with dual function
09/01/11Embedded memory databus architecture
08/25/11Circuit for clamping current in a charge pump
08/25/11Method and processing arbitrary key bit length encryption operations with similar efficiencies
08/18/11Semiconductor memory asynchronous pipeline
08/11/11Source side asymmetrical precharge programming scheme
08/11/11Bridge device architecture for connecting discrete memory devices to a system
07/28/11Apparatus and producing device identifiers for serially interconnected devices of mixed type
07/21/11Independent link and bank selection
07/14/11Nand flash memory having multiple cell substrates
07/14/11Temperature detector in an integrated circuit
07/14/11Dynamic random access memory with fully independent partial array refresh function
07/07/11Method for stacking serially-connected integrated circuits and multi-chip device made from same
06/23/11Hybrid solid-state memory system having volatile and non-volatile memory
06/23/11System and operating memory devices of mixed type
06/23/11Data channel test apparatus and method thereof
06/16/11Circuit and testing multi-device systems
06/02/11Modular command structure for memory and memory system
06/02/11Apparatus and page program operation for memory devices with mirror back-up of data
05/12/11Delay locked loop circuit
05/12/11Stacked semiconductor devices including a master device
Social Network Patent Pack
05/12/11Clock mode determination in a memory system
05/12/11Method and reducing the amplitude modulation of optical signals in external cavity lasers
05/12/11Barrier-metal-free copper camascence technology using atomic hydrogen enhanced reflow
05/05/11Charge pump for pll/dll
05/05/11Dynamic random access memory device and self-refreshing memory cells
04/28/11Process, voltage, temperature independent switched delay compensation scheme
04/28/11Single-strobe operation of memory devices
04/28/11Outlet with analog signal adapter, a use thereof and a network using said outlet
04/28/11Modular outlet
04/21/11Reconfiguring through silicon vias in stacked multi-die packages
04/14/11Apparatus and producing ids for interconnected devices of mixed type
04/07/11System and method providing interoperability between cellular and other wireless systems
03/24/11Semiconductor device having metal lines with slits
03/24/11Non-volatile semiconductor memory with page erase
03/17/11Timing vernier using a delay locked loop
03/03/11Using interrupted through-silicon-vias in integrated circuits adapted for stacking
02/24/11Dynamic impedance control for input/output buffers
02/17/11Package-level integrated circuit connection without top metal pads or bonding wire
02/17/11Telephone communication system and method over local area network wiring
02/10/11Power supplies in flash memory devices and systems
01/20/11Non-volatile memory serial core architecture
01/20/11Apparatus and producing identifiers regardless of mixed device type in a serial interconnection
01/20/11Simultaneous read and write data transfer
01/20/11Synchronous memory read data capture
01/13/11Flash multi-level threshold distribution scheme
01/06/11Memory with output control
12/30/10Bridging device having a frequency configurable clock domain
12/30/10Method and synchronization of row and column access operations
12/30/10Apparatus and capturing serial input data







ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009



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