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Mosys Inc
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Mosys Inc patents

Recent patent applications related to Mosys Inc. Mosys Inc is listed as an Agent/Assignee. Note: Mosys Inc may have other listings under different names/spellings. We're not affiliated with Mosys Inc, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "M" | Mosys Inc-related inventors




Date Mosys Inc patents (updated weekly) - BOOKMARK this page
06/30/16Integrated main memory and coprocessor with low latency
06/30/16Integrated main memory and coprocessor with low latency
06/09/16Hybrid driver circuit
01/21/16Method and randomizer
09/17/15Delay-locked loop with independent phase adjustment of delayed clock output pairs
08/27/15Delay-locked loop with dual loop filters for fast response and wide frequency and delay range
01/15/15Partitioned memory with shared memory resources and configurable functions
10/23/14Memory device with background built-in self-repair using background built-in self-testing
08/07/14Delay-locked loop with dual loop filters for fast response and wide frequency and delay range
07/31/14Delay-locked loop with independent phase adjustment of delayed clock output pairs
03/20/14Programmable memory built in self repair circuit
03/20/14Substitute redundant memory
12/26/13Pseudo-supply hybrid driver
12/19/13Hierarchical multi-bank multi-port memory organization
12/12/13Memory with bank-conflict-resolution (bcr) module including cache
11/28/13Semiconductor chip layout with staggered tx and tx data liness
07/04/13Methods and circuits for adjusting parameters of a transceiver
07/04/13Memory device with background built-in self-testing and background built-in self-repair
06/20/13Delay-locked loop with phase adjustment
03/28/13Low noise bias circuit for a pll oscillator
01/03/13Memory device including a memory block having a fixed latency data output
10/25/12Integrated circuit package with segregated tx and rx data channels
10/04/12Separate pass gate controlled sense amplifier
10/04/12Methods for accessing dram cells using separate bit line control
08/30/12Reducing latency in serializer-deserializer links
06/07/12Multiple cycle memory write completion
03/22/12Vlsi package for high performance integrated circuit
03/08/12Non-volatile memory system with modified memory cells
03/01/12Voltage-mode driver with equalization
02/23/12Data synchronization for circuit resources without using a resource buffer
02/02/12System with logic and embedded mim capacitor
02/02/12Method of forming a mim capacitor
02/02/12Semiconductor chip layout
09/29/11Method and circuit for testing and characterizing high speed signals using an on-chip oscilloscope
09/08/11Reliability protection for non-volatile memories
08/25/11Programmable test engine (pcdte) for emerging memory technologies
08/04/11Reducing latency in serializer-deserializer links
08/04/11Hierarchical multi-bank multi-port memory organization
08/04/11High utilization multi-partitioned serial memory
08/04/11Hierarchical organization of large memory blocks
06/23/11Three state word line driver fora dram memory device
06/16/11Method and restoring data in a non-volatile memory
04/14/11Multiple cycle memory write completion
10/28/10Signal alignment system
10/28/10Porting analog circuit designs
09/16/10Multi-bank multi-port architecture
08/19/10Two bits per cell non-volatile memory architecture
08/12/10Data restoration a non-volatile memory
08/12/10Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard cmos logic process
06/10/10Double polysilicon process for non-volatile memory
05/13/10Embedded dram with bias-independent capacitance
05/13/10Embedded dram with multiple gate oxide thicknesses
12/12/13Memory with bank-conflict-resolution (bcr) module including cache







ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009



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