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Nanya Technology Corp patents


Recent patent applications related to Nanya Technology Corp. Nanya Technology Corp is listed as an Agent/Assignee. Note: Nanya Technology Corp may have other listings under different names/spellings. We're not affiliated with Nanya Technology Corp, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "N" | Nanya Technology Corp-related inventors


 new patent  Three dimensional integrated circuit package and method for manufacturing thereof

A three dimensional integrated circuit (3dic) package includes a redistribution layer, a plurality of semiconductor chips and a plurality of electrical bumpers. The redistribution layer has a first surface and a second surface. ... Nanya Technology Corp

Semiconductor structure and a manufacturing method thereof

A semiconductor structure includes a first package including a substrate and a die disposed over the substrate and electrically connected to the substrate by a first conductive bump; a second package disposed over the first package and electrically connected to the substrate by a second conductive bump; and an adhesive disposed between the die and the second package.. . ... Nanya Technology Corp

Semiconductor package

A semiconductor package includes a first device; a second device laterally adjacent to the first device; a molding member encapsulating the first device and the second device; and a lateral bump structure implementing a lateral signal path between the first device and the second device. A portion of the molding member is disposed between the first device and the second device.. ... Nanya Technology Corp

Method for preparing a wafer level chip-on-chip semiconductor structure

A method for preparing a wafer level chip-on-chip semiconductor structure. The semiconductor structure includes a first semiconductor device; at least one conductive member disposed over the first semiconductor device; a second semiconductor device disposed over the first semiconductor device; a molding member disposed over the first semiconductor device; and a redistribution layer (rdl) disposed over the second semiconductor device and the at least one conductive member. ... Nanya Technology Corp

Wafer level chip-on-chip semiconductor structure

A semiconductor structure includes a first semiconductor device; at least one conductive member disposed over the first semiconductor device; a second semiconductor device disposed over the first semiconductor device; a molding member disposed over the first semiconductor device; and a redistribution layer (rdl) disposed over the second semiconductor device and the at least one conductive member. The molding member surrounds the second semiconductor device and the at least one conductive member. ... Nanya Technology Corp

Semiconductor stacking structure and method for manufacturing thereof

A semiconductor stacking structure is provided. The semiconductor stacking structure includes a substrate and at least one conductor. ... Nanya Technology Corp

Stacked package structure and manufacturing method thereof

A stacked package structure includes a first package structure having a first surface and a second surface opposite to the first surface. The first package structure includes a least one first die having a first active region disposed at a bottom of the first die; a first redistribution layer disposed on the top surface of the first die; and a plurality of first bumps disposed on the bottom surface of the first active region.. ... Nanya Technology Corp

Semiconductor package and manufacturing method thereof

A semiconductor package includes a package substrate, a first semiconductor chip, a second semiconductor chip, and a top interposer. The first semiconductor chip and the second semiconductor chip are disposed on the package substrate. ... Nanya Technology Corp

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface and a recess recessed from the first surface towards the second surface; a conductive layer disposed over the first surface and within the recess; and a passivation disposed over the first surface and partially covering the conductive layer, wherein the conductive layer disposed within the recess is exposed from the passivation.. . ... Nanya Technology Corp

Method for forming semiconductor package

A method of fabricating semiconductor packages includes providing an interposer layer having a first surface and a second surface opposite to the first surface, in which the interposer layer includes through interposer vias embedded inside, and the through interposer vias extended from the first surface toward the second surface, in which through interposer vias are patterned to form repetitive polygonal-packing units, and part of the through interposer vias can be grouped within at least two distinct said polygonal-packing units; subsequently, forming at least one redistribution layer on the first surface to form terminals on a surface of the redistribution layer away from the interposer layer, in which the terminals are selectively connected to the through interposer vias respectively; and then disposing at least one semiconductor chip on the redistribution layer, wherein the semiconductor chip includes active surfaces electrically connected to the terminals respectively.. . ... Nanya Technology Corp

Semiconductor structure

A semiconductor structure includes a substrate; a chip disposed over the substrate; and a molding disposed over the substrate and surrounding the chip at a molding temperature. The warpage of the substrate is convex or about zero at the molding temperature or 10° c. ... Nanya Technology Corp

Semiconductor package and manufacturing method thereof

A semiconductor package includes a semiconductor chip, an interposer, a first redistribution layer, and a molding compound. The semiconductor chip has a first surface and a second surface opposite to the first surface and at least one sidewall connected to the first surface and the second surface. ... Nanya Technology Corp

Semiconductor package and method for forming the same

A method for forming semiconductor packages includes disposing at least one flow hindering supporter onto a substrate, in which the substrate has at least one active region and at least one gap region surrounded the active region, the flow hindering supporter is located on the gap region; subsequently, disposing at least one die structure onto the active region of the substrate respectively; and then injecting a molding compound flowed into the gap region, to mold the flow hindering supporter and the die structure with the molding compound.. . ... Nanya Technology Corp

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface and a recess recessed from the first surface towards the second surface; a conductive layer disposed over the first surface and within the recess; and a passivation disposed over the first surface and partially covering the conductive layer, wherein the conductive layer disposed within the recess is exposed from the passivation.. . ... Nanya Technology Corp

03/22/18 / #20180082963

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate; a pad disposed over the substrate; a first passivation disposed over the substrate, partially covering the pad, and including a protrusion protruded from the first passivation and away from the substrate; a conductive layer disposed over the first passivation and a portion of the pad exposed from the first passivation; and a second passivation disposed over the conductive layer, wherein the conductive layer disposed over the protrusion is exposed from the second passivation.. . ... Nanya Technology Corp

03/22/18 / #20180082934

Semiconductor package and method for fabricating the same

A method of fabricating semiconductor packages includes providing an interposer layer having a first surface and a second surface opposite to the first surface, in which the interposer layer includes through interposer vias embedded inside, and the through interposer vias extended from the first surface toward the second surface, in which through interposer vias are patterned to form repetitive polygonal-packing units, and part of the through interposer vias can be grouped within at least two distinct said polygonal-packing units; subsequently, forming at least one redistribution layer on the first surface to form terminals on a surface of the redistribution layer away from the interposer layer, in which the terminals are selectively connected to the through interposer vias respectively; and then disposing at least one semiconductor chip on the redistribution layer, wherein the semiconductor chip includes active surfaces electrically connected to the terminals respectively.. . ... Nanya Technology Corp

02/08/18 / #20180040575

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; a pad disposed over the first surface; a first passivation disposed over the first surface and partially covering the pad; a redistribution layer (rdl) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line. The conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, wherein the land portion includes a plurality of first protrusions protruded away from the first passivation.. ... Nanya Technology Corp

01/18/18 / #20180019174

Semiconductor device and method for manufacturing the same

One aspect of the present disclosure provides a semiconductor device. In some embodiments, the semiconductor device includes an integrated circuit die, at least one conductive terminal disposed on the integrated circuit die, a frame positioned on the integrated circuit die, wherein the frame substantially exposes the at least one conductive terminal, and at least one conductive bump positioned in the frame, wherein the at least one conductive bump electrically connects the at least one conductive terminal.. ... Nanya Technology Corp

01/18/18 / #20180015569

Chip and method of manufacturing chips

A method of manufacturing chips from a semiconductor wafer having a plurality of streets on a front surface of the semiconductor wafer is provided. The method includes: forming a plurality of crack stopping structures on the semiconductor wafer at locations respectively aligned with intersections of the streets; irradiating a laser beam focused inside the semiconductor wafer along the streets to induce cracks; and breaking the irradiated semiconductor wafer along the cracks to the crack stopping structures, so as to separate the irradiated semiconductor wafer into the chips.. ... Nanya Technology Corp

12/28/17 / #20170373003

Semiconductor chip and multi-chip package using thereof

The present disclosure provides a semiconductor chip having a non-through plug contour (buried alignment mark) for stacking aligmnent and a multi-chip semiconductor device employing thereof, and to a method for manufacturing same. In some embodiments, the semiconductor chip includes a semiconductor substrate having a first side and a second side, a conductive through plug extending through the semiconductor substrate from the first side to the second side, and a non-through plug extending from the first side to an internal plane of the semiconductor substrate without extending through the second side.. ... Nanya Technology Corp

10/12/17 / #20170294380

Semiconductor device and method for forming the same

A semiconductor device with a ring structure surrounding a through silicon via (tsv) electrode and a method for forming the same are disclosed. The method includes receiving a substrate including a back side and a front side having a conductor thereon, forming a via hole in the substrate and exposing the conductor, forming a groove extending from the back side into the substrate and surrounding the via hole, forming a first material layer in the via hole, and forming a second material layer in the groove. ... Nanya Technology Corp

09/14/17 / #20170263536

Chip package having tilted through silicon via

A chip package includes at least one integrated circuit die. The integrated circuit die includes a substrate portion having an internal plane between a front side and a back side, an electrical interconnect portion on the front side, a plurality of first connection terminals on an upper surface of the electrical interconnect portion, a plurality of second connection terminals on the back side of the substrate portion, a plurality of connection wirings electrically connecting the first connection terminals and the second connection terminals, a chip selection terminal between the internal plane of the substrate portion and the upper surface of the electrical interconnect portion, and a chip selection wiring connected to the chip selection terminal and one of the second connection terminals and the first connection terminals. ... Nanya Technology Corp

06/08/17 / #20170162411

Tray

A tray for holding an integrated circuit component includes a base frame and at least a pair of supporting walls. The supporting walls are connected to the base frame. ... Nanya Technology Corp

05/11/17 / #20170133230

Semiconductor device having vertical silicon pillar transistor

A semiconductor device includes a transistor disposed on a substrate, a first insulation layer, a second insulation layer, an epitaxy and a conductive material. The first insulation layer is disposed on the substrate and protruding over the transistor. ... Nanya Technology Corp

01/19/17 / #20170018305

Electronic apparatus applying unified non-volatile memory and unified non-volatile memory controlling method

An electronic apparatus comprising a unified non-volatile memory and a control unit is disclosed. The unified non-volatile memory comprises a first memory section, served as a read only memory; and a second memory section, served as a random access memory. ... Nanya Technology Corp








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