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Nanya Technology Corporation
Nanya Technology Corporation_20100128
  

Nanya Technology Corporation patents

Recent patent applications related to Nanya Technology Corporation. Nanya Technology Corporation is listed as an Agent/Assignee. Note: Nanya Technology Corporation may have other listings under different names/spellings. We're not affiliated with Nanya Technology Corporation, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "N" | Nanya Technology Corporation-related inventors




Date Nanya Technology Corporation patents (updated weekly) - BOOKMARK this page
10/12/17Semiconductor device and forming the same
09/14/17Chip package having tilted through silicon via
06/08/17Tray
05/25/17Dynamic random access memory circuit and voltage controlling method thereof
05/11/17Semiconductor device having vertical silicon pillar transistor
10/20/16Semiconductor device and fabricating the same
10/06/16Etching process in capacitor process of dram using a liquid etchant composition
08/25/16Wire bonding method
03/31/16Chip package and forming the same
03/17/16Pitch-halving integrated circuit process
02/25/16Method for checking result of chip probing test and chip thereof
09/24/15Three dimensional integrated circuit and controlling the same
09/17/15Power generator for data line of memory apparatus
08/27/15Method for clock control in dynamic random access memory devices
07/23/15Liquid etchant composition, and etching process in capacitor process of dram using the same
07/23/15Memory device and control method
07/23/15Method of modifying polysilicon layer through nitrogen incorporation for isolation structure
07/23/15Method of forming an interconnect structure with high process margins
07/16/15Chip package
07/02/15Box-in-box overlay mark
04/30/15Integrated circuit device
04/23/15Memory process
04/09/15Method for manufacturing semiconductor device
04/09/15Multi-die stack structure
03/26/15Chip package and forming the same
03/19/15Semiconductor device and fabricating the same
03/05/15Low power protection circuit
02/19/15Method and layout for detecting die cracks
02/19/15Glitch filter and filtering method
02/19/15Temperature detecting apparatus, switch capacitor apparatus and voltage integrating circuit thereof
02/19/15Delay line ring oscillation apparatus
02/12/15Data buffer system and power control method
02/05/15Method for fabricating semiconductor device
01/29/15Method for semiconductor self-aligned patterning
01/08/15Method and layout for detecting die cracks
12/04/14Circuit in dynamic random access memory devices
11/06/14Voltage tracking circuit
09/18/14Pitch-halving integrated circuit process and integrated circuit structure made thereby
09/18/14Clock cycle compensator and the method thereof
09/18/14Duty cycle corrector
09/11/14Method for fabricating semiconductor device
09/11/14Semiconductor device and fabricating the same
07/31/14Method of forming buried word line structure
07/24/14Alignment mark and manufacturing the same
03/20/14Double patterning process
03/20/14Method of generating assistant feature
03/06/14External programmable dfe strength
03/06/14Overlay mark and forming the same
02/27/14Semiconductor device and fabrication method therof
02/27/14Memory process and memory structure made thereby
02/20/14Phase-locked loop and clock delay adjustment
02/13/14Dram structure with buried word lines and fabrication thereof, and ic structure and fabrication thereof
02/13/14Circuit test system and circuit test method thereof
02/06/14Cassette tray and carrier module
02/06/14Memory device and manufacturing memory structure
02/06/14Voltage generating system and memory device using the same
01/23/14Semiconductor device having vertical gates and fabrication thereof
01/23/14Three-dimensional integrated circuits and fabrication thereof
01/09/14Connecting structure of circuit board
01/02/14Copper interconnect structure and fabricating thereof
12/19/13Mask pattern analysis analyzing mask pattern
12/19/13Method of fabricating semiconductor device
12/05/13Transistor device and manufacturing the same
12/05/13Semiconductor device and manufacturing the same
12/05/13Reflective mask
Patent Packs
11/21/13Electrostatic discharge protection circuit
11/21/13Method for forming patterns of dense conductor lines and their contact pads, and memory array having dense conductor lines and contact pads
11/21/13Voltage doubler and oscillating control signal generator thereof
11/14/13Memory device and manufacturing memory device
11/14/13Dynamic random access memory with multiple thermal sensors disposed therein and control method thereof
10/17/13Method for forming buried conductive line and structure of buried conductive line
09/26/13Through silicon via structure and fabricating the same
07/18/13Semiconductor device and fabricating thereof
07/18/13Overlay mark and application thereof
07/18/13Memory device and fabricating the same
07/18/13Method of fabricating memory device
07/04/13Mask overlay method, mask, and semiconductor device using the same
06/27/13Transistor structure and preparing the same
06/27/13Photomask and forming overlay mark using the same
06/20/13Photomask
Patent Packs
06/06/13Test driving apparatus and circuit testing interface thereof
04/25/13Vertical mosfet electrostatic discharge device
04/25/13Method for fabricating single-sided buried strap in a semiconductor device
04/04/13Circuit test interface and test method thereof
03/28/13Wafer scrubber
03/28/13Memory apparatus
03/28/13Method for forming dope regions with rapid thermal process
03/28/13Method for fabricating integrated devices with reducted plasma damage
03/28/13Method for forming semiconductor structure with reduced line edge roughness
03/21/13Wafer scrubber apparatus
03/21/13Fabricating transistor
03/21/13Semiconductor process
02/28/13Interactive digital duty cycle compensation circuit for receiver
02/28/13Method and implementing slice-level adjustment
02/28/13Method of forming conductive pattern
02/21/13Method for forming fin-shaped semiconductor structure
01/17/13Method of forming isolation structure
01/17/13Process of forming slit in substrate
01/17/13Method for forming openings in semiconductor device
01/03/13Corner transistor and fabricating the same
12/06/12Semiconductor process
12/06/12Semiconductor process
11/29/12Overlay mark and fabricating the same
11/29/12Plasma etching method and plasma etching preparing high-aspect-ratio structures
11/29/12Method for implanting wafer
11/29/12Method for manufacturing memory device
11/29/12Method for via formation in a semiconductor device
11/29/12Pulse-plasma etching method and pulse-plasma etching apparatus
11/29/12Method and system for performing pulse-etching in a semiconductor device
11/22/12Dram structure with buried word lines and fabrication thereof, and ic structure and fabrication thereof
Social Network Patent Pack
11/22/12Test key structure for monitoring gate conductor to deep trench misalignment and testing method thereof
11/22/12Method for manufacturing memory device
11/08/12Method for increasing adhesion between polysilazane and silicon nitride
11/01/12Integrated circuit structure including a copper-aluminum interconnect and fabricating the same
11/01/12Integrated circuit structure including copper-aluminum interconnect and fabricating the same
11/01/12Memory circuit and control method thereof
11/01/12Method for forming trench isolation
11/01/12Method of oxidizing polysilazane
11/01/12Methods for fabricating a gate dielectric layer and for fabricating a gate structure
11/01/12Method for fabricating a gate dielectric layer and for fabricating a gate structure
Patent Packs
10/25/12Method for forming self-aligned contact
10/25/12Capacitor and manufacturing method thereof
10/25/12Method for preparing contact plug structure
10/25/12Method of bevel trimming three dimensional semiconductor device
10/25/12Manufacturing gate dielectric layer
10/25/12Manufacturing gate dielectric layer
10/25/12Polishing pad wear detecting apparatus
10/18/12Chemical mechanical polishing method
10/18/12Method of fabricating semiconductor component
10/18/12Distance monitoring device
10/18/12Membrane
10/11/12Monitoring pattern, and pattern stitch monitoring method and wafer therewith
10/11/12Arc residue-free etching
10/11/12Model of defining a photoresist pattern collapse rule, and photomask layout, semiconductor substrate and improving photoresist pattern collapse
10/11/12Method for matching assistant feature tools
10/04/12Isolation structure and device structure including the same
09/27/12Integrated circuit structure
09/20/12Photomask and a determining a pattern of a photomask
08/23/12Synchronous signal generating circuit
08/02/12Differential receiver
07/26/12Method for fabricating dielectric layer with improved insulating properties
07/12/12Methods for fabricating semiconductor devices and semiconductor devices using the same
06/21/12Gate structure
06/14/12Method for fabricating trench isolation structure
06/14/12Manufacturing device and planarization process
06/07/12Dynamic wafer alignment method in exposure scanner system
05/24/12Integrated circuit device and preparing the same
03/22/12Measured device and test system utilizing the same
03/08/12Seminconductor device and fabrications thereof
03/08/12Stack capacitor of memory device and fabrication method thereof
Patent Packs
02/16/12Semiconductor device and fabricating method thereof
02/09/12Integrated circuit structure with through via for heat evacuating
12/29/11Data programming circuits and memory programming methods
12/01/11Carrier for chip packages
09/22/11Method of patterning metal alloy material layer having hafnium and molybdenum
09/15/11Immersion lithographic apparatuses
06/30/11Fabricating vertical transistor
06/23/11Stack capacitor of memory device and fabrication method thereof
04/28/11Method of forming funnel-shaped opening
04/14/11Cross point memory array devices
04/14/11Test electronic device package and testing electronic device package
04/14/11Integrated circuits modeling manufacturing procedure and manufacturing system utilizing the same
04/14/11Robot parts assembly on a workpiece moving on an assembly line
04/07/11Vertical transistor and array of vertical transistor
04/07/11Litho-litho etch (lle) double patterning methods
03/24/11Sensing circuit for sensing electric fuse and sensing method thereof
03/10/11Semiconductor manufacturing process
01/06/11Illegal command handling
12/23/10Patterning method
12/16/10Method for fabricating opening
Social Network Patent Pack
12/09/10Method of forming carbon-containing layer
11/04/10Manufacturing non-volatile memory
08/12/10Nonvolatile memory device and fabricating the same
08/12/10Manufacturing dynamic random access memory
07/29/10Operation suppressing current leakage in a memory and access the same
06/03/10Method for fabricating a semiconductor device
04/29/10Vertical transistor and fabricating method thereof and vertical transistor array
04/22/10Scanning exposure method
04/22/10Flash memory and flash memory array
03/11/10Method for fabricating device pattern
02/25/10Method of fabricating a phase-change memory
02/18/10Vertical transistor and array with vertical transistors
01/28/10Deep trench device with single sided connecting structure and fabrication method thereof
11/26/09Tester with low signal attenuation
10/15/09Dram and memory array
10/15/09Operation memory
10/08/09Multi-chip stack package
10/08/09Method for suppressing current leakage in memory
09/10/09Chip test apparatus and probe card circuit
07/09/09Method for controlling access of a memory
Social Network Patent Pack
07/02/09Memory device with a length-controllable channel
07/02/09Semiconductor chip package
07/02/09Random access memory data resetting method
06/18/09Method of forming iso space pattern
06/11/09Etchant for metal alloy having hafnium and molybdenum
06/11/09Stacked-type chip package structure and fabrication method thereof
06/11/09Random access memory and data refreshing method thereof
06/11/09Method of fabricating semiconductor device having a recess channel structure therein
05/21/09Non-volatile memory and the manufacturing method thereof
04/30/09Dram stack capacitor and fabrication method thereof
04/30/09Flash memory
04/30/09Exposure method
04/16/09Memory device and fabrication thereof
04/09/09Elevated channel flash device and manufacturing method thereof
04/02/09Two-bit flash memory
04/02/09Interconnect manufacturing process
03/19/09Method for manufacturing a flash memory device
03/12/09Non-volatile memory and manufacturing method thereof
03/12/09Semiconductor devices and fabrication methods thereof
03/12/09Method for fabricating a semiconductor device
03/05/09Window-type ball grid array package structure and fabricating method thereof
03/05/09Method for manufacturing trench isolation structure and non-volatile memory
03/05/09Method for fabricating dynamic random access memory
03/05/09Nonvolatile memory device and fabricating the same
02/19/09Non-volatile memory and manufacturing method thereof
02/19/09Method of manufacturing non-volatile memory
02/05/09Memory device and manufacturing method thereof
01/28/10Deep trench device with single sided connecting structure and fabrication method thereof







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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