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Netspeed Systems
Netspeed Systems Inc
  

Netspeed Systems patents

Recent patent applications related to Netspeed Systems. Netspeed Systems is listed as an Agent/Assignee. Note: Netspeed Systems may have other listings under different names/spellings. We're not affiliated with Netspeed Systems, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "N" | Netspeed Systems-related inventors




Date Netspeed Systems patents (updated weekly) - BOOKMARK this page
08/10/17Verification low power collateral generation
08/10/17Generating physically aware network-on-chip design from a physical system-on-chip specification
04/13/17Clock gating for system-on-chip elements
03/02/17Automatic generation of power management sequence in a soc or noc
03/02/17Hardware and software enabled implementation of power profile management instructions in system on chip
03/02/17Transaction expansion for noc simulation and noc design
03/02/17Automatic generation of physically aware aggregation/distribution networks
03/02/17Automatic performance characterization of a network-on-chip (noc) interconnect
03/02/17System level simulation in network on chip architecture
03/02/17Automatic pipelining of noc channels to meet timing and/or performance
03/02/17Supporting multicast in noc interconnect
03/02/17Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip
03/02/17Hierarchical asymmetric mesh with virtual routers
03/02/17Clock gating for system-on-chip elements
03/02/17Configurable router for a network on chip (noc)
03/02/17System and grouping of network on chip (noc) elements
03/02/17Heterogeneous soc ip core placement in an interconnect to optimize latency and interconnect performance
03/02/17Generation of network-on-chip layout based on user specified topological constraints
03/02/17Heterogeneous channel capacities in an interconnect
03/02/17Qos in a system with end-to-end flow control and qos aware buffer allocation
03/02/17Automatic buffer sizing for optimal network-on-chip design
06/02/16Integrated noc for performing data communication and noc functions
12/24/15Using cuckoo movement for improved cache coherency
12/10/15Transactional traffic specification for network-on-chip design
11/12/15System and improving snoop performance
10/08/15Integrated noc for performing data communication and noc functions
10/08/15Systems and methods for selecting a router to connect a bridge in the network on chip (noc)
08/20/15Qos in a system with end-to-end flow control and qos aware buffer allocation
07/02/15Cache coherent noc with flexible number of cores, i/o devices, directory structure and coherency points
07/02/15Streaming bridge design with host interfaces and network on chip (noc) layers
06/25/15Automatic pipelining of noc channels to meet timing and/or performance
05/21/15Reuse of directory entries for holding state information
04/30/15Using multiple traffic profiles to design a network on chip
04/16/15Noc interface protocol adaptive to varied host interface protocols
02/19/15Combining associativity and cuckoo hashing
02/12/15Supporting multicast in noc interconnect
02/05/15Automatic noc topology generation
01/29/15System level simulation in network on chip architecture
01/15/15Identification of internal dependencies within system components for evaluating potential protocol level deadlocks
12/25/14Multiple clock domains in noc
10/09/14Multiple heterogeneous noc layers
07/31/14Creating multiple noc layers for isolation or avoiding noc traffic congestion
07/24/14Automatic deadlock detection and avoidance in a system interconnect by capturing internal dependencies of ip cores using high level specification
07/24/14Qos in heterogeneous noc by assigning weights to noc node channels and using weighted arbitration at noc nodes
06/26/14Hierarchical asymmetric mesh with virtual routers
06/26/14Tagging and synchronization for fairness in noc interconnects
04/24/14Asymmetric mesh noc topologies
04/24/14Asymmetric mesh noc topologies
04/10/14Heterogeneous channel capacities in an interconnect
03/06/14Automatic construction of deadlock free interconnects
09/14/17Streaming bridge design with host interfaces and network on chip (noc) layers
06/15/17Automatic buffer sizing for optimal network-on-chip design
06/08/17Automatic buffer sizing for optimal network-on-chip design
04/20/17Congestion control and qos in noc by regulating the injection traffic
04/06/17Hardware and software enabled implementation of power profile management instructions in system on chip







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Netspeed Systems in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Netspeed Systems with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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