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Netspeed Systems
Netspeed Systems Inc

Netspeed Systems patents


Recent patent applications related to Netspeed Systems. Netspeed Systems is listed as an Agent/Assignee. Note: Netspeed Systems may have other listings under different names/spellings. We're not affiliated with Netspeed Systems, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "N" | Netspeed Systems-related inventors


Qos in a system with end-to-end flow control and qos aware buffer allocation

The present disclosure is directed to Quality of Service (QoS) and handshake protocols to facilitate endpoint bandwidth allocation among one or more agents in a Network on Chip (NoC) for an endpoint agent. The QoS policy and handshake protocols may involve the use of credits for buffer allocation which are... Netspeed Systems

Verification low power collateral generation

Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating transition state specifications that include information regarding low power behavior of a System on Chip (SoC) and/or a Network on Chip (NoC). Such transition state specifications can enable verification of switching behavior when elements/components of... Netspeed Systems

Generating physically aware network-on-chip design from a physical system-on-chip specification

Different example implementations of the present disclosure relates to methods and computer readable mediums for automatically generating physically aware NoC design and physically aware NoC Specification based on one or more of given SoC architectural details, physical information of SoC, traffic specification, power profile and one or more constraints. The... Netspeed Systems

Clock gating for system-on-chip elements

An aspect of the present disclosure provides a hardware element in a Network on Chip (NoC), wherein the hardware element includes a clock gating circuit configures one or more neighboring hardware elements to activate before receiving new incoming data and to sleep after a defined number of cycles, wherein the... Netspeed Systems

Automatic generation of power management sequence in a soc or noc

Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components,... Netspeed Systems

Hardware and software enabled implementation of power profile management instructions in system on chip

Aspects of the present disclosure relate to a method and system for hybrid and/or distributed implementation of generation and/or execution of power profile management instructions. An embodiment of the present disclosure provides a hardware element of a SoC/NoC that can be configured to generate and/or execute power profile management instructions... Netspeed Systems

Transaction expansion for noc simulation and noc design

Methods and example implementations described herein are generally directed to interconnect architecture, and more specifically, to generation of one or more expanded transactions for conducting simulations and/or NoC design. Aspects of the present disclosure include processing of input traffic specification that is given in terms of groups of hosts, requests,... Netspeed Systems

Automatic generation of physically aware aggregation/distribution networks

Aspects of the present disclosure provide systems and methods for automatic generation of physically aware aggregation/distribution networks that enable optimized arrangement of a plurality of hardware elements, and provide positions and connectivity for one or more intermediate hardware elements. One or more intermediate hardware elements can be configured to aggregate... Netspeed Systems

Automatic performance characterization of a network-on-chip (noc) interconnect

Aspects of the present disclosure are directed to methods, systems, and non-transitory computer readable medium for automatically characterizing performance of a System-on-Chip (SoC) and/or Network-on-Chip (NoC) with respect to latency and throughput attributes of one or more traffic flows/profiles under varying traffic load conditions. The characterization of performance may involve... Netspeed Systems

System level simulation in network on chip architecture

Systems and methods for performing multi-message transaction based performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect architecture by accurately imitating full SoC behavior are described. The example implementations involve simulations to evaluate and detect NoC behavior based on execution of multiple transactions at different rates/times/intervals,... Netspeed Systems

Automatic pipelining of noc channels to meet timing and/or performance

Systems and methods for automatically generating a Network on Chip (NoC) interconnect architecture with pipeline stages are described. The present disclosure includes example implementations directed to automatically determining the number and placement of pipeline stages for each channel in the NoC. Example implementations may also adjust the buffer at one... Netspeed Systems

Supporting multicast in noc interconnect

Example implementations are directed to more efficiently delivering a multicast message to multiple destination components from a source component. Multicast environment is achieved with transmission of a single message from a source component, which gets replicated in the NoC during routing towards the destination components indicated in the message. Example... Netspeed Systems

Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip

Aspects of the present disclosure relates to methods, computer readable mediums, and NoC architectures/systems/constructions that can automatically mark and configure some channel of a NoC as store-and-forward channels, and other channels of the NoC as cut-through channels, and can further resize the buffers/channels based on the given NoC specification and... Netspeed Systems

Hierarchical asymmetric mesh with virtual routers

A network-on-chip configuration includes a first plurality of cores arranged in a two-dimensional mesh; a first plurality of routers, each of the first plurality of routers associated with a corresponding local one of the first plurality of cores, each of the first plurality of routers having a plurality of directional... Netspeed Systems

Clock gating for system-on-chip elements

An aspect of the present disclosure provides a hardware element in a Network on Chip (NoC), wherein the hardware element includes a clock gating circuit configures one or more neighboring hardware elements to activate before receiving new incoming data and to sleep after a defined number of cycles, wherein the... Netspeed Systems

Configurable router for a network on chip (noc)

Example implementations described herein are directed to a configurable building block, such as a router, for implementation of a Network on Chip (NoC). The router is parameterized by a software layer, which can include the number of virtual channels for a port, the number of ports, the membership information of... Netspeed Systems

System and grouping of network on chip (noc) elements

Aspects of the present disclosure are directed to systems, methods and computer readable medium for reducing the number of unique routers/network elements/module instances on a network on chip to get a simplified NoC RTL without effecting the behavior and performance of NoC. According to an example implementation of the present... Netspeed Systems

Heterogeneous soc ip core placement in an interconnect to optimize latency and interconnect performance

Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the position of hosts of various size and shape in a NoC topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization... Netspeed Systems

Generation of network-on-chip layout based on user specified topological constraints

In an aspect, the present disclosure provides a method that comprises automatic generation of a NoC from specified topological information based on projecting NoC elements of the NoC onto a grid layout. In an aspect, the specified topological information, including specification of putting constraints on positions/locations of NoC elements and... Netspeed Systems

Heterogeneous channel capacities in an interconnect

Systems and methods involving construction of a system interconnect in which different channels have different widths in numbers of bits. Example processes to construct such a heterogeneous channel NoC interconnect are disclosed herein, wherein the channel width may be determined based upon the provided specification of bandwidth and latency between... Netspeed Systems

Qos in a system with end-to-end flow control and qos aware buffer allocation

The present disclosure is directed to Quality of Service (QoS) and handshake protocols to facilitate endpoint bandwidth allocation among one or more agents in a Network on Chip (NoC) for an endpoint agent. The QoS policy and handshake protocols may involve the use of credits for buffer allocation which are... Netspeed Systems

Automatic buffer sizing for optimal network-on-chip design

The present disclosure relates to automatic sizing of NoC channel buffers of one or more virtual channels to optimize NoC design, SoC design, and to meet defined performance objectives. The present disclosure further relates to a NoC element such as a router or a bridge having input ports associated with... Netspeed Systems

Streaming bridge design with host interfaces and network on chip (noc) layers

Systems and methods described herein are directed to streaming bridge design implementations that help interconnect and transfer transaction packets between multiple source and destination host interfaces through a Network on Chip (NoC) interconnect, which includes a plurality of NoC router layers and virtual channels (VCs) connecting the router layers. Implementations... Netspeed Systems

Automatic buffer sizing for optimal network-on-chip design

The present disclosure relates to automatic sizing of NoC channel buffers of one or more virtual channels to optimize NoC design, SoC design, and to meet defined performance objectives. The present disclosure further relates to a NoC element such as a router or a bridge having input ports associated with... Netspeed Systems

Automatic buffer sizing for optimal network-on-chip design

The present disclosure relates to automatic sizing of NoC channel buffers of one or more virtual channels to optimize NoC design, SoC design, and to meet defined performance objectives. The present disclosure further relates to a NoC element such as a router or a bridge having input ports associated with... Netspeed Systems

Congestion control and qos in noc by regulating the injection traffic

Systems and methods described herein are directed to solutions for NoC interconnects that provide congestion avoidance and end-to-end uniform and weighted-fair allocation of resource bandwidths among various contenders in a mesh or torus interconnect. The example implementations are fully distributed and involve using explicit congestion notification messages or local congestion... Netspeed Systems

Hardware and software enabled implementation of power profile management instructions in system on chip

Aspects of the present disclosure relate to a method and system for hybrid and/or distributed implementation of generation and/or execution of power profile management instructions. An embodiment of the present disclosure provides a hardware element of a SoC/NoC that can be configured to generate and/or execute power profile management instructions... Netspeed Systems








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