FreshPatents.com Logo

new TOP 200 Companies filing patents this week

new Companies with the Most Patent Filings (2010+)


Similar
Filing Names

Nvidia Corporation
Nvidia Corporation_20100114
Nvidia Corporation_20131212
Nvidia Corporation_20100128

Popular
Companies


Web
Adobe patents
Akamai patents
Amazon patents
Apple patents
Ebay patents
Facebook patents
Google patents
IBM patents
Linkedin patents
Microsoft patents
Oracle patents
Red Hat patents
Yahoo patents

Food/Health
Adidas
Nike patents
Pfizer patents
Monsanto patents
Medtronic patents
Kraft patents

Transportation
Boeing patents
Tesla Motors patents

Telecom
Qualcomm patents
Motorola patents
Nokia patents
RIMM patents

Industrial/Electronics
AMD
Applied Materials
Seagate patents
General Electric
Caterpillar patents
Samsung
Wal-mart patents

Ticker Symbols

Nvidia Corporation patents


      
Recent patent applications related to Nvidia Corporation. Nvidia Corporation is listed as an Agent/Assignee. Note: Nvidia Corporation may have other listings under different names/spellings. We're not affiliated with Nvidia Corporation, we're just tracking patents.

ARCHIVE: New 2014 2013 2012 2011 2010 2009 | Company Directory "N" | Nvidia Corporation-related inventors



Nvidia

Parallel linear complementarity solver for rigid body dynamics

Nvidia

Increased expansion port utilization in a motherboard of a data processing device by a graphics processing unit (gpu)…

Nvidia

Graphics processing unit with a texture return buffer and a texture queue

Search recent Press Releases: Nvidia Corporation-related press releases
Count Application # Date Nvidia Corporation patents (updated weekly) - BOOKMARK this page
12014023944408/28/14 new patent  Buried tsv's used for decaps
22014024001608/28/14 new patent  Low clock energy double-edge-triggered flip-flop circuit
32014024032508/28/14 new patent  Increased expansion port utilization in a motherboard of a data processing device by a graphics processing unit (gpu) thereof
42014024032908/28/14 new patent  Graphics processing unit with a texture return buffer and a texture queue
52014024033008/28/14 new patent  Display multiplier providing independent pixel resolutions
62014024033708/28/14 new patent  Graphics processing unit with a texture return buffer and a texture queue
72014024091808/28/14 new patent  Heat sink with an integrated vapor chamber
82014024146208/28/14 new patent  Circuit and method for envelope tracking and envelope-tracking transmitter for radio-frequency transmission
92014024422108/28/14 new patent  Parallel linear complementarity solver for rigid body dynamics
102014024422208/28/14 new patent  Modified effective mass for parallel rigid body simulation
112014024454808/28/14 new patent  System, method, and computer program product for classification of silicon wafers using radial support vector machines to process ring oscillator parametric data
122014024470308/28/14 new patent  System, method, and computer program product for implementing large integer operations on a graphics processing unit
132014024492108/28/14 new patent  Asymmetric multithreaded fifo memory
142014023236008/21/14Predictive current sensing
152014023236108/21/14Pulsed current sensing
162014023236808/21/14Electric power conversion with assymetric phase response
172014023254008/21/14System, method, and computer program product for implementing a power saving technique using a proximity sensor controlled display
182014023266408/21/14Synchronized touch input recognition
192014023272908/21/14Power efficient attribute handling for tessellation and geometry shaders
202014023361208/21/14Technique for optimizing the phase of a data signal transmitted across a communication link
212014023361608/21/14Communication system and method
222014023361708/21/14Communication system and method
232014023715308/21/14Device-ready-status to function-ready-status conversion
242014023718708/21/14Adaptive multilevel binning to improve hierarchical caching
252014023718908/21/14Compression status bit cache and backing store
262014022557908/14/14Current-parking switching regulator upstream controller
272014022566208/14/14Low-voltage, high-accuracy current mirror circuit
282014022590208/14/14Image pyramid processor and method of multi-resolution image processing
292014022807708/14/14Mobile computing device with expanded display size
302014022975408/14/14Power telemetry remote monitoring
312014022978308/14/14In-circuit test structure for printed circuit board
322014022993508/14/14Virtual interrupt delivery from a graphics processing unit (gpu) of a computing system without hardware support therefor
332014022995308/14/14System, method, and computer program product for management of dependency between tasks
342014021800108/07/14Current-parking switching regulator downstream controller pre-driver
352014021808408/07/14Approach to clock frequency modulation of a fixed frequency clock source
362014021833208/07/14Flat panel electronic device
372014021837608/07/14System and method for image processing
382014021837908/07/14Device, system and method for transferring network data
392014021839008/07/14Modulated and blended anti-aliasing
402014021878708/07/14Flat panel electronic apparatus and display panel thereof
412014021900708/07/14Dram with segmented page configuration
422014021948208/07/14Flat panel electronic device and audio playing apparatus thereof
432014022105408/07/14Saving power in a mobile terminal
442014022108708/07/14Handheld gaming console
452014022321908/07/14Clock frequency controller for a processor and method of operation thereof
462014022322108/07/14Approach to clock frequency modulation of a fixed frequency clock source
472014022323608/07/14Device for testing a graphics card
482014022342008/07/14Convergence analysis in multithreaded programs
492014020859007/31/14Process for manufacturing a printed circuit board having high density microvias formed in a thick substrate
502014021042907/31/14Current-parking switching regulator with a split inductor
512014021043407/31/14Current-parking switching regulator downstream controller
522014021065607/31/14Circuit for implementing a continuous-time deglitching technique for digital analog converters
532014021169207/31/14Communication system and method
542014021434207/31/14Verification of test program stability and wafer fabrication process sensitivity
552014021523607/31/14Power-efficient inter processor communication scheduling
562014020400507/24/14System, method, and computer program product for distributed processing of overlapping portions of pixels
572014020409807/24/14System, method, and computer program product for graphics processing unit (gpu) demand paging
582014020410607/24/14Shader program attribute storage
592014020465707/24/14Sram voltage assist
602014020468707/24/14System and method for performing address-based sram access assists
612014019883907/17/14Low latency sub-frame level video decoding
622014019892307/17/14Real time audio echo and background noise reduction for a mobile device
632014020005107/17/14Radio frequency identification on mobile computing device
642014019076307/10/14Ported enclosure and automated equalization of frequency response in a micro-speaker audio system
652014019206607/10/14Parallel processor with integrated correlation and convolution engine
662014019300207/10/14Ported enclosure and automated equalization of frequency response in a micro-speaker audio system
672014019559407/10/14Method and system for distributed processing, rendering, and displaying of content
682014019559807/10/14System and method for computer peripheral access from cloud computing devices
692014019591207/10/14Method and system for simultaneous display of video content
702014019604307/10/14System and method for re-factorizing a square matrix into lower and upper triangular matrices on a parallel processor
712014018395107/03/14Super n-phase switching mode power supply
722014018417907/03/14Efficient voltage sensing systems and methods
732014018426807/03/14Power conservation using gray-coded address sequencing
742014018450807/03/14Universal adaptive game controller
752014018451307/03/14Softkey magnification on touch screen
762014018451707/03/14Early drawing system and method to improve touch screen response
772014018458307/03/14Method and apparatus to reduce panel power through horizontal interlaced addressing
782014018460107/03/14System and method for frame buffer decompression and/or compression
792014018460307/03/14Method to improve usability of high pixel density displays
802014018461107/03/14Method and apparatus for sending partial frame updates rendered in a graphics processor to a display using framelock signals
812014018461207/03/14Variable-width differential memory compression
822014018461607/03/14System, method, and computer program product for identifying a faulty processing unit
832014018461707/03/14Mid-primitive graphics execution preemption
842014018462507/03/14Stutter buffer transfer techniques for display systems
852014018462607/03/14Frame times by dynamically adjusting frame buffer resolution
862014018462707/03/14Progressive lossy memory compression
872014018462907/03/14Method and apparatus for synchronizing a lower bandwidth graphics processor with a higher bandwidth display using framelock signals
882014018463207/03/14Method and system for index compression for fixed block size texture formats and for non-linear interpolation of index values along an edge in a tile
892014018463307/03/14Conservative bounding region rasterization
902014018466707/03/14Display device with binary mode amoled pixel pattern
912014018481307/03/14Lens shading calibration for cameras
922014018489407/03/14System, method, and computer program product implementing an image processing pipeline for high-dynamic range images
932014018563307/03/14Flexible threshold counter for clock-and-data recovery
942014018585207/03/14Audio channel mapping in a portable electronic device
952014018595107/03/14Summed area computation using ripmap of partial sums
962014018595207/03/14System, method, and computer program product for implementing a spatially varying unsharp mask noise reduction filter
972014018733107/03/14Latency reduction by sub-frame encoding and transmission
982014018896307/03/14Efficient correction of normalizer shift amount errors in fused multiply add operations
992014018909107/03/14Network adaptive latency reduction through frame rate control
1002014018918007/03/14Method and system for changing bus direction in memory systems
1012014018926007/03/14Approach for context switching of lock-bit protected memory
1022014018931007/03/14Fault detection in instruction translations
1032014018931307/03/14Queued instruction re-dispatch after runahead
1042014018931607/03/14Execution pipeline data forwarding
1052014018932907/03/14Cooperative thread array granularity context switch during trap handling
1062014018937507/03/14Distributed power delivery to a processing unit
1072014018938607/03/14Supply-voltage control for device power management
1082014018945207/03/14System for reducing peak power during scan shift at the local level for scan based tests
1092014018945407/03/14Global low power capture scheme for cores
1102014018945507/03/14System for reducing peak power during scan shift at the global level for scan based tests
1112014018954407/03/14Web-based graphics development system and method of graphics program interaction therewith
1122014018964707/03/14System and method for debugging an executing general-purpose computing on graphics processing units (gpgpu) application
1132014018964807/03/14Facilitated quality testing
1142014018969807/03/14Approach for a configurable phase-based priority scheduler
1152014017561906/26/14Stripline and reference plane implementation for interposers using an implant layer
1162014017566506/26/14Chip package using interposer substrate with through-silicon vias
1172014017568106/26/14Absorbing excess under-fill flow with a solder trench
1182014017604106/26/14Semiconductor thermoelectric module charger for mobile computing device
1192014017611606/26/14Quantifying silicon degradation in an integrated circuit
1202014017644006/26/14Apparatus and system for implementing a wireless mouse using a hand-held device
1212014017653206/26/14Method for image correction and an electronic device embodying the same
1222014017654506/26/14System, method, and computer program product implementing an algorithm for performing thin voxelization of a three-dimensional model
1232014017654606/26/14Shadow softening graphics processing unit and method
1242014017654706/26/14Programmable blending via multiple pixel shader dispatches
1252014017654806/26/14Facial image enhancement for video communication
1262014017656806/26/14Programmable blending in multi-threaded processing units
1272014017656906/26/14Graphics processing unit employing a standard processing unit and a method of constructing a graphics processing unit
1282014017657506/26/14System, method, and computer program product for tiled deferred shading
1292014017657706/26/14Method and mechanism for preempting control of a graphics pipeline
1302014017657806/26/14Input output connector for accessing graphics fixed function units in a software-defined pipeline and a method of operating a pipeline
1312014017657906/26/14Efficient super-sampling with per-pixel shader threads
1322014017658806/26/14Technique for storing shared vertices
1332014017658906/26/14Technique for storing shared vertices
1342014017674506/26/14Approach for camera control
1352014017675006/26/14Approach for camera control
1362014017680206/26/14Detection and measurement of video scene transitions
1372014017769306/26/14Influence clock data recovery settling point by applying decision feedback equalization to a crossing sample
1382014017769506/26/14Multipass approach for performing channel equalization training
1392014017771606/26/14Using an average motion vector for a motion search
1402014017937006/26/14System, process, and computer program product for implementing a document scanner in a hand-held device
1412014018133906/26/14Equalization coefficient search algorithm
1422014018134506/26/14Hidden i/o connector assembly for mobile computing devices
1432014018139106/26/14Hardware chip select training for memory using write leveling mechanism
1442014018139206/26/14Hardware chip select training for memory using read commands
1452014018140406/26/14Information coherency maintenance systems and methods
1462014018142906/26/14Multi-dimensional hardware data training between memory controller and memory
1472014018145106/26/14Hardware command training for memory using write leveling mechanism
1482014018145206/26/14Hardware command training for memory using read commands
1492014018146206/26/14Virtual address based memory reordering
1502014018150106/26/14Heterogeneous multiprocessor design for power-efficient and area-efficient computing
1512014018154006/26/14Hybrid battery pack
1522014018154706/26/14Smart charging system for hybrid battery pack
1532014018176906/26/14Netlist cell identification and classification to reduce power consumption
1542014016721606/19/14Low-profile chip package with modified heat spreader
1552014016782806/19/14Small area low power data retention flop
1562014016803406/19/14Near-eye parallax barrier displays
1572014016803506/19/14Near-eye optical deconvolution displays
1582014016809306/19/14Method and system of emulating pressure sensitivity on a surface
1592014016821406/19/14Method of simulating clothing using long range attachments
1602014016822206/19/14Optimizing triangle topology for path rendering
1612014016822706/19/14System and method for versioning buffer states and graphics processing unit incorporating the same
1622014016822806/19/14Fine-grained parallel traversal for ray tracing
1632014016823006/19/14Asynchronous compute integrated into large-scale data rendering using dedicated, separate computing and rendering clusters
1642014016823106/19/14Triggering performance event capture via pipelined state bundles
1652014016823206/19/14Stereo viewpoint graphics processing subsystem and method of sharing geometry data between stereo images in screen-spaced processing
1662014016823806/19/14Fine-grained parallel traversal for ray tracing
1672014016824206/19/14Techniques for setting up and executing draw calls
1682014016824506/19/14Technique for performing memory access operations via texture hardware
1692014016838806/19/14System and method for displaying a three-dimensional image on a video monitor
1702014016878306/19/14Near-eye microlens array displays
1712014016888306/19/14Externally latching i/o housing
1722014016890306/19/14Passive cooling system integrated into a printed circuit board for cooling electronic components
1732014016910806/19/14Mitigating external influences on long signal lines
1742014016947106/19/14Apparatus and method for enhancing motion estimation based on user input
1752014017089106/19/14Externally latching i/o cable
1762014017119006/19/14Implementing a remote gaming server on a desktop computer
1772014017238006/19/14Technique for simulating the dynamics of hair
1782014017300006/19/14System and method for handling message delivery
1792014017314806/19/14Approach for working around starvation problems in a datapath
1802014017319306/19/14Technique for accessing content-addressable memory
1812014017324906/19/14System and method for connecting a system on chip processor and an external processor
1822014017325806/19/14Technique for performing memory access operations via texture hardware
1832014017360606/19/14Streaming processing of short read alignment algorithms
1842014017361106/19/14System and method for launching data parallel and task parallel application threads and graphics processing unit incorporating the same
1852014016001906/12/14Methods for enhancing user interaction with mobile devices
1862014016012406/12/14Visible polygon data structure and method of use thereof
1872014016012606/12/14Computing tessellation coordinates using dedicated hardware
1882014016015106/12/14System and method for compressing bounding box data and processor incorporating the same
1892014016066206/12/14Bracket of add-in card of computer, add-in card system and computer
1902014016087106/12/14System and method for performing sram write assist
1912014016087606/12/14Address bit remapping scheme to reduce access granularity of dram accesses
1922014016117306/12/14System and method for controlling video encoding using content information
1932014016465506/12/14Folded fifo memory generator
1942014016472706/12/14System, method, and computer program product for optimizing the management of thread stack memory
1952014016473606/12/14Lazy runahead operation for a microprocessor
1962014016473806/12/14Instruction categorization for runahead operation
1972014016474306/12/14Reordering buffer for memory access locality
1982014016474506/12/14Register allocation for clustered multi-level register files
1992014016484706/12/14Internal logic analyzer with programmable window capture
2002014016484806/12/14Tracing instruction pointers and data accesses
2012014016504906/12/14Compiler-controlled region scheduling for simd execution of threads
2022014016507206/12/14Technique for saving and restoring thread group operating state
2032014015189206/05/14Three dimensional through-silicon via construction
2042014015265206/05/14Order-preserving distributed rasterizer
2052014015284806/05/14Technique for configuring a digital camera
2062014015334106/05/14Sequential access memory with master-slave latch pairs and method of operating
2072014015363506/05/14Method, computer program product, and system for multi-threaded video encoding
2082014015689106/05/14Systems and methods for automatically generating master-slave latch structures with fully registered flow control
2092014015742306/05/14Code protection using online authentication and encrypted code execution
2102014014604505/29/14System, method, and computer program product for sampling a hierarchical depth map
2112014014605005/29/14System, method, and computer program product for tiled screen space sample scrambling for parallel deterministic consistent light transport simulation
2122014014606205/29/14System, method, and computer program product for debugging graphics programs locally utilizing a system with a single gpu
2132014014606505/29/14Mpi communication of gpu buffers
2142014014662805/29/14Technique for improving static random-access memory sense amplifier voltage differential
2152014014948005/29/14System, method, and computer program product for transposing a matrix
2162014014952805/29/14Mpi communication of gpu buffers
2172014014966805/29/14Prefetching according to attributes of access requests
2182014014967805/29/14Using cache hit information to manage prefetches
2192014014967905/29/14Page crossing prefetches
2202014014972105/29/14Method, computer program product, and system for a multi-input bitwise logical operation
2212014014977005/29/14Low-power states for a computer system with integrated baseband
2222014014978005/29/14Speculative periodic synchronizer
2232014013881105/22/14A semiconductor device including a heat-spreading lid
2242014013881505/22/14Server processing module
2252014013882305/22/14Variable-size solder bump structures for integrated circuit packaging
2262014013882405/22/14Offset integrated circuit packaging interconnects
2272014013927505/22/14Variation-tolerant periodic synchronizer
2282014013927605/22/14Matrix phase detector
2292014014329605/22/14Method and system of transmitting state based input over a network
2302014014329705/22/14Method and system for network driven automatic adaptive rendering impedance
2312014014348505/22/14Technique for optimizing static random-access memory passive power consumption
2322014014356405/22/14Approach to power reduction in floating-point operations
2332014014359905/22/14Test program generator using key enumeration and string replacement
2342014014363505/22/14Techniques for storing ecc checkbits in a level two cache
2352014014374205/22/14Design, layout, and manufacturing techniques for multivariant integrated circuits
2362014014375505/22/14System and method for inserting synchronization statements into a program file to mitigate race conditions
2372014013881105/22/14A semiconductor device including a heat-spreading lid
2382014013881505/22/14Server processing module
2392014013882305/22/14Variable-size solder bump structures for integrated circuit packaging
2402014013882405/22/14Offset integrated circuit packaging interconnects
2412014013927505/22/14Variation-tolerant periodic synchronizer
2422014013927605/22/14Matrix phase detector
2432014014329605/22/14Method and system of transmitting state based input over a network
2442014014329705/22/14Method and system for network driven automatic adaptive rendering impedance
2452014014348505/22/14Technique for optimizing static random-access memory passive power consumption
2462014014356405/22/14Approach to power reduction in floating-point operations
2472014014359905/22/14Test program generator using key enumeration and string replacement
2482014014363505/22/14Techniques for storing ecc checkbits in a level two cache
2492014014374205/22/14Design, layout, and manufacturing techniques for multivariant integrated circuits


ARCHIVE: New 2014 2013 2012 2011 2010 2009



###

This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Nvidia Corporation in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Nvidia Corporation with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

###

     SHARE
  
         


FreshNews promo