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Powertech Technology Inc
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Powertech Technology Inc patents

Recent patent applications related to Powertech Technology Inc. Powertech Technology Inc is listed as an Agent/Assignee. Note: Powertech Technology Inc may have other listings under different names/spellings. We're not affiliated with Powertech Technology Inc, we're just tracking patents.

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Date Powertech Technology Inc patents (updated weekly) - BOOKMARK this page
04/20/17 new patent  Chip package having a protection piece compliantly attached on a chip sensing surface
04/20/17 new patent  Package structure and manufacturing method thereof
03/23/17Semiconductor package
02/23/17Semiconductor package with pillar-top-interconnection (pti) configuration and its mis fabricating method
02/16/17Semiconductor structure
02/16/17Carrier substrate
02/02/17Multi-chip package having encapsulation body to replace substrate core
01/12/17Semiconductor package and manufacturing method thereof
08/18/16Underfill process and processing machine thereof
08/18/16Chip package structure having a shielded molding compound
06/09/16Package structure
04/28/16Chip scale package of image sensor having dam combination
04/07/16Semiconductor packaging structure
04/02/15Substrateless packages with scribe disposed on heat spreader
03/05/15Wafer-level testing singulated 3d-stacked chip cubes
02/19/15Fabrication process and structure to form bumps aligned on tsv on chip backside
02/19/15Fine-pitch pillar bump layout structure on chip
06/19/14Leadframe-type semiconductor package having emi shielding layer connected to ground
03/28/13Method for testing multi-chip stacked packages
12/27/12Memory testing device having cross interconnections of multiple drivers and its implementing method
06/07/12Tape
06/09/11Multi-chip stacked package and its mother chip to save interposer
07/01/10Apparatus for drop testing and method utilizing the same
05/27/10Semiconductor package having isolated inner lead
01/28/10Universal substrate for semiconductor packages and the packages
01/07/10Method for cutting large-size wafer and the same
01/07/10Fiber chopper and controlling force
12/10/09Col (chip-on-lead) multi-chip package
12/10/09Leadframe-based semiconductor package having arched bend in a supporting bar and leadframe for the package
12/10/09Laminate substrate and semiconductor package utilizing the substrate
12/03/09Lead frame and chip package structure and fabricating the same
12/03/09Method for fabricating semiconductor elements
11/19/09Lead-on-chip semiconductor package and leadframe for the package
11/12/09Semiconductor package enhancing variation of movability at ball terminals
10/29/09Semiconductor chip having tsv (through silicon via) and stacked assembly including the chips
10/01/09Window type bga semiconductor package and its substrate
09/24/09Col semiconductor package
09/24/09Thermally-enhanced multi-hole semiconductor package
09/24/09Semiconductor package having substrate id code and its fabricating method
09/10/09Leadframe and semiconductor package having downset baffle paddles
09/10/09Substrate strip for semiconductor packages
09/10/09Substrate and semiconductor package for lessening warpage
09/10/09Method for die bonding having pick-and-probing feature
08/13/09Electronic packaging method and apparatus
07/30/09Method for singulating semiconductor devices
07/09/09Circuit board ready to slot
07/09/09Method for forming a die-attach layer during semiconductor packaging processes
06/25/09Semiconductor package with leads on a chip having multi-row of bonding pads
05/28/09Chip packaging process including simpification and mergence of burn-in test and high temperature test
05/28/09Assembling of doubled-side stacking pulral chips
05/21/09Semiconductor chip device having through-silicon-via (tsv) and its fabrication method
05/21/09Stacked assembly of semiconductor packages with fastening lead-cut ends of leadframe
05/21/09Pop (package-on-package) device encapsulating soldered joints between externals leads
05/21/09Pop (package-on-package) semiconductor device
04/16/09Semiconductor package and substrate for the same
04/09/09Stackable semiconductor package having plural pillars per pad
04/09/09Semiconductor package having restraining ring surfaces against soldering crack
02/19/09Semiconductor package-on-package (pop) device avoiding crack at solder joints of micro contacts during package stacking
01/28/10Universal substrate for semiconductor packages and the packages
01/07/10Fiber chopper and controlling force







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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Powertech Technology Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Powertech Technology Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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