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Rambus Inc patents

Recent patent applications related to Rambus Inc. Rambus Inc is listed as an Agent/Assignee. Note: Rambus Inc may have other listings under different names/spellings. We're not affiliated with Rambus Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "R" | Rambus Inc-related inventors

Memory device comprising programmable command-and-address and/or data interfaces

A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the... Rambus Inc

Methods and synchronizing communication with a memory controller

A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The... Rambus Inc

Adjustable access energy and access latency memory system and devices

Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than... Rambus Inc

Depth measurement using a phase grating

Binocular depth-perception systems use binary, phase-antisymmetric gratings to cast point-source responses onto an array of photosensitive pixels. The gratings and arrays can be manufactured to tight tolerances using well characterized and readily available integrated-circuit fabrication techniques, and can thus be made small, cost-effective, and efficient. The gratings produce point-source responses... Rambus Inc

Integrated circuit comprising fractional clock multiplication circuitry

Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of... Rambus Inc

Calibration methods and circuits to calibrate drive current and termination impedance

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing... Rambus Inc

Systems and methods for lensless image acquisition

Image-sensing devices include odd-symmetry gratings that cast interference patterns over a photodetector array. Grating features offer considerable insensitivity to the wavelength of incident light, and also to the manufactured distance between the grating and the photodetector array. Photographs and other image information can be extracted from interference patterns captured by... Rambus Inc

Memory controller that uses a specific timing reference signal in connection with a data brust following a specified idle period

Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to... Rambus Inc

Memory component with pattern register circuitry to provide data patterns for calibration

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data... Rambus Inc

Memory controller

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing... Rambus Inc

Integrated circuit comprising circuitry to determine settings for an injection-locked oscillator

Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of... Rambus Inc

Phase calibration of clock signals

A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of... Rambus Inc

Communication channel calibration using feedback

A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is... Rambus Inc

High-speed signaling systems with adaptable pre-emphasis and equalization

A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g.... Rambus Inc

Memory device and repair method with column-based error code tracking

A memory device is disclosed that includes a row of storage locations that form plural columns. The plural columns include data columns to store data and a tag column to store tag information associated with error locations in the data columns. Each data column is associated with an error correction... Rambus Inc

Memory with alternative command interfaces

A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured... Rambus Inc

Staggered exit from memory power-down

An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a... Rambus Inc

Memory controller for strobe-based memory systems

An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed... Rambus Inc

System including hierarchical memory modules having different types of integrated circuit memory devices

Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for... Rambus Inc

Digital calibration for multiphase oscillators

A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once... Rambus Inc

On-chip regulator with variable load compensation

An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide... Rambus Inc

Dynamic random access memory (dram) component for high-performance, high-capacity registered memory modules

The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and... Rambus Inc

Memory controller with staggered request signal output

A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is... Rambus Inc

On-die termination

Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices... Rambus Inc

Drift tracking feedback for communication channels

A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe... Rambus Inc

Memory system with threaded transaction support

Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry... Rambus Inc

Deserialized dual-loop clock radio and data recovery circuit

A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of... Rambus Inc

Memory systems, modules, and methods for improved capacity

A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay... Rambus Inc

Calibration protocol for command and address bus voltage reference in low-swing single-ended signaling

A transmitter is coupled to a command and address (CA) bus. The transmitter is configurable with dual-mode support to send commands over the CA bus in a first swing mode and a second swing mode. The transmitter is configurable to send a first command over the CA bus via the... Rambus Inc

High performance, high capacity memory systems and modules

Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility, or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high... Rambus Inc

Memory improved power management

A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular... Rambus Inc

Dram retention test dynamic error correction

A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under... Rambus Inc

Integrated circuit with configurable on-die termination

Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.... Rambus Inc

Receiver with clock recovery circuit and adaptive sample and equalizer timing

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted... Rambus Inc

High speed signaling system with adaptive transmit pre-emphasis

A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first... Rambus Inc

11/23/17 / #20170338999

System and memory access in server communications

Embodiments of the present invention are directed to memories used in server applications. More specifically, embodiments of the present invention provide a server system has a memory management module that is connected to a processor, a memory module, and a network interface. The memory management module is configured to allocate... Rambus Inc

11/16/17 / #20170329719

Memory controller for selective rank or subrank access

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and... Rambus Inc

11/16/17 / #20170330610

High capacity memory system using standard controller component

The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of... Rambus Inc

11/16/17 / #20170330611

Variable width memory module supporting enhanced error detection and correction

Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable, and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width... Rambus Inc

11/16/17 / #20170331477

On-die termination control

A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes... Rambus Inc

11/16/17 / #20170331483

Wide range frequency synthesizer with quadrature generation and spur cancellation

A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the... Rambus Inc

11/16/17 / #20170331615

Communication channel calibration for drift conditions

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link... Rambus Inc

11/16/17 / #20170331648

Receiver with offset calibration

An on-chip AC coupled receiver with offset calibration. The receiver includes AC coupling circuitry to couple a differential input signal into a coupled differential signal having a first signal and a second signal. The receiver includes a first comparator to generate a first error signal indicative of whether a first... Rambus Inc

11/09/17 / #20170323672

Memory controller with phase adjusted clock for performing memory operations

In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs... Rambus Inc

11/09/17 / #20170323690

Controller to detect malfunctioning address of memory device

A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device... Rambus Inc

11/09/17 / #20170324019

Differential cryogenic transmitter

In an integrated-circuit component having a signal transmitter receives a transmitter power supply that cycles periodically between power-off and power-on voltage levels to define a sequence of enable intervals during which the signal transmitter is to output voltage levels corresponding to respective transmit data bits onto an external signaling link.... Rambus Inc

11/09/17 / #20170324591

Selectable-tap equalizer

A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is... Rambus Inc

11/09/17 / #20170324594

Equalized multi-signaling mode driver

A transmit circuit can be configured to output two-level pulse amplitude modulation (PAM-2) or four-level pulse amplitude modulation (PAM-4). In the PAM-2 mode, pre-tap feed-forward equalization (FFE) and post-tap FFE can be applied to the PAM-2 signal by pre-taps and post-taps, respectively. In the PAM-4 mode, at least one post-tap... Rambus Inc

11/09/17 / #20170324920

Conditional-reset, multi-bit read-out image sensor

An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element... Rambus Inc

11/02/17 / #20170315935

Memory access during memory calibration

A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data... Rambus Inc

11/02/17 / #20170315953

Memory system with independently adjustable core and interface data rates

An integrated circuit device is disclosed including core circuitry and interface circuitry. The core circuitry outputs in parallel a set of data bits, while the interface circuitry couples to the core circuitry. The interface circuitry receives in parallel a first number of data bits among the set of data bits... Rambus Inc

11/02/17 / #20170317768

Periodic calibration for communication channels by drift tracking

A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and... Rambus Inc

10/26/17 / #20170308144

Optimizing power in a memory device

Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal... Rambus Inc

10/26/17 / #20170310910

Oversampled image sensor with conditional pixel readout

In a pixel array within an integrated-circuit image sensor, each of a plurality of pixels is evaluated to determine whether charge integrated within the pixel in response to incident light exceeds a first threshold. N-bit digital samples corresponding to the charge integrated within at least a subset of the plurality... Rambus Inc

10/19/17 / #20170300011

Systems and methods for improving resolution in lensless imaging

An optical phase grating produces an interference pattern rich in intensity and spatial-frequency information from the external scene. The grating includes an odd number of repeated sets of adjacent horizontal portions, separated by steps, that fill an area that radiates outward from a central region. At a given distance from... Rambus Inc

10/12/17 / #20170293552

Single command, multiple column-operation memory device

A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense... Rambus Inc

10/12/17 / #20170295040

Decision feedback equalizer

A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit.... Rambus Inc

10/05/17 / #20170287571

Buffer circuit with adaptive repair capability

A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic.... Rambus Inc

10/05/17 / #20170285957

Multiple memory rank system and selection method thereof

A multiple memory rank selection method and system assigns, based at least in part on decoding an assignment signal in a second command/address signal, a first terminal of a memory device to receive a first command/address signal and a second terminal of the memory device to receive the second command/address... Rambus Inc

10/05/17 / #20170286017

Memory controller for micro-threaded memory operations

A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry... Rambus Inc

10/05/17 / #20170287571

Buffer circuit with adaptive repair capability

A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic.... Rambus Inc

09/14/17 / #20170264470

Sampler reference level, dc offset, and afe gain adaptation for pam-n receiver

In a PAM-N receiver, sampler reference levels, DC offset and AFE gain may be jointly adapted to achieve optimal or near-optimal boundaries for the symbol decisions of the PAM-N signal. For reference level adaptation, the hamming distances between two consecutive data samples and their in-between edge sample are evaluated. Reference... Rambus Inc

09/07/17 / #20170256290

Stacked dram device and manufacture

A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and... Rambus Inc

08/31/17 / #20170249265

Asymmetric-channel memory system

A memory-control integrated circuit includes internal data conductors, steering circuitry and distinct first and second data interfaces, the first data interface having twice as many input/output (I/O) transceivers as the second data interface. In a first memory system configuration in which only the first data interface is coupled to a... Rambus Inc

08/31/17 / #20170250840

Serial link receiver with improved bandwidth and accurate eye monitor

A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision... Rambus Inc

Patent Packs
08/24/17 / #20170242807

Memory module threading with staggered data transfers

A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a... Rambus Inc

08/10/17 / #20170229190

Testing through-silicon-vias

Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation... Rambus Inc

08/10/17 / #20170230575

Systems and methods for improving resolution in lensless imaging

An imaging device uses a grating to produce an interference pattern for capture by a photodetector array. Digital photographs and other image information can then be extracted from the pattern. An integrated processor locally supports this extraction by upsampling the captured interference pattern and deconvolving the upsampled pattern with an... Rambus Inc

08/03/17 / #20170222845

Multi-pam output driver with distortion compensation

An integrated circuit device includes an output driver having a data signal terminal, logic circuitry, and a driver circuit coupled to the logic circuitry and data signal terminal. The driver circuit is configured to drive a signal corresponding to a symbol onto the data signal terminal, wherein the symbol is... Rambus Inc

07/27/17 / #20170214515

Phase control block for managing multiple clock domains in systems with frequency offsets

A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock... Rambus Inc

07/27/17 / #20170214869

Low-noise, high dynamic-range image sensor

A sequence of control voltage levels are applied to a control signal line capacitively coupled to a floating diffusion node of a pixel to sequentially adjust a voltage level of the floating diffusion node. A pixel output signal representative of the voltage level of the floating diffusion node is compared... Rambus Inc

07/20/17 / #20170205871

Using dynamic bursts to support frequency-agile memory interfaces

The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in... Rambus Inc

07/20/17 / #20170206168

Methods and apparatuses for addressing memory caches

A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or... Rambus Inc

07/20/17 / #20170207790

Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator

Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning... Rambus Inc

07/20/17 / #20170207791

Integrated circuit having a multiplying injection-locked oscillator

Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator... Rambus Inc

07/20/17 / #20170208272

Image sensor with depletion-level pixel charge transfer control

A pixel circuit within an integrated-circuit image sensor includes a photodiode having a pinning layer of a first conductivity type, a floating diffusion node and a transfer gate disposed between the photodiode and the floating diffusion node. A first control input is coupled to the transfer gate, and a second... Rambus Inc

07/13/17 / #20170199242

Technique for determining performance characteristics of electronic devices and systems

A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission... Rambus Inc

07/13/17 / #20170200489

Method and calibrating write timing in a memory system

A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a... Rambus Inc

07/06/17 / #20170192912

Clock generation for timing communications with ranks of memory devices

A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device... Rambus Inc

07/06/17 / #20170194036

Forwarding signal supply voltage in data transmission system

In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate... Rambus Inc

Patent Packs
07/06/17 / #20170195596

Oversampled high dynamic-range image sensor

In an integrated-circuit image sensor having a pixel array, a first subframe readout policy is selected from among a plurality of subframe readout policies, each of the subframe readout policies specifying a first number of subframes of image data to be readout from the pixel array for each output image... Rambus Inc

06/29/17 / #20170185489

Memory controller system with non-volatile backup storage

The present invention is directed to computer storage systems and methods thereof. More specifically, embodiments of the present invention provide an isolated storage control system that includes both a non-volatile memory and a volatile memory. The non-volatile memory comprises a data area and a metadata area. In power failure or... Rambus Inc

06/29/17 / #20170186478

Memory system topologies including a buffer device and an integrated circuit memory device

Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices... Rambus Inc

06/29/17 / #20170187498

Receiver clock test circuitry and related methods and apparatuses

An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of... Rambus Inc

06/22/17 / #20170176533

Testing fuse configurations in semiconductor devices

Methods, systems, and apparatus for testing semiconductor devices.... Rambus Inc

06/22/17 / #20170177021

Drift detection in timing signal forwarded from memory controller to memory device

A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing... Rambus Inc

06/22/17 / #20170177487

Deterministic operation of storage class memory

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface... Rambus Inc

06/22/17 / #20170177540

Interface with variable data rate

A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a... Rambus Inc

06/22/17 / #20170178702

Memory with deferred fractional row activation

Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be... Rambus Inc

06/22/17 / #20170178713

Memory refresh s

The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device... Rambus Inc

06/22/17 / #20170178723

System and performing memory operations on rram cells

A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to... Rambus Inc

06/22/17 / #20170178726

Resistance change memory cell circuits and methods

The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element... Rambus Inc

06/22/17 / #20170180163

Methods and circuits for adaptive equalization

An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes... Rambus Inc

06/15/17 / #20170168950

Techniques for storing data and tags in different memory arrays

A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location... Rambus Inc

06/15/17 / #20170169876

Memory controller for strobe-based memory systems

An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed... Rambus Inc

06/15/17 / #20170169877

Low-power source-synchronous signaling

A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase... Rambus Inc

06/15/17 / #20170169878

On-die termination of address and command signals

A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one... Rambus Inc

06/15/17 / #20170171002

Adaptive equalization using correlation of edge samples with data patterns

An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the... Rambus Inc

06/08/17 / #20170162252

Reduced transport energy in a memory system

A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to... Rambus Inc

06/01/17 / #20170153599

Systems and methods for improving resolution in lensless imaging

An infrared imaging system includes a phase grating overlying a two-dimensional array of thermally sensitive pixels. The phase grating comprises a two-dimensional array of identical subgratings that define a system of Cartesian coordinates. The subgrating and pixel arrays are sized and oriented such that the pixels are evenly distributed with... Rambus Inc

06/01/17 / #20170154665

Methods and synchronizing communication with a memory controller

A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The... Rambus Inc

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