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Sandisk Technologies Inc
Sandisk Technologies Inc_20131212

Sandisk Technologies Inc patents

Recent patent applications related to Sandisk Technologies Inc. Sandisk Technologies Inc is listed as an Agent/Assignee. Note: Sandisk Technologies Inc may have other listings under different names/spellings. We're not affiliated with Sandisk Technologies Inc, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Sandisk Technologies Inc-related inventors

Date Sandisk Technologies Inc patents (updated weekly) - BOOKMARK this page
03/23/17 new patent  Data storage device for a device accessory
03/23/17 new patent  Dynamic reconditioning of charge trapped based memory
03/23/17 new patent  Detecting data indicated as being uncorrectable at a data storage device
03/23/17 new patent  Write abort detection for multi-state memories
03/23/17 new patent  Non-volatile memory with supplemental select gates
03/23/17 new patent  Lateral stack of cobalt and a cobalt-semiconductor alloy for control gate electrodes in a memory structure
03/23/17 new patent  Method of making self-assembling floating gate electrodes for a three-diemnsional memory device
03/16/17Extending hardware queues with software queues
03/16/17System and counter flush frequency
03/16/17Multiple scheduling schemes for handling read requests
03/16/17Preserving read look ahead data in auxiliary latches
03/16/17Systems and methods of command authorization
03/16/17Proxy wordline stress for read disturb detection
03/16/17Verify operations using different sense node voltages in a memory device
03/09/17Storage device and detecting and handling burst operations
03/09/17System and file detection and usage during compaction
03/09/17Metal line with increased inter-metal breakdown voltage
03/02/17Out of order memory command fetching
03/02/17Adaptive multi-phase erase
03/02/17Memory reducing peak current consumption
03/02/17Memory performing garbage collection on blocks based on their obsolescence patterns
03/02/17Partial memory command fetching
03/02/17Dynamic memory recovery at the sub-block level
03/02/17Dynamic management of programming states to improve endurance
03/02/17Apparatus including core and clock gating circuit and operating same
03/02/17Method of making a multilevel memory stack structure using a cavity containing a sacrificial fill material
03/02/17On-the-fly syndrome and syndrome weight computation architecture for ldpc decoding
02/23/17Shallow trench isolation trenches and methods for nand memory
02/23/17Non-volatile memory having individually optimized silicide contacts and process therefor
02/16/17Soft bit techniques for a data storage device
02/16/17Systems and methods of data transfer
02/16/17Three-dimensional memory devices containing memory block bridges
02/09/17Ring oscillators for temperature detection in wideband supply noise environments
02/09/17Block storage protocol to ram bypass
02/09/17Contact plug constrained by dielectric portions
02/02/17Data storage device with command buffer management module and operating same
02/02/17Block management in a dual write memory system
02/02/17Self-describing cluster association
02/02/17Memory system and generating a seed value
02/02/17Interface adjustment processes for a data storage device
02/02/17Systems and methods of generating shaped random bits
01/26/17Memory adaptive auto-sleep and background operations
01/26/17Optimistic read operation
01/26/17Contact plug extension for bit line connection
01/26/17Select gates with central open areas
01/26/17Select gates with conductive strips on sides
01/26/17Three-dimensional memory device with metal and silicide control gates
01/19/17Storage region mapping for a data storage device
01/05/17Runtime data storage and/or retrieval
01/05/17Multi-host configuration for virtual machine caching
01/05/17Shallow trench air gaps and their formation
01/05/17Height reduction in memory periphery
12/29/16Memory health monitoring
12/29/16Clock freezing technique for charge pumps
12/29/16Differential etch of metal oxide blocking dielectric layer for three-dimensional memory devices
12/22/16Reticle with reduced transmission regions for detecting a defocus condition in a lithography process
12/22/16Memory power management
12/22/16Fast scan to detect bit line discharge time
12/22/16Sense amplifier design for ramp sensing
12/15/16Data retention in a memory block based on local heating
12/15/16Passive devices for integration with three-dimensional memory devices
12/15/16Passive devices for integration with three-dimensional memory devices
12/08/16Scheduling scheme(s) for a multi-die storage device
12/08/16Scheduling scheme(s) for a multi-die storage device
12/08/16Data storage device and storing multiple codewords and redundancy information at a word line
Patent Packs
12/08/16Multi-vt sensing method by varying bit line voltage
12/08/16Method of making a three-dimensional memory device having a heterostructure quantum well channel
12/01/16Smart ring with biometric sensor
12/01/16Multi-state programming for non-volatile memory
12/01/16Shallow trench isolation trenches and methods for nand memory
12/01/16Dynamic clock period modulation scheme for variable charge pump load currents
12/01/16Field effect transistor with elevated active regions and methods of manufacturing the same
11/24/16Method and data storage device with enhanced data retention
11/24/16Block behavior tracking in a memory system
11/24/16System and memory integrated circuit chip write abort indication
11/24/16Read disturb detection in open blocks
11/24/16Stress patterns to detect shorts in three dimensional non-volatile memory
11/24/16Shallow trench isolation trenches and methods for nand memory
11/24/16Memory hole last boxim
11/24/16Nonvolatile storage with gap in inter-gate dielectric
Patent Packs
11/24/16Transaction log acceleration
11/17/16System and storing large files in a storage device
11/17/16Systems and methods for utilizing wear leveling windows with non-volatile memory systems
11/17/16Floating gate separation in nand flash memory
11/17/16Source line formation and structure
11/10/16Protecting a removable device from short circuits
11/10/16Fast read for non-volatile storage
11/10/16Data mapping for non-volatile storage
11/10/16Three-dimensional p-i-n memory device and method reading thereof using hole current detection
11/10/16Input/output interface circuits and methods for memory devices
11/10/16Three dimensional memory device with hybrid source electrode for wafer warpage reduction
11/10/16Portable power supply unit with bus bar adapter and tool-less connection
11/10/16Low-power partial-parallel chien search architecture with polynomial degree reduction
11/03/16Memory differential thermal throttling
11/03/16Biasing schemes for storage of bits in unreliable storage locations
11/03/16System and measuring data retention in a non-volatile memory
11/03/16Multilevel memory stack structure employing support pillar structures
11/03/16Differential comparator with stable offset
11/03/16Tracking and use of tracked bit values for encoding and decoding data in unreliable memory
11/03/16Use of dummy word lines for metadata storage
11/03/16Sidewall assisted process for wide and narrow line formation
10/27/16Method and system to reduce power usage on an i/o interface
10/27/16Non-volatile memory with two phased programming
10/27/16Natural threshold voltage compaction with dual pulse program for non-volatile memory
10/27/16Blocking oxide in memory opening integration scheme for three-dimensional memory structure
10/27/16Adaptive block parameters
10/27/16Integrated circuit with hydrogen absorption structure
10/20/16Selective removal of charge-trapping layer for select gate transistor and dummy memory cells in 3d stacked memory
10/20/16Delay compensation
10/20/16Front rack cable management system and apparatus
Social Network Patent Pack
10/20/16Front rack cable management system and apparatus
10/20/16Centralized variable rate serializer and deserializer for bad column management
10/20/16Metal-semiconductor alloy region for enhancing on current in a three-dimensional memory structure
10/13/16Current based detection and recording of memory hole-interconnect spacing defects
10/13/16Non-volatile memory with prior state sensing
10/13/16Multiple bit line voltage sensing for non-volatile memory
10/13/16Three-dimensional integration schemes for reducing fluorine-induced electrical shorts
10/06/16Inherent adaptive trimming
10/06/16Memory bus management
10/06/16Ad hoc digital multi-die polling for peak icc management
Patent Packs
10/06/16Temperature dependent voltage to unselected drain side select transistor during program of 3d nand
10/06/16Semiconductor device including support pillars on solder mask
10/06/16Bridge line structure for bit line connection in a three-dimensional semiconductor device
09/29/16Memory efficient padding of memory pages
09/29/16Updating resistive memory
09/29/16Patterning for variable depth structures
09/29/163d vertical nand with iii-v channel
09/29/16Method of forming 3d vertical nand with iii-v channel
09/29/16Mid-tunneling dielectric band gap modification for enhanced data retention in a three-dimensional semiconductor device
09/29/16Shallow trench isolation trenches and methods for nand memory
09/29/16Common source line with discrete contact plugs
09/22/16Metallic etch stop layer in a three-dimensional memory structure
09/22/16Honeycomb cell structure three-dimensional non-volatile memory device
09/22/16Modular fashion accessory
09/15/16Multichip dual write
09/15/16Task queues
09/15/16Task queues
09/15/16Crystalline layer stack for forming conductive layers in a three-dimensional memory structure
09/08/16Dynamic clock rate control for power reduction
09/08/16Block management scheme to handle cluster failures in non-volatile memory
09/08/16Word line look ahead read for word line to word line short detection
09/08/16Dynamic clock rate control for power reduction
09/08/16Dynamic clock rate control for power reduction
09/08/16Systems and methods for storage error management
09/08/16Programming techniques for non-volatile memories with charge trapping layers
09/08/16Time domain ramp rate control for erase inhibit in flash memory
09/08/16System and dynamic monitoring of controller current consumption
09/01/16System, preventing data loss due to memory defects using latches
09/01/16Program verify for non-volatile storage
09/01/16Sense amplifier local feedback to control bit line voltage
Patent Packs
09/01/16Apparatus for calibrating off-chip driver/on-die termination circuits
08/25/16Method and configuring a memory device
08/25/16Adaptive host memory buffer (hmb) caching using unassisted hinting
08/25/16Data storage device and operation using multiple security protocols
08/25/16Self-aligned process using variable-fluidity material
08/18/16Multi-die status mode for non-volatile storage
08/18/16Boundary word line search and open block read methods with reduced read disturb
08/18/16Resistance-based memory with auxiliary redundancy information
08/18/16Self-aligned integrated line and via structure for a three-dimensional semiconductor device
08/18/16Non-volatile storage element with suspended charge storage region
08/11/16Memory power-based operation scheduling
08/11/16Safe mode boot loader
08/11/16Adaptive data shaping in nonvolatile memory
08/11/16Techniques for determining local interconnect defects
08/11/16Enhanced channel mobility three-dimensional memory structure and making thereof
08/11/16Memory device with comb- shaped electrode having a plurality of electrode fingers and making thereof
08/04/16Multi-die rolling status mode for non-volatile storage
08/04/16Memory delta writes
08/04/16Memory block allocation by block health
08/04/16Memory securing volatile memory during sleep mode using the same ecc module used to secure non-volatile memory during active mode
Social Network Patent Pack
08/04/16Memory reducing read disturb errors
08/04/16Molybdenum-containing conductive layers for control gate electrodes in a memory structure
07/28/16Apparatus and methods for sensing hard bit and soft bits
07/28/16Adaptive multi-page programming methods and non-volatile memory
07/28/16Partial block erase for block programming in non-volatile memory
07/28/16Method of reducing hot electron injection type of read disturb in dummy memory cells
07/28/16Pre-program detection of threshold voltages of select gate transistors in a memory device
07/28/16Double lockout in non-volatile memory
07/28/16Immediate feedback before or during programming
07/28/16Composite contact via structure containing an upper portion which fills a cavity within a lower portion
07/21/16Systems and methods for generating hint information associated with a host command
07/21/16Initialization techniques for multi-level memory cells using multi-pass programming
07/21/16Operation modes for an inverted nand architecture
07/21/16Temperature independent reference current generation for calibration
07/21/16Method and refresh programming of memory cells based on amount of threshold voltage downshift
07/21/16Selective online burn-in with adaptive and delayed verification methods for memory
07/21/16System, method and apparatus to relieve stresses in a semiconductor die caused by uneven internal metallization layers
07/21/16System, method and apparatus to relieve stresses in a semiconductor wafer caused by uneven internal metallization layers
07/21/16Semiconductor structure with concave blocking dielectric sidewall and making thereof by isotropically etching the blocking dielectric layer
07/21/16Storage operation interrupt
Social Network Patent Pack
07/14/16Addressing, interleave, wear leveling, and initialization schemes for different chip enables and memory arrays of different types
07/14/16System and memory command queue management and configurable memory status checking
07/14/16Conductive lines with protective sidewalls
07/14/16Vertical nand and making thereof using sequential stack etching and self-aligned landing pad
07/14/16Bulk driven low swing driver
07/14/16Systems and methods for storage collision management
07/14/16Three-dimensional memory device containing plural select gate transistors having different characteristics and making thereof
06/30/16Non-volatile memory systems utilizing storage address tables
06/30/16Systems and methods for storage recovery
06/30/16Low voltage detection and initialization for non-volatile memory systems
06/30/16System and utilizing history information in a memory device
06/30/16Optimizing reclaimed flash memory
06/30/16Systems and methods for choosing a memory block for the storage of data based on a frequency with which the data is updated
06/30/16Method and system for using non-volatile memory as a replacement for volatile memory
06/30/16Ring bus architecture for use in a memory module
06/30/16Method and apparatus to tune a toggle mode interface
06/30/16Methods and reducing read time for nonvolatile memory devices
06/30/16Cross-coupled level shifter with transition tracking circuits
06/30/16Systems and methods for managing storage endurance
06/30/16Techniques for programming of select gates in nand memory
06/30/16Methods for making a trim-rate tolerant self-aligned contact via structure array
06/23/16Temperature independent reference current generation for calibration
06/23/16System and managing data in a memory device
06/23/16System and adaptive memory layers in a memory device
06/23/16System and selecting blocks for garbage collection based on block health
06/23/16Dynamic programming adjustments based on memory wear, health, and endurance
06/23/16Trade-off adjustments of memory parameters based on memory wear or data retention
06/23/16Dynamic programming adjustments in memory for non-critical or low power mode tasks
06/23/16Failed bit count memory analytics
06/23/16End of life prediction to reduce retention triggered operations
Social Network Patent Pack
06/23/16Removing read disturb signatures for memory analytics
06/23/16Multi-stage decoder
06/23/16Nonvolatile memory system storing system data in marginal word lines
06/23/16Measuring memory wear and data retention individually based on cell voltage distributions
06/23/16End of life prediction based on memory wear
06/23/16Predicting memory data loss based on temperature accelerated stress time
06/23/16Memory block cycling based on memory wear or data retention
06/23/16Three dimensional nand memory having improved connection between source line and in-hole channel material as well as reduced damage to in-hole layers
06/23/16Fabricating 3d nand memory having monolithic crystalline silicon vertical nand channel
06/23/16On chip zq calibration resistor trimming
06/23/16Time domain ramp rate control for erase inhibit in flash memory
06/23/16Efficient scanning of nonvolatile memory blocks
06/23/16Methods of fabricating memory device with spaced-apart semiconductor charge storage regions
06/16/16Tag-based wear leveling for a data storage device
06/16/16Method to recover cycling damage and improve long term data retention
06/16/16Partial block erase for open block reading in non-volatile memory
06/16/16Contact for vertical memory with dopant diffusion stopper and associated fabrication method
06/16/16Model based configuration parameter management
06/16/16Three dimensional memory device with blocking dielectric having enhanced protection against fluorine attack
06/16/16Selective blocking dielectric formation in a three-dimensional memory structure
06/09/16Data programming for a memory having a three-dimensional memory configuration
06/09/16Meta plane operations for a storage device
06/09/16Memory selecting memory dies to perform memory access operations in based on memory die temperatures
06/09/16Storage parameters for a data storage device
06/09/16Approach to correct ecc errors using duplicate copies of data
06/09/16Rewritable multibit non-volatile memory with soft decode optimization
06/09/16Partial block erase for data refreshing and open-block programming
06/09/16Intrinsic memory block health monitoring
06/09/16Three-dimensional memory structure having a back gate electrode

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009


This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Sandisk Technologies Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Sandisk Technologies Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by