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Sandisk Technologies Inc
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Sandisk Technologies Inc patents

Recent patent applications related to Sandisk Technologies Inc. Sandisk Technologies Inc is listed as an Agent/Assignee. Note: Sandisk Technologies Inc may have other listings under different names/spellings. We're not affiliated with Sandisk Technologies Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Sandisk Technologies Inc-related inventors




Date Sandisk Technologies Inc patents (updated weekly) - BOOKMARK this page
08/17/17 new patent  Implementation of vmco area switching cell to vbl architecture
08/10/17Memory simplifying scheduling on a flash interface module and reducing latencies in a multi-die environment
08/10/17Multi-tier replacement memory stack structure integration scheme
08/03/17Apparatus and data sequencing
08/03/17Method and device to access auxiliary mapping data for a data structure
08/03/17Three-dimensional memory device containing an aluminum oxide etch stop layer for backside contact structure and making thereof
07/27/17Esd centric low-cost io layout design topology
07/13/17Fast settling low dropout voltage regulator
07/13/17Physical addressing schemes for non-volatile memory systems employing multi-die interleave schemes
07/13/17Non-volatile memory with efficient programming
06/29/17Parity storage management
06/08/17On-die measurement technique for i/o dc parameters vol and voh
06/08/17Writing logical groups of data to physical locations in memory using headers
06/08/17Reading logical groups of data from physical locations in memory using headers
06/08/17Efficiently managing unmapped blocks to extend life of solid state drive
06/08/17Efficiently managing unmapped blocks to extend life of solid state drive with low over-provisioning
06/08/17Vertical resistor in 3d memory device with two-tier stack
05/25/17Three dimensional nand device containing dielectric pillars for a buried source line and making thereof
05/25/173d semicircular vertical nand string with recessed inactive semiconductor channel sections
05/18/17Memory improving write performance in a multi-die environment
05/04/17On-chip self calibration of io driver impedance for pvt variation using dynamically adjusted internal reference
05/04/17System and managing extended maintenance scheduling in a non-volatile memory
05/04/17System and data compression
05/04/17Method and system for programming a multi-layer non-volatile memory having a single fold data path
05/04/17System and managing maintenance scheduling in a non-volatile memory
05/04/17System and precision interleaving of data writes in a non-volatile memory
05/04/17Convertible leaf memory mapping
05/04/17System and utilization of a data buffer by command completion in parts
05/04/17System and utilization of a data buffer
05/04/17System and rescheduling host and maintenance operations in a non-volatile memory
05/04/17Storage device operations based on bit error rate (ber) estimate
05/04/17Partial soft bit read
05/04/17User space data storage management
05/04/17Garbage collection based on queued and/or selected write commands
05/04/17System and utilization of a data buffer in a storage device
05/04/17Handling of plane failure in non-volatile storage
05/04/17Data transfer rate adjustment
05/04/17Device soft-start management for enumeration problems with usb hosts
05/04/17System and hibernation using a delta generator engine
05/04/17Dynamic threshold voltage compaction for non-volatile memory
05/04/17Non-volatile memory systems with multi-write direction memory units
05/04/17Smart skip verify mode for programming a memory device
05/04/17Field effect transistor with a multilevel gate electrode for integration with a multilevel memory device
05/04/17Crystalinity-dependent aluminum oxide etching for self-aligned blocking dielectric in a memory structure
05/04/17Three-dimensional memory devices having a shaped epitaxial channel portion and making thereof
05/04/17Three-dimensional memory devices having a shaped epitaxial channel portion
05/04/17Robust nucleation layers for enhanced fluorine protection and stress reduction in 3d nand word lines
05/04/17Esd protection circuit with two discharge time periods
05/04/17Loop delay optimization for multi-voltage self-synchronous systems
05/04/17Program sequencing
04/27/17Systems and methods of detecting errors during read operations and skipping word line portions
04/27/17System for handling erratic word lines for non-volatile memory
04/27/17Pipelined decoder with syndrome feedback path
04/27/17Syndrome-based codeword decoding
04/27/17Identifying storage descriptors based on a metric
04/27/17Multi-level data folding
04/27/17Bit line charging for a device
04/27/17Systems and methods to compensate for threshold voltage shifts
04/27/17Burn-in memory testing
04/27/17Methods and three-dimensional nand non-volatile memory devices with side source line and mechanical support
04/27/17Adaptive scheduler for decoding
04/27/17Data folding in 3d nonvolatile memory
04/27/17Bad column management in nonvolatile memory
04/20/17Systems and methods for sampling data at a non-volatile memory system
04/20/17Memory increasing read parallelism of translation pages
Patent Packs
04/20/17Detection of a sequential command stream
04/20/17Data encoding using an adjoint matrix
04/20/17Ultrathin semiconductor channel three-dimensional memory devices
04/20/17Methods for manufacturing ultrathin semiconductor channel three-dimensional memory devices
04/13/17Voltage level detection and analog circuit arrangements for memory systems
04/13/17Systems and methods for performing an adaptive sustain write in a memory system
04/13/17Descriptor data management
04/13/17Write redirect
04/13/17Systems and methods of storing data
04/13/17Data encoding techniques for a device
04/13/17Memory writing data to a block of an erased page
04/06/17Data storage device with a memory die that includes an interleaver
03/30/17Partially-bad block operation in 3-d nonvolatile memory
03/30/17Memory operation threshold adjustment based on bit line integrity data
03/30/17Zero read on trimmed blocks in a non-volatile memory system
Patent Packs
03/30/17Memory die temperature adjustment based on aging condition
03/30/17Memory die temperature adjustment based on aging condition
03/30/17Error correction based on historical bit error data
03/30/17Reduction of write amplification in object store
03/30/17Epitaxial source region for uniform threshold voltage of vertical transistors in 3d memory devices
03/30/17Memory device containing cobalt silicide control gate electrodes and making thereof
03/23/17Data storage device for a device accessory
03/23/17Dynamic reconditioning of charge trapped based memory
03/23/17Detecting data indicated as being uncorrectable at a data storage device
03/23/17Write abort detection for multi-state memories
03/23/17Non-volatile memory with supplemental select gates
03/23/17Lateral stack of cobalt and a cobalt-semiconductor alloy for control gate electrodes in a memory structure
03/23/17Method of making self-assembling floating gate electrodes for a three-diemnsional memory device
03/16/17Extending hardware queues with software queues
03/16/17System and counter flush frequency
03/16/17Multiple scheduling schemes for handling read requests
03/16/17Preserving read look ahead data in auxiliary latches
03/16/17Systems and methods of command authorization
03/16/17Proxy wordline stress for read disturb detection
03/16/17Verify operations using different sense node voltages in a memory device
03/09/17Storage device and detecting and handling burst operations
03/09/17System and file detection and usage during compaction
03/09/17Metal line with increased inter-metal breakdown voltage
03/02/17Out of order memory command fetching
03/02/17Adaptive multi-phase erase
03/02/17Memory reducing peak current consumption
03/02/17Memory performing garbage collection on blocks based on their obsolescence patterns
03/02/17Partial memory command fetching
03/02/17Dynamic memory recovery at the sub-block level
03/02/17Dynamic management of programming states to improve endurance
Social Network Patent Pack
03/02/17Apparatus including core and clock gating circuit and operating same
03/02/17Method of making a multilevel memory stack structure using a cavity containing a sacrificial fill material
03/02/17On-the-fly syndrome and syndrome weight computation architecture for ldpc decoding
02/23/17Shallow trench isolation trenches and methods for nand memory
02/23/17Non-volatile memory having individually optimized silicide contacts and process therefor
02/16/17Soft bit techniques for a data storage device
02/16/17Systems and methods of data transfer
02/16/17Three-dimensional memory devices containing memory block bridges
02/09/17Ring oscillators for temperature detection in wideband supply noise environments
02/09/17Block storage protocol to ram bypass
Patent Packs
02/09/17Contact plug constrained by dielectric portions
02/02/17Data storage device with command buffer management module and operating same
02/02/17Block management in a dual write memory system
02/02/17Self-describing cluster association
02/02/17Memory system and generating a seed value
02/02/17Interface adjustment processes for a data storage device
02/02/17Systems and methods of generating shaped random bits
01/26/17Memory adaptive auto-sleep and background operations
01/26/17Optimistic read operation
01/26/17Contact plug extension for bit line connection
01/26/17Select gates with central open areas
01/26/17Select gates with conductive strips on sides
01/26/17Three-dimensional memory device with metal and silicide control gates
01/19/17Storage region mapping for a data storage device
01/05/17Runtime data storage and/or retrieval
01/05/17Multi-host configuration for virtual machine caching
01/05/17Shallow trench air gaps and their formation
01/05/17Height reduction in memory periphery
12/29/16Memory health monitoring
12/29/16Clock freezing technique for charge pumps
12/29/16Differential etch of metal oxide blocking dielectric layer for three-dimensional memory devices
12/22/16Reticle with reduced transmission regions for detecting a defocus condition in a lithography process
12/22/16Memory power management
12/22/16Fast scan to detect bit line discharge time
12/22/16Sense amplifier design for ramp sensing
12/15/16Data retention in a memory block based on local heating
12/15/16Passive devices for integration with three-dimensional memory devices
12/15/16Passive devices for integration with three-dimensional memory devices
12/08/16Scheduling scheme(s) for a multi-die storage device
12/08/16Scheduling scheme(s) for a multi-die storage device
Patent Packs
12/08/16Data storage device and storing multiple codewords and redundancy information at a word line
12/08/16Multi-vt sensing method by varying bit line voltage
12/08/16Method of making a three-dimensional memory device having a heterostructure quantum well channel
12/01/16Smart ring with biometric sensor
12/01/16Multi-state programming for non-volatile memory
12/01/16Shallow trench isolation trenches and methods for nand memory
12/01/16Dynamic clock period modulation scheme for variable charge pump load currents
12/01/16Field effect transistor with elevated active regions and methods of manufacturing the same
11/24/16Method and data storage device with enhanced data retention
11/24/16Block behavior tracking in a memory system
11/24/16System and memory integrated circuit chip write abort indication
11/24/16Read disturb detection in open blocks
11/24/16Stress patterns to detect shorts in three dimensional non-volatile memory
11/24/16Shallow trench isolation trenches and methods for nand memory
11/24/16Memory hole last boxim
11/24/16Nonvolatile storage with gap in inter-gate dielectric
11/24/16Transaction log acceleration
11/17/16System and storing large files in a storage device
11/17/16Systems and methods for utilizing wear leveling windows with non-volatile memory systems
11/17/16Floating gate separation in nand flash memory
Social Network Patent Pack
11/17/16Source line formation and structure
11/10/16Protecting a removable device from short circuits
11/10/16Fast read for non-volatile storage
11/10/16Data mapping for non-volatile storage
11/10/16Three-dimensional p-i-n memory device and method reading thereof using hole current detection
11/10/16Input/output interface circuits and methods for memory devices
11/10/16Three dimensional memory device with hybrid source electrode for wafer warpage reduction
11/10/16Portable power supply unit with bus bar adapter and tool-less connection
11/10/16Low-power partial-parallel chien search architecture with polynomial degree reduction
11/03/16Memory differential thermal throttling
11/03/16Biasing schemes for storage of bits in unreliable storage locations
11/03/16System and measuring data retention in a non-volatile memory
11/03/16Multilevel memory stack structure employing support pillar structures
11/03/16Differential comparator with stable offset
11/03/16Tracking and use of tracked bit values for encoding and decoding data in unreliable memory
11/03/16Use of dummy word lines for metadata storage
11/03/16Sidewall assisted process for wide and narrow line formation
10/27/16Method and system to reduce power usage on an i/o interface
10/27/16Non-volatile memory with two phased programming
10/27/16Natural threshold voltage compaction with dual pulse program for non-volatile memory
Social Network Patent Pack
10/27/16Blocking oxide in memory opening integration scheme for three-dimensional memory structure
10/27/16Adaptive block parameters
10/27/16Integrated circuit with hydrogen absorption structure
10/20/16Selective removal of charge-trapping layer for select gate transistor and dummy memory cells in 3d stacked memory
10/20/16Delay compensation
10/20/16Front rack cable management system and apparatus
10/20/16Front rack cable management system and apparatus
10/20/16Centralized variable rate serializer and deserializer for bad column management
10/20/16Metal-semiconductor alloy region for enhancing on current in a three-dimensional memory structure
10/13/16Current based detection and recording of memory hole-interconnect spacing defects
10/13/16Non-volatile memory with prior state sensing
10/13/16Multiple bit line voltage sensing for non-volatile memory
10/13/16Three-dimensional integration schemes for reducing fluorine-induced electrical shorts
10/06/16Inherent adaptive trimming
10/06/16Memory bus management
10/06/16Ad hoc digital multi-die polling for peak icc management
10/06/16Temperature dependent voltage to unselected drain side select transistor during program of 3d nand
10/06/16Semiconductor device including support pillars on solder mask
10/06/16Bridge line structure for bit line connection in a three-dimensional semiconductor device
09/29/16Memory efficient padding of memory pages
09/29/16Updating resistive memory
09/29/16Patterning for variable depth structures
09/29/163d vertical nand with iii-v channel
09/29/16Method of forming 3d vertical nand with iii-v channel
09/29/16Mid-tunneling dielectric band gap modification for enhanced data retention in a three-dimensional semiconductor device
09/29/16Shallow trench isolation trenches and methods for nand memory
09/29/16Common source line with discrete contact plugs
09/22/16Metallic etch stop layer in a three-dimensional memory structure
09/22/16Honeycomb cell structure three-dimensional non-volatile memory device
09/22/16Modular fashion accessory
Social Network Patent Pack
09/15/16Multichip dual write
09/15/16Task queues
09/15/16Task queues
09/15/16Crystalline layer stack for forming conductive layers in a three-dimensional memory structure
09/08/16Dynamic clock rate control for power reduction
09/08/16Block management scheme to handle cluster failures in non-volatile memory
09/08/16Word line look ahead read for word line to word line short detection
09/08/16Dynamic clock rate control for power reduction
09/08/16Dynamic clock rate control for power reduction
09/08/16Systems and methods for storage error management
09/08/16Programming techniques for non-volatile memories with charge trapping layers
09/08/16Time domain ramp rate control for erase inhibit in flash memory
09/08/16System and dynamic monitoring of controller current consumption
09/01/16System, preventing data loss due to memory defects using latches
09/01/16Program verify for non-volatile storage
09/01/16Sense amplifier local feedback to control bit line voltage
09/01/16Apparatus for calibrating off-chip driver/on-die termination circuits
08/25/16Method and configuring a memory device
08/25/16Adaptive host memory buffer (hmb) caching using unassisted hinting
08/25/16Data storage device and operation using multiple security protocols
08/25/16Self-aligned process using variable-fluidity material
08/18/16Multi-die status mode for non-volatile storage
08/18/16Boundary word line search and open block read methods with reduced read disturb
08/18/16Resistance-based memory with auxiliary redundancy information
08/18/16Self-aligned integrated line and via structure for a three-dimensional semiconductor device
08/18/16Non-volatile storage element with suspended charge storage region
08/11/16Memory power-based operation scheduling
08/11/16Safe mode boot loader
08/11/16Adaptive data shaping in nonvolatile memory







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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