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Sandisk Technologies Llc patents

Recent patent applications related to Sandisk Technologies Llc. Sandisk Technologies Llc is listed as an Agent/Assignee. Note: Sandisk Technologies Llc may have other listings under different names/spellings. We're not affiliated with Sandisk Technologies Llc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Sandisk Technologies Llc-related inventors




Date Sandisk Technologies Llc patents (updated weekly) - BOOKMARK this page
12/14/17 new patent  Three-dimensional nand non-volatile memory and dram memory devices on a single substrate
12/14/17 new patent  Cell current based bit line voltage
12/14/17 new patent  Within-array through-memory-level via structures and making thereof
12/14/17 new patent  Method of forming a staircase in a semiconductor device using a linear alignmnent control feature
12/07/17Systems and methods for managing storage endurance
12/07/17Non-volatile memory with customized control of injection type of disturb during program verify for improved program performance
12/07/17Three-dimensional memory device having multilayer word lines containing selectively grown cobalt or ruthenium and making the same
12/07/17Through-memory-level via structures between staircase regions in a three-dimensional memory device and making thereof
11/30/17System and fast secure destruction or erase of data in a non-volatile memory
11/30/17Word line-dependent and temperature-dependent erase depth
11/30/17Reducing neighboring word line in interference using low-k oxide
11/16/17Biasing schemes for storage of bits in unreliable storage locations
11/16/17Biasing schemes for storage of bits in unreliable storage locations
11/09/17Packaging of high performance system topology for nand memory systems
11/09/17Packaging of high performance system topology for nand memory systems
11/02/17Virtualization support for storage devices
11/02/17High accuracy leakage detection through low voltage biasing
11/02/17Resistive memory elment employing electron density modulation and structural relaxation
10/26/17Volatile memory device employing a resistive memory element
10/26/17Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell
10/26/17Architecture for cmos under array
10/26/17Independent multi-plane read and low latency hybrid read
10/26/17Multi-die programming with die-jumping induced periodic delays
10/26/17Implementation of vmco area switching cell to vbl architecture
10/26/17Low power barrier modulated cell for storage class memory
10/12/17Multi-tier three-dimensional memory devices including vertically shared source lines and making thereof
10/05/17Method and system for blending data reclamation and data integrity garbage collection
10/05/17Nand structure with tier select gate transistors
10/05/17Multilevel memory stack structure employing stacks of a support pedestal structure and a support pillar structure
09/28/17Three-dimensional memory device containing vertically isolated charge storage regions and making thereof
09/28/17Shallow trench isolation trenches and methods for nand memory
09/21/17Hybrid checkpointed memory
09/21/17Three-dimensional memory device containing annular etch-stop spacer and making thereof
09/14/17Vertical resistor in 3d memory device with two-tier stack
09/07/17Erase health metric to rank memory portions
09/07/17Multi-type parity bit generation for encoding and decoding
09/07/17Ecc and raid-type decoding
09/07/17Ecc decoding using raid-type parity
09/07/17Erasure correcting coding using data subsets and partial parity symbols
09/07/17Skeleton i/o generation for early esd analysis
09/07/17Techniques for programming of select gates in nand memory
09/07/17High accuracy temperature sensor
09/07/17Convolutional low-density parity-check coding
09/07/17Method and data storage device to estimate a number of errors using convolutional low-density parity-check coding
08/31/17Single chamber multi-partition deposition tool and operating same
08/31/17Data storage device with temperature sensor and temperature calibration circuitry and operating same
08/31/17Three-dimensional memory device with vertical semiconductor bit lines located in recesses and making thereof
08/24/17Methods and systems for transitioning to and from different storage device power states using host memory buffer (hmb)
08/24/17Methods, systems, and computer readable media for storage device workload detection using power consumption
08/24/17Coalescing metadata and data writes via write serialization with device-level address remapping
08/24/17Efficient implementation of optimized host-based garbage collection strategies using xcopy and arrays of flash devices
08/24/17Efficient implementation of optimized host-based garbage collection strategies using xcopy and multiple logical stripes
08/24/17Memory-efficient block/object address mapping
08/24/17Write abort detection for multi-state memories
08/17/17System and memory integrated circuit chip write abort indication
08/17/17Multi-tier memory device with through-stack peripheral contact via structures and making thereof
08/17/17Multi-tier three-dimensional memory devices containing annular dielectric spacers within memory openings and methods of making the same
08/17/17Wordline sidewall recess for integrating planar selector device
08/17/17Self-aligned isolation dielectric structures for a three-dimensional memory device
08/10/17Data recovery in three dimensional non-volatile memory array after word line short
08/10/17Shallow trench isolation trenches and methods for nand memory
08/03/17Variable bit encoding per nand flash cell to improve device endurance and extend life of flash-based storage devices
08/03/17Programming techniques for non-volatile memories with charge trapping layers
08/03/17Vacancy-modulated conductive oxide resistive ram device including an interfacial oxygen source layer
08/03/17End of life prediction based on memory wear
Patent Packs
07/27/17Systems and methods for immediate physical erasure of data stored in a memory system in response to a user command
07/27/17Pulse mechanism for memory circuit interruption
07/27/17Proxy wordline stress for read disturb detection
07/20/17Non-volatile memory having individually optimized silicide contacts and process therefor
07/13/17Data path control for non-volatile memory
07/13/17Memory system temperature management
07/13/17Multi-level raid-type encoding with random correction capability
07/06/17Memory power management for reducing a variable credit value by a computed consumed energy value for each corresponding updated cycle
07/06/17Fast bulk secure erase at the device level
06/29/17Rewritable multibit non-volatile memory with soft decode optimization
06/29/17Key-value store with partial data access
06/29/17Solid state drive optimized for wafers
06/22/17Pulsed electron beam current probe and methods of operating the same
06/22/17Leveraging portable system power to enhance memory management and enable application level features
06/22/17Methods, systems, and computer readable media for automatically and selectively enabling burst mode operation in a storage device
Patent Packs
06/22/17Sub-block mode for non-volatile memory
06/22/17Through-memory-level via structures for a three-dimensional memory device
06/22/17Through-memory-level via structures for a three-dimensional memory device
06/22/17Through-memory-level via structures for a three-dimensional memory device
06/22/17Through-memory-level via structures for a three-dimensional memory device
06/22/17Through-memory-level via structures for a three-dimensional memory device
06/15/17Variable bit encoding per nand flash cell to extend life of flash-based storage devices and preserve over-provisioning
06/15/17Paired metablocks in non-volatile storage device
06/15/17Voltage generator to compensate for process corner and temperature variations
06/08/17Differential etch of metal oxide blocking dielectric layer for three-dimensional memory devices
06/01/17Floating staircase word lines and process in a 3d non-volatile memory having vertical bit lines
06/01/17Method of fabricating memory array having divided apart bit lines and partially divided bit line selector switches
05/25/17Multi-level logical to physical address mapping using distributed processors in non-volatile storage device
05/25/17Updating read voltages
05/25/17Method and system for adaptively adjusting a verify voltage to reduce storage raw bit error rate
05/25/17Within array replacement openings for a three-dimensional memory device
05/25/17Split memory cells with unsplit select gates in a three-dimensional memory device
05/25/17Three-dimensional nand device containing support pedestal structures for a buried source line and making the same
05/25/17Three-dimensional nand device containing support pedestal structures for a buried source line and making the same
05/18/17Variable-term error metrics adjustment
05/18/17Data logger
05/18/17State dependent sensing for wordline interference correction
05/18/17Non-volatile memory device containing oxygen-scavenging material portions and making thereof
05/18/17Memory cells including vertically oriented adjustable resistance structures
05/04/17Methods, systems, and computer readable media for aggregating completion entries in a nonvolatile storage device
05/04/17Methods, systems and computer readable media for submission queue pointer management
05/04/17Multi-processor non-volatile memory system having a lockless flow data path
05/04/17Multi-stage programming at a storage device using multiple instructions from a host
05/04/173d nand device with five-folded memory stack structure configuration
04/27/17Three dimensional non-volatile memory with current sensing programming status
Social Network Patent Pack
04/27/17Source line driver for three dimensional non-volatile memory
04/27/17Three dimensional non-volatile memory with shorting source line/bit line pairs
04/20/17Independent sense amplifier addressing and quota sharing in non-volatile memory
04/06/17Three-dimensional memory structure having a back gate electrode
04/06/17Vertical bit line non-volatile memory systems and methods of fabrication
03/30/17Methods, systems and computer readable media for intelligent fetching of data storage device commands from submission queues
03/30/17Memory die temperature adjustment based on a power condition
03/23/17Reference voltage generator for temperature sensor with trimming capability at two temperatures
03/23/17Adaptive operation of 3d nand memory
03/23/17Adaptive operation of 3d memory
Patent Packs
03/23/17Dense arrays and charge storage devices
03/16/17Power cord retainer
03/16/17Programming of nonvolatile memory with verify level dependent on memory state and programming loop count
03/09/17System and selectively routing cached objects
03/02/17Nand boosting using dynamic ramping of word line voltages
03/02/17Heat dissipation for substrate assemblies
02/16/17Process for word line connections in 3d memory
02/09/17Persistent memory manager
02/09/17Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell
02/09/173d memory having vertical switches with surround gates and method thereof
02/02/17Three dimensional nand memory having improved connection between source line and in-hole channel material as well as reduced damage to in-hole layers
02/02/17High voltage generation using low voltage devices
01/26/17Determination of word line to word line shorts between adjacent blocks
01/26/17Three-dimensional junction memory device and method reading thereof using hole current detection
01/19/17Ultrahigh density vertical nand memory device and making thereof
01/05/17Systems and methods for performing data recovery in a memory system
01/05/17Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture
12/29/16Multi-layer memory system having multiple partitions in a layer
12/22/16Memory power management
12/22/16Three dimensional nand device with channel contacting conductive source line and making thereof
12/15/16Data storage system with dynamic erase block grouping mechanism and operation thereof
12/08/16Reducing hot electron injection type of read disturb in 3d non-volatile memory for edge word lines
12/01/16Content addressable memory cells, memory arrays and methods of forming the same
12/01/16Cobalt-containing conductive layers for control gate electrodes in a memory structure
11/10/16Three dimensional memory device having well contact pillar and making thereof
11/03/16Multiheight contact via structures for a multilevel interconnect structure
10/27/16Rewritable multibit non-volatile memory with soft decode optimization
10/20/16Patterning low-k inter-metal dielectrics and associated semiconductor device
10/20/16Multiheight contact via structures for a multilevel interconnect structure
10/20/16Three dimensional nand device with channel located on three sides of lower select gate and making thereof
Patent Packs
10/20/16Vertical thin film transistor selection devices and methods of fabrication
10/06/16Vertical floating gate nand with selectively deposited ald metal films
09/29/16Nand memory strings and methods of fabrication thereof
09/29/16Method of manufacturing semiconductor device and semiconductor device having unequal pitch vertical channel transistors
09/29/16Vertical thin film transistors in non-volatile storage systems
09/22/16Systems and methods for performing adaptive host memory buffer caching of transition layer tables
09/22/16Multilevel interconnect structure and methods of manufacturing the same
09/15/16System and distributed computing in non-volatile memory
09/15/16Method of operating memory array having divided apart bit lines and partially divided bit line selector switches







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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