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Semiconductor Manufacturing International shanghai Corporation
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Semiconductor Manufacturing International shanghai Corporation patents


Recent patent applications related to Semiconductor Manufacturing International shanghai Corporation. Semiconductor Manufacturing International shanghai Corporation is listed as an Agent/Assignee. Note: Semiconductor Manufacturing International shanghai Corporation may have other listings under different names/spellings. We're not affiliated with Semiconductor Manufacturing International shanghai Corporation, we're just tracking patents.

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Semiconductor structure and fabrication method thereof

A semiconductor structure and a fabrication method are provided. A fabrication method includes providing a plurality of fins on a substrate including an NMOS region and a PMOS region adjacent to the NMOS region; forming an N-type well in the PMOS region and a P-type well in the NMOS region... Semiconductor Manufacturing International shanghai Corporation

Fin-fet devices and fabrication methods thereof

A Fin-FET device and its fabrication method are provided. The method for fabricating the Fin-FET device includes forming a plurality of fin structures on a substrate, forming an isolation film on the substrate between neighboring fin structures, removing a portion of the isolation film to form an initial isolation layer... Semiconductor Manufacturing International shanghai Corporation

Method for testing inter-layer connections

A method for testing inter-layer connections is presented. The method entails: providing a test semiconductor device, wherein the test semiconductor device comprises a two-port resistance network; measuring base input resistances on at least one of the first and the second ports of the test semiconductor device for different numbers of... Semiconductor Manufacturing International shanghai Corporation

Bandgap with system sleep mode

A method operates a bandgap voltage reference circuit that includes a bias circuit for receiving a feedback signal and outputting a bias signal, an amplifier for receiving the bias signal and outputting a first reference signal as the feedback signal, an output circuit for receiving the first reference signal and... Semiconductor Manufacturing International shanghai Corporation

Method for fluorocarbon film used as middle stop layer for porous low k film

A method for manufacturing an interconnect structure includes providing a metal interconnect layer, forming a first dielectric layer on the metal interconnect layer, forming a fluorocarbon layer on the first dielectric layer, forming a second dielectric layer on the fluorocarbon layer, and performing an etch process on the second dielectric... Semiconductor Manufacturing International shanghai Corporation

Method for improving wire bonding strength of an image sensor

A method for manufacturing a bond pad structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, and a passivation layer on the first metal layer, the passivation layer having an opening extending to the first metal layer; and filling the opening of the... Semiconductor Manufacturing International shanghai Corporation

Semiconductor structures and fabrication methods thereof

A method for fabricating a semiconductor structure includes providing a substrate including a device region, an isolation region, and a transition region between the device region and the isolation region, forming a plurality of fin structures on the device region of the substrate, forming a plurality of dummy fin structures... Semiconductor Manufacturing International shanghai Corporation

Top-down fabricating nanowire device

A method for manufacturing a semiconductor device includes providing a semiconductor substrate, performing an etch process on the semiconductor substrate to form a fin and a trench on opposite sides of the fin, forming an etch guide layer filling the trench, performing an etch process on the etch guide layer... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device and manufacturing method therefor

The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a substrate structure including a substrate and a first material layer on the substrate, wherein a recess is formed in the substrate and the... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device and manufacturing method thereof

The present disclosure relates to the technical field of semiconductor technologies and discloses a semiconductor device and a manufacturing method therefor. The method includes forming a growth substrate by providing a substrate structure containing a sacrificial substrate, a first dielectric layer on the sacrificial substrate, and a plurality of recesses... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device and manufacturing method therefor

The present disclosure relates to the technical field of semiconductor processes and discloses a semiconductor device and a manufacturing method therefor. The method includes: providing a substrate containing a first dielectric layer; forming a lower gate material layer on the first dielectric layer; patterning the lower gate material layer to... Semiconductor Manufacturing International shanghai Corporation

Method and assembling multilayer microlens array elements

A method for assembling a microlens array assembly including a set of microlens array elements having at least two array elements having a first array element and a second array element includes adsorbing the first array element using a mobile platform, adsorbing the second array element using a fixture platform,... Semiconductor Manufacturing International shanghai Corporation

Optical scattering measurement method and apparatus using micro lens matrix

An apparatus for detecting a defect on a surface of a substrate includes an optical microlens array disposed adjacent to the substrate and including an array of microlenses configured to direct light incident on a second surface of the optical microlens array to exit a first surface of the optical... Semiconductor Manufacturing International shanghai Corporation

Defect inspection method and apparatus using micro lens matrix

A substrate surface defect detection device includes an optical waveguide for receiving first light and directing the received first light to a surface of a to be tested substrate, the optical waveguide having a first surface facing toward the substrate and a second surface facing away from the substrate, a... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device, related manufacturing method, and related electronic device

A semiconductor device may include the following elements: a first doped portion; a second doped portion; an enclosing member, which encloses both the first doped portion and the second doped portion; a first barrier, which directly contacts the first doped portion; a second barrier, which directly contacts the second doped... Semiconductor Manufacturing International shanghai Corporation

Method for preventing excessive etching of edges of an insulator layer

A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a first insulator layer on the first semiconductor layer, forming a patterned second semiconductor layer on the first insulator layer, the patterned second semiconductor layer having an actual thickness greater than a... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device and fabrication method thereof

Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on a surface of the semiconductor substrate; forming an isolation flowable layer covering the plurality of fins over the semiconductor substrate; performing a first annealing process to turn... Semiconductor Manufacturing International shanghai Corporation

Die sorting apparatus and die sorting method

A die sorting apparatus includes a fixing mechanism for fixing a wafer having a plurality of dies, a positioning mechanism including an indicator for selecting a die of the wafer using die coordinates, an ejection mechanism below the wafer for applying a force to the selected die, a moving mechanism... Semiconductor Manufacturing International shanghai Corporation

Method for reducing cracks in a step-shaped cavity

A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a substrate and a multilayer film having a step-shaped portion on the substrate; forming a protective layer covering the step-shaped portion of the multilayer film; forming a capping layer having a plurality of steps on the protective... Semiconductor Manufacturing International shanghai Corporation

Protection circuit and integrated circuit

Protection circuit and integrated circuit are provided. A protection circuit includes a discharge passage, configured to perform an electro-static discharge and a controller configured to blow out the electric fuse after the discharge passage fulfills electro-static discharge. The discharge passage includes an electric fuse.... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device layout structure and manufacturing method thereof

A semiconductor device includes a semiconductor substrate, a trench isolator portion in the semiconductor substrate, a dummy gate on the semiconductor substrate, a first doped region between the trench isolator portion and the dummy gate in the semiconductor substrate, and a first connecting member electrically connected the dummy gate with... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device

The present disclosure provides a fabrication method for forming a semiconductor device, including: forming a substrate, the substrate including first fins, second fins, and a first trench located in the substrate between a first fin and an adjacent fin; forming a first mask layer on the substrate, the first fins,... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device, related manufacturing method, and related electronic device

A semiconductor device may include a first-type substrate. The semiconductor device may further include a second-type well configured to form a PN junction with the first-type substrate. The semiconductor device may further include a diode component configured to form a diode with the second-type well. The diode may be connected... Semiconductor Manufacturing International shanghai Corporation

Method for correcting target patterns and mask having corrected target patterns

Methods for correcting target patterns and masks having corrected target patterns are provided. An exemplary correction method includes dividing contours of target patterns into fragments; performing an optical proximity correction to obtain mask patterns; obtaining simulated exposure patterns; detecting the simulated exposure patterns to find out existence of at least... Semiconductor Manufacturing International shanghai Corporation

Memory array, and reading, programming and erasing memory array

Memory arrays and reading, programming and erasing methods of the memory arrays are provided. An exemplary memory array includes a plurality of memory columns. Each memory column has a plurality of flash memory cells. The memory columns are divided into at least two blocks. At least one source pull down... Semiconductor Manufacturing International shanghai Corporation

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming a substrate including a plurality of initial fins, and forming an isolation layer on the substrate between the adjacent initial fins. The method also includes forming a stop layer, and forming a filling... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device and fabrication method thereof

Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming an isolation layer in the base substrate; forming dummy gate structures on the base substrate at two sides of the isolation layer; forming an additional gate structure on the isolation layer and... Semiconductor Manufacturing International shanghai Corporation

Electrostatic discharge protection structure and fabricating method thereof

An electrostatic discharge protection structure and a fabricating method thereof are provided. The electrostatic discharge protection structure comprises: a substrate; multiple fin portions arranged on the substrate; a gate structure on the substrate across the fin portions, and on a portion of top surfaces and sidewalls of the fin portions;... Semiconductor Manufacturing International shanghai Corporation

Semiconductor structure and fabrication method thereof

Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first region, a second region and an isolation region between the first region and the second region; forming a plurality of first fins on the semiconductor substrate in the first region... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device and fabrication method thereof

Semiconductor devices and fabrication methods thereof are provided. An exemplary semiconductor device includes at least one FinFET device. The FinFET device includes a substrate, a plurality of fins protruding from the substrate, at least one gate structure on the substrate and across the plurality of fins by covering portions of... Semiconductor Manufacturing International shanghai Corporation

Laterally diffused metal-oxide-semiconductor devices and fabrication methods thereof

The present disclosure provides a laterally diffused metal-oxide-semiconductor (LDMOS) device. The LDMOS device includes a plurality of fin structures formed on a substrate including a first device region, a second device region, and an isolation region sandwiched between the two regions. An opening is formed in the fin structures in... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device and fabrication method thereof

A semiconductor device and a method for fabricating the semiconductor device are provided. The method includes providing a semiconductor substrate including a first region and a second region, and forming a plurality of fins on the semiconductor substrate in the first region and the second region. The method also includes... Semiconductor Manufacturing International shanghai Corporation

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming a base substrate, including a substrate, a gate structure on the substrate, source and drain doped regions in the substrate on both sides of the gate structure, and a dielectric layer on the... Semiconductor Manufacturing International shanghai Corporation

Semiconductor structures and fabrication methods thereof

Semiconductor structure and fabrication method thereof are provided. An exemplary method includes providing a semiconductor substrate including a plurality of first fin structures, each having a first width, and a plurality of second fin structures, each having a second width greater than the first width. The method further includes forming... Semiconductor Manufacturing International shanghai Corporation

Semiconductor structure and fabrication method thereof

Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate; forming gate structures over the base substrate; forming source/drain doping regions in the base substrate at two sides of each of the gate structures; forming an interlayer dielectric layer over the base substrate and... Semiconductor Manufacturing International shanghai Corporation

02/15/18 / #20180047638

Semiconductor structures and fabrication methods thereof

A method for fabricating a semiconductor structure includes forming a plurality of dummy gate structures on a substrate. Each dummy gate structure includes a gate dielectric layer, a dummy gate electrode, and two sidewall spacers. The method also includes forming a dielectric layer on the substrate between neighboring dummy gate... Semiconductor Manufacturing International shanghai Corporation

02/15/18 / #20180047665

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate including a device region and a peripheral region. The base substrate includes a base interconnection structure. The method also includes forming a medium layer on the base substrate. In addition,... Semiconductor Manufacturing International shanghai Corporation

02/15/18 / #20180047829

Semiconductor structure and fabrication method thereof

The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a substrate having a first region and a second region; forming a trench in the substrate in the first region; forming a compensation doping region in a side surface of the trench adjacent to... Semiconductor Manufacturing International shanghai Corporation

02/15/18 / #20180047831

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a plurality of dummy gates on a substrate, a capping layer on each dummy gate, and a dielectric layer over the substrate, wherein the dielectric layer has a top surface above each dummy... Semiconductor Manufacturing International shanghai Corporation

02/08/18 / #20180038742

Method and device for temperature measurement of finfet devices

A semiconductor structure includes a semiconductor device that includes an active region having a semiconductor fin and a gate structure across the semiconductor fin. The gate structure includes a gate electrode. The semiconductor structure also includes a gate line extending from the gate electrode and a metal wiring that is... Semiconductor Manufacturing International shanghai Corporation

02/08/18 / #20180040506

Semiconductor device and manufacture thereof

The contact hole has a wider opening in the upper part than in the lower part.... Semiconductor Manufacturing International shanghai Corporation

02/08/18 / #20180040604

Diode design of finfet device

A method for manufacturing an electrostatic discharge (ESD) protection device includes providing a semiconductor structure including a semiconductor substrate including a first region of a first conductivity type and a semiconductor fin on the semiconductor substrate; forming an electrode on the semiconductor fin; and performing a doping process on the... Semiconductor Manufacturing International shanghai Corporation

02/08/18 / #20180040605

Electrostatic discharge protection device and method

An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a semiconductor fin located on the semiconductor substrate. The semiconductor fin includes a well region, a first doped region, and a second doped region. The first doped region and the second doped region are respectively adjacent to and being... Semiconductor Manufacturing International shanghai Corporation

02/01/18 / #20180033624

Semiconductor device, related manufacturing method, and related electronic device

A method for manufacturing a semiconductor device may include the following steps: preparing a first substrate; providing a first conductor, which is configured to electrically connect two elements associated with the first substrate; providing a second conductor on the first substrate, wherein the second conductor is electrically connected to the... Semiconductor Manufacturing International shanghai Corporation

02/01/18 / #20180033734

Method for fabricating cu interconnection using graphene

A method for manufacturing an interconnect structure includes providing a substrate structure comprising a substrate, a first dielectric layer on the substrate, and a metal interconnect line formed in the first dielectric layer and extending through to a surface of the substrate; removing a portion of the first dielectric layer... Semiconductor Manufacturing International shanghai Corporation

02/01/18 / #20180033790

Increasing thickness of functional layer according to increasing recess area

A method of manufacturing a semiconductor device includes providing a substrate having first and second semiconductor fins, forming an insulating layer on the substrate having first and second recesses exposing a portion of the respective first and second semiconductor fins, forming a gate dielectric layer on the first and second... Semiconductor Manufacturing International shanghai Corporation

01/11/18 / #20180012664

Non-volatile memories and data reading methods thereof

A non-volatile memory (NVM) includes at least one memory unit region, each including a memory array and having first memory cells in the odd columns and second memory cells in the even columns. Corresponding to each memory unit region, the NVM includes a multiplexer including first bit line decoders and... Semiconductor Manufacturing International shanghai Corporation

01/11/18 / #20180012765

Semiconductor device, related manufacturing method, and related electronic device

A semiconductor device may include the following elements: a first doped region; a second doped region, which contacts the first doped region; a third doped region, which contacts the first doped region; a first dielectric layer, which contacts the above-mentioned doped regions; a first gate member, which is conductive and... Semiconductor Manufacturing International shanghai Corporation

01/11/18 / #20180012797

Method for reducing via rc delay

A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, a dielectric layer on the substrate and covering the first metal layer, and an opening extending to the first metal layer; forming a first barrier layer on a... Semiconductor Manufacturing International shanghai Corporation

01/11/18 / #20180012810

Semiconductor structures and fabrication methods thereof

A method for fabricating a semiconductor structure includes providing a base structure including a substrate, a dielectric layer formed on the substrate, a plurality of first openings formed in the dielectric layer in a first transistor region, and a plurality of second openings formed in the dielectric layer in a... Semiconductor Manufacturing International shanghai Corporation

01/11/18 / #20180012842

Semiconductor structures

A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer; simultaneously forming a plurality of discrete first metal layers and openings by etching the initial metal layer; forming a plurality of sidewalls covering the side surface of the first... Semiconductor Manufacturing International shanghai Corporation

01/11/18 / #20180012888

Semiconductor structure and fabrication method thereof

The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a plurality of fins on a semiconductor substrate; forming an anti-diffusion layer, containing anti-diffusion ions, in the fins; forming an anti-punch through layer, containing anti-punch through ions, in the fins, a top surface of... Semiconductor Manufacturing International shanghai Corporation

01/04/18 / #20180005878

Semiconductor interconnect structure and manufacturing method thereof

This semiconductor interconnect structure provides improved reliability over conventional structures.... Semiconductor Manufacturing International shanghai Corporation

01/04/18 / #20180005886

Contact structure and associated flash memory

A method for manufacturing a semiconductor device includes providing a substrate structure having an action region and a gate structure having a gate dielectric layer, a gate, a hardmask. The method also includes forming a first dielectric layer on the gate structure, forming a second dielectric layer on the first... Semiconductor Manufacturing International shanghai Corporation

01/04/18 / #20180005890

Semiconductor device and related manufacturing method

A semiconductor device may include a substrate, an n-channel field-effect transistor positioned on the substrate, and a p-channel field-effect transistor positioned on the substrate. The n-channel field-effect transistor may include an n-type silicide source portion, an n-type silicide drain portion, and a first n-type channel region. The first n-type channel... Semiconductor Manufacturing International shanghai Corporation

01/04/18 / #20180005894

Semiconductor structure having contact holes between sidewall spacers

The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality of discrete gate structures, and a plurality of sidewall spacers are formed on a semiconductor substrate. The plurality of discrete gate structures and sidewall spacers are formed in the... Semiconductor Manufacturing International shanghai Corporation

01/04/18 / #20180005915

Semiconductor device and manufacturing method therefor

The present disclosure is directed to a semiconductor device and a manufacturing method thereof, which relate to the field of semiconductor technologies. The semiconductor device includes a fin ESD element. The method includes: providing a substrate structure, where the substrate structure includes a semiconductor substrate, and a semiconductor fin for... Semiconductor Manufacturing International shanghai Corporation

01/04/18 / #20180005952

Method for capping cu layer using graphene in semiconductor

An interconnect structure includes a substrate, a dielectric layer on the substrate, a metal interconnect layer in the dielectric layer and in contact with the substrate, the metal interconnect layer having an upper surface flush with an upper surface of the dielectric layer, and a graphene layer on the metal... Semiconductor Manufacturing International shanghai Corporation

01/04/18 / #20180006031

Method and device for finfet with graphene nanoribbon

A method for forming a semiconductor device includes providing a substrate structure, which has a semiconductor substrate and a semiconductor fin on the substrate. The method also includes forming a catalytic material layer overlying the semiconductor fins, and forming an isolation region covering the catalytic material layer in a lower... Semiconductor Manufacturing International shanghai Corporation

01/04/18 / #20180006063

Semiconductor device and finfet transistor

The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least... Semiconductor Manufacturing International shanghai Corporation

01/04/18 / #20180006086

Structure and memory cell array

A memory cell array structure includes memory cells arranged in m rows and n columns on a substrate, and n columns of first and second well regions with different conductivity types alternatively arranged along the column direction. Each of the memory cells includes first and second diodes. The first diode... Semiconductor Manufacturing International shanghai Corporation

01/04/18 / #20180006112

Three-dimensional transisor

The disclosed subject matter provides a method for fabricating a three-dimensional transistor. The method includes forming an active region and two isolation structures on a semiconductor substrate. The active region is formed between the two isolation structures. The method further includes forming a photoresist layer on the active region and... Semiconductor Manufacturing International shanghai Corporation

01/04/18 / #20180006127

Mos-varactor design to improve tuning efficiency

A gate stack structure for a MOS varactor includes a substrate including a channel region, a high-k dielectric layer on the channel region of the substrate, a P-type work function adjustment layer on the high-k dielectric layer, an N-type work function adjustment layer on the P-type work function adjustment layer,... Semiconductor Manufacturing International shanghai Corporation

01/04/18 / #20180006135

Epi integrality on source/drain region of finfet

A method for manufacturing a semiconductor device includes providing a substrate structure including a semiconductor fin on a substrate, and a trench isolation structure surrounding the fin and having an upper surface flush with an upper surface of the fin and including first and second trench isolation portions on opposite... Semiconductor Manufacturing International shanghai Corporation

01/04/18 / #20180006148

Ldmos transistor and fabrication method thereof

Lateral double-diffused MOSFET transistor and fabrication method thereof are provided. A shallow trench isolation structure is formed in a semiconductor substrate. A drift region is formed in the semiconductor substrate and surrounding the shallow trench isolation structure. A body region is formed in the semiconductor substrate and distanced from the... Semiconductor Manufacturing International shanghai Corporation

Patent Packs
01/04/18 / #20180006162

Finfet varactor

A varactor transistor includes a semiconductor fin having a first conductivity type, a plurality of gate structures separated from each other and surrounding a portion of the semiconductor fin. The plurality of gates structures include a dummy gate structure on an edge of the semiconductor fin, and a first gate... Semiconductor Manufacturing International shanghai Corporation

01/04/18 / #20180006169

Method for fabricating nanopillar solar cell using graphene

A method of manufacturing a semiconductor device includes providing a substrate structure. The substrate structure includes a conductive layer and a plurality of nanopillars spaced apart from each other overlying the conductive layer. Each nanopillar includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer.... Semiconductor Manufacturing International shanghai Corporation

12/28/17 / #20170370698

Measuring system and measuring method

System and method for measuring an aerial image are provided. The system may include a lighting unit for providing illuminating light to pass through a mask to form initial light. An imaging unit is configured for imaging the initial light to form imaging light. A beam splitting unit is for... Semiconductor Manufacturing International shanghai Corporation

12/28/17 / #20170373060

Device for a finfet

A semiconductor device includes a semiconductor substrate, multiple fins formed on a front surface of the semiconductor substrate, a stress layer formed on a top surface of the fins, multiple strip-shaped gate structures formed above the stress layers, each of which extending in a direction substantially perpendicular to a direction... Semiconductor Manufacturing International shanghai Corporation

12/28/17 / #20170373169

Semiconductor structure

A method for forming a semiconductor structure includes providing a semiconductor substrate having a metal gate structure formed on the semiconductor substrate; forming a first dielectric layer covering a side surface of the metal gate structure on the semiconductor substrate; forming a cap layer on the metal gate structure; etching... Semiconductor Manufacturing International shanghai Corporation

12/21/17 / #20170365479

Semiconductor device

The present disclosure provides semiconductor devices and fabrication methods thereof. A work function layer is formed on the semiconductor substrate. A buffer layer is formed on the work function layer. The work function layer is doped through the buffer layer with impurity ions. The buffer layer obstructs a flow of... Semiconductor Manufacturing International shanghai Corporation

12/21/17 / #20170365527

Transistor, semiconductor structure, and fabrication method thereof

A method for forming a transistor is provided. The method includes providing a semiconductor substrate, and forming a dielectric layer on the semiconductor substrate. The dielectric layer has a gate structure recess. The method also includes forming a work function layer on a bottom and sidewalls of the gate structure... Semiconductor Manufacturing International shanghai Corporation

12/21/17 / #20170365602

Ldmos design for a finfet device

A method of manufacturing a semiconductor device is provided. The device includes a substrate including a first type region and a second type region, first and second fins protruding from the substrate and separated by a trench. The first fin includes first and second portions of the first type on... Semiconductor Manufacturing International shanghai Corporation

12/21/17 / #20170365603

Ldmos finfet device

A method of manufacturing a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, first and second fins on the semiconductor substrate and separated by a trench. The first fin includes a first portion having a first conductivity type and a second portion having a second conductivity type... Semiconductor Manufacturing International shanghai Corporation

12/21/17 / #20170365690

Transistor device and fabrication method

Transistor devices and fabrication methods are provided. A transistor is formed by forming a dummy gate film on a substrate and doping an upper portion of the dummy gate film to form a modified film. The modified film and the remaining dummy gate film are etched to form a modified... Semiconductor Manufacturing International shanghai Corporation

12/14/17 / #20170358577

Field-effect-transistors and fabrication methods thereof

A method for fabrication a field-effect-transistor includes forming a plurality of fin structures on a substrate, forming a gate structure across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, forming a first doped layer, made of a first semiconductor material and doped... Semiconductor Manufacturing International shanghai Corporation

12/14/17 / #20170358578

Fin-fet devices and fabrication methods thereof

A method for fabricating a Fin-FET includes forming a plurality of fin structures, an isolation layer, and an interlayer dielectric layer on an NMOS region of a substrate, forming a first opening in the interlayer dielectric layer to expose a portion of the fin structures. A region adjacent to a... Semiconductor Manufacturing International shanghai Corporation

12/14/17 / #20170358661

Semiconductor device and fabrication method thereof

The present disclosure provides a method for forming a semiconductor device, including: providing a substrate; forming a gate material layer over the substrate; performing a first etching process on the gate material layer to remove a first portion of the gate material layer and expose a first portion of the... Semiconductor Manufacturing International shanghai Corporation

12/14/17 / #20170358676

Semiconductor device

The present disclosure provides semiconductor devices and fabrication methods thereof. A stacked substrate includes an insulating layer between a substrate and a semiconductor layer. First openings are formed in the semiconductor layer to define a first distance between adjacent sidewalls of adjacent first openings. Spacers are formed on sidewall surfaces... Semiconductor Manufacturing International shanghai Corporation

12/07/17 / #20170348819

Chemical mechanical polishing (cmp) apparatus and method

A chemical mechanical polishing apparatus includes a polishing zone having a wafer entrance and a wafer exit, first wafer platform, polishing module, slurry injection module, polishing cleaning module, and film-thickness measuring module. The first wafer platform includes a wafer loading region, and is able to move from the wafer entrance... Semiconductor Manufacturing International shanghai Corporation

Patent Packs
12/07/17 / #20170351622

Self-enabled bus conflict detection circuit

A bus contention detection circuit includes a delay unit having an input terminal for receiving an output signal of an I/O driver, a duty cycle adjustment unit connected to the delay unit, and a comparison unit having a first input terminal for receiving the output signal, a second terminal for... Semiconductor Manufacturing International shanghai Corporation

12/07/17 / #20170352389

Word line voltage generator for multiple-time programmable memory

A word line voltage generator circuit, a semiconductor device, and an electronic device are provided. The word line voltage generator circuit includes a switch circuit connected to a high-level signal and a low-level signal and configured to output the high-level signal or the low-level signal as a word line voltage... Semiconductor Manufacturing International shanghai Corporation

12/07/17 / #20170352595

Method for reducing n-type finfet source and drain resistance

A method of manufacturing a semiconductor device includes providing a substrate structure, the substrate structure having a semiconductor substrate including a first semiconductor fin, a first gate structure, and a first mask layer on a first semiconductor region. The method includes forming a second mask layer on the substrate structure,... Semiconductor Manufacturing International shanghai Corporation

12/07/17 / #20170352653

Esd protection device and method

An ESD protection device includes a substrate structure having a substrate, first and second fins, and first and second doped regions having different conductivity types. The first doped region includes a first portion of the substrate and a first region of the first fin, the second doped region includes a... Semiconductor Manufacturing International shanghai Corporation

12/07/17 / #20170352658

Method for forming finfet device

A method includes providing a semiconductor structure including an active region having a first doped region, a first contact member on the first doped region, first and second gates on opposite sides of the first contact member, an interlayer dielectric layer surrounding the first and second gates and the first... Semiconductor Manufacturing International shanghai Corporation

12/07/17 / #20170352663

Semiconductor device and manufacturing method therefor

The present disclosure provides a semiconductor device and a manufacturing method therefor. The device may include: a semiconductor substrate; a fin projecting from the semiconductor substrate, where trenches are formed on sides of the fin; a first insulator layer partially filling the trenches, where the fin protrudes from the first... Semiconductor Manufacturing International shanghai Corporation

12/07/17 / #20170352668

Method and device for finfet sram

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an interlayer dielectric layer, multiple trenches in the interlayer dielectric layer including first, second, third trenches for forming respective gate structures of first, second, and third transistors, forming an interface layer on the bottom of... Semiconductor Manufacturing International shanghai Corporation

12/07/17 / #20170352739

Method and device for compound semiconductor fin structure

A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate, forming a stack of semiconductor layer structures on the first semiconductor layer, and etching the stack to form a fin structure. Each of the semiconductor layer structures includes a first insulator layer and a... Semiconductor Manufacturing International shanghai Corporation

12/07/17 / #20170352758

Semiconductor device and manufacturing method therefor

The present disclosure relates to the technical field of semiconductors and discloses a semiconductor device and a manufacturing method therefor. Forms of the method may include: providing a substrate structure, where the substrate structure includes: a semiconductor substrate, a semiconductor fin on the semiconductor substrate, isolation regions at two sides... Semiconductor Manufacturing International shanghai Corporation

11/30/17 / #20170345660

Ldmos transistor, esd device, and fabrication method thereof

A method is provided for fabricating an LDMOS transistor. The method includes providing a base substrate. The method also includes forming a first well area doped with a first well ion in the base substrate. In addition, the method includes forming a second well area doped with a second well... Semiconductor Manufacturing International shanghai Corporation

11/30/17 / #20170345916

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating a semiconductor structure are provided. The method includes forming one or more fins on a substrate, wherein each fin includes a first sidewall and a second sidewall opposing each other. The method also includes forming a sacrificial layer over the fin. Further,... Semiconductor Manufacturing International shanghai Corporation

11/16/17 / #20170329241

Alignment method and alignment system thereof

An alignment method and an alignment system are provided. The alignment method includes: providing a wafer including an exposed surface, wherein an alignment mark and a reference point with a reference distance are provided on the exposed surface; placing the wafer on a reference plane; performing an alignment measurement on... Semiconductor Manufacturing International shanghai Corporation

11/16/17 / #20170330602

Memory and reference circuit calibration method thereof

A memory and a reference circuit calibration method are provided. The memory includes: a memory array including a plurality of memory cells; a reference circuit including a reference memory cell and a reference connection terminal, wherein the reference memory cell is a same as the memory cell; a calibration circuit... Semiconductor Manufacturing International shanghai Corporation

11/16/17 / #20170330758

Semiconductor structure and fabrication method thereof

A method is provided for fabricating a semiconductor structure. The method includes providing a substrate including a first region for forming a first transistor and a second region for forming a second transistor. The method also includes forming a first stress layer in the substrate in the first region and... Semiconductor Manufacturing International shanghai Corporation

11/16/17 / #20170330765

Semiconductor structure and fabrication method thereof

A method is provided for fabricating a semiconductor structure. The method includes forming a base substrate including a substrate and a stress layer formed in the substrate, where a top surface of the stress layer is higher than a surface of the substrate. The method also includes forming a first... Semiconductor Manufacturing International shanghai Corporation

11/16/17 / #20170330879

Fin-fet devices and fabrication methods thereof

A method for fabricating a Fin-FET device includes forming a fin structure on a semiconductor substrate having two peripheral regions and a core region, forming a plurality of dummy gate structures across the fin structure in the core region with each including a dummy gate electrode layer on top and... Semiconductor Manufacturing International shanghai Corporation

11/09/17 / #20170323888

Finfet and fabrication method thereof

A method is provided for fabricating a FinFET. The method includes providing a substrate including an NMOS region; forming a plurality of fins on the substrate; forming an isolation layer between adjacent fins and on the substrate; forming a gate structure across a length portion of the fin; forming a... Semiconductor Manufacturing International shanghai Corporation

11/02/17 / #20170317037

Method for manufacturing a seal ring structure to avoid delamination defect

A method for manufacturing a semiconductor device includes providing a semiconductor substrate, forming a plurality of integrated circuit (IC) devices on the semiconductor substrate, and forming a seal ring structure surrounding each of the IC devices. Forming the seal ring structure includes forming a plurality of interlayer dielectric layers on... Semiconductor Manufacturing International shanghai Corporation

11/02/17 / #20170317218

Transistor and fabrication method thereof

A method for fabricating a transistor is provided. The method includes providing a semiconductor substrate; and forming at least a nanowire suspending in the semiconductor substrate. The method also includes forming a channel layer surrounding the nanowire; and forming a contact layer surrounding the channel layer. Further, the method includes... Semiconductor Manufacturing International shanghai Corporation

10/26/17 / #20170309474

Metal interconnect structure

A method is provided for fabricating a metal interconnect structure. The method includes forming a reticle having a metal line pattern region and at least a scattering bar by an optical proximity correction process; and providing a semiconductor substrate having a first dielectric layer and at least one conductive via.... Semiconductor Manufacturing International shanghai Corporation

10/26/17 / #20170309513

Method for improving adhesion between porous low k dielectric and barrier layer

A semiconductor device includes a semiconductor substrate, a porous low-k dielectric layer, a copper interconnect structure in the porous low-k dielectric layer, a diffusion barrier layer disposed between the copper interconnect structure and the porous low-k dielectric layer, and a silicon nitride layer disposed between the diffusion barrier layer and... Semiconductor Manufacturing International shanghai Corporation

10/26/17 / #20170309536

Method and appratus for semiconductor packaging

A method of forming a package includes providing a die, which includes a substrate having a circuit, a first passivation layer on the substrate, a plurality of pads on the first passivation layer, and a second passivation layer disposed on the first passivation layer and covering the plurality of pads.... Semiconductor Manufacturing International shanghai Corporation








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