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Semiconductor Manufacturing International shanghai Corporation
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Semiconductor Manufacturing International shanghai Corporation patents


Recent patent applications related to Semiconductor Manufacturing International shanghai Corporation. Semiconductor Manufacturing International shanghai Corporation is listed as an Agent/Assignee. Note: Semiconductor Manufacturing International shanghai Corporation may have other listings under different names/spellings. We're not affiliated with Semiconductor Manufacturing International shanghai Corporation, we're just tracking patents.

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Non-volatile memories and data reading methods thereof

A non-volatile memory (NVM) includes at least one memory unit region, each including a memory array and having first memory cells in the odd columns and second memory cells in the even columns. Corresponding to each memory unit region, the NVM includes a multiplexer including first bit line decoders and... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device, related manufacturing method, and related electronic device

A semiconductor device may include the following elements: a first doped region; a second doped region, which contacts the first doped region; a third doped region, which contacts the first doped region; a first dielectric layer, which contacts the above-mentioned doped regions; a first gate member, which is conductive and... Semiconductor Manufacturing International shanghai Corporation

Method for reducing via rc delay

A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, a dielectric layer on the substrate and covering the first metal layer, and an opening extending to the first metal layer; forming a first barrier layer on a... Semiconductor Manufacturing International shanghai Corporation

Semiconductor structures and fabrication methods thereof

A method for fabricating a semiconductor structure includes providing a base structure including a substrate, a dielectric layer formed on the substrate, a plurality of first openings formed in the dielectric layer in a first transistor region, and a plurality of second openings formed in the dielectric layer in a... Semiconductor Manufacturing International shanghai Corporation

Semiconductor structures

A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer; simultaneously forming a plurality of discrete first metal layers and openings by etching the initial metal layer; forming a plurality of sidewalls covering the side surface of the first... Semiconductor Manufacturing International shanghai Corporation

Semiconductor structure and fabrication method thereof

The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a plurality of fins on a semiconductor substrate; forming an anti-diffusion layer, containing anti-diffusion ions, in the fins; forming an anti-punch through layer, containing anti-punch through ions, in the fins, a top surface of... Semiconductor Manufacturing International shanghai Corporation

Semiconductor interconnect structure and manufacturing method thereof

This semiconductor interconnect structure provides improved reliability over conventional structures.... Semiconductor Manufacturing International shanghai Corporation

Contact structure and associated flash memory

A method for manufacturing a semiconductor device includes providing a substrate structure having an action region and a gate structure having a gate dielectric layer, a gate, a hardmask. The method also includes forming a first dielectric layer on the gate structure, forming a second dielectric layer on the first... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device and related manufacturing method

A semiconductor device may include a substrate, an n-channel field-effect transistor positioned on the substrate, and a p-channel field-effect transistor positioned on the substrate. The n-channel field-effect transistor may include an n-type silicide source portion, an n-type silicide drain portion, and a first n-type channel region. The first n-type channel... Semiconductor Manufacturing International shanghai Corporation

Semiconductor structure having contact holes between sidewall spacers

The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality of discrete gate structures, and a plurality of sidewall spacers are formed on a semiconductor substrate. The plurality of discrete gate structures and sidewall spacers are formed in the... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device and manufacturing method therefor

The present disclosure is directed to a semiconductor device and a manufacturing method thereof, which relate to the field of semiconductor technologies. The semiconductor device includes a fin ESD element. The method includes: providing a substrate structure, where the substrate structure includes a semiconductor substrate, and a semiconductor fin for... Semiconductor Manufacturing International shanghai Corporation

Method for capping cu layer using graphene in semiconductor

An interconnect structure includes a substrate, a dielectric layer on the substrate, a metal interconnect layer in the dielectric layer and in contact with the substrate, the metal interconnect layer having an upper surface flush with an upper surface of the dielectric layer, and a graphene layer on the metal... Semiconductor Manufacturing International shanghai Corporation

Method and device for finfet with graphene nanoribbon

A method for forming a semiconductor device includes providing a substrate structure, which has a semiconductor substrate and a semiconductor fin on the substrate. The method also includes forming a catalytic material layer overlying the semiconductor fins, and forming an isolation region covering the catalytic material layer in a lower... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device and finfet transistor

The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least... Semiconductor Manufacturing International shanghai Corporation

Structure and memory cell array

A memory cell array structure includes memory cells arranged in m rows and n columns on a substrate, and n columns of first and second well regions with different conductivity types alternatively arranged along the column direction. Each of the memory cells includes first and second diodes. The first diode... Semiconductor Manufacturing International shanghai Corporation

Three-dimensional transisor

The disclosed subject matter provides a method for fabricating a three-dimensional transistor. The method includes forming an active region and two isolation structures on a semiconductor substrate. The active region is formed between the two isolation structures. The method further includes forming a photoresist layer on the active region and... Semiconductor Manufacturing International shanghai Corporation

Mos-varactor design to improve tuning efficiency

A gate stack structure for a MOS varactor includes a substrate including a channel region, a high-k dielectric layer on the channel region of the substrate, a P-type work function adjustment layer on the high-k dielectric layer, an N-type work function adjustment layer on the P-type work function adjustment layer,... Semiconductor Manufacturing International shanghai Corporation

Epi integrality on source/drain region of finfet

A method for manufacturing a semiconductor device includes providing a substrate structure including a semiconductor fin on a substrate, and a trench isolation structure surrounding the fin and having an upper surface flush with an upper surface of the fin and including first and second trench isolation portions on opposite... Semiconductor Manufacturing International shanghai Corporation

Ldmos transistor and fabrication method thereof

Lateral double-diffused MOSFET transistor and fabrication method thereof are provided. A shallow trench isolation structure is formed in a semiconductor substrate. A drift region is formed in the semiconductor substrate and surrounding the shallow trench isolation structure. A body region is formed in the semiconductor substrate and distanced from the... Semiconductor Manufacturing International shanghai Corporation

Finfet varactor

A varactor transistor includes a semiconductor fin having a first conductivity type, a plurality of gate structures separated from each other and surrounding a portion of the semiconductor fin. The plurality of gates structures include a dummy gate structure on an edge of the semiconductor fin, and a first gate... Semiconductor Manufacturing International shanghai Corporation

Method for fabricating nanopillar solar cell using graphene

A method of manufacturing a semiconductor device includes providing a substrate structure. The substrate structure includes a conductive layer and a plurality of nanopillars spaced apart from each other overlying the conductive layer. Each nanopillar includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer.... Semiconductor Manufacturing International shanghai Corporation

Measuring system and measuring method

System and method for measuring an aerial image are provided. The system may include a lighting unit for providing illuminating light to pass through a mask to form initial light. An imaging unit is configured for imaging the initial light to form imaging light. A beam splitting unit is for... Semiconductor Manufacturing International shanghai Corporation

Device for a finfet

A semiconductor device includes a semiconductor substrate, multiple fins formed on a front surface of the semiconductor substrate, a stress layer formed on a top surface of the fins, multiple strip-shaped gate structures formed above the stress layers, each of which extending in a direction substantially perpendicular to a direction... Semiconductor Manufacturing International shanghai Corporation

Semiconductor structure

A method for forming a semiconductor structure includes providing a semiconductor substrate having a metal gate structure formed on the semiconductor substrate; forming a first dielectric layer covering a side surface of the metal gate structure on the semiconductor substrate; forming a cap layer on the metal gate structure; etching... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device

The present disclosure provides semiconductor devices and fabrication methods thereof. A work function layer is formed on the semiconductor substrate. A buffer layer is formed on the work function layer. The work function layer is doped through the buffer layer with impurity ions. The buffer layer obstructs a flow of... Semiconductor Manufacturing International shanghai Corporation

Transistor, semiconductor structure, and fabrication method thereof

A method for forming a transistor is provided. The method includes providing a semiconductor substrate, and forming a dielectric layer on the semiconductor substrate. The dielectric layer has a gate structure recess. The method also includes forming a work function layer on a bottom and sidewalls of the gate structure... Semiconductor Manufacturing International shanghai Corporation

Ldmos design for a finfet device

A method of manufacturing a semiconductor device is provided. The device includes a substrate including a first type region and a second type region, first and second fins protruding from the substrate and separated by a trench. The first fin includes first and second portions of the first type on... Semiconductor Manufacturing International shanghai Corporation

Ldmos finfet device

A method of manufacturing a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, first and second fins on the semiconductor substrate and separated by a trench. The first fin includes a first portion having a first conductivity type and a second portion having a second conductivity type... Semiconductor Manufacturing International shanghai Corporation

Transistor device and fabrication method

Transistor devices and fabrication methods are provided. A transistor is formed by forming a dummy gate film on a substrate and doping an upper portion of the dummy gate film to form a modified film. The modified film and the remaining dummy gate film are etched to form a modified... Semiconductor Manufacturing International shanghai Corporation

Field-effect-transistors and fabrication methods thereof

A method for fabrication a field-effect-transistor includes forming a plurality of fin structures on a substrate, forming a gate structure across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, forming a first doped layer, made of a first semiconductor material and doped... Semiconductor Manufacturing International shanghai Corporation

Fin-fet devices and fabrication methods thereof

A method for fabricating a Fin-FET includes forming a plurality of fin structures, an isolation layer, and an interlayer dielectric layer on an NMOS region of a substrate, forming a first opening in the interlayer dielectric layer to expose a portion of the fin structures. A region adjacent to a... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device and fabrication method thereof

The present disclosure provides a method for forming a semiconductor device, including: providing a substrate; forming a gate material layer over the substrate; performing a first etching process on the gate material layer to remove a first portion of the gate material layer and expose a first portion of the... Semiconductor Manufacturing International shanghai Corporation

Semiconductor device

The present disclosure provides semiconductor devices and fabrication methods thereof. A stacked substrate includes an insulating layer between a substrate and a semiconductor layer. First openings are formed in the semiconductor layer to define a first distance between adjacent sidewalls of adjacent first openings. Spacers are formed on sidewall surfaces... Semiconductor Manufacturing International shanghai Corporation

Chemical mechanical polishing (cmp) apparatus and method

A chemical mechanical polishing apparatus includes a polishing zone having a wafer entrance and a wafer exit, first wafer platform, polishing module, slurry injection module, polishing cleaning module, and film-thickness measuring module. The first wafer platform includes a wafer loading region, and is able to move from the wafer entrance... Semiconductor Manufacturing International shanghai Corporation

Self-enabled bus conflict detection circuit

A bus contention detection circuit includes a delay unit having an input terminal for receiving an output signal of an I/O driver, a duty cycle adjustment unit connected to the delay unit, and a comparison unit having a first input terminal for receiving the output signal, a second terminal for... Semiconductor Manufacturing International shanghai Corporation

12/07/17 / #20170352389

Word line voltage generator for multiple-time programmable memory

A word line voltage generator circuit, a semiconductor device, and an electronic device are provided. The word line voltage generator circuit includes a switch circuit connected to a high-level signal and a low-level signal and configured to output the high-level signal or the low-level signal as a word line voltage... Semiconductor Manufacturing International shanghai Corporation

12/07/17 / #20170352595

Method for reducing n-type finfet source and drain resistance

A method of manufacturing a semiconductor device includes providing a substrate structure, the substrate structure having a semiconductor substrate including a first semiconductor fin, a first gate structure, and a first mask layer on a first semiconductor region. The method includes forming a second mask layer on the substrate structure,... Semiconductor Manufacturing International shanghai Corporation

12/07/17 / #20170352653

Esd protection device and method

An ESD protection device includes a substrate structure having a substrate, first and second fins, and first and second doped regions having different conductivity types. The first doped region includes a first portion of the substrate and a first region of the first fin, the second doped region includes a... Semiconductor Manufacturing International shanghai Corporation

12/07/17 / #20170352658

Method for forming finfet device

A method includes providing a semiconductor structure including an active region having a first doped region, a first contact member on the first doped region, first and second gates on opposite sides of the first contact member, an interlayer dielectric layer surrounding the first and second gates and the first... Semiconductor Manufacturing International shanghai Corporation

12/07/17 / #20170352663

Semiconductor device and manufacturing method therefor

The present disclosure provides a semiconductor device and a manufacturing method therefor. The device may include: a semiconductor substrate; a fin projecting from the semiconductor substrate, where trenches are formed on sides of the fin; a first insulator layer partially filling the trenches, where the fin protrudes from the first... Semiconductor Manufacturing International shanghai Corporation

12/07/17 / #20170352668

Method and device for finfet sram

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an interlayer dielectric layer, multiple trenches in the interlayer dielectric layer including first, second, third trenches for forming respective gate structures of first, second, and third transistors, forming an interface layer on the bottom of... Semiconductor Manufacturing International shanghai Corporation

12/07/17 / #20170352739

Method and device for compound semiconductor fin structure

A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate, forming a stack of semiconductor layer structures on the first semiconductor layer, and etching the stack to form a fin structure. Each of the semiconductor layer structures includes a first insulator layer and a... Semiconductor Manufacturing International shanghai Corporation

12/07/17 / #20170352758

Semiconductor device and manufacturing method therefor

The present disclosure relates to the technical field of semiconductors and discloses a semiconductor device and a manufacturing method therefor. Forms of the method may include: providing a substrate structure, where the substrate structure includes: a semiconductor substrate, a semiconductor fin on the semiconductor substrate, isolation regions at two sides... Semiconductor Manufacturing International shanghai Corporation

11/30/17 / #20170345660

Ldmos transistor, esd device, and fabrication method thereof

A method is provided for fabricating an LDMOS transistor. The method includes providing a base substrate. The method also includes forming a first well area doped with a first well ion in the base substrate. In addition, the method includes forming a second well area doped with a second well... Semiconductor Manufacturing International shanghai Corporation

11/30/17 / #20170345916

Semiconductor structure and fabrication method thereof

A semiconductor structure and a method for fabricating a semiconductor structure are provided. The method includes forming one or more fins on a substrate, wherein each fin includes a first sidewall and a second sidewall opposing each other. The method also includes forming a sacrificial layer over the fin. Further,... Semiconductor Manufacturing International shanghai Corporation

11/16/17 / #20170329241

Alignment method and alignment system thereof

An alignment method and an alignment system are provided. The alignment method includes: providing a wafer including an exposed surface, wherein an alignment mark and a reference point with a reference distance are provided on the exposed surface; placing the wafer on a reference plane; performing an alignment measurement on... Semiconductor Manufacturing International shanghai Corporation

11/16/17 / #20170330602

Memory and reference circuit calibration method thereof

A memory and a reference circuit calibration method are provided. The memory includes: a memory array including a plurality of memory cells; a reference circuit including a reference memory cell and a reference connection terminal, wherein the reference memory cell is a same as the memory cell; a calibration circuit... Semiconductor Manufacturing International shanghai Corporation

11/16/17 / #20170330758

Semiconductor structure and fabrication method thereof

A method is provided for fabricating a semiconductor structure. The method includes providing a substrate including a first region for forming a first transistor and a second region for forming a second transistor. The method also includes forming a first stress layer in the substrate in the first region and... Semiconductor Manufacturing International shanghai Corporation

11/16/17 / #20170330765

Semiconductor structure and fabrication method thereof

A method is provided for fabricating a semiconductor structure. The method includes forming a base substrate including a substrate and a stress layer formed in the substrate, where a top surface of the stress layer is higher than a surface of the substrate. The method also includes forming a first... Semiconductor Manufacturing International shanghai Corporation

11/16/17 / #20170330879

Fin-fet devices and fabrication methods thereof

A method for fabricating a Fin-FET device includes forming a fin structure on a semiconductor substrate having two peripheral regions and a core region, forming a plurality of dummy gate structures across the fin structure in the core region with each including a dummy gate electrode layer on top and... Semiconductor Manufacturing International shanghai Corporation

11/09/17 / #20170323888

Finfet and fabrication method thereof

A method is provided for fabricating a FinFET. The method includes providing a substrate including an NMOS region; forming a plurality of fins on the substrate; forming an isolation layer between adjacent fins and on the substrate; forming a gate structure across a length portion of the fin; forming a... Semiconductor Manufacturing International shanghai Corporation

11/02/17 / #20170317037

Method for manufacturing a seal ring structure to avoid delamination defect

A method for manufacturing a semiconductor device includes providing a semiconductor substrate, forming a plurality of integrated circuit (IC) devices on the semiconductor substrate, and forming a seal ring structure surrounding each of the IC devices. Forming the seal ring structure includes forming a plurality of interlayer dielectric layers on... Semiconductor Manufacturing International shanghai Corporation

11/02/17 / #20170317218

Transistor and fabrication method thereof

A method for fabricating a transistor is provided. The method includes providing a semiconductor substrate; and forming at least a nanowire suspending in the semiconductor substrate. The method also includes forming a channel layer surrounding the nanowire; and forming a contact layer surrounding the channel layer. Further, the method includes... Semiconductor Manufacturing International shanghai Corporation

10/26/17 / #20170309474

Metal interconnect structure

A method is provided for fabricating a metal interconnect structure. The method includes forming a reticle having a metal line pattern region and at least a scattering bar by an optical proximity correction process; and providing a semiconductor substrate having a first dielectric layer and at least one conductive via.... Semiconductor Manufacturing International shanghai Corporation

10/26/17 / #20170309513

Method for improving adhesion between porous low k dielectric and barrier layer

A semiconductor device includes a semiconductor substrate, a porous low-k dielectric layer, a copper interconnect structure in the porous low-k dielectric layer, a diffusion barrier layer disposed between the copper interconnect structure and the porous low-k dielectric layer, and a silicon nitride layer disposed between the diffusion barrier layer and... Semiconductor Manufacturing International shanghai Corporation

10/26/17 / #20170309536

Method and appratus for semiconductor packaging

A method of forming a package includes providing a die, which includes a substrate having a circuit, a first passivation layer on the substrate, a plurality of pads on the first passivation layer, and a second passivation layer disposed on the first passivation layer and covering the plurality of pads.... Semiconductor Manufacturing International shanghai Corporation

10/19/17 / #20170301545

Transistor and fabrication method thereof

A transistor and a method of forming the transistor are provided. The method includes forming a first interlayer dielectric layer on a substrate, forming an opening through the first interlayer dielectric layer, and forming a work function layer over side surfaces and a bottom of the opening. The method further... Semiconductor Manufacturing International shanghai Corporation

10/19/17 / #20170301570

Wafer cassette and placement method thereof

A wafer cassette and a method for placing a wafer are provided. The wafer cassette includes a box body including a plurality of groups of card slots formed on sidewalls of the box body. Each group of the card slots is configured to hold a wafer and includes a wafer... Semiconductor Manufacturing International shanghai Corporation

10/19/17 / #20170301644

Clamping system, wire bonding machine, and bonding wires

A clamping system, a wire bonding machine and a method for bonding wires are provided. An exemplary clamping system includes a clamping device. The clamping device includes: at least one linear guide rail; a first clamping rod arranged perpendicular to the linear guide rail; and a second clamping rod arranged... Semiconductor Manufacturing International shanghai Corporation

10/19/17 / #20170301730

Memory cell structures

A memory cell includes a first diode, a second diode, and a random access memory cell element. The first diode and the random access memory cell element are series connected between a bit line and a word line. The second diode and the random access memory cell element are series... Semiconductor Manufacturing International shanghai Corporation

10/19/17 / #20170302278

Low core power leakage structure in io receiver during io power down

A receiver includes a first transfer gate, a first inverter, a second inverter, a second transfer gate, a third inverter, and a fourth inverter connected in series, a first power supply supplying power to the first and second inverters, a second power supply supplying power to the third and fourth... Semiconductor Manufacturing International shanghai Corporation

10/19/17 / #20170302286

Frequency divider circuit and a frequency synthesizer circuit

a control module, wherein the first flip-flop is connected to a voltage source through the control module, the control module is connected to the control signal and controls the connection between the first flip-flop and the voltage source. When the control signal is a first-mode signal, the first flip-flop is... Semiconductor Manufacturing International shanghai Corporation

10/12/17 / #20170293711

Chemical mechanical polishing simulation methods and simulation devices thereof

A CMP simulation method includes inputting a chip pattern layout including a plurality of graphic patterns, partitioning the chip pattern layout into targeting grids including a plurality of surrounding grids, and then calculating grid geometry characteristics of the targeting grids. The CMP simulation method also includes generating shifted grids by... Semiconductor Manufacturing International shanghai Corporation

10/12/17 / #20170294284

Semiconductor device and related manufacturing method

A semiconductor device may include the following elements: a semiconductor substrate, an insulator positioned on the substrate, a source electrode positioned on the insulator, a drain electrode positioned on the insulator, a gate electrode positioned between the source electrode and the drain electrode, a hallow channel surrounded by the gate... Semiconductor Manufacturing International shanghai Corporation

10/12/17 / #20170294315

Semiconductor structure and fabrication method thereof

A method is provided for fabricating a semiconductor structure. The method includes providing a substrate having a dielectric layer formed on the substrate, where an opening is formed in the dielectric layer, and bottom of the opening exposes surface of the substrate. The method also includes forming a first metal... Semiconductor Manufacturing International shanghai Corporation

Patent Packs
10/12/17 / #20170294343

Etching method and fabrication semiconductor structures

An etching method and a fabrication method of semiconductor structures are provided. The etching method includes forming trenches in a to-be-etched structure, and forming a dielectric layer in the trenches. The etching method further includes etching the dielectric layer in the trenches by an etching process, and controlling at least... Semiconductor Manufacturing International shanghai Corporation

10/12/17 / #20170294392

Semiconductor structures and fabrication methods thereof

A method for fabricating a semiconductor structure includes providing a wafer and a carrier wafer. The wafer includes a first bonding surface and a plurality of radio-frequency (RF) devices and the carrier wafer includes a second bonding surface. The method further includes performing a surface treatment process on the second... Semiconductor Manufacturing International shanghai Corporation

10/12/17 / #20170294535

Semiconductor device and fabrication method thereof

A semiconductor device and fabrication method thereof are provided. The method includes forming at least one dummy gate structure and sidewall spacers of the dummy gate structure in a first dielectric layer, together on a substrate, and removing the dummy gate structure, thereby forming a first opening between the sidewall... Semiconductor Manufacturing International shanghai Corporation

10/05/17 / #20170285099

Method and system for predicting high-temperature operating life of sram devices

A method for predicting high-temperature operating life of an integrated circuit (IC) includes performing bias temperature instability tests and high-temperature operating life tests on a device of the IC, establishing a relationship between the device bias temperature instability and the IC's high-temperature operating life based on a result of the... Semiconductor Manufacturing International shanghai Corporation

10/05/17 / #20170287552

Write-tracking circuit for memory

A write tracking circuit includes a dummy memory cell coupled to a first dummy bit line, a second dummy bit line, and a dummy word line, a logic operation unit coupled to the dummy word line and to the first dummy bit line and configured to output a write feedback... Semiconductor Manufacturing International shanghai Corporation

10/05/17 / #20170287897

High voltage esd device for finfet technology

An ESD protection device includes a semiconductor substrate, first and second fins, first and second doped regions adjacent to each other and having different conductivity types. The first doped region includes a first portion of the substrate and a first region of the first fin. The second doped region includes... Semiconductor Manufacturing International shanghai Corporation

10/05/17 / #20170287908

Method for forming deep trench isolation for rf devices on soi

... Semiconductor Manufacturing International shanghai Corporation

10/05/17 / #20170287922

Semiconductor memory device and fabrication method thereof

A method is provided for fabricating a semiconductor memory device. The method includes providing a substrate and forming a stacked layer on the substrate, where the stacked layer includes a tunneling dielectric layer and a floating gate layer sequentially formed on the substrate. The method also includes forming a plurality... Semiconductor Manufacturing International shanghai Corporation

10/05/17 / #20170288020

Ldmos device

The disclosed subject matter provides an LDMOS device and fabrication method thereof. In an LDMOS device, a drift region and a body region are formed in a substrate. A first trench is formed in the drift region and in the substrate between the drift region and the body region. The... Semiconductor Manufacturing International shanghai Corporation

10/05/17 / #20170288043

Power semiconductor device

A method for forming a power semiconductor device is provided. The method includes providing a substrate having a first surface and a second surface; and forming a plurality of trenches in the second surface of the substrate. The method also includes forming a semiconductor pillar in each of the plurality... Semiconductor Manufacturing International shanghai Corporation

10/05/17 / #20170288049

Method for fabricating finfet structure

A method of forming a semiconductor device includes providing a substrate structure having a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure includes a semiconductor layer and a hard mask layer on top of the semiconductor layer. The method also includes forming a spacer layer... Semiconductor Manufacturing International shanghai Corporation

10/05/17 / #20170288532

Charge pump voltage regulator

A charge pump voltage regulator is provided. The charge pump voltage regulator includes a charge pump circuit, where an output terminal of the charge pump circuit outputs a stable voltage. The charge pump voltage regulator also includes a voltage divider circuit suitable to divide the stable voltage to output a... Semiconductor Manufacturing International shanghai Corporation

10/05/17 / #20170288680

Crystal oscillator circuit

A crystal oscillator circuit is provided. The crystal oscillator circuit includes an oscillator start-up circuit having a first output terminal and a second output terminal, where the second output terminal outputs a first oscillation signal; and a waveform conversion circuit configured to convert the first oscillation signal to a rectangular... Semiconductor Manufacturing International shanghai Corporation

09/28/17 / #20170278864

3d nand device

A method for forming a 3D NAND structure includes providing a semiconductor substrate; forming a control gate structure having a plurality of staircase-stacked layers, each layer has a first end and a second end; forming a dielectric layer covering the semiconductor substrate, and the control gate structure; forming a hard... Semiconductor Manufacturing International shanghai Corporation

09/21/17 / #20170271306

Packaging structure and packaging method thereof

A packaging structure and a packaging method are provided. The packaging structure includes a carrier semiconductor structure including a carrier substrate, a carrier dielectric layer, and a carrier top conductive layer inside the carrier dielectric layer and having a top exposed by the carrier dielectric layer. The packaging structure also... Semiconductor Manufacturing International shanghai Corporation

Patent Packs
09/21/17 / #20170271482

Semiconductor device and fabrication method thereof

The present disclosure provides a method for forming a semiconductor device, including: forming a mask layer over a substrate, the mask layer containing an opening, exposing a surface portion of the substrate to form an exposed surface portion of the substrate; forming an insulation structure between the mask layer and... Semiconductor Manufacturing International shanghai Corporation

09/14/17 / #20170263647

Semiconductor structure and fabrication method thereof

A method is provided for fabricating a semiconductor structure. The method includes providing a bottom substrate having a first region and a second region, and forming a trench in the first region by patterning the bottom substrate. The method also includes forming an insulation layer in the trench in the... Semiconductor Manufacturing International shanghai Corporation

09/14/17 / #20170263778

Flash memory structure and fabrication method thereof

A method is provided for fabricating a flash memory structure. The method includes providing a substrate; and forming a gate structure and a hard mask layer. The method also includes forming a sidewall structure on side walls of the gate structure and the hard mask layer; and forming an etching... Semiconductor Manufacturing International shanghai Corporation

09/14/17 / #20170264263

Thin-film bulk acoustic resonator, semiconductor apparatus comprising of such an acoustic resonator, and manufacture thereof

A thin-film bulk acoustic resonator, a semiconductor apparatus including the acoustic resonator and its manufacturing methods are presented. The thin-film bulk acoustic resonator includes a lower dielectric layer, a first cavity inside the lower dielectric layer, an upper dielectric layer, a second cavity inside the upper dielectric layer, and a... Semiconductor Manufacturing International shanghai Corporation

09/14/17 / #20170264264

Thin-film bulk acoustic resonator, semiconductor apparatus comprising of such an acoustic resonator, and manufacture thereof

A thin-film bulk acoustic resonator, a semiconductor apparatus including the acoustic resonator and its manufacturing method are presented. The thin-film bulk acoustic resonator includes a lower dielectric layer, a first cavity inside the lower dielectric layer, an upper dielectric layer, a second cavity inside the upper dielectric layer, and a... Semiconductor Manufacturing International shanghai Corporation

09/14/17 / #20170264265

Resonator and related manufacturing method

A resonator may include a first dielectric member, a second dielectric member, and a composite member. The first dielectric member may have a first cavity. The composite member may include a piezoelectric layer and may overlap at least one of the first dielectric member and the second dielectric member. At... Semiconductor Manufacturing International shanghai Corporation

09/14/17 / #20170264297

Input-output receiver

An input-output (I/O) receiver includes a receiving terminal, a first N-type metal-oxide-semiconductor (NMOS) transistor, a reformation circuit, and a compensation unit. The receiving terminal is coupled with an external voltage signal. The first NMOS transistor has a source electrode coupled with the receiving terminal and a gate electrode coupled with... Semiconductor Manufacturing International shanghai Corporation

08/31/17 / #20170250175

Ldmos transistor

A LDMOS transistor includes a semiconductor substrate with a first doping type; a plurality of first trenches formed in the semiconductor substrate; a wave-shaped drift region with an increased conductive path and a second doping type formed on the semiconductor substrate between adjacent first trenches and the semiconductor substrate exposed... Semiconductor Manufacturing International shanghai Corporation

08/24/17 / #20170243792

Method to improve hci performance for finfet

A semiconductor device includes a substrate structure, multiple fins protruding from the substrate structure, each of the fins having a first portion, a second portion on opposite sides of the first portion, and a third portion at an outer side of the first portion and adjacent to the second portion,... Semiconductor Manufacturing International shanghai Corporation

08/24/17 / #20170243958

Method to improve ge channel interfacial layer quality for cmos finfet

A method for manufacturing a semiconductor device includes providing a semiconductor structure having a substrate structure, multiple fins having a germanium layer, a dummy gate structure including sequentially a hardmask, a dummy gate, a dummy gate insulating material on the germanium layer, and spacers on opposite sides of the dummy... Semiconductor Manufacturing International shanghai Corporation

08/17/17 / #20170236945

Vertical junctionless transistor devices

A semiconductor device includes a silicon substrate, a silicon germanium (SiGe) layer including a lower portion extending over the silicon substrate and a fin structure protruding above the lower portion, a first dielectric layer disposed over a side surface of the fin structure and a top surface of the lower... Semiconductor Manufacturing International shanghai Corporation

08/10/17 / #20170229367

Semiconductor structure and fabrication method thereof

The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary semiconductor structure includes an insulation material layer having a top semiconductor layer having transistor regions formed on a top surface of the insulation material layer; isolation structures formed in the top semiconductor layer between adjacent transistor regions; a... Semiconductor Manufacturing International shanghai Corporation

08/10/17 / #20170229468

Static random access memory and fabrication method thereof

An SRAM includes a substrate containing a plurality of first substrate regions and a plurality of second substrate regions, a plurality of pull-down transistors formed in the first substrate regions with each pull-down transistor including a first gate structure, and a plurality of pass-gate transistors formed in the second substrate... Semiconductor Manufacturing International shanghai Corporation

08/10/17 / #20170229540

Non-volatile memory device having reduced drain and read disturbances

A source-drain structure is disclosed. The source-drain structure includes a substrate containing a drain region and a source region. The drain region includes a lightly-doped ultra-shallow junction and a heavily-doped region, and a drain-substrate junction disposed in the vicinity of a junction between a side portion and a bottom portion... Semiconductor Manufacturing International shanghai Corporation

08/10/17 / #20170229559

Finfet devices having a material formed on reduced source/drain region

A semiconductor device includes a fin structure of a first semiconductor material on a substrate. The fin structure has a source region, a drain region, and a channel region between the source region and the drain region. The device also has a gate structure overlying the fin structure. The source... Semiconductor Manufacturing International shanghai Corporation

08/10/17 / #20170229560

Semiconductor structure and fabrication method thereof

The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on the semiconductor substrate, each fin having a first sidewall surface and an opposing second sidewall surface; performing an asymmetric oxidation process on the fins to... Semiconductor Manufacturing International shanghai Corporation

08/03/17 / #20170222017

Memory cell and fabrication method thereof

Memory cells and fabrication methods thereof are provided. An exemplary method includes providing a substrate having a well region; forming a select gate structure, a floating gate structure and a dummy gate structure on a surface of the well region; forming a first lightly doped region, a second lightly doped... Semiconductor Manufacturing International shanghai Corporation

08/03/17 / #20170221575

Methods for reading and operating memory device

The present disclosure provides a memory. The memory includes an array of memory cells arranged as a plurality of rows by a plurality of columns. A memory cell is connected to at least one redundant memory cell in series in a same row for storing same data as the memory... Semiconductor Manufacturing International shanghai Corporation

08/03/17 / #20170221576

Methods for reading and operating memory device

The present disclosure provides a memory. The memory includes an array of memory cells arranged as a plurality of rows by a plurality of columns. A memory cell is connected to at least one redundant memory cell in series in a same row for storing same data as the memory... Semiconductor Manufacturing International shanghai Corporation

08/03/17 / #20170221754

Apparatus and forming metal by hot-wire assisted cleaning and atomic layer deposition

An apparatus includes a housing, a chamber disposed in the housing and configured to receive a substrate, a shower head disposed outside the housing and configured to supply a process gas to the chamber, and a hot wire at a first temperature disposed between the shower head and the substrate.... Semiconductor Manufacturing International shanghai Corporation

08/03/17 / #20170221759

Method and system for uniform deposition of metal

A method for manufacturing a semiconductor device includes providing a substrate, performing a nucleation process on the substrate to form a nucleation layer of a metal, performing a first deposition process at a first temperature on the nucleation layer to form a first layer of the metal, etching back the... Semiconductor Manufacturing International shanghai Corporation

08/03/17 / #20170221833

Mark structure and fabrication method thereof

The present disclosure provides mark structures and fabrication methods thereof. An exemplary fabrication process includes providing a substrate having a device region, a first mark region and a second mark region; sequentially forming a device layer, a dielectric layer and a mask layer on a surface of the substrate; forming... Semiconductor Manufacturing International shanghai Corporation

08/03/17 / #20170221892

Method to improve device performance for finfet

A method includes providing a semiconductor structure comprising multiple fins and a gate structure on the fins. The method also includes removing a portion of the fins not covered by the gate structure to form a remaining portion of the fins, performing a first epitaxially growth process to form first... Semiconductor Manufacturing International shanghai Corporation

08/03/17 / #20170221908

Method and structure for finfet sram

A method for forming a semiconductor device includes providing a substrate structure having a plurality of semiconductor fins disposed on a substrate and a hard mask layer on the semiconductor fins. A first insulating material layer is formed covering the semiconductor fins, the hard masks, and the spaces between the... Semiconductor Manufacturing International shanghai Corporation

08/03/17 / #20170221914

Nonvolatile memory device and manufacturing the same

A method for manufacturing a semiconductor device includes providing a substrate structure having an active region, a gate insulating layer, a charge storage layer, a gate dielectric layer, and a gate layer sequentially formed on the active region. The method also includes forming a patterned metal layer on the substrate... Semiconductor Manufacturing International shanghai Corporation

08/03/17 / #20170222654

Asar adc circuit and conversion method thereof

The present disclosure provides asynchronous successive approximation register analog-to-digital convener (ASAR ADC) circuits and signal conversion method thereof. An exemplary ASAR AC circuit includes a sample/hold circuit configured to input a first analog signal and output a second analog signal; a digital-to-analog converter circuit configured to output a third analog... Semiconductor Manufacturing International shanghai Corporation








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