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Silicon Storage Technology Inc
Silicon Storage Technology Inc_20100107

Silicon Storage Technology Inc patents


Recent patent applications related to Silicon Storage Technology Inc. Silicon Storage Technology Inc is listed as an Agent/Assignee. Note: Silicon Storage Technology Inc may have other listings under different names/spellings. We're not affiliated with Silicon Storage Technology Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Silicon Storage Technology Inc-related inventors


Method of forming resistive random access memory (rram) cells

A method of forming a memory device includes forming a first layer of conductive material having opposing upper and lower surfaces, forming a layer of amorphous silicon on the upper surface of the first layer of conductive material, stripping away the layer of amorphous silicon, wherein some of the amorphous silicon remains in the upper surface of the first layer of conductive material, forming a layer of transition metal oxide material on the upper surface of the first layer of conductive material, and forming a second layer of conductive material on the layer of transition metal oxide material. The method smoothes the upper surface of the bottom electrode, and also provides an bottom electrode upper surface with stable material that is hard to oxidize.. ... Silicon Storage Technology Inc

Sensing amplifier comprising voltage offset circuitry for use in flash memory devices

The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors.. ... Silicon Storage Technology Inc

Sense amplifier with bit line pre-charge circuit for reading flash memory cells in an array

The present invention relates to an improved sense amplifier for reading values in flash memory cells in an array. In one embodiment, a sense amplifier comprises an improved pre-charge circuit for pre-charging a bit line during a pre-charge period to increase the speed of read operations. ... Silicon Storage Technology Inc

Method of forming pairs of three-gate non-volatile flash memory cells using two polysilicon deposition steps

A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. ... Silicon Storage Technology Inc

Method and apparatus for configuring array columns and rows for accessing flash memory cells

In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.. ... Silicon Storage Technology Inc

Method and apparatus for configuring array columns and rows for accessing flash memory cells

In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.. ... Silicon Storage Technology Inc

High speed sensing for advanced nanometer flash memory device

Improved flash memory sensing circuits are disclosed. In one embodiment, a sensing circuit comprises a memory data read block, a memory reference block, a differential amplifier, and a precharge circuit. ... Silicon Storage Technology Inc

Method of forming low height split gate memory cells

A method of forming a memory device that includes forming a first insulation layer on a semiconductor substrate, forming a conductive material layer on the first insulation layer, forming an insulation block on the conductive material layer, forming an insulation spacer along a side surface of the insulation block and on the conductive material layer, etching the conductive material layer to form a block of the conductive material disposed directly under the insulation block and the insulation spacer, removing the insulation spacer, forming a second insulation layer having a first portion wrapping around an exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer over the substrate, and forming a conductive block insulated from the block of the conductive material by the second insulation layer and from the substrate by the first and second insulation layers.. . ... Silicon Storage Technology Inc

Non-volatile split gate memory cells with integrated high k metal gate logic device and metal-free erase gate, and method of making same

A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having hkmg logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. ... Silicon Storage Technology Inc

Dynamic programming of advanced nanometer flash memory

An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.. . ... Silicon Storage Technology Inc

Method of integrating finfet cmos devices with embedded nonvolatile memory cells

A method of forming a memory device with memory cells over a planar substrate surface and finfet logic devices over fin shaped substrate surface portions, including forming a protective layer over previously formed floating gates, erase gates, word line poly and source regions in a memory cell portion of the substrate, then forming fins into the surface of the substrate and forming logic gates along the fins in a logic portion of the substrate, then removing the protective layer and completing formation of word line gates from the word line poly and drain regions in the memory cell portion of the substrate.. . ... Silicon Storage Technology Inc

Sensing amplifier comprising a built-in sensing offset for flash memory devices

The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, the sensing amplifier includes a built-in voltage offset. ... Silicon Storage Technology Inc

Method of making split gate non-volatile flash memory cell

A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.. . ... Silicon Storage Technology Inc

Flash memory cell and associated decoders

The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. ... Silicon Storage Technology Inc

11/23/17 / #20170337971

Array of three-gate flash memory cells with individual memory cell read, program and erase

A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. ... Silicon Storage Technology Inc

11/16/17 / #20170330949

Reduced size split gate non-volatile flash memory cell and method of making same

A reduced size non-volatile memory cell array is achieved by forming first trenches in an insulation layer in the row direction, filling the first trenches with insulation material, forming second trenches in the insulation layer in the column direction, forming the sti isolation material in the second trenches, and forming the source regions through the first trenches. Alternately, the sti isolation regions can be made continuous, and the source diffusion implant has sufficient energy to form continuous source line diffusions that each extend across the active regions and under the sti isolation regions. ... Silicon Storage Technology Inc

11/09/17 / #20170323682

Three-dimensional flash nor memory system with configurable pins

A three-dimensional flash memory system is disclosed. The system comprises a memory array comprising a plurality of stacked dies, where each die comprises memory cells. ... Silicon Storage Technology Inc

09/21/17 / #20170269662

Power sequencing for embedded flash memory devices

A system and method for improved power sequencing within an embedded flash memory device is disclosed.. . ... Silicon Storage Technology Inc

07/06/17 / #20170194055

Low power sense amplifier for a flash memory system

Multiple embodiments of a low power sense amplifier for use in a flash memory system are disclosed. In some embodiments, the loading on a sense amplifier can be adjusted by selectively attaching one or more bit lines to the sense amplifier, where the one or more bit lines each is coupled to an extraneous memory cell.. ... Silicon Storage Technology Inc

06/22/17 / #20170179141

Method of making split gate non-volatile memory cell with 3d finfet structure

A non-volatile memory cell, and method of making, that includes a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. ... Silicon Storage Technology Inc

05/04/17 / #20170125603

Integration of metal floating gate in non-volatile memory

A non-volatile memory cell that includes a silicon substrate, source and drain regions formed in the silicon substrate (where a channel region of the substrate is defined between the source and drain regions), a metal floating gate disposed over and insulated from a first portion of the channel region, a metal control gate disposed over and insulated from the metal floating gate, a polysilicon erase gate disposed over and insulated from the source region, and a polysilicon word line gate disposed over and insulated from a second portion of the channel region.. . ... Silicon Storage Technology Inc

05/04/17 / #20170125429

Split gate non-volatile flash memory cell having metal gates and method of making same

A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. ... Silicon Storage Technology Inc

04/27/17 / #20170117285

Method of forming flash memory with separate wordline and erase gates

A method of forming a non-volatile memory cell includes forming spaced apart first and second regions in a substrate, defining a channel region there between. A floating gate is formed over a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region. ... Silicon Storage Technology Inc

04/20/17 / #20170110194

Power driven optimization for flash memory

A memory device, and method of operation, includes an array of non-volatile memory cells and a controller. The controller is configured to perform an operation (e.g. ... Silicon Storage Technology Inc

04/13/17 / #20170103991

Method of forming memory array and logic devices

A method of forming a memory device on a substrate having memory, core and hv device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and hv device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. ... Silicon Storage Technology Inc

04/13/17 / #20170103989

Method of making embedded memory device with silicon-on-insulator substrate

A method of forming a semiconductor device with memory cells and logic devices on the same silicon-on-insulator substrate. The method includes providing a substrate that includes silicon, a first insulation layer directly over the silicon, and a silicon layer directly over the first insulation layer. ... Silicon Storage Technology Inc

04/06/17 / #20170098654

Non-volatile split gate memory cells with integrated high k metal gate, and method of making same

A method of forming a pair of memory cells that includes forming a polysilicon layer over and insulated from a semiconductor substrate, forming a pair of conductive control gates over and insulated from the polysilicon layer, forming first and second insulation layers extending along inner and outer side surfaces of the control gates, removing portions of the polysilicon layer adjacent the outer side surfaces of the control gates, forming an hkmg layer on the structure and removing portions thereof between the control gates, removing a portion of the polysilicon layer adjacent the inner side surfaces of the control gates, forming a source region in the substrate adjacent the inner side surfaces of the control gates, forming a conductive erase gate over and insulated from the source region, forming conductive word line gates laterally adjacent to the control gates, and forming drain regions in the substrate adjacent the word line gates.. . ... Silicon Storage Technology Inc

04/06/17 / #20170098474

Fully depleted silicon on insulator flash memory design

The present invention relates to a flash memory system wherein one or more circuit blocks utilize fully depleted silicon-on-insulator transistor design to minimize leakage. . ... Silicon Storage Technology Inc

03/16/17 / #20170076809

Flash memory system using complementary voltage supplies

A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. ... Silicon Storage Technology Inc

02/02/17 / #20170032846

Split gate nand flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing

A split gate nand flash memory structure is formed on a semiconductor substrate of a first conductivity type. The nand structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. ... Silicon Storage Technology Inc

01/26/17 / #20170025427

Non-volatile split gate memory cells with integrated high k metal gate logic device and metal-free erase gate, and method of making same

A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having hkmg logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. ... Silicon Storage Technology Inc

01/26/17 / #20170025424

Self-aligned source for split-gate non-volatile memory cell

A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. ... Silicon Storage Technology Inc

01/12/17 / #20170012049

Split gate non-volatile memory cell having a floating gate, word line, erase gate, and method of manufacturing

A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between, and a conductive floating gate disposed over a first portion of the channel region and a first portion of the source region. An erase gate includes a first portion that is laterally adjacent to the floating gate and over the source region, and a second portion that extends up and over the floating gate. ... Silicon Storage Technology Inc

01/12/17 / #20170011810

Three-dimensional flash memory system

A three-dimensional flash memory system is disclosed.. . ... Silicon Storage Technology Inc








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