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Sk Hynix Memory Solutions Inc patents

Recent patent applications related to Sk Hynix Memory Solutions Inc. Sk Hynix Memory Solutions Inc is listed as an Agent/Assignee. Note: Sk Hynix Memory Solutions Inc may have other listings under different names/spellings. We're not affiliated with Sk Hynix Memory Solutions Inc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Sk Hynix Memory Solutions Inc-related inventors




Date Sk Hynix Memory Solutions Inc patents (updated weekly) - BOOKMARK this page
10/05/17Throttling for a memory system and operating method thereof
03/23/17Vss ldpc decoder with improved throughput for hard decoding
03/02/17Delaying hot block garbage collection with adaptation
01/26/17Data temperature profiling by smart counter
01/26/17Programmable protocol independent bar memory for ssd controller
01/26/17High performance host queue monitor for pcie ssd controller
01/12/17Peripheral component interconnect express card
01/12/17Start-up circuit for bandgap reference
12/22/16Read disturb reclaim policy
12/22/16Enhanced chip-kill schemes by using sub-trunk crc
12/22/16Enhanced chip-kill schemes by using ecc syndrome pattern
12/15/16Efficient encoder based on modified ru algorithm
12/08/16Modeling threshold voltage distributions
12/08/16One-shot decoder for two-error-correcting bch codes
11/24/16Hybrid read disturb count management
11/24/16Generalized product codes for flash storage
11/24/16Performance optimization in soft decoding for turbo product codes
11/17/16Reduction of maximum latency using dynamic self-tuning for redundant array of independent disks
11/17/16Adaptive read disturb reclaim policy
11/17/16Data separation by delaying hot block garbage collection
11/17/16Apparatus for correcting gain error of analog-to-digital converter
11/17/16Miscorrection avoidance for turbo product codes
11/03/16Temperature sensing apparatus
10/27/16Controller adaptation to memory program suspend-resume
09/29/16Memory system and operating method thereof
09/29/16Memory system and operating method thereof
09/29/16Memory system and operating improving rebuild efficiency
09/22/16Scalable spor algorithm for flash memories
09/22/16System optimization in flash memories
09/22/16Memory controller and operating method thereof
09/22/16Incremental llr generation for flash memories
09/08/16Encoder and decoder design for near-balanced codes
08/25/16Efficient mapping scheme with deterministic power transition times for flash storage devices
08/25/16Scheme to avoid miscorrection for turbo product codes
08/18/16Embedded system and method thereof
08/04/16Data integrity and loss resistance in high performance and high capacity storage deduplication
08/04/16Method and system for endurance enhancing, deferred deduplication with hardware-hash-enabled storage device
07/28/16Reading and writing to nand flash memories using charge constrained codes
07/21/16Methods of system optimization by over-sampling read
07/14/16Methods of system optimization by over-sampling read
07/07/16Reliability-assisted bit-flipping decoding algorithm
06/23/16Memory system and the operation method thereof
06/23/16Driver structure for chip-to-chip communications
06/09/16Turbo product codes for nand flash
06/02/16Storage node based on pci express interface
05/26/16Apparatus and turbo product codes
05/19/16Hot-cold data separation method in flash translation layer
05/19/16Deduplication using a master and a slave
05/19/16Generating soft read values using multiple reads and/or bins
05/12/16Optimal read threshold estimation
05/12/16Read-threshold calibration in a solid state storage system
05/05/16Memory system and memory management method thereof
04/28/16Calibration device and memory system having the same
04/21/16Lba blocking table for ssd controller
04/14/16Low power bias scheme for mobile storage soc
04/07/16Sizing a cache while taking into account a total bytes written requirement
03/31/16Techniques for selecting amounts of over-provisioning
01/28/16Encoder by-pass with scrambler
11/19/15Read disturb detection
08/20/15Flash multiple-pass write with accurate first-pass write
06/04/15Error recovery for flash memory
05/21/15Finding optimal read thresholds and related voltages for solid state memory
05/14/15Threshold estimation using bit flip counts and minimums
03/26/15Storage of read thresholds for nand flash storage using linear approximation
03/26/15Error recovery using erasures for nand flash
Patent Packs
03/19/15Generating read thresholds using gradient descent and without side information
02/19/15Generating soft read values which optimize dynamic range
02/19/15Error correction capability improvement in the presence of hard bit errors
02/12/15Voltage regulator soft start
01/29/15Advance clocking scheme for ecc in storage
01/29/15Buffer management in a turbo equalization system
01/15/15Manufacturing testing for ldpc codes
01/01/15Manufacturing testing for ldpc codes
12/25/14Flash multiple-pass write with accurate first-pass write
11/06/14Margining decoding utilizing soft-inputs
10/30/14Memory protection cache
10/30/14Solid state device coding architecture for chipkill and endurance improvement
09/18/14Coding architecture for multi-level nand flash memory with stuck cells
08/07/14Flash multiple-pass write with accurate first-pass write
07/10/14Mtr and rll code design and encoder and decoder
Patent Packs
07/10/14Inter-track interference cancelation for shingled magnetic recording
07/10/14Ldpc decoding with on the fly error recovery
07/03/14Soft input, soft ouput mappers and demappers for block codes
06/19/14Error recovery for flash memory
06/05/14Blind and decision directed multi-level channel estimation
05/29/14Measure of health for writing to locations in flash
05/22/14Matching signal dynamic range for turbo equalization system
05/22/14Defect scan and manufacture test
05/08/14Turbo-product codes (tpc) with interleaving
05/01/14Multiple interleavers in a coding system
02/06/14Data independent error computation and usage with decision directed error computation
01/09/14Error recovery for flash memory
11/28/13Measure of health for writing to locations in flash
09/19/13Ldpc selective decoding scheduling using a cost function







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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Sk Hynix Memory Solutions Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Sk Hynix Memory Solutions Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

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