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Sk Hynix Memory Solutions Inc patents

Date	Sk Hynix Memory Solutions Inc patents (updated weekly) - BOOKMARK this page
03/23/17	Vss ldpc decoder with improved throughput for hard decoding
03/02/17	Delaying hot block garbage collection with adaptation
01/26/17	Data temperature profiling by smart counter
01/26/17	Programmable protocol independent bar memory for ssd controller
01/26/17	High performance host queue monitor for pcie ssd controller
01/12/17	Peripheral component interconnect express card
01/12/17	Start-up circuit for bandgap reference
12/22/16	Read disturb reclaim policy
12/22/16	Enhanced chip-kill schemes by using sub-trunk crc
12/22/16	Enhanced chip-kill schemes by using ecc syndrome pattern
12/15/16	Efficient encoder based on modified ru algorithm
12/08/16	Modeling threshold voltage distributions
12/08/16	One-shot decoder for two-error-correcting bch codes
11/24/16	Hybrid read disturb count management
11/24/16	Generalized product codes for flash storage
11/24/16	Performance optimization in soft decoding for turbo product codes
11/17/16	Reduction of maximum latency using dynamic self-tuning for redundant array of independent disks
11/17/16	Adaptive read disturb reclaim policy
11/17/16	Data separation by delaying hot block garbage collection
11/17/16	Apparatus for correcting gain error of analog-to-digital converter
11/17/16	Miscorrection avoidance for turbo product codes
11/03/16	Temperature sensing apparatus
10/27/16	Controller adaptation to memory program suspend-resume
09/29/16	Memory system and operating method thereof
09/29/16	Memory system and operating method thereof
09/29/16	Memory system and operating improving rebuild efficiency
09/22/16	Scalable spor algorithm for flash memories
09/22/16	System optimization in flash memories
09/22/16	Memory controller and operating method thereof
09/22/16	Incremental llr generation for flash memories
09/08/16	Encoder and decoder design for near-balanced codes
08/25/16	Efficient mapping scheme with deterministic power transition times for flash storage devices
08/25/16	Scheme to avoid miscorrection for turbo product codes
08/18/16	Embedded system and method thereof
08/04/16	Data integrity and loss resistance in high performance and high capacity storage deduplication
08/04/16	Method and system for endurance enhancing, deferred deduplication with hardware-hash-enabled storage device
07/28/16	Reading and writing to nand flash memories using charge constrained codes
07/21/16	Methods of system optimization by over-sampling read
07/14/16	Methods of system optimization by over-sampling read
07/07/16	Reliability-assisted bit-flipping decoding algorithm
06/23/16	Memory system and the operation method thereof
06/23/16	Driver structure for chip-to-chip communications
06/09/16	Turbo product codes for nand flash
06/02/16	Storage node based on pci express interface
05/26/16	Apparatus and turbo product codes
05/19/16	Hot-cold data separation method in flash translation layer
05/19/16	Deduplication using a master and a slave
05/19/16	Generating soft read values using multiple reads and/or bins
05/12/16	Optimal read threshold estimation
05/12/16	Read-threshold calibration in a solid state storage system
05/05/16	Memory system and memory management method thereof
04/28/16	Calibration device and memory system having the same
04/21/16	Lba blocking table for ssd controller
04/14/16	Low power bias scheme for mobile storage soc
04/07/16	Sizing a cache while taking into account a total bytes written requirement
03/31/16	Techniques for selecting amounts of over-provisioning
01/28/16	Encoder by-pass with scrambler
11/19/15	Read disturb detection
08/20/15	Flash multiple-pass write with accurate first-pass write
06/04/15	Error recovery for flash memory
05/21/15	Finding optimal read thresholds and related voltages for solid state memory
05/14/15	Threshold estimation using bit flip counts and minimums
03/26/15	Storage of read thresholds for nand flash storage using linear approximation
03/26/15	Error recovery using erasures for nand flash
03/19/15	Generating read thresholds using gradient descent and without side information
02/19/15	Generating soft read values which optimize dynamic range
02/19/15	Error correction capability improvement in the presence of hard bit errors
02/12/15	Voltage regulator soft start
01/29/15	Advance clocking scheme for ecc in storage
01/29/15	Buffer management in a turbo equalization system
01/15/15	Manufacturing testing for ldpc codes
01/01/15	Manufacturing testing for ldpc codes
12/25/14	Flash multiple-pass write with accurate first-pass write
11/06/14	Margining decoding utilizing soft-inputs
10/30/14	Memory protection cache
10/30/14	Solid state device coding architecture for chipkill and endurance improvement
09/18/14	Coding architecture for multi-level nand flash memory with stuck cells
08/07/14	Flash multiple-pass write with accurate first-pass write
07/10/14	Mtr and rll code design and encoder and decoder
07/10/14	Inter-track interference cancelation for shingled magnetic recording
07/10/14	Ldpc decoding with on the fly error recovery
07/03/14	Soft input, soft ouput mappers and demappers for block codes
06/19/14	Error recovery for flash memory
06/05/14	Blind and decision directed multi-level channel estimation
05/29/14	Measure of health for writing to locations in flash
05/22/14	Matching signal dynamic range for turbo equalization system
05/22/14	Defect scan and manufacture test
05/08/14	Turbo-product codes (tpc) with interleaving
05/01/14	Multiple interleavers in a coding system
02/06/14	Data independent error computation and usage with decision directed error computation
01/09/14	Error recovery for flash memory
11/28/13	Measure of health for writing to locations in flash
09/19/13	Ldpc selective decoding scheduling using a cost function