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Sk Hynix Memory Solutions Inc patents


Recent patent applications related to Sk Hynix Memory Solutions Inc. Sk Hynix Memory Solutions Inc is listed as an Agent/Assignee. Note: Sk Hynix Memory Solutions Inc may have other listings under different names/spellings. We're not affiliated with Sk Hynix Memory Solutions Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Sk Hynix Memory Solutions Inc-related inventors


Data mapping scheme for generalized product codes

Memory systems and operating methods thereof comprise a memory storage and an error control coding (ecc) unit. The memory storage stores data which is split into a plurality of data chunks. ... Sk Hynix Memory Solutions Inc

Media quality aware ecc decoding method selection to reduce data access latency

A memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action.. ... Sk Hynix Memory Solutions Inc

Bit-flipping ldpc decoding algorithm with hard channel information

Memory systems may include a memory storage, and an error correcting code (ecc) unit suitable for determining a number of unsatisfied check nodes of a channel output in a decoding iteration of a decoding process, updating a flipping indicator of a variable node, comparing the flipping indicator of the variable node with a flipping threshold associated with the decoding process, flipping a bit of the variable node when the flipping indicator is greater than the flipping threshold, and ending the decoding process when decoding is determined to be successful or a maximal iteration number is reached.. . ... Sk Hynix Memory Solutions Inc

Semiconductor memory system and operating method thereof

A semiconductor memory system and an operating method thereof includes: a one-time-programmable memory device storing at least a customer identification (id) identifying a customer; a memory device; and a memory controller including a processor, and coupled to the memory device, containing instructions executed by the processor, and suitable for authenticating whether a program is authorized by a controller provider for the customer in a first-level signature authentication, in accordance with a customer image format, authenticating whether the program is authorized by the customer in a second-level signature authentication, in accordance with a program image format, after the first-level signature authentication is passed, when the customer image indicates the second-level signature authentication, wherein the program image format is different than the customer image format, storing the program into the memory device after the first-level signature authentication and second-level signature authentication are passed, and executing the program after the program is authenticated.. . ... Sk Hynix Memory Solutions Inc

Cyclically interleaved xor array for error recovery

Memory systems may include a memory storage including at least a first stripe and a second stripe, the first stripe including data pages corresponding to the first stripe and a first parity page suitable for storing a first xor parity, and the second stripe including data pages corresponding to the second stripe and a second parity page suitable for storing a second xor parity, the data pages and parity pages being stored over a plurality of memory dies, wherein each memory die includes a number of planes; and a controller suitable for cyclically interleaving the data pages corresponding to the first stripe and the data pages corresponding to the second stripe.. . ... Sk Hynix Memory Solutions Inc

Memory system with file level secure erase and operating method thereof

An apparatus of a memory system and an operating method thereof include: a plurality of memory devices, wherein each of the plurality of memory devices includes a plurality of blocks, each of the plurality of blocks has multiple pages corresponding to multiple wordlines, respectively; and a memory controller coupled with the plurality of memory devices, wherein the memory controller is configured to determine an overhead of an erase block where a deleted file resides therein, perform file level secure erase operation on the erase block in accordance with at least the overhead, and mark target pages corresponding to the deleted file as “trimmed” in a logic block address (lba) table.. . ... Sk Hynix Memory Solutions Inc

Memory system of 3d nand flash and operating method thereof

An apparatus of a memory system and an operating method thereof include: memory blocks, each of the memory blocks includes strings, each of the stings has flash cells and select gates thereon, wherein the select gates of each of the strings with a same index number in each of the memory blocks are connected with each other, in each of the memory blocks, the strings are divided into groups, each of the groups includes at least one string, and each of the groups has own read counts management thereof.. . ... Sk Hynix Memory Solutions Inc

Page health prediction using product codes decoder in nand flash storage

An apparatus of a memory system and an operating method thereof includes: a plurality of memory devices; and a controller including a decoder and a ber predictor, coupled with the plurality of memory devices, configured to perform a decoding iteration includes to conduct nand read and generate nand data; decode in accordance with the nand data and generate decoder information by the decoder; predict a ber in accordance with at least the decode information by the ber predictor; and evaluate the predicted ber and generate evaluation result by the ber predictor.. . ... Sk Hynix Memory Solutions Inc

Memory system with read threshold estimation and operating method thereof

An apparatus of a memory system and an operating method thereof includes a plurality of memory devices; and a controller coupled to the plurality of memory devices, wherein the controller is configured to perform a symmetric ovs read with at least an initial read threshold, and create a symmetric read result; perform an asymmetric ovs read with at least the initial read threshold, and create an asymmetric read result; adjust the initial read threshold according to at least the symmetric read result and asymmetric read result, and create an optimal read threshold; and execute data recovery process with the optimal read threshold.. . ... Sk Hynix Memory Solutions Inc

Memory system of optimal read reference voltage and operating method thereof

An apparatus of a memory system and an operating method thereof includes a plurality of memory devices; and a controller coupled with the plurality of memory devices, configured to determine a range of read reference voltages having a plurality of read reference voltages, the read reference voltages achieving a minimal rber; calculate an optimal read reference voltage in accordance with at least the range of read reference voltages; achieve a rber in accordance with at least the optimal read reference voltage; and execute error correction process with at least the optimal read reference voltage.. . ... Sk Hynix Memory Solutions Inc

Automated testing system and operating method thereof

A system and an operating method thereof include at least a system under test (sut) having collection of flash storages including hardware of array of flash storages, collection of partitions including logical volumes, a kernel subsystem including operating system, and an application layer including services, applications, systems, or a combination thereof; test drivers configured to drive tests, wherein the tests are configured for testing the sut, test fixtures configured to generate test data sets corresponding to the test drivers, observers configured to track test results of test cases created in accordance with the test drivers and the test data sets, wherein the test results include metrics, and archives configured to store historical data of the test cases.. . ... Sk Hynix Memory Solutions Inc

Memory system and method for accelerating boot time

A memory system includes a plurality of memory channels, each of the plurality of memory channels includes a plurality of memory dies and a die processor, each of the plurality of memory dies includes a plurality of memory blocks; and a memory controller including a monarch processor, coupled to the plurality of memory channels, wherein the die processor on each of the plurality of memory channels is configured in parallel to process to find last written data within at least a predetermined block of the plurality of memory dies; and provide information regarding the last written data to the monarch processor, the monarch processor determines which boot record to be used to identify firmware images based on the information.. . ... Sk Hynix Memory Solutions Inc

System of multiple configurations and operating method thereof

A system and an operating method thereof include a system on chip (soc) flash controller having at least one soc channel; at least one memory device coupled with the at least one soc channel; a printed circuit board (pcb), wherein the soc flash controller and the at least one memory device are mounted thereon; a flash address translation (ftl) address translator automatically managing the at least one memory device in accordance with a pcb board configuration file of the pcb board and a drive configuration file of the at least one memory device; and a fuse storing an open data plane (odp) fuse setting generated in accordance with at least in part with data of the pcb board configuration file and the drive configuration file.. . ... Sk Hynix Memory Solutions Inc

Memory system having optimal threshold voltage and operating method thereof

A semiconductor memory system and an operating method thereof include a memory device; and a memory controller including a sequence generator, a sequence analyzer, and a processor coupled to the memory device and containing instructions executed by the processor, and configured to generate a sequence by the sequence generator, wherein the sequence comprises a sequence of digital data, write the sequence associated with a user data to the memory device, read out a read data including the sequence and the associated user data, analyze the sequence to understand characters of the read data and create analysis result by the sequence analyzer, identify an optimal threshold voltage in accordance with the analysis result, and provide the optimal threshold voltage to an ecc engine.. . ... Sk Hynix Memory Solutions Inc

11/16/17 / #20170329709

Memory system having multiple cache pages and operating method thereof

A semiconductor memory system and an operating method thereof include a controller; and a memory device including a memory page manager, nand pages, and multiple cache pages, wherein the nand pages include current nand pages and next nand pages, wherein the current nand pages is corresponding to a read command received from the controller, the memory page manager is configured to manage correlation of the nand pages and the multiple cache pages, predict next nand pages in accordance at least in part with the read command, the current nand pages, or a combination thereof, and send the nand pages to the controller, and the multiple cache pages contain pages loaded from the nand pages.. . ... Sk Hynix Memory Solutions Inc

11/16/17 / #20170329703

Self-management memory system and operating method thereof

A semiconductor memory system and an operating method thereof include a controller configured to perform macro management; and a memory device including nand pages, counters, a self-management component, and devoted memories, wherein the memory device is coupled and controlled by the controller, the nand pages contains data corresponding to commands received from the controller, the counters are configured to track operation information corresponding to the nand pages in accordance with the commands, the devoted memories are configured to record recovery information, and the self-management component configured to perform micro management in accordance at least in part with the operation information or the recovery information.. . ... Sk Hynix Memory Solutions Inc

10/26/17 / #20170310316

Efficient digital duty cycle adjusters

The embodiments of the present invention provide an apparatus of an efficient digital duty cycle adjuster and the method of operation thereof. The method includes: providing an input clock having an input clock duty cycle; inserting at least one programmable delay of a programmable delay line to the input clock, the input clock has a first delay inserted for a delayed rise edge, and a second delay inserted for a delayed fall edge, wherein the first delay, the second delay, or the combination thereof, includes the programmable delay; and adjusting an output clock duty cycle of an output clock by configuring the programmable delay, the output clock is generated by a selecting circuit, the selecting circuit includes a select signal, and the select signal is determined in accordance with the first delay and the second delay.. ... Sk Hynix Memory Solutions Inc

10/05/17 / #20170285945

Throttling for a memory system and operating method thereof

A semiconductor memory system and an operating method thereof include: a memory device; and a memory controller including a processor, coupled to the memory device, containing instructions executed by the processor, and configured to provide sets of throttling numbers, select a throttling mode, calculate a garbage collection (gc)/host ratio based on at least a part of invalid count of garbage collection (gc) blocks and valid count of bgc blocks, and adjust throttling parameters of commands in accordance with the gc/host ratio and a number of erased blocks.. . ... Sk Hynix Memory Solutions Inc

03/23/17 / #20170085276

Vss ldpc decoder with improved throughput for hard decoding

Memory systems may include a memory storage, a pre-processing checksum unit suitable for, during a first decoding iteration, receiving hard read data including channel input (lch) sign values, and computing a checksum of the lch sign values as a checksum_pre value, and a low-density parity-check (ldpc) decoder including an lch memory and a checksum update unit, the ldpc decoder suitable for, during the first decoding iteration, storing the lch sign values in the lch memory of the ldpc decoder, receiving, with the checksum update unit, the checksum_pre value, and decoding a codeword in at least a second decoding iteration based at least in part on the checksum_pre value computed and received being a parity check on the hard read performed in the first decoding iteration.. . ... Sk Hynix Memory Solutions Inc

03/02/17 / #20170060428

Delaying hot block garbage collection with adaptation

Memory systems may include a memory storage, and a controller suitable for measuring a write amplification (wa) value of a first, current window, comparing the wa value for the first window with a previous wa value for a previous window, and calculating and setting a value of a ratio threshold based on the comparison of the wa value for the current window threshold to the wa value of the previous window threshold.. . ... Sk Hynix Memory Solutions Inc

01/26/17 / #20170024333

High performance host queue monitor for pcie ssd controller

Memory systems may include a plurality of queues, a queue ready indicator suitable for grouping the plurality of queues into a predefined number of queue ranges, each queue range having associated with it a queue range ready signal, and setting a queue range ready signal to ready when each queue in the queue range associated with the queue range ready signal is ready for processing, and a queue process sequencer suitable for determining a queue range ready for processing based on the queue range ready signals, and processing a queue within the queue range determined to be ready for processing.. . ... Sk Hynix Memory Solutions Inc

01/26/17 / #20170024332

Programmable protocol independent bar memory for ssd controller

Memory systems may include a programmable bit control unit suitable for defining read-write properties to locations in a base address register (bar) memory, a read-write switch suitable for receiving a memory access request, and identifying whether the memory access request is a read access or a write access, and an access control unit suitable for receiving the memory access request from the read-write switch when the memory access request is identified as a write access, determining a read-write property associated with the write access, and processing the write access to a location in the bar memory with a defined read-write property that is the same as the determined read-write property associated with the write request.. . ... Sk Hynix Memory Solutions Inc

01/26/17 / #20170024163

Data temperature profiling by smart counter

Memory systems may include a logical block address (lba) space divided into a number of zones, a counter associated with each zone, each counter suitable for incrementing a count value when a read is performed on an lba in the zone with which the counter is associated, and a controller suitable for calculating a temperature of each zone based on the count values of the counters, sorting the zones according to the calculated temperature, combining the zones into a number of superzones based on the sorting, and splitting the number of superzones into the number of zones into which the lba space was divided.. . ... Sk Hynix Memory Solutions Inc

01/12/17 / #20170012609

Start-up circuit for bandgap reference

A start-up circuit for a bandgap reference circuit include an operational amplifier and a diode coupled to a second input terminal of the operational amplifier. The circuit includes a first current branch including a first transistor and a second transistor in series, for generating a first current in response to an output voltage at an output terminal of the operational amplifier and a second current branch including a third transistor and a fourth transistor in series, for generating a second current in response to the output voltage. ... Sk Hynix Memory Solutions Inc

01/12/17 / #20170011002

Peripheral component interconnect express card

A peripheral component interconnect express (pcie) card may include a base card, a mezzanine card and mezz connectors. The base card may be coupled to a host device, and host a first group of solid state drives (ssds). ... Sk Hynix Memory Solutions Inc








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