Sk Hynix Memory Solutions Inc patents

Memory system of optimal read reference voltage and operating method thereof

An apparatus of a memory system and an operating method thereof includes a plurality of memory devices; and a controller coupled with the plurality of memory devices, configured to determine a range of read reference voltages having a plurality of read reference voltages, the read reference voltages achieving a minimal... Sk Hynix Memory Solutions Inc

Memory system with read threshold estimation and operating method thereof

An apparatus of a memory system and an operating method thereof includes a plurality of memory devices; and a controller coupled to the plurality of memory devices, wherein the controller is configured to perform a symmetric OVS read with at least an initial read threshold, and create a symmetric read... Sk Hynix Memory Solutions Inc

Page health prediction using product codes decoder in nand flash storage

An apparatus of a memory system and an operating method thereof includes: a plurality of memory devices; and a controller including a decoder and a BER predictor, coupled with the plurality of memory devices, configured to perform a decoding iteration includes to conduct NAND read and generate NAND data; decode... Sk Hynix Memory Solutions Inc

Memory accelerating boot time

A memory system includes a plurality of memory channels, each of the plurality of memory channels includes a plurality of memory dies and a die processor, each of the plurality of memory dies includes a plurality of memory blocks; and a memory controller including a monarch processor, coupled to the... Sk Hynix Memory Solutions Inc

Automated testing system and operating method thereof

A system and an operating method thereof include at least a system under test (SUT) having collection of flash storages including hardware of array of flash storages, collection of partitions including logical volumes, a kernel subsystem including operating system, and an application layer including services, applications, systems, or a combination... Sk Hynix Memory Solutions Inc

System of multiple configurations and operating method thereof

A system and an operating method thereof include a system on chip (SOC) flash controller having at least one SOC channel; at least one memory device coupled with the at least one SOC channel; a printed circuit board (PCB), wherein the SOC flash controller and the at least one memory... Sk Hynix Memory Solutions Inc

Self-management memory system and operating method thereof

A semiconductor memory system and an operating method thereof include a controller configured to perform macro management; and a memory device including Nand pages, counters, a self-management component, and devoted memories, wherein the memory device is coupled and controlled by the controller, the Nand pages contains data corresponding to commands... Sk Hynix Memory Solutions Inc

Memory system having multiple cache pages and operating method thereof

A semiconductor memory system and an operating method thereof include a controller; and a memory device including a memory page manager, Nand pages, and multiple cache pages, wherein the Nand pages include current Nand pages and next Nand pages, wherein the current Nand pages is corresponding to a read command... Sk Hynix Memory Solutions Inc

Memory system having optimal threshold voltage and operating method thereof

A semiconductor memory system and an operating method thereof include a memory device; and a memory controller including a sequence generator, a sequence analyzer, and a processor coupled to the memory device and containing instructions executed by the processor, and configured to generate a sequence by the sequence generator, wherein... Sk Hynix Memory Solutions Inc

Efficient digital duty cycle adjusters

The embodiments of the present invention provide an apparatus of an efficient digital duty cycle adjuster and the method of operation thereof. The method includes: providing an input clock having an input clock duty cycle; inserting at least one programmable delay of a programmable delay line to the input clock,... Sk Hynix Memory Solutions Inc

Throttling for a memory system and operating method thereof

A semiconductor memory system and an operating method thereof include: a memory device; and a memory controller including a processor, coupled to the memory device, containing instructions executed by the processor, and configured to provide sets of throttling numbers, select a throttling mode, calculate a garbage collection (GC)/HOST ratio based... Sk Hynix Memory Solutions Inc

Vss ldpc decoder with improved throughput for hard decoding

Memory systems may include a memory storage, a pre-processing checksum unit suitable for, during a first decoding iteration, receiving hard read data including channel input (Lch) sign values, and computing a checksum of the Lch sign values as a checksum_pre value, and a low-density parity-check (LDPC) decoder including an Lch... Sk Hynix Memory Solutions Inc

Delaying hot block garbage collection with adaptation

Memory systems may include a memory storage, and a controller suitable for measuring a write amplification (WA) value of a first, current window, comparing the WA value for the first window with a previous WA value for a previous window, and calculating and setting a value of a ratio threshold... Sk Hynix Memory Solutions Inc

Data temperature profiling by smart counter

Memory systems may include a logical block address (LBA) space divided into a number of zones, a counter associated with each zone, each counter suitable for incrementing a count value when a read is performed on an LBA in the zone with which the counter is associated, and a controller... Sk Hynix Memory Solutions Inc

Programmable protocol independent bar memory for ssd controller

Memory systems may include a programmable bit control unit suitable for defining read-write properties to locations in a base address register (BAR) memory, a read-write switch suitable for receiving a memory access request, and identifying whether the memory access request is a read access or a write access, and an... Sk Hynix Memory Solutions Inc

High performance host queue monitor for pcie ssd controller

Memory systems may include a plurality of queues, a queue ready indicator suitable for grouping the plurality of queues into a predefined number of queue ranges, each queue range having associated with it a queue range ready signal, and setting a queue range ready signal to ready when each queue... Sk Hynix Memory Solutions Inc

Peripheral component interconnect express card

A peripheral component interconnect express (PCIe) card may include a base card, a mezzanine card and mezz connectors. The base card may be coupled to a host device, and host a first group of solid state drives (SSDs). The mezzanine card may be stacked over the base card, and host... Sk Hynix Memory Solutions Inc

Start-up circuit for bandgap reference

A start-up circuit for a bandgap reference circuit include an operational amplifier and a diode coupled to a second input terminal of the operational amplifier. The circuit includes a first current branch including a first transistor and a second transistor in series, for generating a first current in response to... Sk Hynix Memory Solutions Inc