Real Time Touch



new TOP 200 Companies filing patents this week

new Companies with the Most Patent Filings (2010+)




Real Time Touch

Soft Machines Inc patents


Recent patent applications related to Soft Machines Inc. Soft Machines Inc is listed as an Agent/Assignee. Note: Soft Machines Inc may have other listings under different names/spellings. We're not affiliated with Soft Machines Inc, we're just tracking patents.

ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Soft Machines Inc-related inventors


Single cycle multi-branch prediction including shadow cache for early far branch prediction

A method of identifying instructions including accessing a plurality of instructions that comprise multiple branch instructions. For each branch instruction of the multiple branch instructions, a respective first mask is generated representing instructions that are executed if a branch is taken. ... Soft Machines Inc

Systems and methods for read request bypassing a last level cache that interfaces with an external fabric

Methods for read request bypassing a last level cache which interfaces with an external fabric are disclosed. A method includes identifying a read request for a read transaction, generating a phantom read transaction identifier for the read transaction and forwarding said read transaction with said phantom read transaction identifier beyond a last level cache before detection of a hit or miss with respect to said read transaction, and wherein said read transaction is canceled if said read transaction is a hit in said last level cache or does not access said last level cache.. ... Soft Machines Inc

Method for emulating a guest centralized flag architecture by using a native distributed flag architecture

A method for emulating a guest centralized flag architecture by using a native distributed flag architecture. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks, wherein each of the instruction blocks comprise two half blocks; scheduling the instructions of the instruction block to execute in accordance with a scheduler; and using a distributed flag architecture to emulate a centralized flag architecture for the emulation of guest instruction execution.. ... Soft Machines Inc

Method for dependency broadcasting through a source organized source view data structure

A method for dependency broadcasting through a source organized source view data structure is disclosed. The method comprises receiving an incoming instruction sequence using a global front end and grouping the instructions to form instruction blocks. ... Soft Machines Inc

Method for populating register view data structure by using register template snapshots

A method for populating a source view data structure by using register template snapshots. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the blocks of instructions; populating a source view data structure, wherein the source view data structure stores sources corresponding to the instruction blocks as recorded by the plurality of register templates; and determining which of the plurality of instruction blocks are ready for dispatch by using the populated source view data structure.. ... Soft Machines Inc

Method for populating a source view data structure by using register template snapshots

A method for populating a source view data structure by using register template snapshots. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the blocks of instructions; populating a source view data structure, wherein the source view data structure stores sources corresponding to the instruction blocks as recorded by the plurality of register templates; and determining which of the plurality of instruction blocks are ready for dispatch by using the populated source view data structure.. ... Soft Machines Inc

Unified shadow register file and pipeline architecture supporting speculative architectural states

A method for supporting architecture speculation in a microprocessor is disclosed. The method comprises maintaining two registers for a register file entry, wherein a first one of the two registers supports a shadow register state for speculative instructions and a second one of the two registers supports a committed register state for committed instructions. ... Soft Machines Inc

Instruction sequence buffer to enhance branch prediction efficiency

A method for outputting alternative instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor. ... Soft Machines Inc

Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor

A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions, and assembling the plurality of guest instructions into a guest instruction block. ... Soft Machines Inc

Hardware accelerated conversion system using pattern matching

A method for converting guest instructions into native instructions is disclosed. The method comprises accessing a guest instruction and performing a first level translation of the guest instruction. ... Soft Machines Inc

Allocation of an interconnect structure comprising shared buses to support the execution of instruction sequences by a plurality of engines

A method for allocation of a shared interconnect structure in an integrated circuit is disclosed. The method comprises receiving a plurality of requests from a plurality of resource consumers of a plurality of engines to access a plurality of resources, wherein the resources are spread across the plurality of engines and contain data for supporting execution of multiple code sequences. ... Soft Machines Inc

Allocation of a segmented interconnect to support the execution of instruction sequences by a plurality of engines

A method for allocation of a segmented interconnect in an integrate circuit is disclosed. The method comprises receiving a plurality of requests from a plurality of resource consumers of a plurality of engines to access a plurality of resources, wherein the resources are spread across the plurality of engines and contain data for supporting execution of multiple code sequences. ... Soft Machines Inc

Microprocessor accelerated code optimizer

A method for accelerating code optimization a microprocessor. The method includes fetching an incoming microinstruction sequence using an instruction fetch component and transferring the fetched macroinstructions to a decoding component for decoding into microinstructions. ... Soft Machines Inc

Hardware acceleration components for translating guest instructions to native instructions

A hardware based translation accelerator. The hardware includes a guest fetch logic component for accessing guest instructions; a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling guest instructions into a guest instruction block; and conversion tables coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block. ... Soft Machines Inc

01/12/17 / #20170010977

Systems and methods for accessing a unified translation lookaside buffer

Systems and methods for accessing a unified translation lookaside buffer (tlb) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (l1tlb) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes that correspond to translation table entries (ttes) that have been evicted from the l1tlb, where a page size is identified, and searching a second level tlb and identifying a physical address that is contained in the second level tlb. ... Soft Machines Inc








ARCHIVE: New 2018 2017 2016 2015 2014 2013 2012 2011 2010 2009



###

This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Soft Machines Inc in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Soft Machines Inc with additional patents listed. Browse our Agent directory for other possible listings. Page by FreshPatents.com

###