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Soft Machines Inc patents

Recent patent applications related to Soft Machines Inc. Soft Machines Inc is listed as an Agent/Assignee. Note: Soft Machines Inc may have other listings under different names/spellings. We're not affiliated with Soft Machines Inc, we're just tracking patents.

ARCHIVE: New 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Soft Machines Inc-related inventors




Date Soft Machines Inc patents (updated weekly) - BOOKMARK this page
03/09/17Allocation of a segmented interconnect to support the execution of instruction sequences by a plurality of engines
03/09/17Allocation of an interconnect structure comprising shared buses to support the execution of instruction sequences by a plurality of engines
03/09/17Hardware accelerated conversion system using pattern matching
03/09/17Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor
03/09/17Instruction sequence buffer to enhance branch prediction efficiency
01/26/17Hardware acceleration components for translating guest instructions to native instructions
01/26/17Microprocessor accelerated code optimizer
01/12/17Systems and methods for accessing a unified translation lookaside buffer
12/22/16Methods, systems and predicting the way of a set associative cache
12/08/16Systems and methods for load canceling in a processor that is connected to an external interconnect fabric
12/08/16Systems and methods for load canceling in a processor that is connected to an external interconnect fabric
11/17/16Method and apparatus to avoid deadlock during instruction scheduling using dynamic port remapping
11/17/16Interconnect structure to support the execution of instruction sequences by a plurality of engines
11/10/16Method and sorting elements in hardware structures
11/03/16Guest to native block address mappings and management of native code storage
09/29/16Guest instruction block with near branching and far branching sequence construction to native instruction block
09/08/16Multiport memory cell having improved density area
08/25/16Systems and methods for implementing weak stream software data and instruction prefetching using a hardware data prefetcher
08/04/16Methods and systems for managing synonyms in virtually indexed physically tagged caches
08/04/16Variable caching structure for managing physical storage
07/21/16Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
07/21/16Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
06/02/16Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
05/19/16Systems and methods for non-blocking implementation of cache flush instructions
04/21/16Systems and methods for invalidating directory of non-home locations ways
04/21/16Methods and systems for tracking addresses stored in non-home cache locations
02/11/16Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
02/11/16Systems and methods for supporting a plurality of load and store accesses of a cache
02/11/16Systems and methods for supporting a plurality of load accesses of a cache in a single cycle
01/28/16System converter that implements a reordering process through jit (just in time) optimization that ensures loads do not dispatch ahead of other loads that are to the same address
01/28/16System converter that implements a run ahead run time guest instruction conversion/decoding process and a prefetching process where guest code is pre-fetched from the target of guest branches in an instruction sequence
01/28/16Using a plurality of conversion tables to implement an instruction set agnostic runtime architecture
01/28/16System for an instruction set agnostic runtime architecture
01/28/16System converter that executes a just in time optimizer for executing code from a guest image
01/28/16An allocation and issue stage for reordering a microinstruction sequence into an optimized microinstruction sequence to implement an instruction set agnostic runtime architecture
01/28/16Using a conversion look aside buffer to implement an instruction set agnostic runtime architecture
11/26/15Systems and methods for faster read after write forwarding using a virtual address
11/12/15Method and providing hardware support for self-modifying code
10/22/15Systems and methods for accessing a unified translation lookaside buffer
10/08/15Cache replacement policy
09/24/15Apparatus and processing an instruction matrix specifying parallel and dependent operations
09/03/15Fast unaligned memory access
07/23/15Load store buffer agnostic to threads implementing forwarding from different threads based on store seniority
05/14/15Virtual load store queue having a dynamic dispatch window with a distributed structure
04/09/15Semaphore method and system with out of order loads in a memory consistency model that constitutes loads reading from memory in order
04/09/15Disambiguation-free out of order load store queue
04/09/15Reordered speculative instruction sequences with a disambiguation-free out of order load store queue
04/02/15Lock-based and synch-based out of order loads in a memory consistency model using shared memory resources
04/02/15Method and system for filtering the stores to prevent all stores from having to snoop check against all words of a cache
04/02/15Instruction definition to implement load store reordering and optimization
04/02/15Virtual load store queue having a dynamic dispatch window with a unified structure
04/02/15Method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization
03/05/15Systems and methods for faster read after write forwarding using a virtual address
02/19/15Systems and methods for acquiring data for loads at different access times from hierarchical sources using a load queue as a temporary storage buffer and completing the load early
02/19/15Systems and methods for read request bypassing a last level cache that interfaces with an external fabric
02/19/15Systems and methods for invasive debug of a processor without processor execution of instructions
02/12/15Method for using register templates to track interdependencies among blocks of instructions
02/12/15Method for executing blocks of instructions using a microprocessor architecture having a register view, source view, instruction view, and a plurality of register templates
02/05/15Microprocessor accelerated code optimizer
01/22/15Multiport memory cell having improved density area
12/18/14Method and efficient scheduling for asymmetrical execution units
10/30/14Method for a stage optimized high speed adder
10/23/14Method and preventing non-temporal entries from polluting small structures using a transient buffer
10/23/14Method for performing dual dispatch of blocks and half blocks
10/09/14Method and apparatus to increase the speed of the load access and data return speed path using early lower address bits
Patent Packs
09/18/14Method for implementing a line speed interconnect structure
09/18/14Method and apparatus to speed up the load access and data return speed path using early lower address bits
09/18/14Methods, systems and predicting the way of a set associative cache
09/18/14Method and predicting forwarding of data from a store to a load
09/18/14Method and guest return address stack emulation supporting speculation
09/18/14Method and predicting forwarding of data from a store to a load
09/18/14Method and nearest potential store tagging
09/18/14Method and apparatus to allow early dependency resolution and data forwarding in a microprocessor
09/18/14Method for dependency broadcasting through a source organized source view data structure
09/18/14Method for populating and instruction view data structure by using register template snapshots
09/18/14Method for implementing a reduced size register view data structure in a microprocessor
09/18/14Method and sorting elements in hardware structures
09/18/14Method for populating a source view data structure by using register template snapshots
09/18/14Method for implementing a reduced size register view data structure in a microprocessor
09/18/14Method for populating register view data structure by using register template snapshots
Patent Packs
09/18/14Method for emulating a guest centralized flag architecture by using a native distributed flag architecture
09/18/14Method for a delayed branch implementation by using a front end track table
09/18/14Methods, systems and supporting wide and efficient front-end operation with guest-architecture emulation
09/18/14Method and apparatus to avoid deadlock during instruction scheduling using dynamic port remapping
09/18/14Method for executing multithreaded instructions grouped into blocks
09/18/14Method for dependency broadcasting through a block organized source view data structure
06/26/14Parallel processing of a sequential program using hardware generated threads and their instruction groups executing on plural execution units and accessing register file segments using dependency inheritance vectors across multiple engines
06/05/14Method and supporting a plurality of load accesses of a cache in a single cycle to maintain throughput
04/17/14Systems and methods for load canceling in a processor that is connected to an external interconnect fabric
04/17/14Systems and methods for non-blocking implementation of cache flush instructions
04/17/14Systems and methods for implementing weak stream softeare data and instruction prefetching using a hardware data prefetcher
03/13/14Instruction sequence buffer to store branches having reliably predictable instruction sequences
01/30/14Systems and methods for flushing a cache with modified data
01/30/14Systems and methods for supporting a plurality of load accesses of a cache in a single cycle
01/30/14Systems and methods for supporting a plurality of load and store accesses of a cache
01/30/14Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
11/21/13Instruction sequence buffer to enhance branch prediction efficiency
09/12/13Systems and methods for accessing a unified translation lookaside buffer
04/11/13Apparatus and processing an instruction matrix specifying parallel and dependent operations
01/24/13Multilevel conversion table cache for translating guest instructions to native instructions
01/24/13Hardware acceleration components for translating guest instructions to native instructions
11/22/12Decentralized allocation of resources and interconnnect structures to support the execution of instruction sequences by a plurality of engines
11/22/12Interconnect structure to support the execution of instruction sequences by a plurality of engines
09/27/12Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
09/27/12Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
09/27/12Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
08/02/12Guest to native block address mappings and management of native code storage
08/02/12Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor
08/02/12Variable caching structure for managing physical storage
08/02/12Guest instruction block with near branching and far branching sequence construction to native instruction block
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