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Spansion Llc
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Spansion Llc patents

Recent patent applications related to Spansion Llc. Spansion Llc is listed as an Agent/Assignee. Note: Spansion Llc may have other listings under different names/spellings. We're not affiliated with Spansion Llc, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Spansion Llc-related inventors




Date Spansion Llc patents (updated weekly) - BOOKMARK this page
09/22/16Device and resisting non-invasive attacks
09/08/16Voltage detector and detecting voltage
08/11/16Control circuit
06/09/16Methods, circuits, devices, systems and machine executable code for reading from a non-volatile memory array
05/26/16Temperature detection circuit and temperature measurement circuit
05/12/16Protecting circuit and integrated circuit
05/05/16Charge-trapping memory device
04/21/16Overlaid erase block mapping
04/21/16Simultaneous programming of many bits in flash memory
04/14/16System-on-chip verification
04/07/16Analog-digital conversion controlling the same
02/25/16Switching circuit
02/18/16Integration of semiconductor memory cells and logic cells
02/04/16Control apparatus, buck-boost power supply and control method
02/04/16Crystal oscillation circuit
01/28/16Detecting the drift of the data valid window in a transaction
12/31/15Booting an application from multiple memories
11/26/15Methods, circuits, devices and systems for sensing an nvm cell
11/26/15Methods, circuits, devices and systems for comparing signals
11/26/15Methods, circuits, devices and systems for integrated circuit voltage level shifting
11/19/15Tilted implant for poly resistors
09/24/15Semiconductor device and manufacturing thereof
09/17/15Buried trench isolation in integrated circuits
09/10/15Memory access bases on erase cycle time
09/10/15Method to improve charge trap flash memory top oxide quality
08/27/15Memory subsystem with wrapped-to-continuous read
07/09/15Varied silicon richness silicon nitride formation
07/09/15Multi-layer inter-gate dielectric structure
07/02/15Formation of gate sidewall structure
06/25/15Ct-nor differential bitline sensing architecture
06/25/15Gate formation memory by planarization
06/18/15Fractured erase system and method
06/18/15Process for forming edge wordline implants adjacent edge wordlines
06/18/15Increasing lithographic depth of focus window using wafer topography
06/11/15Forming charge trap separation in a flash memory semiconductor device
06/04/15Generation of wake-up words
06/04/15Reduction of charging induced damage in photolithography wet process
05/28/15Method of forming controllably conductive oxide
05/28/15Auto resume of irregular erase stoppage of a memory sector
05/14/15Output switching circuit
05/07/15Methods, circuits, systems and computer executable instruction sets for providing error correction of stored data and data storage devices utilizing same
04/23/15Three-dimensional charge trapping nand cell with discrete charge trapping film
04/23/15Multiple phase-shift photomask and semiconductor manufacturing method
04/16/15Ion implantation-assisted etch-back process for improving spacer shape and spacer width control
04/16/15Spacer formation with straight sidewall
04/16/15Multi-pass soft programming
04/16/15Hidden markov model processing engine
04/16/15Managed-nand with embedded random-access non-volatile memory
04/16/15Memory program upon system failure
04/16/15Method for providing read data flow control or error reporting using a read data strobe
04/09/15Buried trench isolation in integrated circuits
04/09/15Self-aligned trench isolation in integrated circuits
04/09/15Methods circuits apparatuses and systems for providing current to a non-volatile memory array and non-volatile memory devices produced accordingly
04/02/15Die seal layout for vftl dual damascene in a semiconductor device
03/12/15Semiconductor memory device having lowered bit line resistance
02/26/15Apparatus and smart vcc trip point design for testability
02/26/15Chip positioning in multi-chip package
02/19/15Line-edge roughness improvement for small pitches
02/12/15Semiconductor device sealed in a resin section and manufacturing the same
02/05/15Method to improve charge trap flash memory core cell performance and reliability
01/29/15Integrated circuits with non-volatile memory and methods for manufacture
01/15/15Non-volatile memory with silicided bit line contacts
01/01/15Semiconductor device, controlling the same, and manufacturing the same
12/25/14Method of depositing copper using physical vapor deposition
12/25/14Method of depositing copper using physical vapor deposition
Patent Packs
12/18/14Screening for reference cells in a memory
12/18/14Non-volatile finfet memory array and manufacturing method thereof
11/27/14Differential file system for computer memory
10/23/14Charge-trap nor with silicon-rich nitride as a charge trap layer
10/23/14System and manufacturing self-aligned sti with single poly
10/23/14Die seal layout for vftl dual damascene in a semiconductor device
10/16/14Dc-dc converter with adaptive phase compensation controller
10/09/14Modified local segmented self-boosting of memory cell channels
10/09/14Authentication for recognition systems
10/09/14Combining of results from multiple decoders
09/25/14Node system and supervisory node
09/25/14Inter-bus communication interface device
09/11/14Pipelining in a memory
09/11/14Semiconductor device having chip mounted on an interposer
08/28/14Mitigate flash write latency and bandwidth limitation
Patent Packs
08/21/14Contact configuration for undertaking tests on circuit board
08/21/14Apparatus and method to reduce bit line disturbs
08/14/14Flash memory cells having trenched storage elements
08/14/14Data pattern analysis (as amended)
08/14/14Operating system based dram and flash management
08/07/14Semiconductor memory device
08/07/14Memory buffering system that improves read/write performance and provides low latency for mobile systems
08/07/14Non-volatile memory device
07/31/14Semiconductor device and control the same
07/31/14Convex shaped thin-film transistor device
07/31/14Non-volatile memory with silicided bit line contacts
07/31/14Manufacturing of fet devices having lightly doped drain and source regions
07/31/14Variable read latency on a serial memory bus
07/24/14Switchable memory diodes based on ferroelectric/conuugated polymer heterostructures and/or their composites
07/24/14Control circuit of step-down dc-dc converter, control circuit of step-up dc-dc converter and step-up/step-down dc-dc converter
07/17/14Debug control circuit
07/10/14Self-aligned double patterning for memory and other microelectronic devices
07/10/14Multi-chip package assembly with improved bond wire separation
07/10/14Programmable and flexible reference cell selection memory devices
07/10/14Buried hard mask for embedded semiconductor device patterning
07/10/14Distributed speech recognition system
07/03/14Design for test (dft) read speed through transition detector in built-in self-test (bist) sort
06/26/14Chip positioning in multi-chip package
06/26/14Memory device with internal combination logic
06/26/14Hybrid hashing scheme for active hmms
06/26/14Histogram based pre-pruning scheme for active hmms
06/26/14Phoneme score accelerator
06/19/14Memory gate landing pad made from dummy features
06/19/14Process charging protection for split gate charge trapping flash
06/19/14Charge trapping device with improved select gate to memory gate isoloation
Social Network Patent Pack
06/19/14High voltage gate formation
06/19/14Hto offset for long leffective, better device performance
06/19/14Integrated circuits with non-volatile memory and methods for manufacture
06/19/14Memory first process flow and device
06/19/14Charge trapping split gate embedded flash memory and associated methods
06/19/14Use disposable gate cap to form transistors, and split gate charge trapping memory cells
06/19/14Method for amnufacturing a semiconductor device
06/19/14Three dimensional capacitor
06/19/14Charge trapping split gate device and fabricating same
06/12/14Gate fringine effect based channel formation for semiconductor device
Patent Packs
06/12/14Authenticated memory and controller slave
06/05/14Memory device interconnects and manufacture
06/05/14Signal processor and communication device
05/29/14Memory device interconnects and manufacture
05/29/14Parallel bitline nonvolatile memory employing channel-based processing technology
05/29/14Non-volatile finfet memory device and manufacturing method thereof
05/29/14Forming a substantially uniform wing height among elements in a charge trap semiconductor device
05/29/14Forming charge trap separation in a flash memory semiconductor device
05/22/14Inter-layer insulator for electronic devices and forming same
05/22/14Method to improve charge trap flash memory core cell performance and reliability
05/22/14Data refresh in non-volatile memory
05/15/14Distribution of gas over a semiconductor water in batch processing
05/08/14Electrically programmable and eraseable memory device
05/08/14Recognition of speech with different accents
05/08/14Wear leveling in flash memory devices with trim commands
05/01/14Integrating transistors with different poly-silicon heights on the same die
05/01/14Semiconductor device and manufacturing the same
05/01/14Data writing method and system
04/24/14Semiconductor device and manufacturing thereof
04/17/14Partial local self boosting for nand
04/10/14Spacer design to prevent trapped electrons
04/10/14Output voltage controller, electronic device, and output voltage control method
04/10/14Supply power dependent controllable write throughput for memory applications
04/03/14Method, apparatus, and manufacture for staggered start for memory module
04/03/14Semiconductor device and manufacturing the same
03/27/14Voltage adjustment circuit and display device driving circuit
03/27/14Processor system optimization
03/20/14Semiconductor device and manufacturing thereof
03/13/14Semiconductor integrated circuit, operating semiconductor integrated circuit, and debug system
03/13/14Execution history tracing method
Patent Packs
03/06/14Multi-chip module and manufacture
02/27/14Power supply device, control circuit, electronic device and control power supply
02/06/14Semiconductor device and programming method
02/06/14Apparatus and a metal oxide semiconductor field effect transistor with source side punch-through protection implant
02/06/14Power savings memory device using delay locked loop
01/23/14Dual storage node memory
01/16/14Leakage reducing writeline charge protection circuit
01/02/14Self-aligned si rich nitride charge trap layer isolation for charge trap flash memory
12/19/13Heat dissipation methods and structures for semiconductor device
12/19/13Power-efficient voice activation
12/05/13Method, apparatus, and manufacture for flash memory adaptive algorithm
11/28/13Self-aligned nand flash select-gate wordlines for spacer double patterning
11/21/13Soft error resistant circuitry
10/03/13Adaptively programming or erasing flash memory blocks
09/12/13Method and protection against process-induced charging
09/12/13Metal-insulator-metal (mim) device and formation thereof
09/05/13Memory device protection layer
08/01/13System and detecting particles with a semiconductor device
07/18/13Semiconductor device and fabricating thereof
07/11/13Fabricating mirror bit memory device having split ono film with top oxide film formed by oxidation process
Social Network Patent Pack
07/04/13Semiconductor device and control the same
06/27/13Fabricating mirror bit memory device having split ono film with top oxide film formed by oxidation process
06/20/13Acoustic processing unit
06/20/13Acoustic processing unit interface
06/20/13Arithmetic logic unit architecture
06/13/13Rapid memory buffer write storage system and method
06/06/13Void free interlayer dielectric
05/30/13Device having multiple wire bonds for a bond area and methods thereof
05/23/13Table lookup operation on masked data
05/16/13Partial allocate paging mechanism
05/02/13Flash memory cell with flair gate
05/02/13Storage device, control storage device, and control storage control device
04/25/13Semiconductor device and fabrication method therefore
04/18/13Semiconductor device and controlling the same
04/04/13Apparatus and smart vcc trip point design for testability
03/14/13Hardware based wear leveling mechanism
03/07/13Variable read latency on a serial memory bus
02/07/13Imaging device
01/24/13Method and manufacture for embedded flash to achieve high quality spacers for core and high voltage devices and low temperature spacers for high performance logic devices
01/24/13Error correction for flash memory
Social Network Patent Pack
01/03/13Radiation detecting device and operating
01/03/13Local interconnect having increased misalignment tolerance
01/03/13Local interconnect having increased misalignment tolerance
12/27/12High read speed memory with gate isolation
12/20/12Method, apparatus, and manufacture for staggered start for memory module
12/13/12Mitigate flash write latency and bandwidth limitation
11/29/12Method and system for providing contact to a first polysilicon layer in a flash memory device
11/22/12Controlling ac disturbance while programming
11/01/12Apparatus and external charge pump on flash memory module
11/01/12Method, apparatus, and manufacture for flash memory write algorithm for fast bits
11/01/12Method and temperature compensation for programming and erase distributions in a flash memory
10/25/12Relocating data in a memory device
09/27/12Integrating transistors with different poly-silicon heights on the same die
08/30/12Electronic devices with ultraviolet blocking layers and processes of forming the same
08/09/12Patterned dummy wafers loading in batch type cvd
07/19/12Non-volatile finfet memory array and manufacturing method thereof
06/28/12System, reducing plasma noise on power path of electrostatic chuck
06/07/12Method and nand memory with recessed source/drain region
06/07/12Method and enhanced lifetime and performance of ion source in an ion implantation system
03/15/12Apparatus and data capture using a read preamble
03/15/12Apparatus and read preamble disable
03/15/12Apparatus, method, and manufacture for using a read preamble to optimize data capture
03/15/12Apparatus and programmable read preamble
03/08/12Method and device employing polysilicon scaling
03/01/12Resistance changing memory cell architecture
02/09/12Gate trim process using either wet etch or dry etch approach to target cd for selected transistors
02/09/12Method and manufacture for high voltage gate oxide formation after shallow trench isolation formation
12/29/11High read speed memory with gate isolation
11/17/11Oro and orpro with bit line trench to suppress transport program disturb
09/29/11Controlling ac disturbance while programming
Social Network Patent Pack
09/29/11Fuel cell catalyst regeneration
09/29/11Sacrificial nitride and gate replacement
09/29/11Variable read latency on a serial memory bus
09/29/11Memory device and method
09/15/11Non-volatile finfet memory device and manufacturing method thereof
09/15/11Nand array source/drain doping scheme
09/15/11Home and building automation
09/15/11Systems and methods for controlling an electronic device
09/15/11Electronic devices using removable and programmable active processing modules
08/18/11Apparatus and extended nitride layer in a flash memory
08/11/11Planar cell on cut using in-situ polymer deposition and etch
07/21/11Junction leakage suppression in memory devices
07/21/11Field upgradable firmware for electronic devices
07/21/11Programmable read preamble
07/21/11Field programmable redundant memory for electronic devices
07/14/11Hto offset and bl trench process for memory device to improve device performance
07/07/11Memory device
06/30/11Method for forming narrow structures in a semiconductor device
06/23/11High read speed electronic memory with serial array transistors
06/23/11Variable read latency on a serial memory bus
06/23/11Read preamble for data capture optimization
06/09/11Processes for forming electronic devices including polishing metal-containing layers
06/02/11Local interconnect having increased misalignment tolerance
05/26/11Method and performing semiconductor memory operations
04/28/11Split charge storage node outer spacer process
04/14/11Local interconnect having increased misalignment tolerance
04/07/11Parallel bitline nonvolatile memory employing channel-based processing technology
03/03/11Memory device
12/30/10Electronic device having a molding compound including a composite material







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