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Stats Chippac Ltd
Stats Chippac Ltd_20100107
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Stats Chippac Ltd patents

Recent patent applications related to Stats Chippac Ltd. Stats Chippac Ltd is listed as an Agent/Assignee. Note: Stats Chippac Ltd may have other listings under different names/spellings. We're not affiliated with Stats Chippac Ltd, we're just tracking patents.

ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009 | Company Directory "S" | Stats Chippac Ltd-related inventors




Date Stats Chippac Ltd patents (updated weekly) - BOOKMARK this page
12/01/16Semiconductor device and forming substrate including embedded component with symmetrical structure
10/13/16Double-sided semiconductor package and dual-mold making same
10/13/16Semiconductor device and forming a package in-fan out package
09/22/16Semiconductor device and forming pop semiconductor device with rdl over top package
08/11/16Semiconductor device and forming 3d dual side die embedded build-up semiconductor package
07/28/16Semiconductor device and forming mems package
07/28/16Semiconductor device and forming wlcsp with semiconductor die embedded within interconnect structure
07/07/16Semiconductor device and forming sacrificial adhesive over contact pads of semiconductor die
07/07/16Semiconductor device and forming shielding layer over integrated passive device using conductive channels
06/09/16Semiconductor device and bonding semiconductor die to substrate in reconstituted wafer form
05/26/16Semiconductor device and forming holes in substrate to interconnect top shield and ground shield
05/19/16Semiconductor device and forming a low profile embedded wafer level ball grid array molded laser package (ewlb-mlp)
04/28/16Semiconductor device and fabricating 3d package with short cycle time and high yield
04/28/16Semiconductor device and fabricating 3d package with short cycle time and high yield
04/21/16Semiconductor device and forming interposer frame over semiconductor die to provide vertical interconnect
04/14/16Semiconductor device and forming prefabricated heat spreader frame with embedded semiconductor die
04/14/16Semiconductor device and forming ewlb semiconductor package with vertical interconnect structure and cavity region
03/10/16Semiconductor device and self-confinement of conductive bump material during reflow without solder mask
02/11/16Semiconductor device and forming double-sided fan-out wafer level package
01/14/16Semiconductor device and forming wafer-level interconnect structures with advanced dielectric characteristics
12/31/15Semiconductor device and forming conductive vias by direct via reveal with organic passivation
12/31/15Semiconductor device and forming conductive vias by backside via reveal with cmp
12/17/15Method for building up a fan-out rdl structure with fine pitch line-width and line-spacing
12/17/15Semiconductor device and forming a dampening structure to improve board level reliability
12/10/15Semiconductor die and forming fo-wlcsp vertical interconnect using tsv and tmv
12/03/15Semiconductor device and forming adhesive layer over insulating layer for bonding carrier to mixed surfaces of semiconductor die and encapsulant
12/03/15Semiconductor device and forming electromagnetic (em) shielding for lc circuits
11/12/15Semiconductor device and embedding tsv semiconductor die within substrate for vertical interconnect in pop
10/29/15Semiconductor device and forming bump-on-lead interconnection
10/15/15Semiconductor device and forming a vertical interconnect structure for 3-d fo-wlcsp
10/08/15Semiconductor device and forming a vertical interconnect structure for 3-d fo-wlcsp
10/01/15Semiconductor device and forming rdl and vertical interconnect by laser direct structuring
10/01/15Semiconductor device and forming substrate having conductive columns
09/24/15Semiconductor device and forming 3d dual side die embedded build-up semiconductor package
09/17/15Semiconductor device and forming microelectromechanical systems (mems) package
09/17/15Semiconductor device and dual-molding die formed on opposite sides of build-up interconnect structure
09/03/15Semiconductor device and forming wlp with semiconductor die embedded within penetrable encapsulant between tsv interposers
08/27/15Semiconductor device and forming encapsulated wafer level chip scale package (ewlcsp)
08/13/15Semiconductor device and forming insulating layer disposed over the semiconductor die for stress relief
08/13/15Semiconductor device and mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the die
08/13/15Semiconductor device and embedding thermally conductive layer in interconnect structure for heat dissipation
07/30/15Semiconductor device and self-confinement of conductive bump material during reflow without solder mask
06/25/15Semiconductor device and making embedded wafer level chip scale packages
06/25/15Semiconductor device and wafer thinning involving edge trimming and cmp
06/25/15Semiconductor device and forming fine pitch rdl over semiconductor die in fan-out package
06/25/15Semiconductor device and forming stress relief layer between die and interconnect structure
06/25/15Semiconductor device and forming build-up interconnect structures over a temporary substrate
06/18/15Semiconductor device and reducing warpage using a silicon to encapsulant ratio
06/04/15Semiconductor device and forming repassivation layer for robust low cost fan-out semiconductor package
05/28/15Semiconductor device and forming compliant stress relief buffer around large array wlcsp
05/28/15Semiconductor device and forming stepped interconnect layer for stacked semiconductor die
05/21/15Semiconductor device and forming wlcsp using wafer sections containing multiple die
05/21/15Semiconductor device and forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die tsv
05/21/15Semiconductor device and forming wire bondable fan-out ewlb package
05/07/15Semiconductor device and forming interposer frame electrically connected to embedded semiconductor die
04/30/15Semiconductor device and forming a shielding layer between stacked semiconductor die
04/30/15Semiconductor device and balancing surfaces of an embedded pcb unit with a dummy copper pattern
04/09/15Semiconductor device and forming conductive layer over substrate with vents to channel bump material and reduce interconnect voids
04/02/15Semiconductor device and forming conductive vias through interconnect structures and encapsulant of wlcsp
04/02/15Semiconductor device and making an embedded wafer level ball grid array (ewlb) package on package (pop) device with a slotted metal carrier interposer
04/02/15Semiconductor device and forming patterned repassivation openings between rdl and ubm to reduce adverse effects of electro-migration
03/26/15Semiconductor device and forming dual fan-out semiconductor package
03/26/15Semiconductor device and controlling warpage in reconstituted wafer
03/05/15Semiconductor device and forming openings and trenches in insulating layer by first lda and second lda for rdl formation
03/05/15Semiconductor device and forming interconnect structure for encapsulated die having pre-applied protective layer
Patent Packs
02/26/15Semiconductor device and forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure
02/26/15Semiconductor device and forming pad layout for flipchip semiconductor die
02/12/15Semiconductor device and making wafer level chip scale package
01/29/15Semiconductor device and forming through mold hole with alignment and dimension control
01/29/15Semiconductor device and forming overlapping semiconductor die with coplanar vertical interconnect structure
01/22/15Semiconductor device and forming thermal lid for balancing warpage and thermal management
01/08/15Semiconductor device and forming sacrificial protective layer to protect semiconductor die edge during singulation
01/01/15Semiconductor device and individual die bonding followed by simultaneous multiple die thermal compression bonding
01/01/15Semiconductor device and using substrate with conductive posts and protective layers to form embedded sensor die package
01/01/15Semiconductor device and forming low profile 3d fan-out package
01/01/15Semiconductor device and stacking semiconductor die on a fan-out wlcsp
01/01/15Semiconductor device and forming trench and disposing semiconductor die over substrate to control outward flow of underfill material
01/01/15Semiconductor device and forming an interposer including a beveled edge
01/01/15Methods of forming conductive jumper traces
01/01/15Methods of forming conductive materials on contact pads
Patent Packs
01/01/15Methods of forming conductive and insulating layers
12/18/14Semiconductor device and making an embedded wafer level ball grid array (ewlb) package on package (pop) device with a slotted metal carrier interposer
12/11/14Semiconductor device and using leadframe bodies to form openings through encapsulant for vertical interconnect of semiconductor die
12/04/14Semiconductor device and forming interconnect structure and mounting semiconductor die in recessed encapsulant
11/06/14Semiconductor device and forming interposer frame over semiconductor die to provide vertical interconnect
10/30/14Semiconductor device and forming stress-reduced conductive joint structures
10/09/14Semiconductor device and forming conductive vias using backside via reveal and selective passivation
10/02/14Methods of manufacturing flip chip semiconductor packages using double-sided thermal compression bonding
09/25/14Semiconductor device and forming pip with inner known good die interconnected with conductive bumps
09/18/14Semiconductor device and forming an inductor on polymer matrix composite substrate
09/18/14Semiconductor device including rdl along sloped side surface of semiconductor die for z-direction interconnect
09/18/14Semiconductor device and using partial wafer singulation for improved wafer level embedded system in package
09/18/14Semiconductor device and forming a dual ubm structure for lead free bump connections
09/18/14Semiconductor device and forming ubm structure on back surface of tsv semiconductor wafer
09/18/14Semiconductor device and forming wlcsp with semiconductor die embedded within interconnect structure
09/18/14Semiconductor device and calibrating warpage testing system to accurately measure semiconductor package warpage
09/11/14Semiconductor device and forming embedded conductive layer for power/ground planes in fo-ewlb
09/11/14Semiconductor device and forming sacrificial adhesive over contact pads of semiconductor die
09/11/14Semiconductor device and forming ultra high density embedded semiconductor die package
09/11/14Semiconductor device and forming repassivation layer with reduced opening to contact pad of semiconductor die
09/04/14Semiconductor device and forming insulating layer disposed over the semiconductor die for stress relief
08/28/14Semiconductor device and forming a vertical interconnect structure for 3-d fo-wlcsp
08/28/14Semiconductor device and forming micro-vias partially through insulating material over bump interconnect conductive layer for stress relief
08/28/14Semiconductor device and forming topside and bottom-side interconnect structures around core die with tsv
08/21/14Semiconductor device and embedding bumps formed on semiconductor die into penetrable adhesive layer to reduce die shifting during encapsulation
08/14/14Semiconductor device with conductive pillars having recesses or protrusions to detect interconnect continuity between semiconductor die and substrate
08/14/14Semiconductor device and confining conductive bump material during reflow with solder mask patch
08/14/14Semiconductor device and forming insulating layer in notches around conductive tsv for stress relief
08/07/14Semiconductor device and forming stress relieving vias for improved fan-out wlcsp package
08/07/14Semiconductor device and forming conductive vias with trench in saw street
Social Network Patent Pack
07/24/14Semiconductor device and providing z-interconnect conductive pillars with inner polymer core
07/17/14Extended redistribution layers bumped wafer
07/17/14Semiconductor device and forming through-silicon-via with sacrificial layer
07/03/14Semiconductor device and using a standardized carrier to form embedded wafer level chip scale packages
07/03/14Semiconductor device and forming embedded wafer level chip scale packages
06/26/14Semiconductor device and forming discontinuous esd protection layers between semiconductor die
06/26/14Semiconductor device and simultaneous molding and thermalcompression bonding
06/26/14Semiconductor device and bonding semiconductor die to substrate in reconstituted wafer form
06/26/14Semiconductor device and forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties
06/26/14Semiconductor device and making bumpless flipchip interconnect structures
Patent Packs
06/12/14Semiconductor device having high-density interconnect array with core pillars formed with osp coating
06/12/14Semiconductor device and forming low profile fan-out package with vertical interconnection units
05/15/14Semiconductor device and self-confinement of conductive bump material during reflow without solder mask
05/08/14Embedded semiconductor die package and making the same using metal frame carrier
04/24/14Semiconductor package and mounting semiconductor die to opposite sides of tsv substrate
04/24/14Semiconductor device having an interconnect structure with tsv using encapsulant for structural support
04/24/14Semiconductor device and confining conductive bump material with solder mask patch
04/17/14Semiconductor device and forming non-linear interconnect layer with extended length for joint reliability
04/17/14Semiconductor device and forming conductive ink layer as interconnect structure between semiconductor packages
04/17/14Semiconductor device and forming a pop device with embedded vertical interconnect units
04/03/14Semiconductor device and forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package
04/03/14Semiconductor device and using a standardized carrier in semiconductor packaging
04/03/14Semiconductor device and depositing encapsulant along sides and surface edge of semiconductor die in embedded wlcsp
03/27/14Semiconductor device and forming integrated passive device over semiconductor die with conductive bridge and fan-out redistribution layer
03/27/14Semiconductor device with protective structure around semiconductor die for localized planarization of insulating layer
03/20/14Semiconductor device with protective layer over exposed surfaces of semiconductor die
03/20/14Semiconductor device and forming build-up interconnect structures over carrier for testing at interim stages
03/20/14Semiconductor device and forming dual-sided interconnect structures in fo-wlcsp
03/20/14Semiconductor device and forming dual-sided interconnect structures in fo-wlcsp
03/20/14Semiconductor device and forming wire studs as vertical interconnect in fo-wlp
03/20/14Semiconductor device and forming fo-wlcsp with multiple encapsulants
03/20/14Semiconductor device and using substrate having base and conductive posts to form vertical interconnect structure in embedded die package
03/13/14Semiconductor device and forming multi-layered ubm with intermediate insulating buffer layer to reduce stress for semiconductor wafer
03/13/14Semiconductor device and forming conductive thv and rdl on opposite sides of semiconductor die for rdl-to-rdl bonding
03/06/14Semiconductor device and forming thick encapsulant for stiffness with recesses for stress relief in fo-wlcsp
02/27/14Semiconductor device and forming rdl using uv-cured conductive ink over wafer level package
02/20/14Semiconductor device and forming a fan-out pop device with pwb vertical interconnect units
02/20/14Semiconductor device and dual-molding die formed on opposite sides of build-up interconnect structure
01/30/14Semiconductor device and forming vertical interconnect structure with conductive micro via array for 3-d fo-wlcsp
01/09/14Semiconductor device and forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material
Patent Packs
01/09/14Semiconductor device and forming electrical interconnection between semiconductor die and substrate with continuous body of solder tape
01/09/14Semiconductor device and forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure
01/09/14Semiconductor device and forming bump-on-lead interconnection
01/09/14Optical semiconductor device having pre-molded leadframe with window and method therefor
01/02/14Semiconductor device and embedding thermally conductive layer in interconnect structure for heat dissipation
01/02/14Semiconductor device having balanced band-pass filter implemented with lc resonators
01/02/14Semiconductor device and forming mold underfill using dispensing needle having same width as semiconductor die
12/26/13Semiconductor device and forming an embedded sop fan-out package
12/26/13Semiconductor device and forming a wafer level package with top and bottom solder bump interconnection
12/12/13Bump-on-lead flip chip interconnection
12/05/13Semiconductor device and backgrinding and singulation of semiconductor wafer while reducing kerf shifting and protecting wafer surfaces
12/05/13Semiconductor device and reflow soldering for conductive column structure in flip chip package
11/14/13Semiconductor device and depositing underfill material with uniform flow rate
11/14/13Semiconductor device and controlling warpage in semiconductor package
11/14/13Air humidifier
10/24/13Semiconductor device and forming bump-on-lead interconnection
10/24/13Semiconductor device and forming composite bump-on-lead interconnection
10/03/13Integrated circuit packaging system with routable circuitry and manufacture thereof
09/26/13Semiconductor device and simultaneous testing of multiple interconnects for electro-migration
09/26/13Semiconductor device and forming duplex plated bump-on-lead pad over substrate for finer pitch between adjacent traces
Social Network Patent Pack
09/26/13Semiconductor device and singulating semiconductor wafer along modified region within non-active region formed by irradiating energy through mounting tape
09/26/13Semiconductor device and forming openings and trenches in insulating layer by first lda and second lda for rdl formation
09/26/13Semiconductor device and forming partially-etched conductive layer recessed within substrate for bonding to semiconductor die
09/26/13Semiconductor device of forming a fan-out pop device with pwb vertical interconnect units
09/26/13Semiconductor device and forming conductive layer over metal substrate for electrical interconnect of semiconductor die
09/26/13Semiconductor device and forming micro-vias partially through insulating material over bump interconnect conductive layer for stress relief
09/26/13Semiconductor device and forming a robust fan-out package including vertical interconnects and mechanical support layer
09/26/13Semiconductor device and forming rdl wider than contact pad along first axis and narrower than contact pad along second axis
09/26/13Semiconductor of forming a fan-out pop device with pwb vertical interconnect units
09/19/13Semiconductor device and forming base substrate with recesses for capturing bumped semiconductor die
09/19/13Semiconductor device and mounting cover to semiconductor die and interposer with adhesive material
09/19/13Semiconductor device and forming semiconductor package having build-up interconnect structure over semiconductor die with different cte insulating layers
09/19/13Semiconductor device and forming compliant conductive interconnect structure in flipchip package
09/19/13Semiconductor device and forming interposer and opposing build-up interconnect structure with connecting conductive tmv for electrical interconnect of fo-wlcsp
09/12/13Semiconductor device and forming non-linear interconnect layer with extended length for joint reliability
09/12/13Thin 3d fan-out embedded wafer level package (ewlb) for application processor and memory integration
09/12/13Semiconductor device and forming vertically offset conductive pillars over first substrate aligned to vertically offset bot interconnect sites formed over second substrate
09/05/13Semiconductor device and forming a low profile embedded wafer level ball grid array molded laser package (ewlp-mlp)
09/05/13Semiconductor device and forming protective coating over interconnect structure to inhibit surface oxidation
08/29/13Semiconductor device and forming semiconductor die with active region responsive to external stimulus
Social Network Patent Pack
08/22/13Package-in-package using through-hole via die on saw streets
08/22/13Semiconductor device and forming base leads from base substrate as standoff for stacking semiconductor die
08/22/13Semiconductor device and forming bond-on-lead interconnection for mounting semiconductor die in fo-wlcsp
08/15/13Semiconductor device and forming a shielding layer over a semiconductor die after forming a build-up interconnect structure
08/08/13Semiconductor device and forming pre-molded substrate to reduce warpage during die molding
08/08/13Semiconductor device and forming a vertical interconnect structure for 3-d fo-wlcsp
07/18/13Semiconductor device and forming an inductor on polymer matrix composite substrate
07/11/13Semiconductor device and making integrated passive devices
07/11/13Semiconductor device and forming insulating layer disposed over the semiconductor die for stress relief
07/11/13Semiconductor device and forming reduced surface roughness in molded underfill for improved c-sam inspection
07/04/13Method of forming top electrode for capacitor and interconnection in integrated passive device (ipd)
06/27/13Semiconductor device and forming insulating layer in notches around conductive tsv for stress relief
06/27/13Semiconductor device and forming extended semiconductor device with fan-out interconnect structure to reduce complexity of substrate
06/20/13Semiconductor device and forming vertically offset bond on trace interconnect structure on leadframe
06/20/13Semiconductor device and forming leadframe interposer over semiconductor die and tsv substrate for vertical electrical interconnect
06/20/13Semiconductor device and forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties
06/20/13Semiconductor device and forming vertical interconnect structure with conductive micro via array for 3-d fo-wlcsp
06/13/13Semiconductor device and forming conductive pillars having recesses or protrusions to detect interconnect continuity between semiconductor die and substrate
06/13/13Semiconductor device and forming insulating layer around semiconductor die
06/13/13Semiconductor device and forming recesses in conductive layer to detect continuity for interconnect between semiconductor die and substrate
06/13/13Semiconductor device and forming ubm structure on back surface of tsv semiconductor wafer
06/13/13Semiconductor device and making single layer substrate with asymmetrical fibers and reduced warpage
06/13/13Semiconductor device and forming thick encapsulant for stiffness with recesses for stress relief in fo-wlcsp
06/13/13Semiconductor device and forming guard ring around conductive tsv through semiconductor wafer
06/13/13Semiconductor device and forming adjacent channel and dam material around die attach area of substrate to control outward flow of underfill material
06/06/13Semiconductor device and forming cavity in build-up interconnect structure for short signal path between die
06/06/13Semiconductor device and forming patterned repassivation openings between rdl and ubm to reduce adverse effects of electro-migration
06/06/13Semiconductor device and forming semiconductor package having build-up interconnect structure over semiconductor die with different cte insulating layers
05/30/13Semiconductor device and forming rdl under bump for electrical connection to enclosed bump
05/30/13Semiconductor device having vertically offset bond on trace interconnects on recessed and raised bond fingers
Social Network Patent Pack
05/23/13Semiconductor device and forming reconstituted wafer with larger carrier to achieve more ewlb packages per wafer with encapsulant deposited under temperature and pressure
05/23/13Semiconductor device and laser-marking laminate layer formed over ewlb with tape applied to opposite surface
05/23/13Semiconductor device and forming conductive layer over substrate with vents to channel bump material and reduce interconnect voids
05/16/13Semiconductor device and forming ewlb package containing stacked semiconductor die electrically connected through conductive vias formed in encapsulant around die
05/09/13Semiconductor device and forming insulating layer disposed over the semiconductor die for stress relief
05/09/13Semiconductor device and forming a metallurgical interconnection between a chip and a substrate in a flip chip package
05/09/13Semiconductor device and forming sloped surface in patterning layer to separate bumps of semiconductor die from patterning layer
05/02/13Semiconductor device and forming thermal interface material and heat spreader over semiconductor die
05/02/13Semiconductor die and forming sloped surface in photoresist layer to enhance flow of underfill material between semiconductor die and substrate
05/02/13Semiconductor device and forming conductive posts and heat sink over semiconductor die using leadframe
05/02/13Semiconductor device and forming interposer frame over semiconductor die to provide vertical interconnect
04/25/13Semiconductor device and forming directional rf coupler with ipd for additional rf signal processing
04/25/13Semiconductor device and forming interposer frame electrically connected to embedded semiconductor die
04/18/13Semiconductor device and forming air gap adjacent to stress sensitive region of the die
04/18/13Semiconductor device and forming conductive pillar having an expanded base
04/11/13Semiconductor device and forming a shielding layer between stacked semiconductor die
04/11/13Semiconductor device and forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die
04/11/13Semiconductor device and forming bump on substrate to prevent elk ild delamination during reflow process
04/11/13Semiconductor device and forming conductive tsv with insulating annular ring
04/11/13Semiconductor device and forming reconstituted wafer with larger carrier to achieve more ewlb packages per wafer with encapsulant deposited under temperature and pressure
03/28/13Semiconductor package and forming z-direction conductive posts embedded in structurally protective encapsulant
03/28/13Semiconductor device and forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
03/28/13Semiconductor device and forming conductive posts embedded in photosensitive encapsulant
03/28/13Semiconductor device and forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die
03/28/13Semiconductor device and forming fo-wlcsp having conductive layers and conductive vias separated by polymer layers
03/28/13Semiconductor device and forming stacked vias within interconnect structure for fo-wlcsp
03/28/13Semiconductor device and forming interconnect substration for fo-wlcsp
03/21/13Semiconductor device and forming rf fem with lc filter and ipd filter over substrate
03/21/13Semiconductor device and forming conductive protrusions over conductive pillars or bond pads as fixed offset vertical interconnect structures







ARCHIVE: New 2017 2016 2015 2014 2013 2012 2011 2010 2009



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