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Stats Chippac Pte Ltd patents

Recent patent applications related to Stats Chippac Pte Ltd. Stats Chippac Pte Ltd is listed as an Agent/Assignee. Note: Stats Chippac Pte Ltd may have other listings under different names/spellings. We're not affiliated with Stats Chippac Pte Ltd, we're just tracking patents.

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Date Stats Chippac Pte Ltd patents (updated weekly) - BOOKMARK this page
05/25/17 new patent  Semiconductor device and forming openings through insulating layer over encapsulant for enhanced adhesion of interconnect structure
05/11/17Semiconductor device and using a standardized carrier in semiconductor packaging
05/11/17Semiconductor device and controlling warpage in reconstituted wafer
04/20/17Semiconductor device and forming semiconductor die with active region responsive to external stimulus
04/06/17Semiconductor device and using substrate having base and conductive posts to form vertical interconnect structure in embedded die package
04/06/17Semiconductor device and forming sacrificial protective layer to protect semiconductor die edge during singulation
03/30/17Semiconductor device and singulating thin semiconductor wafer on carrier along modified region within non-active region formed by irradiating energy
03/23/17Semiconductor device and forming repassivation layer for robust low cost fan-out semiconductor package
03/09/17Integrated circuit packaging system with single-layer support structure
03/02/17Semiconductor device and forming interconnect structure and mounting semiconductor die in recessed encapsulant
02/02/17Antenna in embedded wafer-level ball-grid array package
01/19/17Semiconductor device and forming emi shielding layer with conductive material around semiconductor die
01/12/17Semiconductor device and depositing encapsulant along sides and surface edge of semiconductor die in embedded wlcsp
12/01/16Semiconductor device and balancing surfaces of an embedded pcb unit with a dummy copper pattern
11/17/16Semiconductor device and forming a thin wafer without a carrier
11/17/16Semiconductor device and forming wire studs as vertical interconnect in fo-wlp
11/10/16Methods of forming conductive and insulating layers
10/06/16Semiconductor device and forming wafer level ground plane and power ring
09/29/16Semiconductor package with embedded die
09/22/16Semiconductor device and forming build-up interconnect structures over carrier for testing at interim stages
09/22/16Semiconductor device and method to minimize stress on stack via
09/22/16Semiconductor device and forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package
09/22/16Semiconductor device and forming stacked vias within interconnect structure for fo-wlcsp
09/22/16Semiconductor device and forming an embedded sop fan-out package
09/08/16Semiconductor device and self-confinement of conductive bump material during reflow without solder mask
09/08/16Semiconductor device and self-confinement of conductive bump material during reflow without solder mask

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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. is not affiliated or associated with Stats Chippac Pte Ltd in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Stats Chippac Pte Ltd with additional patents listed. Browse our Agent directory for other possible listings. Page by